CY7C1361C-117BZI [CYPRESS]
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM; 9兆位（ 256K ×36 / 512K ×18 ）流通型SRAM
| 型号： | CY7C1361C-117BZI |
| 厂家： | 
CYPRESS |
| 描述： | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM |
| 文件： | 总30页 (文件大小：476K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1361C
CY7C1363C
PRELIMINARY
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
Features
Functional Description[1]
• Supports 133-MHz bus operations
• 256K × 36/512K × 18 common I/O
• 3.3V –5% and +10% core power supply (VDD
The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x
18 Synchronous Flowthrough SRAMs, respectively designed
to interface with high-speed microprocessors with minimum
glue logic. Maximum access delay from clock rise is 6.5 ns
(133-MHz version). A 2-bit on-chip counter captures the first
address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
)
• 2.5V or 3.3V I/O supply (VDDQ
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
— 7.5 ns (117-MHz version)
— 8.5 ns (100-MHz version)
)
addresses, all data inputs, address-pipelining Chip Enable
[2]
(
), depth-expansion Chip Enables (CE and
), Burst
CE3
CE1
2
Control inputs (
,
,
), Write Enables
(
ADV
BWx
and
,
• Provide high-performance 2-1-1-1 access rate
ADSC ADSP
), and Global Write (
BWE
). Asynchronous
GW
and
inputs
• User-selectable burst counter supporting Intel
(
)
and the ZZ pin
OE
.
include the Output Enable
Pentium interleaved or linear burst sequences
The CY7C1361C/CY7C1363C allows either interleaved or
linear burst sequences, selected by the MODE input pin. A
HIGH selects an interleaved burst sequence, while a LOW
selects a linear burst sequence. Burst accesses can be
initiated with the Processor Address Strobe (ADSP) or the
cache Controller Address Strobe (ADSC) inputs. Address
advancement is controlled by the Address Advancement
(ADV) input.
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• AvailableinLead-Free100TQFP,119BGAand165fBGA
packages Both 2 and 3 Chip Enable Options for TQFP
• IEEE 1149.1 compatible JTAG Boundary Scan for BGA
and fBGA packages
•“ZZ” Sleep Mode option
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (
) or
ADSP
Address Strobe Controller (
) are active. Subsequent
ADSC
burst addresses can be internally generated as controlled by
the Advance pin ( ).
ADV
The CY7C1361C/CY7C1363C operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
133 MHz
117 MHz
7.5
100 MHz
8.5
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
6.5
250
30
220
30
180
30
Notes:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE is for A version of TQFP ( 3 Chip Enable Option) and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.
3
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05541 Rev. *A
Revised October 5, 2004
CY7C1361C
CY7C1363C
PRELIMINARY
Logic Block Diagram – CY7C1361C (256K x 36)
ADDRESS
REGISTER
A0, A1, A
A[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
AND LOGIC
Q0
CLR
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D, DQPD
DQ
BYTE
WRITE REGISTER
D, DQPD
BW
D
DQ
BYTE
WRITE REGISTER
C, DQPC
DQ
BYTE
WRITE REGISTER
C, DQPC
BW
C
OUTPUT
BUFFERS
DQs
MEMORY
ARRAY
SENSE
AMPS
DQP
DQP
DQP
A
DQ
BYTE
WRITE REGISTER
B, DQPB
B
C
DQ
BYTE
WRITE REGISTER
B, DQPB
BW
B
DQPD
DQ
BYTE
WRITE REGISTER
A, DQPA
DQ
A, DQPA
BW
A
BYTE
BWE
WRITE REGISTER
INPUT
REGISTERS
GW
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
1
Logic Block Diagram – CY7C1363C (512K x 18)
ADDRESS
REGISTER
A0,A1,A
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B,DQPB
DQ
B,DQPB
WRITE DRIVER
WRITE REGISTER
BW
B
A
MEMORY
ARRAY
OUTPUT
BUFFERS
DQs
DQP
DQP
SENSE
AMPS
A
B
DQ
A,DQPA
DQA,DQPA
WRITE REGISTER
WRITE DRIVER
BW
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
Document #: 38-05541 Rev. *A
Page 2 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Pin Configurations
100-pin TQFP Pinout (3 Chip Enables) (A version)
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
A
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
NC
2
DQC
3
NC
NC
3
VDDQ
4
5
VDDQ
VSSQ
NC
VDDQ
VSSQ
NC
4
VSSQ
5
DQC
6
6
DQC
7
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
7
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS/DNU
VDD
8
DQC
9
9
VSSQ
10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
11
DQC
12
DQC
13
VSS/DNU
14
VDD
15
NC
CY7C1363C
(512K x 18)
CY7C1361C
(256K x 36)
NC
16
VDD
ZZ
NC
VDD
ZZ
VSS
17
VSS
DQD
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
VDDQ
20
VSSQ
21
DQD
22
DQD
23
DQD
24
DQD
25
NC
VSSQ
26
VSSQ
VDDQ
NC
VSSQ
VDDQ
NC
VDDQ
27
DQD
28
DQD
29
NC
NC
DQPD
30
NC
NC
Document #: 38-05541 Rev. *A
Page 3 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Pin Configurations (continued)
100-pin TQFP (2 Chip Enables) (AJ Version)
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
A
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
NC
2
DQC
3
NC
NC
3
VDDQ
4
5
VDDQ
VSSQ
NC
VDDQ
VSSQ
NC
4
VSSQ
5
DQC
6
6
DQC
7
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
7
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS/DNU
VDD
8
DQC
9
9
VSSQ
10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
11
DQC
12
DQC
13
VSS/DNU
14
VDD
15
NC
CY7C1363C
(512K x 18)
CY7C1361C
NC
16
VDD
ZZ
NC
VDD
ZZ
VSS
17
(256K x 36)
VSS
DQD
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
VDDQ
20
VSSQ
21
DQD
22
DQD
23
DQD
24
DQD
25
NC
VSSQ
26
VSSQ
VDDQ
NC
VSSQ
VDDQ
NC
VDDQ
27
DQD
28
DQD
29
NC
NC
DQPD
30
NC
NC
Document #: 38-05541 Rev. *A
Page 4 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Pin Configurations (continued)
119-ball BGA (2 Chip Enables with JTAG)
CY7C1361C (256K x 36)
1
2
3
4
5
6
7
VDDQ
A
A
A
A
VDDQ
A
ADSP
B
C
NC
NC
CE2
A
A
A
A
A
A
A
NC
NC
ADSC
VDD
DQC
DQC
VDDQ
DQPC
DQC
DQC
VSS
VSS
VSS
NC
CE1
OE
VSS
VSS
VSS
DQPB
DQB
DQB
DQB
DQB
VDDQ
D
E
F
DQC
DQC
VDDQ
DQD
DQD
VDDQ
DQD
DQC
DQC
VDD
DQB
DQB
VDD
DQA
DQA
DQA
DQA
DQB
DQB
VDDQ
DQA
DQA
VDDQ
DQA
G
H
J
BWC
VSS
NC
ADV
GW
VDD
CLK
NC
BWE
A1
BWB
VSS
NC
DQD
VSS
VSS
K
L
M
N
DQD
DQD
DQD
BWD
VSS
VSS
BWA
VSS
VSS
P
R
DQD
NC
DQPD
A
VSS
MODE
A0
VDD
VSS
NC
DQPA
A
DQA
NC
T
U
NC
VDDQ
NC
TMS
A
TDI
A
TCK
A
TDO
NC
NC
ZZ
VDDQ
CY7C1363C (512K x 18)
2
A
CE2
A
NC
DQB
NC
1
3
A
A
4
5
A
A
A
VSS
VSS
VSS
VSS
VSS
6
A
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
VDDQ
NC
NC
DQB
NC
VDDQ
NC
DQB
VDDQ
VDDQ
NC
NC
NC
DQA
VDDQ
DQA
NC
VDDQ
ADSP
ADSC
VDD
A
A
DQPA
NC
A
VSS
VSS
VSS
BWB
VSS
NC
NC
CE1
OE
ADV
DQA
DQB
NC
VDD
NC
DQA
VDD
NC
DQA
NC
GW
VDD
NC
VSS
NC
DQB
VSS
CLK
NC
BWE
A1
DQA
DQB
VDDQ
DQB
NC
NC
DQB
NC
VSS
VSS
VSS
VSS
NC
VDDQ
NC
BWA
VSS
VSS
VSS
DQA
NC
DQPB
A0
DQA
R
T
NC
NC
A
A
MODE
A
VDD
NC
NC
A
A
A
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Document #: 38-05541 Rev. *A
Page 5 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Pin Configurations (continued)
165-ball fBGA (3 Chip Enable)
CY7C1361C (256K x 36)
1
NC / 288M
NC
DQPC
DQC
2
A
A
NC
DQC
DQC
DQC
DQC
VSS
DQD
DQD
DQD
DQD
NC
3
4
5
6
7
8
9
10
11
NC
NC / 144M
DQPB
DQB
CE1
BWC
BWB
CE3
BWE
GW
VSS
VSS
VSS
ADSC
ADV
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
BWD
VSS
VDD
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
NC
DQB
DQC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
DQB
DQB
DQB
NC
DQA
DQA
DQA
DQA
NC
A
DQB
DQC
DQC
NC
DQD
DQD
DQD
DQD
DQPD
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
DQB
DQB
ZZ
DQA
DQA
DQA
DQA
DQPA
A
VSS
NC
TDI
VSS
NC / 18M
A1
VDD
VSS
A
NC / 72M
A0
MODE NC / 36M
A
A
TMS
TCK
A
A
A
A
R
CY7C1363C (512K x 18)
1
NC / 288M
NC
2
3
4
5
6
7
8
9
10
11
A
A
CE1
BWB
NC
CE
BWE
GW
VSS
VSS
ADSC
ADV
A
A
3
A
NC
DQB
DQB
DQB
DQB
VSS
NC
NC
NC
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
A
NC
NC
NC
NC
NC
NC / 144M
DQPA
DQA
B
C
D
E
F
G
H
J
K
L
NC
NC
NC
NC
NC
VSS
DQB
DQB
DQB
VSS
DQA
VSS
VSS
VSS
VSS
VSS
VSS
DQA
DQA
ZZ
NC
NC
NC
DQA
DQA
DQA
NC
DQB
DQPB
NC
NC
NC
NC / 72M
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
NC / 18M
A1
VSS
NC
TDO
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
MODE NC / 36M
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05541 Rev. *A
Page 6 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Pin Definitions
Name
I/O
Description
A0, A1 , A
Input-
Address Inputs used to select one of the address locations. Sampled at the rising
Synchronous edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2] are sampled
active. A[1:0] feed the 2-bit counter.
BWA,BWB
BWC,BWD
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
Synchronous SRAM. Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
GW
Synchronous global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE).
CLK
Input-
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
Clock
the burst counter when ADV is asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
CE1
CE2
Synchronous conjunction with CE2 and CE3[2] to select/deselect the device. ADSP is ignored
if CE1 is
CE is sampled only when a new external address is loaded.
HIGH.
1
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE3[2] to select/deselect the device. CE2 is sampled only when
a new external address is loaded.
[2]
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
CE3
Synchronous conjunction with CE1 and CE2 to select/ deselect the device.CE3 is sampled only when
a new external address is loaded.
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
OE
Asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is masked during the first clock of a read cycle
when emerging from a deselected state.
Input-
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automat-
ADV
Synchronous ically increments the address in a burst cycle.
Input-
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
ADSP
Synchronous When asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when
is deasserted HIGH.
CE1
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
ADSC
Synchronous When asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
BWE
ZZ
Synchronous must be asserted LOW to conduct a byte write.
Input-
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull-down.
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
DQs
Synchronous triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous
clock rise of
the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,
the pins behave as outputs. When HIGH, DQs and DQPX are placed in a three-state
The outputs are automatically three-stated during the data portion of a write
condition.
sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
I/O-
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs.
DQPX
Synchronous During write sequences, DQPX is controlled by BWX correspondingly.
MODE
Input-
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD
or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an internal pull-up.
Static
VDD
VDDQ
VSS
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground
Ground for the core of the device.
Document #: 38-05541 Rev. *A
Page 7 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Pin Definitions (continued)
Name
I/O
Description
VSSQ
TDO
I/O Ground
Ground for the I/O circuitry.
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
Synchronous JTAG feature is not being utilized, this pin should be left unconnected. This pin is not
available on TQFP packages.
TDI
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
Synchronous feature is not being utilized, this pin can be left floating or connected to VDD through a pull
up resistor. This pin is not available on TQFP packages.
TMS
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
Synchronous feature is not being utilized, this pin can be disconnected or connected to VDD. This pin
is not available on TQFP packages.
TCK
NC
JTAG-
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
Clock
be connected to VSS. This pin is not available on TQFP packages.
–
No Connects. Not internally connected to the die. 18M, 36M, 72M, 144M and 288M are
address expansion pins are not internally connected to the die.
VSS/DNU
Ground/DNU
This pin can be connected to Ground or should be left floating.
Document #: 38-05541 Rev. *A
Page 8 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ[A:D] will be
written into the specified address location. Byte writes are
allowed. All I/Os are three-stated when a write is detected,
even a byte write. Since this is a common I/O device, the
asynchronous OE input signal must be deasserted and the
I/Os must be three-stated prior to the presentation of data to
DQs. As a safety precaution, the data lines are three-stated
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (tCDV) is 6.5 ns (133-MHz device).
The CY7C1361C/CY7C1363C supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium® and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
once a write cycle is detected, regardless
of the state of OE.
Burst Sequences
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
The CY7C1361C/CY7C1363C provides an on-chip two-bit
wraparound burst counter inside the SRAM. The burst counter
is fed by A[1:0], and can follow either a linear or interleaved
burst order. The burst order is determined by the state of the
MODE input. A LOW on MODE will select a linear burst
sequence. A HIGH on MODE will select an interleaved burst
order. Leaving MODE unconnected will cause the device to
default to a interleaved burst sequence.
Byte write operations are qualified with the Byte Write Enable
X
(BWE) and Byte Write Select (BW ) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3[2]) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE1 is HIGH.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
Single Read Accesses
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
A single read access is initiated when the following conditions
[2]
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to tCDV after clock
rise. ADSP is ignored if CE1 is HIGH.
Linear Burst Address Table (MODE = GND)
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
[2]
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BWX)are ignored during this first clock
cycle. If the write inputs are asserted active (see Write Cycle
Descriptions table for appropriate states that indicate a write)
on the next clock rise,the appropriate data will be latched and
written into the device.Byte writes are allowed. All I/Os are
three-stated during a byte write.Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be three-stated prior to the presentation of
data to DQs. As a safety precaution, the data lines are
three-stated once a write cycle is detected, regardless of the
state of OE.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
“sleep” mode. CE , CE , CE [2], ADSP, and ADSC must
the
1
2
3
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3[2] are all asserted
Document #: 38-05541 Rev. *A
Page 9 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
Min.
Max.
35
2tCYC
Unit
mA
ns
tZZREC
tZZI
tRZZI
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
2tCYC
0
ns
ns
ns
2tCYC
Truth Table [ 3, 4, 5, 6, 7]
Address
Cycle Description
Used CE1 CE2 CE3 ZZ ADSP
ADSC ADV WRITE OE CLK
DQ
Deselected Cycle, Power-down None
Deselected Cycle, Power-down None
Deselected Cycle, Power-down None
Deselected Cycle, Power-down None
Deselected Cycle, Power-down None
H
L
L
L
X
X
L
L
L
L
L
X
L
X
L
X
X
X
X
H
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
L
L
X
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
L-H three-state
L-H three-state
L-H three-state
L-H three-state
L-H three-state
Sleep Mode, Power-down
None
X
L-H
three-state
Q
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
External
External
External
External
External
Next
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L-H three-state
L-H
L-H
D
Q
L-H three-state
L-H
L-H three-state
L-H
L-H three-state
X
X
H
H
H
H
Q
Next
Next
Q
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Next
Next
Next
Current
Current
Current
Current
Current
Current
H
X
H
X
X
H
H
X
H
H
H
H
H
H
H
H
H
H
L-H
L-H
L-H
D
D
Q
L
H
H
H
H
H
H
H
H
H
H
L
L-H three-state
L-H
L-H three-state
Q
H
X
X
L-H
L-H
D
D
Write Cycle, Suspend Burst
L
Notes:
3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H..
5. The DQ pins are controlled by the current cycle and the signal. is asynchronous and is not sampled with the clock.
OE
OE
must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks after
X
the
or with the assertion of
. As a result,
is a don't
OE
ADSC
OE
ADSP
care for the remainder of the write cycle.
7.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when
OE
is
OE
inactive or when the device is deselected, and all data bits behave as output when
is active (LOW).
OE
Document #: 38-05541 Rev. *A
Page 10 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Partial Truth Table for Read/Write[3, 8]
Function (CY7C1361C)
Read
Read
Write Byte (A, DQPA)
Write Byte (B, DQPB)
BWD
X
BWC
X
BWB
BWA
X
H
L
H
L
H
L
H
L
H
L
H
L
GW
BWE
H
H
X
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
X
Write Bytes (B, A, DQPA, DQPB)
Write Byte (C, DQPC)
Write Bytes (C, A, DQPC, DQPA)
Write Bytes (C, B, DQPC, DQPB)
Write Bytes (C, B, A, DQPC, DQPB, DQPA)
Write Byte (D, DQPD)
Write Bytes (D, A, DQPD, DQPA)
Write Bytes (D, B, DQPD, DQPA)
Write Bytes (D, B, A, DQPD, DQPB, DQPA)
Write Bytes (D, B, DQPD, DQPB)
Write Bytes (D, B, A, DQPD, DQPC, DQPA)
Write Bytes (D, C, A, DQPD, DQPB, DQPA)
Write All Bytes
L
H
H
L
L
H
H
L
L
H
H
L
L
X
H
L
H
L
L
L
L
X
Write All Bytes
X
Truth Table for Read/Write[3, 8]
Function (CY7C1363C)
BWB
BWA
BWE
GW
Read
Read
H
H
X
X
H
L
H
L
H
H
H
H
L
L
L
L
L
X
H
H
L
L
X
Write Byte A – ( DQA and DQPA)
Write Byte B – ( DQB and DQPB)
Write All Bytes
Write All Bytes
X
Note:
8. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid Appropriate write will be done based on which byte write is active.
X
Document #: 38-05541 Rev. *A
Page 11 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Test MODE SELECT (TMS)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
The CY7C1361C/CY7C1363C incorporates a serial boundary
scan test access port (TAP) in the BGA package only. The
TQFP package does not offer this functionality. This part
operates in accordance with IEEE Standard 1149.1-1900, but
doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure .
TDI is internally pulled up and can be unconnected if the TAP
is unused in an application. TDI is connected to the most
significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
The CY7C1361C/CY7C1363C contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0
TAP Controller State Diagram
Bypass Register
TEST-LOGIC
1
2
1
0
0
0
RESET
0
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
S
election
TDI
TDO
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
Circuitr
y
.
.
. 2 1
0
0
1
1
CAPTURE-DR
CAPTURE-IR
x
.
.
.
.
. 2 1
0
0
Boundary Scan Register
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
TCK
TMS
0
0
TAP CONTROLLER
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
UPDATE-DR
UPDATE-IR
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Document #: 38-05541 Rev. *A
Page 12 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Instruction Register
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
Bypass Register
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
IDCODE
Boundary Scan Register
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1-mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the in-
struction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possi-
ble that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE / PRELOAD instruction. If
this is an issue, it is still possible to capture all other signals
and simply ignore the value of the CK and CK# captured in the
boundary scan register.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
Document #: 38-05541 Rev. *A
Page 13 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Once the data is captured, it is possible to shift out the data by
BYPASS
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required–that is, while data
captured is shifted out, the preloaded data can be shifted in.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter
Clock
tTCYC
tTF
Parameter
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
tTH
tTL
25
25
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
5
ns
ns
0
Setup Times
tTMSS
TMS Set-Up to TCK Clock Rise
TDI Set-Up to TCK Clock Rise
Capture Set-Up to TCK Rise
5
5
5
ns
ns
tTDIS
tCS
Hold Times
tTMSH
tTDIH
tCH
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
5
5
5
ns
ns
ns
Notes:
9. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
10. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
Document #: 38-05541 Rev. *A
Page 14 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ........ ........................................VSS to 3.3V
Input rise and fall times...................... ..............................1ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Input pulse levels ......................................... VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels................... ......................1.25V
Output reference levels .................. ..............................1.25V
Test load termination supply voltage .................... ........1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
ZO= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.3V ±0.165V unless
otherwise noted)[11]
Parameter
VOH1
Description
Output HIGH Voltage
Description
IOH = –4.0 mA
Conditions
VDDQ = 3.3V
Min.
2.4
Max.
Unit
V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
2.0
2.9
2.1
V
V
IOH = –1.0 mA
IOH = –100 µA
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
V
0.4
0.4
V
IOL = 8.0 mA
IOL = 8.0 mA
IOL = 100 µA
V
0.2
V
0.2
V
2.0
1.7
VDD + 0.3
VDD + 0.3
0.7
V
V
VDDQ = 3.3V
–0.5
–0.3
–5
V
VIL
VDDQ = 2.5V
0.7
V
5
µA
IX
GND < VIN < VDDQ
Identification Register Definitions
CY7C1361C
CY7C1363C
(512K x18)
Instruction Field
(256K x36)
Description
000
01011
000
01011
Revision Number (31:29)
Device Depth (28:24)[12]
Describes the version number.
Reserved for Internal Use
000001
100110
00000110100
1
000001
010110
00000110100
1
Device Width (23:18)
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Note:
11. All voltages referenced to VSS (GND) .
12. Bit #24 is “1” in the Register Definitions for both 2.5v and 3.3v versions of this device.
Document #: 38-05541 Rev. *A
Page 15 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Scan Register Sizes
Register Name
Bit Size (×36) Bit Size (×18)
Instruction
Bypass
ID
3
1
32
71
3
1
32
71
Boundary Scan Order
(119-ball BGA package)
Boundary Scan Order
71
71
(165-ball fBGA package)
Identification Codes
Instruction
Code
Description
000
001
010
EXTEST
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
SAMPLE Z
011
100
RESERVED
SAMPLE/PRELOAD
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
101
110
111
RESERVED
RESERVED
BYPASS
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
Document #: 38-05541 Rev. *A
Page 16 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
119-Ball BGA Boundary Scan Order
CY7C1361C (256K x 36)
CY7C1363C (512K x 18)
BALL
ID
Signal
Signal
Signal
Signal
BIT#
Name
BIT# BALL ID
Name
A0
BIT# BALL ID
Name
BIT# BALL ID
Name
1
2
3
4
5
6
7
8
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
37
38
39
40
41
42
43
44
P4
N4
R6
T5
T3
R2
R3
P2
1
2
3
4
5
6
7
8
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
37
38
39
40
41
42
43
44
P4
N4
R6
T5
T3
R2
R3
Internal
A0
A1
A
A
A
K4
H4
M4
F4
B4
A4
G4
C3
K4
H4
M4
F4
B4
A4
G4
C3
A1
A
A
A
A
A
MODE
DQPD
MODE
Internal
9
B3
D6
H7
G6
E6
D7
E7
F6
G7
H6
T7
K7
L6
A
DQPB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
ZZ
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
P1
L2
DQD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
Internal
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQPC
A
9
B3
T2
A
A
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Internal
Internal
Internal
P2
Internal
Internal
Internal
DQPB
DQB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
K1
Internal
Internal
Internal
D6
Internal
Internal
Internal
DQPA
DQA
DQA
DQA
DQA
ZZ
N2
N1
N1
M2
L1
M2
DQB
E7
L1
DQB
K2
F6
K2
DQB
Internal
H1
G7
Internal
H1
Internal
DQB
H6
G2
E2
T7
G2
DQB
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQPA
A
K7
DQA
DQA
DQA
DQA
Internal
Internal
Internal
Internal
Internal
A
E2
DQB
D1
L6
D1
DQB
N6
P7
N7
M6
L7
H2
N6
Internal
Internal
Internal
Internal
Internal
C2
Internal
Internal
Internal
Internal
Internal
A
G1
F2
P7
Internal
Internal
Internal
Internal
Internal
T6
E1
D2
K6
P6
T4
A3
C5
B5
A5
C6
C2
A2
A
A2
A
E4
CE1
E4
CE1
A
B2
CE2
A3
A
B2
CE2
A
L3
BWD
BWC
BWB
BWA
Internal
C5
A
Internal
Internal
G3
Internal
Internal
BWB
A
G3
G5
L5
B5
A
A
A5
A
A
C6
A
L5
BWA
35
36
A6
B6
A
A
Internal
35
36
A6
B6
A
A
Internal
Internal
Document #: 38-05541 Rev. *A
Page 17 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
165-Ball fBGA Boundary Scan Order
CY7C1361C (256K x 36)
CY7C1363C (512K x 18)
BALL
ID
B6
B7
A7
B8
A8
B9
A9
Signal
Signal
Signal
Signal
Name
A0
A1
A
BIT#
1
2
3
4
5
6
7
8
Name
BIT# BALL ID
Name
A0
BIT# BALL ID
Name
BIT# BALL ID
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
R6
P6
R4
P4
R3
P3
R1
N1
L2
K2
J2
M2
M1
L1
K1
J1
Internal
G2
F2
E2
D2
G1
F1
E1
D1
C1
B2
A2
A3
B3
B4
A4
A5
B5
A6
1
B6
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
R6
P6
R4
P4
R3
P3
R1
Internal
Internal
Internal
Internal
N1
M1
L1
K1
J1
Internal
G2
F2
E2
D2
Internal
Internal
Internal
Internal
Internal
B2
A2
A3
B3
Internal
Internal
A4
B5
A6
A1
A
A
A
2
B7
3
A7
4
B8
A
A
A
5
A8
A
6
B9
MODE
DQPD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
Internal
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQPC
A
7
A9
MODE
Internal
Internal
Internal
Internal
DQPB
DQB
DQB
DQB
DQB
Internal
DQB
DQB
DQB
DQB
Internal
Internal
Internal
Internal
Internal
A
B10
A10
C11
E10
F10
G10
D10
D11
E11
F11
G11
H11
J10
K10
L10
M10
J11
K11
L11
M11
N11
R11
R10
P10
R9
8
B10
9
A
9
A10
A
A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DQPB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
ZZ
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQPA
A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
A11
Internal
Internal
Internal
C11
D11
E11
F11
G11
H11
J10
K10
Internal
Internal
Internal
DQPA
DQA
DQA
DQA
DQA
ZZ
DQA
DQA
DQA
DQA
Internal
Internal
Internal
Internal
Internal
A
L10
M10
Internal
Internal
Internal
Internal
Internal
R11
R10
P10
R9
A
A
CE1
CE2
Internal
Internal
BWB
BWA
CE3
CE1
CE2
BWD
BWC
BWB
BWA
CE3
A
A
A
A
A
A
A
A
A
A
A
A
A
A
P9
R8
P8
P11
P9
R8
P8
P11
Document #: 38-05541 Rev. *A
Page 18 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Range
Temperature
VDD
VDDQ
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
DC Voltage Applied to Outputs
to VDD
in three-state....................................... –0.5V to VDDQ + 0.5V
Industrial
–40°C to +85°C
DC Input Voltage....................................–0.5V to VDD + 0.5V
[13, 14]
Electrical Characteristics Over the Operating Range
Parameter
VDD
VDDQ
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
3.6
VDD
Unit
V
V
V
V
V
V
V
V
VDDQ = 3.3V
VDDQ = 2.5V
2.625
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
2.0
0.4
0.4
VDD + 0.3V
VDD + 0.3V
0.8
Input HIGH Voltage[13] VDDQ = 3.3V
VDDQ = 2.5V
2.0
1.7
–0.3
–0.3
–5
V
V
V
Input LOW Voltage[13]
VDDQ = 3.3V
VDDQ = 2.5V
GND ≤ VI ≤ VDDQ
0.7
5
Input Load
Input Current of MODE Input = VSS
Input = VDD
µA
µA
µA
µA
µA
µA
mA
mA
–30
5
Input Current of ZZ
Input = VSS
Input = VDD
–5
–5
30
5
250
220
180
40
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled
VDD Operating Supply VDD = Max., IOUT = 0 mA,
7.5-ns cycle, 133 MHz
8.8-ns cycle, 117 MHz
10-ns cycle, 100 MHz
All speeds
Current
f = fMAX = 1/tCYC
ISB1
ISB2
ISB3
Automatic CE
Max. VDD, Device Deselected,
mA
mA
mA
mA
Power-down
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
Current—TTL Inputs
inputs switching
Automatic CE
Max. VDD, Device Deselected,
All speeds
All speeds
All Speeds
30
40
40
Power-down
V
IN ≥ VDD – 0.3V or VIN ≤ 0.3V,
Current—CMOS Inputs f = 0, inputs static
Automatic CE
Max. VDD, Device Deselected,
Power-down
V
IN ≥ VDDQ – 0.3V or VIN ≤ 0.3V,
Current—CMOS Inputs f = fMAX, inputs switching
ISB4
Automatic CE
Max. VDD, Device Deselected,
IN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
Power-down
V
Current—TTL Inputs
Notes:
13. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > -2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
14. T
: Assumes a linear ramp from 0v to V (min.) within 200ms. During this time V < V and V
< V
.
DD
Power-up
DD
IH
DD
DDQ
Document #: 38-05541 Rev. *A
Page 19 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Thermal Resistance[15]
TQFP
BGA
fBGA
Parameter
Description
Test Conditions
Package
Package
Package
Unit
ΘJA
Thermal Resistance
Test conditions follow standard
test methods and procedures
for measuring thermal
25
25
27
°C/W
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
9
6
6
°C/W
impedance, per EIA/JESD51
Capacitance[15]
TQFP
BGA
fBGA
Parameter
CIN
CCLK
CI/O
Description
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
Test Conditions
Package
Package
Package
Unit
pF
pF
TA = 25°C, f = 1 MHz,
5
5
5
5
5
7
5
5
7
V
DD = 3.3V
V
DDQ = 2.5V
pF
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
R = 317Ω
3.3V
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
90%
Z = 50Ω
0
10%
R = 50Ω
10%
L
GND
≤ 1ns
5 pF
R = 351Ω
≤ 1ns
INCLUDING
JIG AND
SCOPE
V = 1.5V
T
(a)
(b)
(c)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
OUTPUT
Z = 50Ω
0
R = 50Ω
10%
10%
L
5 pF
R =1538Ω
≤ 1ns
≤ 1ns
V = 1.25V
T
INCLUDING
JIG AND
SCOPE
(a)
(b)
(c)
Switching Characteristics Over the Operating Range[20, 21]
133 MHz
117 MHz
Min. Max.
100 MHz
Parameter
tPOWER
Clock
tCYC
tCH
tCL
Description
Min.
Max.
Min.
Max.
Unit
ms
VDD(Typical) to the first Access[16]
1
1
1
Clock Cycle Time
Clock HIGH
7.5
3.0
3.0
8.5
3.2
3.2
10
4.0
4.0
ns
ns
ns
Clock LOW
Output Times
tCDV
tDOH
tCLZ
tCHZ
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[17, 18, 19]
6.5
7.5
8.5
ns
ns
ns
ns
ns
ns
2.0
0
2.0
0
2.0
0
Clock to High-Z[17, 18, 19]
3.5
3.5
3.5
3.5
3.5
3.5
tOEV
tOELZ
OE LOW to Output Valid
OE LOW to Output Low-Z[17, 18, 19]
0
0
0
Note:
15. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05541 Rev. *A
Page 20 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Switching Characteristics Over the Operating Range[20, 21]
133 MHz
117 MHz
100 MHz
Parameter
tOEHZ
Description
Min.
Max.
3.5
Min.
Max.
3.5
Min.
Max.
3.5
Unit
ns
OE HIGH to Output High-Z[17, 18, 19]
Set-up Times
tAS
tADS
tADVS
tWES
Address Set-up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ADSP, ADSC Set-up Before CLK Rise
ADV Set-up Before CLK Rise
Set-up Before CLK
GW, BWE, BW[A:D]
Rise
tDS
tCES
Data Input Set-up Before CLK Rise
Chip Enable Set-up
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
Hold Times
tAH
tADH
tWEH
tADVH
tDH
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ADSP, ADSC Hold After CLK Rise
,
,
GW BWE BW[A:D] Hold After CLK Rise
ADV Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tCEH
Notes:
16. This part has a voltage regulator internally; t
can be initiated.
is the time that the power needs to be supplied above V ( minimum) initially, before a read or write operation
DD
POWER
17. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
18. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
19. This parameter is sampled and not 100% tested.
20. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05541 Rev. *A
Page 21 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Timing Diagrams
Read Cycle Timing[22]
t
CYC
t
CLK
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
X
Deselect Cycle
t
t
CES
CEH
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note:
22. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05541 Rev. *A
Page 22 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Timing Diagrams (continued)
Write Cycle Timing[22, 23]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW
X
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
DON’T CARE
UNDEFINED
Notes:
23.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document #: 38-05541 Rev. *A
Page 23 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Timing Diagrams (continued)
Read/Write Cycle Timing[22, 24, 25]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
Back-to-Back READs
Single WRITE
BURST READ
WRITEs
DON’T CARE
UNDEFINED
Notes:
24.
25.
.
The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by
GW is HIGH.
ADSP or ADSC
26. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
27. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05541 Rev. *A
Page 24 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Timing Diagrams (continued)
ZZ Mode Timing[26, 27]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Speed
Package
Operating
Range
Commercial
(MHz)
Ordering Code
CY7C1361C-133AXC
CY7C1363C-133AXC
CY7C1361C-133AXI
CY7C1363C-133AXI
CY7C1361C-133AJXC
CY7C1363C-133AJXC
CY7C1361C-133AJXI
CY7C1363C-133AJXI
CY7C1361C-133BGC
CY7C1363C-133BGC
CY7C1361C-133BGI
CY7C1363C-133BGI
CY7C1361C-133BZC
CY7C1363C-133BZC
CY7C1361C-133BZI
CY7C1363C-133BZI
Name
Part and Package Type
133
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
3 Chip Enables
A101
A101
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
3 Chip Enables
Industrial
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
2 Chip Enables
Commercial
Industrial
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
2 Chip Enables
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and Commercial
JTAG
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
Industrial
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial
3 Chip Enables and JTAG
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
3 Chip Enables and JTAG
Industrial
Document #: 38-05541 Rev. *A
Page 25 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Ordering Information (continued)
Speed
Package
Operating
Range
Commercial
(MHz)
Ordering Code
CY7C1361C-117AXC
CY7C1363C-117AXC
CY7C1361C-117AXI
CY7C1363C-117AXI
CY7C1361C-117AJXC
CY7C1363C-117AJXC
CY7C1361C-117AJXI
CY7C1363C-117AJXI
CY7C1361C-117BGC
CY7C1363C-117BGC
CY7C1361C-117BGI
CY7C1363C-117BGI
CY7C1361C-117BZC
CY7C1363C-117BZC
CY7C1361C-117BZI
CY7C1363C-117BZI
CY7C1361C-100AXC
CY7C1363C-100AXC
CY7C1361C-100AXI
CY7C1363C-100AXI
CY7C1361C-100AJXC
CY7C1363C-100AJXC
CY7C1361C-100AJXI
CY7C1363C-100AJXI
CY7C1361C-100BGC
CY7C1363C-100BGC
CY7C1361C-100BGI
CY7C1363C-100BGI
CY7C1361C-100BZC
CY7C1363C-100BGC
CY7C1361C-100BZI
CY7C1363C-100BGI
Name
Part and Package Type
117
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
A101
A101
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Industrial
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
2 Chip Enables
Commercial
Industrial
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
2 Chip Enables
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and Commercial
JTAG
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
Industrial
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Commercial
3 Chip Enables and JTAG
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Industrial
Commercial
Industrial
100
A101
A101
A101
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
2 Chip Enables
Commercial
Industrial
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
2 Chip Enables
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and Commercial
JTAG
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
Industrial
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Commercial
3 Chip Enables and JTAG
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Industrial
Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.Lead-free BG and BZ packages (Ordering
code:BGX,BZX) will be available in 2005.
Document #: 38-05541 Rev. *A
Page 26 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
ꢁ6.00 0.20
ꢁ4.00 0.ꢁ0
ꢁ.40 0.05
ꢁ00
ꢀꢁ
ꢀ0
ꢁ
0.30 0.0ꢀ
0.65
TYP.
ꢁ2° ꢁ°
SEE DETAIL
A
(ꢀX)
30
5ꢁ
3ꢁ
50
0.20 MAX.
ꢁ.60 MAX.
R 0.0ꢀ MIN.
0.20 MAX.
0° MIN.
STAND-OFF
0.05 MIN.
0.ꢁ5 MAX.
SEATING PLANE
0.25
GAUGE PLANE
R 0.0ꢀ MIN.
0.20 MAX.
0°-7°
0.60 0.ꢁ5
0.20 MIN.
ꢁ.00 REF.
51-85050-*A
DETAIL
A
Document #: 38-05541 Rev. *A
Page 27 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05541 Rev. *A
Page 28 of 30
CY7C1361C
CY7C1363C
PRELIMINARY
Package Diagrams (continued)
165 FBGA 13 x 15 x 1.40 mm BB165D
51-85180-**
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05541 Rev. *A
Page 29 of 30
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1361C
CY7C1363C
PRELIMINARY
Document History Page
Document Title: CY7C1361C/CY7C1363C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM (Preliminary)
Document Number: 38-05541
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
241690
See ECN
RKF
New data sheet
*A
278969
See ECN
RKF
Changed Boundary Scan order to match the B rev of these devices.
Document #: 38-05541 Rev. *A
Page 30 of 30
相关型号：
CY7C1361C-133AXIT
Standard SRAM, 256KX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100
CYPRESS
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