CY7C1362B-250BZC_技术文档

CY7C1360B

CY7C1362B

PRELIMINARY

256K x 36/512K x 18 Pipelined SRAM

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

Maximum access delay from the clock rise is 2.6 ns (250 MHz

Features

• Supports bus operation up to 250 MHz

— Available speed grades are 250, 200, and 166 MHz

device).

• Fully registered inputs and outputs for pipelined

operation

• Single 3.3V power supply

• Supports 3.3V and 2.5V I/Os

• Fast clock-to-output times

— 2.6ns (for 250-MHz device)

The CY7C1360B and CY7C1362B support either the inter-

leaved burst sequence used by the Intel Pentium processor or

a linear burst sequence used by processors such as the

PowerPC™. The burst sequence is selected through the

MODE pin (Pin 31 and ball R3 for the TQFP and BGA

packages, respectively.) Accesses can be initiated by

asserting either the Processor Address Strobe (ADSP) or the

Controller Address Strobe (ADSC) at clock rise. Address

advancement through the burst sequence is controlled by the

ADV input. A 2-bit on-chip wraparound burst counter captures

the first address in a burst sequence and automatically incre-

ments the address for the rest of the burst access.

— 3.0ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

• Available as a 100-pin TQFP, 119-Ball BGA, 165-Ball

fBGA

Byte write operations are qualified with the Byte Write Select

(BW_a,b,c,dfor 1360B and BW_a,bfor 1362B) inputs. A Global

Write Enable (GW) overrides all byte write inputs and writes

data to all four bytes. All writes are conducted with on-chip

synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to provide

proper data during depth expansion, OE is masked during the

first clock of a read cycle when emerging from a deselected

state.

• TQFP Available with 3-Chip Enable and 2-Chip Enable

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

The CY7C1360B and CY7C1362B are 3.3V, 256K x 36 and

512K x 18 synchronous-pipelined cache SRAM, respectively.

D

CLK

Logic Block Diagram

Data-In REG.

CE

Q

ADV

A

x

GW

CE

CONTROL

and WRITE

LOGIC

256Kx36/

512Kx18

1

1360B

1362B

CE

2

DQ

DQP

A

x

A

MEMORY

ARRAY

[17:0]

[18:0]

X

3

BWE

BW

DQ

a,b

a,b,c,d

DQ

X

x

DQP

BW

DQP

a,b,c,d

a,b

X

MODE

ADSP

ADSC

BW

a,b,c,d

a,b

X

ZZ

OE

Selection Table

CY7C1360B-250

CY7C1362B-250

CY7C1360B-200

CY7C1362B-200

CY7C1360B-166

CY7C1362B-166

Unit

ns

Maximum Access Time

2.6

250

30

3.0

220

30

3.5

180

30

Maximum Operating Current

Commercial

mA

Maximum CMOS Standby Current Commercial

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05291 Rev. *A

Revised August 15, 2002

CY7C1360B

CY7C1362B

PRELIMINARY

Pin Configurations

100-pin TQFP Pinout (3 Chip Enables)

DQPc

1

DQPb

DQb

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

NC

A

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQc

2

NC

V

NC

DQPa

DQa

V

DQa

V

NC

V

ZZ

DQa

V

DQc

3

4

5

6

7

8

9

V

DDQ

V

DDQ

V

SSQ

V

SSQ

NC

DQb

SSQ

DQc

DQb

9

V

SSQ

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SSQ

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

SSQ

V

DDQ

V

DDQ

DQc

NC

DQb

NC

V

SS

V

DD

NC

V

DD

CY7C1362B

(512K x 18)

CY7C1360B

(256K X 36)

V

NC

DD

V

SS

ZZ

DQa

V

SS

DQd

DQb

V

DDQ

V

DDQ

V

DQd

SSQ

V

SSQ

DQb

DQPb

NC

V

SSQ

DQa

NC

V

SSQ

V

SSQ

V

DDQ

V

DDQ

V

DDQ

DQd

DQPd

DQa

DQPa

NC

Document #: 38-05291 Rev. *A

Page 2 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Pin Configurations (continued)

100-pin TQFP (2 Chip Enables)

DQPc

1

DQPb

DQb

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

NC

A

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQc

2

NC

V

NC

DQPa

DQa

V

DQa

V

NC

V

ZZ

DQa

V

DQc

3

4

5

6

7

8

9

V

DDQ

V

DDQ

V

SSQ

V

SSQ

NC

DQb

SSQ

DQc

DQb

9

V

SSQ

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SSQ

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

SSQ

V

DDQ

V

DDQ

DQc

NC

DQb

NC

V

SS

V

DD

NC

V

DD

CY7C1362B

(512K x 18)

CY7C1360B

(256K X 36)

V

NC

DD

V

SS

ZZ

DQa

V

SS

DQd

DQb

V

DDQ

V

DDQ

V

DQd

SSQ

V

SSQ

DQb

DQPb

NC

V

SSQ

DQa

NC

V

SSQ

V

SSQ

V

DDQ

V

DDQ

V

DDQ

DQd

DQPd

DQa

DQPa

NC

Document #: 38-05291 Rev. *A

Page 3 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Pin Configurations (continued)

119-ball BGA (2 Chip Enables with JTAG)

CY7C1360B (256K x 36)

1

2

3

4

5

6

7

A

V_DDQ

A

ADSP

A

V_DDQ

B

C

D

E

F

NC

CE₂

A

ADSC

V_DD

NC

A

NC

A

DQ_c

V_DDQ

DQP_c

DQ_c

V_SS

DQP_b

DQ_b

V_DDQ

CE₁

OE

G

H

J

DQ_c

V_DD

DQ_d

BW_c

V_SS

NC

ADV

GW

V_DD

CLK

BW_b

V_SS

NC

DQ_b

V_DD

DQ_a

DQ_b

V_DDQ

DQ_a

V_DDQ

DQ_d

K

V_SS

L

M

N

DQ_d

V_DDQ

DQ_d

BW_d

V_SS

NC

BWE

A1

BW_a

V_SS

DQ_a

V_DDQ

DQ_a

P

R

DQ_d

NC

DQP_d

A

V_SS

A0

V_SS

NC

DQP_a

A

DQ_a

NC

MODE

V_DD

T

NC

A

NC

ZZ

U

V_DDQ

TMS

TDI

TCK

TDO

V_DDQ

CY7C1362B (512K x 18)

2

A

1

3

A

4

5

A

6

A

7

A

B

C

D

E

F

V_DDQ

NC

ADSP

ADSC

V_DD

NC

V_DDQ

NC

CE₂

A

NC

A

NC

DQ_b

NC

DQ_b

NC

V_SS

DQP_a

NC

DQ_a

NC

CE₁

OE

DQ_a

V_DDQ

G

H

J

NC

DQ_b

V_DDQ

DQ_b

NC

V_DD

BW_b

V_SS

NC

ADV

GW

V_DD

V_SS

NC

DQ_d

V_DD

DQ_a

NC

V_DDQ

K

NC

DQ_b

V_SS

CLK

V_SS

NC

DQ_a

L

M

N

P

DQ_b

V_DDQ

DQ_b

NC

DQ_b

NC

V_SS

NC

BWE

A1

BW_a

V_SS

DQ_a

NC

V_DDQ

NC

DQ_a

NC

DQP_b

A0

DQ_a

R

T

NC

A

MODE

A

Vdd

NC

A

NC

ZZ

U

V_DDQ

TMS

TDI

TCK

TDO

NC

V_DDQ

Document #: 38-05291 Rev. *A

Page 4 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Pin Configurations (continued)

165-ball TQFP fBGA (3 Chip Enable with JTAG)

CY7C1360B (256K x 36)

1

2

A

3

CE₁

4

BW_c

5

BW_b

6

CE₃

7

8

9

ADV

10

A

11

NC

E(288)

BWE

GW

V_SS

ADSC

A

B

C

D

NC

A

CE2

V_DDQ

BW_d

V_SS

V_DD

BW_a

V_SS

CLK

V_SS

OE

V_SS

V_DD

ADSP

V_DDQ

A

E(144)

DQP_b

DQ_b

DQP_c

DQ_c

NC

DQ_c

NC

DQ_b

DQ_c

NC

DQ_c

V_SS

DQ_d

V_DDQ

NC

V_DD

V_SS

V_DD

V_DDQ

NC

DQ_b

NC

DQ_b

ZZ

E

F

G

H

J

DQ_d

V_DDQ

DQ_a

K

L

DQ_d

DQP_d

NC

DQ_d

NC

V_DDQ

A

V_DD

V_SS

NC

V_SS

E(18)

A1

V_SS

V_DD

V_SS

V_DDQ

A

DQ_a

NC

A

DQ_a

DQP_a

A

M

N

P

E(72)

TDI

TDO

A

A0

MODE

E(36)

A

TMS

TCK

A

R

CY7C1362B (512K x 18)

1

E(288)

NC

2

A

3

CE₁

4

BW_b

5

NC

6

CE₃

7

8

ADSC

OE

9

10

A

11

A

BWE

GW

V_SS

ADV

ADSP

V_DDQ

A

B

C

D

A

CE2

V_DDQ

NC

BW_a

V_SS

CLK

V_SS

A

E(144)

DQP_a

DQ_a

NC

DQ_b

V_SS

V_DD

V_SS

NC

V_DD

NC

DQ_b

V_SS

NC

V_DDQ

NC

V_DD

V_SS

V_DD

V_DDQ

NC

E

F

NC

V_SS

DQ_a

ZZ

NC

G

H

J

NC

DQ_b

V_DDQ

DQ_a

NC

K

L

NC

DQ_b

DQP_b

NC

V_DDQ

A

V_DD

V_SS

A

V_SS

NC

V_SS

E(18)

A1

V_SS

V_DD

V_SS

A

V_DDQ

A

DQ_a

NC

A

NC

A

M

N

P

E(72)

TDI

TDO

MODE

E(36)

A

TMS

A0

TCK

A

R

Document #: 38-05291 Rev. *A

Page 5 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Pin Definitions

Pin Name

I/O

Pin Description

A0

A1

A

Input-

Synchronous

Address Inputs used to select one of the address locations. Sampled at the rising edge of

the CLK if ADSP or ADSC is active LOW, and CE₁, CE₂, and CE₃are sampled active. A_[1:0]

feed the two-bit counter.

BW_a

BW_b

BW_c

BW_d

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.

Sampled on the rising edge of CLK.

GW

Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a

global write is conducted (ALL bytes are written, regardless of the values onBW_a,b,c,dandBWE).

BWE

CLK

CE₁

CE₂

CE₃

Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must

be asserted LOW to conduct a byte write.

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the

burst counter when ADV is asserted LOW, during a burst operation.

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE₂and CE₃to select/deselect the device. ADSP is ignored if CE₁is HIGH.

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction

with CE₁and CE₃to select/deselect the device.

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE₁and CE₃to select/deselect the device. This pin is not available on the 2CE TQFP

package.

OE

Input-

Output Enable, asynchronous input, activeLOW. Controls the direction of the I/O pins. When

Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and

act as input data pins. OE is masked during the first clock of a read cycle when emerging from

a deselected state.

ADV

Input-

Synchronous

Advance Input signal, active LOW, sampled on the rising edge of CLK. When asserted, it

automatically increments the address in a burst cycle.

ADSP

Input-

Synchronous

Address Strobe from Processor, active LOW, sampled on the rising edge of CLK. When

asserted LOW, A is captured in the address registers. A_[1:0]are also loaded into the burst

counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ADSP is ignored

when CE₁is deasserted HIGH.

ADSC

MODE

Input-

Synchronous

Address Strobe from Controller, active LOW, sampled on the rising edge of CLK. When

asserted LOW, A_[x:0]is captured in the address registers. A_[1:0]are also loaded into the burst

counter. When ADSP and ADSC are both asserted, only ADSP is recognized.

Input-

Static

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V_DDor

left floating selects interleaved burst sequence. This is a strap pin and should remain static

during device operation.

DQ_a,DQP_a

DQ_b,DQP_b

DQ_c,DQP_c

DQ_d,DQP_d

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by A during the previous clock rise of the read cycle. The direction of the pins is

controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ_x

and DQP_xare placed in a three-state condition.

ZZ

Input-

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”

Asynchronous condition with data integrity preserved. During normal operation, this pin can be connected to

Vss or left floating.

V_DD

Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply.

V_SS

Ground

Ground for the core of the device. Should be connected to ground of the system.

V_DDQ

I/O Power

Supply

Power supply for the I/O circuitry. Should be connected to a 3.3V power supply. See Errata

on page 34 for 2.5V V_DDQoperation.

V_SSQ

TDO

I/O Ground

Ground for the I/O circuitry. Should be connected to ground of the system.

JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG

Synchronous

feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP

packages.

Document #: 38-05291 Rev. *A

Page 6 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Pin Definitions (continued)

Pin Name

I/O

Pin Description

TDI

JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is

Synchronous

not being utilized, this pin can be disconnected or connected to V_CC. This pin is not available

on TQFP packages.

TMS

TCK

NC

Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.

Synchronous

If JTAG the feature is not being utilized, this pin can be disconnected or connected to V_SS. This

pin is not available on TQFP packages.

JTAG-Clock

Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin can be

disconnected, connected to V_SSor connected to V_DD. This pin is not available on TQFP

packages.

–

No Connects.

E(18,36,72,

144, 288)

These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M

and 288M densities.

from a deselected state to a selected state; its outputs are

always three-stated during the first cycle of the access. After

the first cycle of the access, the outputs are controlled by the

OE signal. Consecutive single read cycles are supported.

Once the SRAM is deselected at clock rise by the chip select

and either ADSP or ADSC signals, its output will three-state

immediately.

Introduction

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

Maximum access delay from the clock rise (t_CO) is 2.6 ns (250

MHz device).

Single Write Accesses Initiated by ADSP

The CY7C1360B and CY7C1362B support secondary cache

in systems utilizing either a linear or interleaved burst

sequence. The interleaved burst order supports Pentium and

i486 processors. The linear burst sequence is suited for

processors that utilize a linear burst sequence. The burst order

is user selectable, and is determined by sampling the MODE

input. Accesses can be initiated with either the Processor

Address Strobe (ADSP) or the Controller Address Strobe

(ADSC). Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2) CE₁, CE₂, CE₃are all asserted active. The address

presented is loaded into the address register and the address

advancement logic while being delivered to the RAM core. The

write signals (GW, BWE, and BW_x) and ADV inputs are

ignored during this first cycle.

ADSP triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQ_xinputs is written into the corre-

sponding address location in the RAM core. If GW is HIGH,

then the write operation is controlled by BWE and BWx

signals. The CY7C1360B and 1362B provide byte write

capability that is described in the Write Cycle Description table.

Asserting the Byte Write Enable input (BWE) with the selected

Byte Write ( BW_a,b,c,dfor CY7C1360B and BW_a,bfor

CY7C1362B input will selectively write to only the desired

bytes. Bytes not selected during a byte write operation will

remain unaltered. A synchronous self-timed write mechanism

has been provided to simplify the write operations.

Byte write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW_a,b,c,dfor CY7C1360B and

BW_a,bfor CY7C1362B) inputs. A Global Write Enable (GW)

overrides all byte write inputs and writes data to all four bytes.

All writes are simplified with on-chip synchronous self-timed

write circuitry.

Three synchronous Chip Selects (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. ADSP is ignored if

CE₁is HIGH.

Because the CY7C1360B and CY7C1362B are common I/O

devices, the Output Enable (OE) must be deasserted HIGH

before presenting data to the DQ inputs. Doing so will

three-state the output drivers. As a safety precaution, DQ are

automatically three-stated whenever a write cycle is detected,

regardless of the state of OE.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,

(2) CE₁, CE₂, CE₃are all asserted active, and (3) the write

signals (GW, BWE) are all deasserted HIGH. ADSP is ignored

if CE₁is HIGH. The address presented to the address inputs

is stored into the address advancement logic and the Address

Register while being presented to the memory core. The corre-

sponding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next clock the data

is allowed to propagate through the output register and onto

the data bus within 2.6 ns (250-MHz device) if OE is active

LOW. The only exception occurs when the SRAM is emerging

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deasserted HIGH, (3) CE₁, CE₂, CE₃are all asserted active,

and (4) the appropriate combination of the write inputs (GW,

BWE, and BW_x) are asserted active to conduct a write to the

desired byte(s). ADSC triggered write accesses require a

single clock cycle to complete. The address presented to

A_[17:0]is loaded into the address register and the address

advancement logic while being delivered to the RAM core. The

Document #: 38-05291 Rev. *A

Page 7 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

ADV input is ignored during this cycle. If a global write is

conducted, the data presented to the DQ_[x:0]is written into the

corresponding address location in the RAM core. If a byte write

is conducted, only the selected bytes are written. Bytes not

selected during a byte write operation will remain unaltered. A

synchronous self-timed write mechanism has been provided

to simplify the write operations.

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CE₁, CE₂, CE₃, ADSP, and ADSC must

remain inactive for the duration of t_ZZRECafter the ZZ input

returns LOW.

Because the CY7C1360B and CY7C1362B are common I/O

devices, the Output Enable (OE) must be deasserted HIGH

before presenting data to the DQ_[x:0]inputs. Doing so will

three-state the output drivers. As a safety precaution, DQ_[x:0]

are automatically three-stated whenever a write cycle is

detected, regardless of the state of OE.

Interleaved Burst Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

A_[1:0]]

00

A_[1:0]

01

A_[1:0]

10

A_[1:0]

11

Burst Sequences

01

00

11

10

The CY7C1360B and CY7C1362B provide

a

two-bit

10

11

00

01

wraparound counter, fed by A_[1:0], that implements either an

interleaved or linear burst sequence. The interleaved burst

sequence is designed specifically to support Intel Pentium

applications. The linear burst sequence is designed to support

processors that follow a linear burst sequence. The burst

sequence is user selectable through the MODE input.

11

10

01

00

Linear Burst Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both read and write burst operations are supported.

A_[1:0]

00

A_[1:0]

01

A_[1:0]

10

A_[1:0]

11

01

10

11

00

Sleep Mode

10

11

00

01

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

11

00

01

10

ZZ Mode Electrical Characteristics

Parameter

Description

Snooze mode standby current

Device operation to ZZ

ZZ recovery time

Test Conditions

Min. Max. Unit

35 mA

I_DDZZ

t_ZZS

ZZ > V_DD− 0.2V

ZZ < 0.2V

2t_CYCns

t_ZZREC

[1, 2, 3]

Cycle Description

Next Cycle

Unselected

Add. Used

None

ZZ

L

CE₃

X

1

CE₂

X

0

CE₁

1

ADSP

ADSC

ADV

X

OE

X

1

DQ

Hi-Z

Write

X

0

1

0

1

X

1

0

X

0

X

0

1

Unselected

None

0

X

Hi-Z

DQ

X

Unselected

None

X

1

0

X

Unselected

None

X

0

X

Unselected

None

X

0

X

Begin Read

Continue Read

External

0

X

0

1

0

X

Read

X

1

0

1

Hi-Z

DQ

0

Suspend Read

Current

X

1

Hi-Z

Notes:

1. X = ”Don’t care,” 1 = HIGH, 0 = LOW.

2. Write is defined by BWE, BW_x, and GW. See Write Cycle Description table.

3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

Document #: 38-05291 Rev. *A

Page 8 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Cycle Description (continued)^{[1, 2, 3]}

Next Cycle

Suspend Read

Begin Write

Add. Used

Current

External

L

CE₃

X

CE₂

X

CE₁

X

1

ADSP

ADSC

ADV

1

OE

0

DQ

Write

Read

Write

X

1

X

1

0

1

X

L

X

1

Hi-Z

DQ

L

X

1

0

L

X

1

X

Hi-Z

Begin Write

L

X

1

Begin Write

L

0

1

0

X

0

Continue Write

Suspend Write

ZZ “sleep”

L

X

1

X

1

0

Current

None

L

X

1

L

X

1

H

X

Write Cycle Description^[1]

Function (1360)

Read

GW

BWE

BW_d

BW_c

X

1

BW_b

BW_a

1

0

1

0

X

1

0

X

1

0

1

0

1

0

1

0

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

Read

Write Byte 0 – DQ_a

Write Byte 1 – DQ_b

Write Bytes 1, 0

Write Byte 2 – DQ_c

Write Bytes 2, 0

Write Bytes 2, 1

Write Bytes 2, 1, 0

Write Byte 3 – DQ_d

Write Bytes 3, 0

Write Bytes 3, 1

Write Bytes 3, 1, 0

Write Bytes 3, 2

Write Bytes 3, 2, 0

Write Bytes 3, 2, 1

Write All Bytes

1

0

1

0

Write All Bytes

X

Function (1362)

Read

GW

1

BWE

BW_b

BW_a

1

0

X

1

0

X

1

0

1

0

X

Read

1

Write Byte 0 – DQ_[7:0]and DQP₀

Write Byte 1 – DQ_[15:8]and DQP₁

Write All Bytes

1

Write All Bytes

0

Document #: 38-05291 Rev. *A

Page 9 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

circuitry. Only one register can be selected at a time through

the instruction registers. Data is serially loaded into the TDI pin

on the rising edge of TCK. Data is output on the TDO pin on

the falling edge of TCK.

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1360B and CY7C1362B incorporate a serial

boundary scan Test Access Port (TAP) in the FBGA package

only. This port operates in accordance with IEEE Standard

1149.1-1900, but does not have the set of functions required

for full 1149.1 compliance. These functions from the IEEE

specification are excluded because their inclusion places an

added delay in the critical speed path of the SRAM. Note that

the TAP controller functions in a manner that does not conflict

with the operation of other devices using 1149.1 fully compliant

TAPs. The TAP operates using JEDEC standard for 3.3V and

2.5V I/O logic levels.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

register. This register is loaded when it is placed between the

TDI and TDO pins as shown in the TAP Controller Block

Diagram. Upon power-up, the instruction register is loaded

with the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.

When the TAP controller is in the CaptureIR state, the two least

significant bits are loaded with a binary "01" pattern to allow for

fault isolation of the board level serial test path.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(V_SS) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to V_DDthrough a pull-up resistor. TDO should

be left unconnected. Upon power-up, the device will come up

in a reset state which will not interfere with the operation of the

device.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain states. The bypass

register is a single-bit register that can be placed between TDI

and TDO pins. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

(V_SS) when the BYPASS instruction is executed.

Test Access Port –Test Clock

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

Boundary Scan Register

The boundary scan register is connected to all the input and

output pins on the SRAM. Several no connect (NC) pins are

also included in the scan register to reserve pins for higher

density devices. The x36 configuration has a xx-bit-long

register, and the x18 configuration has a yy-bit-long register.

Test Mode Select

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this pin unconnected if the TAP is not used. The pin is

pulled up internally, resulting in a logic HIGH level.

The boundary scan register is loaded with the contents of the

RAM Input and Output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and

TDO pins when the controller is moved to the Shift-DR state.

The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-

tions can be used to capture the contents of the Input and

Output ring.

Test Data-In (TDI)

The TDI pin is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. For

information on loading the instruction register, see the TAP

Controller State Diagram. TDI is internally pulled up and can

be unconnected if the TAP is unused in an application. TDI is

connected to the Most Significant Bit (MSB) on any register.

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI, and the LSB is connected to TDO.

Identification (ID) Register

Test Data Out (TDO)

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

The TDO output pin is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine (see TAP Controller State

Diagram). The output changes on the falling edge of TCK.

TDO is connected to the Least Significant Bit (LSB) of any

register.

Performing a TAP Reset

TAP Instruction Set

A Reset is performed by forcing TMS HIGH (V_DD) for five rising

edges of TCK. This RESET does not affect the operation of

the SRAM and may be performed while the SRAM is

operating. At power-up, the TAP is reset internally to ensure

that TDO comes up in a high-Z state.

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in the

Instruction Code table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

The TAP controller used in this SRAM is not fully compliant to

the 1149.1 convention because some of the mandatory 1149.1

instructions are not fully implemented. The TAP controller

cannot be used to load address, data or control signals into the

TAP Registers

Registers are connected between the TDI and TDO pins and

allow data to be scanned into and out of the SRAM test

Document #: 38-05291 Rev. *A

Page 10 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

SRAM and cannot preload the Input or Output buffers. The

SRAM does not implement the 1149.1 commands EXTEST or

INTEST or the PRELOAD portion of SAMPLE/PRELOAD;

rather it performs a capture of the Inputs and Output ring when

these instructions are executed.

When the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 10 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is

possible that during the Capture-DR state, an input or output

will undergo a transition. The TAP may then try to capture a

signal while in transition (metastable state). This will not harm

the device, but there is no guarantee as to the value that will

be captured. Repeatable results may not be possible.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO pins.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be

executed whenever the instruction register is loaded with all

0s. EXTEST is not implemented in the TAP controller, and

therefore this device is not compliant to the 1149.1 standard.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller’s capture set-up plus

hold times (t_CSand t_CH). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE/PRELOAD instruction. If this

is an issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK# captured in the

boundary scan register.

The TAP controller does recognize an all-0 instruction. When

an EXTEST instruction is loaded into the instruction register,

the SRAM responds as if a SAMPLE/PRELOAD instruction

has been loaded. There is one difference between the two

instructions. Unlike the SAMPLE/PRELOAD instruction,

EXTEST places the SRAM outputs in a High-Z state.

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the

boundary scan register between the TDI and TDO pins.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO pins and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state. The IDCODE instruction

is loaded into the instruction register upon power-up or

whenever the TAP controller is given a test logic reset state.

Note that since the PRELOAD part of the command is not

implemented, putting the TAP into the Update to the

Update-DR state while performing a SAMPLE/PRELOAD

instruction will have the same effect as the Pause-DR

command.

Bypass

When the BYPASS instruction is loaded in the instruction

register and the TAP is placed in a Shift-DR state, the bypass

register is placed between the TDI and TDO pins. The

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO pins when the TAP

controller is in a Shift-DR state. It also places all SRAM outputs

into a High-Z state.

SAMPLE/PRELOAD

Reserved

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The

PRELOAD portion of this instruction is not implemented, so

the TAP controller is not fully 1149.1-compliant.

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

Document #: 38-05291 Rev. *A

Page 11 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

TAP Controller State Diagram ^[4]

TEST-LOGIC

1

RESET

1

TEST-LOGIC/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

0

1

CAPTURE-DR

0

SHIFT-DR

0

SHIFT-IR

0

1

EXIT1-DR

0

1

EXIT1-IR

0

1

0

PAUSE-DR

1

PAUSE-IR

1

0

EXIT2-DR

1

EXIT2-IR

1

UPDATE-DR

UPDATE-IR

1

0

Note:

4. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document #: 38-05291 Rev. *A

Page 12 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

TAP Controller Block Diagram

0

Bypass Register

Selection

Circuitry

Selection

Circuitry

2

1

0

TDO

Instruction Register

29

Identification Register

31 30

.

2

1

0

TDI

.

x

.

2

Boundary Scan Register

TCK

TMS

TAP Controller

TAP Electrical Characteristics Over the Operating Range^{[5, 6]}

Parameter

Description

Test Conditions

I_OH= –2.0 mA, V_DDQ= 3.3V

I_OH= –2.0 mA, V_DDQ= 2.5V

I_OH= –100 µA, V_DDQ= 3.3V

I_OH= –100 µA, V_DDQ= 2.5V

I_OL= 2.0 mA

Min.

Max.

Unit

V

V_OH1

Output HIGH Voltage

2.0

1.7

2.0

V

V_OH2

Output HIGH Voltage

V

V_OL1

V_OL2

V_IH

Output LOW Voltage

Input HIGH Voltage

0.7

0.2

V

I_OL= 100 µA

V

V_DDQ= 3.3V

2.0

1.7

V_DD+ 0.3

V

V_DDQ= 3.3V

V

V_IL

I_X

Input LOW Voltage

Input Load Current

–0.3

–30

0.7

30

V

GND ≤ V_I≤ V_DDQ

µA

I_X

Input Load Current

TMS,TCK, and TDI

5. All Voltage referenced to Ground.

6. Overshoot: V_IH(AC) < V_DD+ 1.5V for t < t_TCYC/2; undershoot: V_IL(AC) < 0.5V for t < t_TCYC/2; power-up: V_IH< 3.3V and V_DD< 3.3V and V_DDQ< 1.7V for t < 200 ms.

Document #: 38-05291 Rev. *A

Page 13 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

TAP AC Switching Characteristics Over the Operating Range^{[7, 8]}

Parameters

t_TCYC

Description

Min.

Max.

Unit

ns

TCK Clock Cycle Time

TCK Clock Frequency

TCK Clock HIGH

100

t_TF

10

MHz

ns

t_TH

40

t_TL

TCK Clock LOW

ns

Set-up Times

t_TMSS

TMS Set-up to TCK Clock Rise

TDI Set-up to TCK Clock Rise

Capture Set-up to TCK Rise

10

ns

t_TDIS

t_CS

Hold Times

t_TMSH

TMS Hold after TCK Clock Rise

TDI Hold after Clock Rise

10

ns

t_TDIH

t_CH

Capture Hold after Clock Rise

Output Times

t_TDOV

TCK Clock LOW to TDO Valid

TCK Clock LOW to TDO Invalid

20

ns

t_TDOX

0

Notes:

7.

t_CSand t_CHrefer to the set-up and hold time requirements of latching data from the boundary scan register.

8. Test conditions are specified using the load in TAP AC test conditions. t_R/t_F= 1 ns.

Document #: 38-05291 Rev. *A

Page 14 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

TAP Timing and Test Conditions

1.5V for 3.3V V

1.25V for 2.5V V

DDQ

ALL INPUT PULSES

V

= 3.0V/2.5V

0V

DDQ

1.5V for 3.0V V

1.25V for 2.5V V

DDQ

50Ω

TDO

Z = 50Ω

0

C = 20 pF

L

(a)

t_TL

t_TH

GND

Test Clock

TCK

t_TCYC

t_TMSS

t_TMSH

Test Mode Select

TMS

t_TDIS

t_TDIH

Test Data-In

TDI

Test Data-Out

TDO

t_TDOV

t_TDOX

Identification Register Definitions

Instruction Field

Revision Number (31:29)

Device Depth (28:12)

CY7C1360B

0000

CY7C1362

Description

000

Reserved for version number.

01010000000100110

00000110100

1

01010000000010110 Defines the type of SRAM.

Cypress JEDEC ID (11:1)

ID Register Presence (0)

00000110100

1

Allows unique identification of SRAM vendor.

Indicate the presence of an ID register.

Scan Register Sizes

Register Name

Bit Size (x36)

Bit Size (x18)

Instruction

Bypass

3

1

3

1

ID

32

70

32

51

Boundary Scan

Document #: 38-05291 Rev. *A

Page 15 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Identification Codes

Instruction

EXTEST

Code

Description

000

001

010

011

Captures the Input/Output ring contents. Places the boundary scan register between the TDI

and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.

IDCODE

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

SAMPLE Z

Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100

Captures the Input/Output ring contents. Places the boundary scan register between TDI and

TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload

function and is therefore not 1149.1-compliant.

RESERVED

BYPASS

101

110

111

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operation.

Boundary Scan Exit Order (x36)

Boundary Scan Exit Order (x36) (continued)

Bit #

1

Signal Name

TBD

119-Ball ID

TBD

165-Ball ID

TBD

Bit #

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

Signal Name

TBD

119-Ball ID

TBD

165-Ball ID

TBD

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

Document #: 38-05291 Rev. *A

Page 16 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Boundary Scan Exit Order (x36) (continued)

Boundary Scan Exit Order (x18) (continued)

Bit #

59

60

61

62

63

64

65

66

67

68

69

70

Signal Name

TBD

119-Ball ID

TBD

165-Ball ID

TBD

Bit #

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

Signal Name

TBD

119- Ball ID

TBD

165- Ball ID

TBD

Boundary Scan Exit Order (x18)

Bit #

1

Signal Name

TBD

119- Ball ID

TBD

165- Ball ID

TBD

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

Document #: 38-05291 Rev. *A

Page 17 of 31

CY7C1360B

CY7C1362B

P R E L IM IN A R Y

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-up Current..................................................... >200 mA

Operating Range

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on VDD Relative to GND........−0.3V to +3.6V

DC to Outputs in High-Z State^[9]......... –0.5V to V_DDQ+ 0.5V

DC Input Voltage^[9].............................. –0.5V to V_DDQ+ 0.5V

Ambient

Range Temperature^[10]

V_DD/V_DDQ

Com’l

0°C to +70°C

3.135 – 3.6V /

3.135 – 3.6V or 2.375 – 2.9V

Electrical Characteristics Over the Operating Range

Parameter

V_DD

Description

Power Supply Voltage

I/O Supply Voltage

Test Conditions

Min.

3.135

2.375

2.4

Max.

3.6

Unit

V

V_DDQ

V_DDQ= 3.3V

V_DDQ= 2.5V (See Errata on page 34)

V_DD

2.9

V

V_OH

V_OL

V_IH

V_IL

I_X

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage^[9]

V_DD= Min., I_OH= −4.0 mA, V_DDQ= 3.3V

V_DD= Min., I_OH= −1.0 mA, V_DDQ= 2.5V

V_DD= Min., I_OH= 8.0 mA, V_DDQ= 3.3V

V_DD= Min., I_OH= 1.0 mA, V_DDQ= 2.5V

V_DDQ= 3.3V

V

2.0

V

0.4

V

2.0 V_DDQ+ 0.3V

1.7

V

V_DDQ= 2.5V (See Errata on page 34)

V_DDQ= 3.3V

V

–0.3

–5

0.8

0.7

5

V

V_DDQ= 2.5V (See Errata on page 34)

GND ≤ V_I≤ V_DDQ

V

Input Load Current

µA

except ZZ and MODE

I_OZ

I_ZZ

Output Leakage Current GND ≤ V_I≤ V_DDQ,Output Disabled

–5

5

µA

Input Current of MODE

and ZZ pins

–30

30

I_DD

V_DDOperating Supply V_DD= Max., I_OUT= 0 mA,

4.0-ns cycle,250 MHz

5.0-ns cycle, 200 MHz

6.0-ns cycle, 166 MHz

4.0-ns cycle,250 MHz

5.0-ns cycle, 200 MHz

6.0-ns cycle, 166 MHz

250

220

180

250

220

180

mA

Current

f = f_MAX= 1/t_CYC

I_SB1

Automatic CS

Power-down

Max. V_DD, Device Deselected,

V_IN≥ V_IHor V_IN≤ V_IL

Current—TTL Inputs

f = f_MAX= 1/t_CYC

I_SB2

Automatic CS

Power-down

Max. V_DD, Device Deselected, V_IN

≤ 0.3V or V_IN> V_DDQ– 0.3V, f = 0

30

mA

Current—CMOS Inputs

I_SB3

Automatic CS

Power-down

Current—CMOS Inputs f = f_MAX= 1/t_CYC

Max. V_DD, Device Deselected, or 4.0-ns cycle,250 MHz

250

220

180

40

mA

V_IN≤ 0.3V or V_IN> V_DDQ– 0.3V

5.0-ns cycle, 200 MHz

6.0-ns cycle, 166 MHz

I_SB4

Automatic CS

Power-down

Max. V_DD, Device Deselected,

_IN≥ V_IHor V_IN≤ V_IL, f = 0

V

Current—TTL Inputs

Notes:

9. Minimum voltage equals –2.0V for < 1 ns or -0.5V for pulse durations of less than 20 ns.

10. _Ais the temperature.

T

Document #: 38-05291 Rev. *A

Page 18 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Capacitance^[11]

Parameter

Description

Test Conditions

Max.

Unit

pF

C_IN

Input Capacitance

T_A= 25°C, f = 1 MHz,

_DD= 3.3V,

_DDQ= 2.5V

4

V

C_CLK

C_I/O

Clock Input Capacitance

Input/Output Capacitance

pF

AC Test Loads and Waveforms (See Errata on page 34 for 2.5V V_DDQoperation)^[12]

R = 1667/317Ω

2.5/3.3V

[11,12]

OUTPUT

ALL INPUT PULSES

90%

OUTPUT

2.5/3.0V

90%

10%

Z =50Ω

0

R = 50Ω

L

10%

1.5V for 3.0V V

DDQ

GND

5 pF

1.25V for 2.5V V

DDQ

R = 1538/351Ω

≤ 1.0ns

V = 1.25/1.5V

L

INCLUDING

JIG AND

SCOPE

(a)

Thermal Characteristics^[12]

(b)

(c)

Parameter

Description

Test Conditions

BGA Typ. fBGA Typ. TQFP Typ. Unit

Notes

Q_JA

Thermal Resistance

(Junction to Ambient)

Still Air, soldered on a 4.25 x

1.125 inch, 4-layer printed

circuit board

25

27

25

°C/W

14

Q_JC

Thermal Resistance

(Junction to Case)

6

9

°C/W

14

[14, 15, 16, 17]

Switching Characteristics Over the Operating Range (See Errata on page 34 for 2.5V V_DDQoperation)

-250

Max.

-200

Max.

-166

Max.

Parameter

Clock

t_CYC

Description

Min.

Unit

Clock Cycle Time

4.0

5

6

ns

MHz

ns

F_MAX

t_CH

Maximum Operating Frequency

Clock HIGH

250

200

166

1.7

2.0

2.4

t_CL

Clock LOW

ns

Output Times

t_CO

Data Output Valid After CLK Rise

2.6

3.0

3.5

ns

t_EOV

t_DOH

t_CHZ

t_CLZ

OE LOW to Output Valid^[16]

Data Output Hold After CLK Rise

Clock to High-Z^[16]

Clock to Low-Z^[16]

OE HIGH to Output High-Z^{[16, 14]}

OE LOW to Output Low-Z^{[15, 14]}

1.25

2.6

3.0

3.5

t_EOHZ

t_EOLZ

Set-up Times

0

t_AS

Address Set-up Before CLK Rise

1.2

1.5

ns

Notes:

11. Tested initially and after any design or process changes that may affect these parameters.

12. Input waveform should have a slew rate > 1V/ns.

13. Tested initially and after any design or process change that may affect these parameters.

14. At any given voltage and temperature, t_EOHZis less than t_EOLZand t_CHZis less than t_CLZ

.

15. Unless otherwise noted, test conditions assume signal transition time of 1 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output

loading of the specified I_OL/I_OHand load capacitance. Shown in (a), (b) and (c) of AC Test Loads.

16. t_CHZ, t_CLZ, t_OEV, t_EOLZ, and t_EOHZare specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state

voltage.

17. AC parameters may exceed minimums and maximums during the first 20 microseconds of operation.

Document #: 38-05291 Rev. *A

Page 19 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Switching Characteristics Over the Operating Range (See Errata on page 34 for 2.5V V_DDQoperation) (continued)^[14,

15, 16, 17]

-250

Max.

-200

Max.

-166

Max.

Parameter

t_DS

Description

Data Input Set-up Before CLK Rise

ADSP, ADSC Set-up Before CLK Rise

WE, BWS_xSet-up Before CLK Rise

ADV Set-up Before CLK Rise

Chip Select Set-up

Min.

1.2

Min.

1.5

Min.

1.5

Unit

ns

t_ADS

ns

t_WES

ns

t_ADVS

t_CES

ns

Hold Times

t_AH

Address Hold After CLK Rise

Data Input Hold After CLK Rise

ADSP, ADSC Hold After CLK Rise

WE, BW_xHold After CLK Rise

ADV Hold after CLK Rise

0.3

0.5

ns

t_DH

t_ADH

t_WEH

t_ADVH

t_CEH

Chip Select Hold After CLK Rise

Document #: 38-05291 Rev. *A

Page 20 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Switching Waveforms

Write Cycle Timing^{[18, 19]}

Single Write

t_CYC

t_ADH

Burst Write

Pipelined Write

t_CH

Unselected

CLK

t_ADS

t_CL

ADSP ignored with CE₁inactive

ADSP

ADSC

ADV

t_ADH

t_ADS

ADSC initiated write

t_ADVH

t_ADVS

t_AS

ADV Must Be Inactive for ADSP Write

WD3

ADD

GW

WE

CE₁

WD1

WD2

t_AH

t_WH

t_WS

t_CES

t_CEH

CE₁masks ADSP

t_CEH

t_CES

Unselected with CE₂

CE₂

CE₃

OE

t_CES

t_CEH

t_DH

t_DS

High-Z

Data-

In

3a

2a

1a

2b

2c

2d

= UNDEFINED

= DON’T CARE

Notes:

18. WE is the combination of BWE, BW_x, and GW to define a write cycle (see Write Cycle Description table).

19. WDx stands for Write Data to Address X.

Document #: 38-05291 Rev. *A

Page 21 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Switching Waveforms (continued)

Read Cycle Timing^{[18, 20]}

Burst Read

Single Read

t_CYC

Unselected

t_CH

Pipelined Read

CLK

t_ADH

t_ADS

t_CL

ADSP ignored with CE₁inactive

ADSP

t_ADS

ADSC initiated read

ADSC

ADV

t_ADVS

t_ADH

Suspend Burst

t_ADVH

t_AS

ADD

GW

RD1

RD3

RD2

t_AH

t_WS

t_WH

WE

t_CES

t_CEH

t_WH

CE₁masks ADSP

CE₁

Unselected with CE₂

CE₂

t_CES

t_CEH

CE₃

OE

t_CES

t_EOV

t_CEH

t_OEHZ

t_DOH

t_CO

Data Out

2c

1a

2d

3a

2a

2b

t_CLZ

t_CHZ

= DON’T CARE

= UNDEFINED

Note:

20. RDx stands for Read Data from Address X.

Document #: 38-05291 Rev. *A

Page 22 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Switching Waveforms (continued)

Read/Write Cycle Timing^{[18, 19, 20]}

Single Read

t_CYC

Single Write

t_CH

Unselected

Burst Read

Pipelined Read

CLK

t_ADH

t_ADS

t_CL

ADSP ignored with CE₁inactive

ADSP

ADSC

ADV

t_ADS

t_ADVS

t_ADH

t_AS

t_ADVH

WD2

ADD

GW

RD1

RD3

t_AH

t_WS

t_WH

WE

t_CES

t_CEH

t_WH

CE₁masks ADSP

CE₁

CE₂

t_CES

t_CEH

CE₃

OE

t_CES

t_EOV

t_CEH

t_EOHZ

t_DS

t_DH

t_DOH

t_EOLZ

t_CO

2a

Out

3b

Out

3c

Out

3a

Out

3d

Out

Data In/Out

1a

2a

In

Out

t_CHZ

= UNDEFINED

= DON’T CARE

Document #: 38-05291 Rev. *A

Page 23 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Switching Waveforms (continued)

Pipeline Timing^{[21, 22]}

t_CYC

t_CL

t_CH

CLK

t_AS

WD1

WD2

WD3

WD4

RD1

RD2

RD3

RD4

ADD

t_ADS

t_ADH

ADSC initiated Reads

ADSC

ADSP initiated Reads

ADSP

ADV

t_CEH

t_CES

CE₁

CE

t_WES

t_WEH

WE

OE

ADSP ignored

with CE₁HIGH

t_CLZ

Data In/Out

1a

In

1a

2a

3a

4a

2a

In

3a

In

4a

D(C)

Out Out Out Out

In

t_CDV

t_DOH

Back to Back Reads

t_CHZ

= UNDEFINED

= DON’T CARE

Notes:

21. Device originally deselected.

22. CE is the combination of CE₂and CE₃. All chip selects need to be active in order to select the device.

Document #: 38-05291 Rev. *A

Page 24 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Switching Waveforms (continued)

E Switching Waveforms

OE

t_EOV

t_EOHZ

Three-state

I/Os

t_EOLZ

ZZ Mode Timing ^{[23, 24]}

CLK

ADSP

HIGH

ADSC

CE₁

LOW

HIGH

CE₂

CE₃

ZZ

t_ZZS

I_DD

I_DD(active)

Three-state

t_ZZREC

I_DDZZ

I/O’s

Notes:

23. Device must be deselected when entering ZZ mode. See Cycle Description Table for all possible signal conditions to deselect the device.

24. I/Os are in three-state when exiting ZZ sleep mode.

Document #: 38-05291 Rev. *A

Page 25 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Ordering Information

Speed

(MHz)

Package

Name

Operating

Range

Ordering Code

Part and Package Type

250

CY7C1360B-250AC

CY7C1362B-250AC

CY7C1360B-250AJC

CY7C1362B-250AJC

CY7C1360B-250BGC

CY7C1362B-250BGC

CY7C1360B-250BZC

CY7C1362B-250BZC

CY7C1360B-200AC

CY7C1362B-200AC

CY7C1360B-200AJC

CY7C1362B-200AJC

CY7C1360B-200BGC

CY7C136B2-200BGC

CY7C1360B-200BZC

CY7C1362B-200BZC

CY7C1360B-166AC

CY7C1362B-166AC

CY7C1360B-166AJC

CY7C1362B-166AJC

CY7C1360B-166BGC

CY7C1362B-166BGC

CY7C1360B-166BZC

CY7C1362B-166BZC

A101

100-lead Thin Quad Flat Pack 3 Chip Enables

Commercial

A101

100-lead Thin Quad Flat Pack 2 Chip Enables

BG119

BB165A

A101

119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables

and JTAG

165-ball Fine-Pitch Ball Grid Array 3 Chip

Enables and JTAG

200

100-lead Thin Quad Flat Pack 3 Chip Enables

A101

100-lead Thin Quad Flat Pack 2 Chip Enables

BG119

BB165A

A101

119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables

and JTAG

165-ball Fine-Pitch Ball Grid Array 3 Chip

Enables and JTAG

166

100-lead Thin Quad Flat Pack 3 Chip Enables

A101

100-lead Thin Quad Flat Pack 2 Chip Enables

BG119

BB165A

119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables

and JTAG

165-ball Fine-Pitch Ball Grid Array 3 Chip

Enables and JTAG

Document #: 38-05291 Rev. *A

Page 26 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Package Diagrams

100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

51-85050-A

Document #: 38-05291 Rev. *A

Page 27 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Package Diagrams (continued)

119-lead BGA (14 x 22 x 2.4) BG119

51-85115-*A

Document #: 38-05291 Rev. *A

Page 28 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

Package Diagrams (continued)

165-ball FBGA (13 x 15 x 1.2 mm) BB165A

51-85122-*B

Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and

company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05291 Rev. *A

Page 29 of 31

CY7C1360B

CY7C1362B

PRELIMINARY

We are in the process of releasing this product with full

functionality at 2.5V Vddq.

2.5V Vddq Errata

These devices do not currently support the datasheet param-

eters for 2.5V Vddq. If operated at 2.5V Vddq, we expect the

following parameters to be affected:

For further information, please contact your local sales office.

Contact information is available at www.cypress.com.

For your reference, the table below describes the anticipated

functionality of the current devices at 2.5V Vddq. Parameters

that do not meet standard operating conditions are printed in

bold text.

• Output times (t_{CO, EOV}, t_CHZ, t_EOHZ) will be 0.8 ns longer.

t

• The hold time for data and control lines will be 0.8 ns in

comparison to a specification of 0.4 ns

Switching Characteristics

-250

-200

-166

Max.

Parameter

Clock

t_CYC

Description

Clock Cycle Time

Min.

Max.

Min.

Max.

Min.

Unit

4.0

5

6

ns

MHz

ns

F_MAX

t_CH

Maximum Operating Frequency

Clock HIGH

250

200

166

1.7

2.0

2.4

t_CL

Clock LOW

ns

Output Times

t_CO

Data Output Valid After CLK Rise

OE LOW to Output Valid^[14]

Data Output Hold After CLK Rise

Clock to High-Z^[14]

Clock to Low-Z^[14]

OE HIGH to Output High-Z^{[16, 16]}

OE LOW to Output Low-Z^{[16, 16]}

3.4

3.8

4.3

ns

t_EOV

t_DOH

1.25

t_CHZ

3.4

3.8

4.3

t_CLZ

t_EOHZ

t_EOLZ

Set-up Times

t_AS

0

Address Set-up Before CLK Rise

Data Input Set-up Before CLK Rise

CEN Set-up Before CLK Rise

WE, BWS_xSet-up Before CLK Rise

ADV/LD Set-up Before CLK Rise

Chip Select Set-up

1.2

1.5

ns

t_DS

t_CENS

t_WES

t_ALS

t_CES

Hold Times

t_AH

Address Hold After CLK Rise

Data Input Hold After CLK Rise

CEN Hold After CLK Rise

0.8

ns

t_DH

t_CENH

t_WEH

WE, BW_xHold After CLK Rise

ADV/LD Hold after CLK Rise

Chip Select Hold After CLK Rise

t_ALH

t_CEH

Document #: 38-05291 Rev. *A

Page 30 of 31

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C1360B

CY7C1362B

PRELIMINARY

Document Title: CY7C1360B/CY7C1362B 256K x 36/512K x 18 Pipelined SRAM

Document Number: 38-05291

Orig. of

REV.

**

ECN NO. Issue Date Change

Description of Change

114766

117939

08/08/02

08/20/02

RCS

New Data Sheet

Added A0 and A1 to 165 fBGA pinout

*A

Document #: 38-05291 Rev. *A

Page 31 of 31


型号：	CY7C1362B-250BZC
厂家：	CYPRESS
描述：	Cache SRAM, 512KX18, 3.4ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165 静态存储器内存集成电路
文件：	总31页 (文件大小：805K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C1362B-250BZC [CYPRESS]

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