CY7C1366C-225AXC [CYPRESS]
9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM; 9兆位（ 256K ×36 / 512K ×18 ）流水线DCD同步SRAM
| 型号： | CY7C1366C-225AXC |
| 厂家： | 
CYPRESS |
| 描述： | 9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM |
| 文件： | 总27页 (文件大小：457K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1366C
CY7C1367C
PRELIMINARY
9-Mbit (256K x 36/512K x 18) Pipelined DCD
Sync SRAM
Features
Functional Description[1]
• Supports bus operation up to 225 MHz
The CY7C1366C/CY7C1367C SRAM integrates 262,144 x 36
and 524,288 x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
• Available speed grades are 225, 200 and 166 MHz
• Registered inputs and outputs for pipelined operation
•Optimal for performance (Double-Cycle deselect)
—Depth expansion without wait state
•3.3V –5% and +10% core power supply (VDD
• 2.5V / 3.3V I/O operation
address-pipelining Chip Enable (
), depth-expansion Chip
CE1
)
Enables (CE and
[2]), Burst Control inputs (
,
,
CE3
2
ADSC ADSP
), Write Enables (
, and
BWX
), and Global Write
and
ADV
BWE
(
). Asynchronous inputs include the Output Enable (
GW
)
OE
• Fast clock-to-output times
and the ZZ pin.
— 2.8 ns (for 225-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor ( ) or
ADSP
) are active. Subsequent
Address Strobe Controller (
ADSC
burst addresses can be internally generated as controlled by
the Advance pin ( ).
• Provide high-performance 3-1-1-1 access rate
ADV
• User-selectable burst counter supporting Intel
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
controlled by the byte write control inputs.
active
GW
LOW
This device incorporates an
causes all bytes to be written.
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
• AvailableinLead-Free100TQFP,119BGAand165fBGA
packages
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
The CY7C1366C/CY7C1367C operates from a +3.3V core
power supply while all outputs operate with a +3.3V or a +2.5V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
225 MHz
200 MHz
3.0
166 MHz
3.5
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
2.8
250
30
220
30
180
30
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Notes:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE is for TQFP and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.
3
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05542 Rev. *A
Revised October 5, 2004
CY7C1366C
CY7C1367C
PRELIMINARY
1
Logic Block Diagram – CY7C1366C (256K x 36)
ADDRESS
A0,A1,A
REGISTER
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQD,DQP
D
DQD,DQP
D
BYTE
BYTE
BW
D
WRITE REGISTER
WRITE DRIVER
DQ
BYTE
WRITE DRIVER
c,DQPC
DQ
BYTE
WRITE REGISTER
c,DQPC
MEMORY
ARRAY
BW
C
OUTPUT
BUFFERS
OUTPUT
REGISTERS
SENSE
AMPS
DQs
DQP
DQP
DQP
A
DQ
BYTE
WRITE DRIVER
B,DQPB
E
DQ
BYTE
WRITE REGISTER
B,DQPB
B
C
BW
BW
B
A
DQP
D
DQA,DQP
A
DQA,DQP
A
BYTE
WRITE DRIVER
BYTE
WRITE REGISTER
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
ZZ
CONTROL
2
Logic Block Diagram – CY7C1367C (512K x 18)
ADDRESS
REGISTER
A0, A1, A
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQB , DQP
BYTE
WRITE DRIVER
B
DQB, DQP
BYTE
WRITE REGISTER
B
OUTPUT
BUFFERS
BW
B
A
OUTPUT
REGISTERS
DQs,
DQP
DQP
SENSE
AMPS
MEMORY
ARRAY
A
DQA, DQP
BYTE
WRITE DRIVER
A
B
E
DQA , DQP
BYTE
WRITE REGISTER
A
BW
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE
CE
CE
1
PIPELINED
ENABLE
2
3
OE
SLEEP
ZZ
CONTROL
Document #: 38-05542 Rev. *A
Page 2 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Pin Configurations
100-pin TQFP Pinout (3 Chip Enables)
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
A
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
NC
2
DQC
3
NC
NC
3
VDDQ
4
5
VDDQ
VSSQ
NC
VDDQ
VSSQ
NC
4
VSSQ
5
DQC
6
6
DQC
7
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
7
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
8
DQC
9
9
VSSQ
10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
11
DQC
12
DQC
13
NC
14
VDD
15
NC
VDD
NC
CY7C1367C
(512K x 18)
CY7C1366C
(256K X 36)
NC
16
VDD
ZZ
VDD
ZZ
VSS
17
VSS
DQD
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
VDDQ
20
VSSQ
21
DQD
22
DQD
23
DQD
24
DQD
25
NC
VSSQ
26
VSSQ
VDDQ
NC
VSSQ
VDDQ
NC
VDDQ
27
DQD
28
DQD
29
NC
NC
DQPD
30
NC
NC
Document #: 38-05542 Rev. *A
Page 3 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Pin Configurations (continued)
119-ball BGA (2 Chip Enable with JTAG)
CY7C1366C (256K x 36)
1
2
3
4
5
6
7
VDDQ
A
A
A
A
VDDQ
A
B
C
ADSP
ADSC
VDD
NC
NC
CE2
A
A
A
A
A
A
A
NC
NC
DQC
DQC
VDDQ
DQPC
DQC
DQC
VSS
VSS
VSS
NC
CE1
VSS
VSS
VSS
DQPB
DQB
DQB
DQB
DQB
VDDQ
D
E
F
OE
DQC
DQC
VDDQ
DQD
DQD
VDDQ
DQD
DQC
DQC
VDD
BWC
VSS
NC
BWB
VSS
NC
DQB
DQB
VDD
DQA
DQA
DQA
DQA
DQB
DQB
VDDQ
DQA
DQA
VDDQ
DQA
G
H
J
ADV
GW
VDD
CLK
NC
BWE
A1
DQD
VSS
VSS
K
L
M
N
DQD
DQD
DQD
BWD
VSS
VSS
BWA
VSS
VSS
P
R
DQD
NC
DQPD
A
VSS
MODE
A0
VDD
VSS
NC
DQPA
A
DQA
NC
T
U
NC
VDDQ
NC
TMS
A
TDI
A
TCK
A
TDO
NC
NC
ZZ
VDDQ
CY7C1367C (512K x 18)
2
A
CE2
A
NC
DQB
NC
1
3
A
A
4
5
A
A
6
A
A
7
A
B
C
D
E
F
VDDQ
NC
NC
DQB
NC
VDDQ
VDDQ
NC
NC
NC
DQA
VDDQ
ADSP
ADSC
VDD
NC
CE1
A
A
A
VSS
VSS
VSS
VSS
VSS
VSS
DQPA
NC
DQA
OE
G
H
J
NC
DQB
VDDQ
DQB
NC
VDD
VSS
VSS
NC
NC
DQA
VDD
DQA
NC
VDDQ
BWB
VSS
NC
ADV
GW
VDD
NC
DQB
VSS
CLK
NC
BWE
A1
VSS
NC
DQA
NC
DQA
NC
DQA
K
L
M
N
P
DQB
VDDQ
DQB
NC
NC
DQB
NC
VSS
VSS
VSS
VSS
NC
VDDQ
NC
BWA
VSS
VSS
VSS
DQPB
A0
DQA
R
T
NC
NC
A
A
MODE
A
VDD
NC
NC
A
A
A
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Document #: 38-05542 Rev. *A
Page 4 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Pin Configurations (continued)
165-ball fBGA (3 Chip Enable)
CY7C1366C (256K x 36)
1
NC / 288M
NC
DQPC
DQC
2
A
A
NC
DQC
DQC
DQC
DQC
VSS
3
4
5
6
7
8
9
10
11
NC
NC / 144M
DQPB
DQB
A
A
B
C
D
E
F
G
H
J
K
L
CE1
BWC
BWD
VSS
VDD
BWB
BWA
VSS
VSS
CE3
CLK
VSS
VSS
ADSC
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
A
NC
DQB
DQB
DQB
DQB
NC
DQA
DQA
DQA
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DQC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQB
DQC
DQC
NC
DQD
DQD
DQD
DQB
DQB
ZZ
DQA
DQA
DQA
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
DQD
DQPD
NC
DQD
NC
NC / 72M
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
NC / 18M
A1
VSS
NC
TDO
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
A0
MODE NC / 36M
A
A
TMS
TCK
A
A
A
A
R
CY7C1367C (512K x 18)
1
NC / 288M
NC
2
3
CE1
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
4
BWB
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
5
6
7
8
9
10
11
A
A
NC
A
A
CE
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ADSC
OE
VSS
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
3
A
NC
DQB
DQB
DQB
DQB
VSS
NC
NC
NC
BWA
VSS
VSS
VSS
VSS
VSS
VSS
‘VSS
VSS
VSS
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
NC
NC
NC
NC
NC
NC / 144M
DQPA
DQA
B
C
D
E
F
G
H
J
K
L
NC
NC
NC
NC
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DQA
DQA
DQA
ZZ
NC
NC
NC
NC
DQB
DQB
DQB
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
DQB
DQPB
NC
NC
NC
NC / 72M
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
NC / 18M
A1
VSS
NC
TDO
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
MODE NC / 36M
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05542 Rev. *A
Page 5 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Pin Definitions
Name
I/O
Description
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK if or
is active LOW, and CE , CE , and CE [2]are sampled active. A1: A0
A0, A1, A
Input-
Synchronous
ADSP ADSC
are fed to the two-bit counter.
1
2
3
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
BWA,BWB
BWC,BWD
Synchronous
Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
GW
Synchronous
global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE).
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must
BWE
CLK
Synchronous
be asserted LOW to conduct a byte write.
Input-
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
Clock
burst counter when ADV is asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is
sampled only when a new external address is loaded.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3[2] to select/deselect the device.CE2 is sampled only when a new external
address is loaded.
CE1
CE2
Synchronous
Input-
Synchronous
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
[2]
CE3
Synchronous
with CE and CE to select/deselect the device.
Not connected for BGA. Where referenced,
1
CE3[2] is assume2d active throughout this document for BGA.
CE3 is sampled only when a new external address is loaded.
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ pins are three-stated, and
act as input data pins. OE is masked during the first clock of a read cycle when emerging from
a deselected state.
OE
Asynchronous
Input-
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
ADV
Synchronous
automatically increments the address in a burst cycle.
Input-
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1:
A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSP
Synchronous
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1:
A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized.
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.
ADSC
ZZ
Synchronous
Input-
Asynchronous
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
DQs,
Synchronous
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
DQPs
specified by the addresses presented during the previous
clock rise of the read
cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQPX are placed in a three-state condition.
VDD
VSS
VSSQ
VDDQ
MODE
Power Supply
Ground
I/O Ground
Power supply inputs to the core of the device.
Ground for the core of the device.
Ground for the I/O circuitry.
I/O Power Supply Power supply for the I/O circuitry.
Input-
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or
Static
left floating selects interleaved burst sequence. This is a strap pin and should remain static
during device operation. Mode Pin has an internal pull-up.
TDO
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
Synchronous
feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP
packages.
Document #: 38-05542 Rev. *A
Page 6 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Pin Definitions (continued)
Name
TDI
I/O
Description
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
Synchronous
not being utilized, this pin can be disconnected or connected to VDD. This pin is not available
on TQFP packages.
TMS
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
Synchronous
not being utilized, this pin can be disconnected or connected to VDD. This pin is not available
on TQFP packages.
TCK
NC
JTAG-
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be
connected to VSS. This pin is not available on TQFP packages.
–
No Connects. Not internally connected to the die.
Single Write Accesses Initiated by ADSP
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1366C/CY7C1367C supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The write signals (GW, BWE, and
ignored during this first cycle.
) and ADV inputs are
BWX
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the memory core. If GW is HIGH,
Accesses can
Strobe (ADSP)
be initiated with either the Processor Address
or the Controller Address Strobe (ADSC).
then the write operation is controlled by BWE and
BWX
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
signals. The CY7C1366C/CY7C1367C provides byte write
capability that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
Because the CY7C1366C/CY7C1367C is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
self-timed write circuitry.
synchronous
[2]
Synchronous Chip Selects CE1, CE2, CE3
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control.
is ignored if
and an
ADSP
is HIGH.
CE1
Single Write Accesses Initiated by ADSC
Single Read Accesses
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within tco if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always three-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE signal. Consecutive
single read cycles are supported.
and
) are asserted active to conduct a write to the desired
BWX
byte(s). ADSC triggered write accesses require a single clock
cycle to complete. The address presented is loaded into the
address register and the address advancement logic while
being delivered to the memory core. The ADV input is ignored
during this cycle. If a global write is conducted, the data
presented to the DQX is written into the corresponding address
location in the memory core. If a byte write is conducted, only
the selected bytes are written. Bytes not selected during a byte
write operation will remain unaltered.
A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
Because the CY7C1366C/CY7C1367C is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQX inputs. Doing so will
three-state the output drivers. As a safety precaution, DQX are
The CY7C1366C/CY7C1367C is a double-cycle deselect part.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately after the next clock rise.
Document #: 38-05542 Rev. *A
Page 7 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
automatically three-stated whenever a write cycle is detected,
Interleaved Burst Address Table
regardless of the state of OE.
(MODE = Floating or VDD)
Burst Sequences
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
The CY7C1366C/CY7C1367C provides a two-bit wraparound
counter, fed by A[1:0], that implements either an interleaved or
linear burst sequence. The interleaved burst sequence is
designed specifically to support Intel® Pentium applications.
The linear burst sequence is designed to support processors
that follow a linear burst sequence. The burst sequence is user
selectable through the MODE input. Both read and write burst
operations are supported.
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
Sleep Mode
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Partial Truth Table for Read/Write[5, 10]
Function (CY7C1366C)
GW
BWD
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
BWC
BWB
BWA
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
BWE
Read
Read
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
X
H
H
L
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
Write Byte C – (DQC and DQPC)
Write Bytes C, A
L
H
H
L
Write Bytes C, B
Write Bytes C, B, A
Write Byte D – (DQD and DQPD)
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
L
H
H
L
L
H
H
L
L
X
L
X
Write All Bytes
X
Truth Table for Read/Write[5, 10]
Function (CY7C1367C)
GW
BWE
BWB
BWA
Read
Read
H
H
H
H
H
L
H
L
L
L
L
X
X
H
H
L
L
X
X
H
L
H
L
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write All Bytes
Write All Bytes
X
Document #: 38-05542 Rev. *A
Page 8 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Test MODE SELECT (TMS)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
The CY7C1366C/CY7C1367C incorporates a serial boundary
scan test access port (TAP)in the BGA package only. The
TQFP package does not offer this functionality. This part
operates in accordance with IEEE Standard 1149.1-1900, but
doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure .
TDI is internally pulled up and can be unconnected if the TAP
is unused in an application. TDI is connected to the most
significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
The CY7C1366C/CY7C1367C contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Test Data-Out (TDO)
Disabling the JTAG Feature
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
TAP Controller Block Diagram
0
TAP Controller State Diagram
Bypass Register
TEST-LOGIC
2
1
0
0
0
1
RESET
0
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
Selection
TDI
TDO
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
Circuitr
y
.
.
. 2 1
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
x
.
.
.
.
. 2 1
0
0
Boundary Scan Register
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
TCK
TMS
EXIT1-DR
EXIT1-IR
TAP CONTROLLER
0
0
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
Performing a TAP Reset
EXIT2-DR
1
EXIT2-IR
1
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
UPDATE-DR
UPDATE-IR
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Document #: 38-05542 Rev. *A
Page 9 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Instruction Register
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
Bypass Register
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
IDCODE
Boundary Scan Register
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
SAMPLE/PRELOAD
SAMPLE / PRELOAD is a 1149.1 mandatory instruction.
When the SAMPLE / PRELOAD instructions are loaded into
the instruction register and the TAP controller is in the Cap-
ture-DR state, a snapshot of data on the inputs and output pins
is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possi-
ble that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE / PRELOAD instruction. If
this is an issue, it is still possible to capture all other signals
and simply ignore the value of the CK and CK# captured in the
boundary scan register.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
Document #: 38-05542 Rev. *A
Page 10 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells pri-
or to the selection of another boundary scan test operation.
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required - that is, while data
captured is shifted out, the preloaded data can be shifted in.
future use. Do not use these instructions.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the operating Range[3, 4]
Parameter
Symbol
Min
Max
Unit
Clock
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
Output Times
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
Setup Times
tTCYC
tTF
tTH
50
ns
MHz
ns
20
5
25
25
tTL
ns
tTDOV
tTDOX
ns
ns
0
TMS Set-Up to TCK Clock Rise
TDI Set-Up to TCK Clock Rise
Capture Set-Up to TCK Rise
Hold Times
tTMSS
tTDIS
tCS
5
5
5
ns
ns
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
tTMSH
tTDIH
tCH
5
5
5
ns
ns
ns
Document #: 38-05542 Rev. *A
Page 11 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
TAP AC Switching Characteristics Over the operating Range[3, 4]
Parameter
Symbol
Min
Max
Unit
Notes:
3. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
4. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document #: 38-05542 Rev. *A
Page 12 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ....... ........................................VSS to 3.3V
Input rise and fall times...................... ..............................1ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Input pulse levels ........................................ V to 2.5V
SS
Input rise and fall time ......................................................1ns
Input timing reference levels................... ......................1.25V
Output reference levels .................. ..............................1.25V
Test load termination supply voltage .................... ........1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
ZO= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)[5]
Parameter
VOH1
Description
Output HIGH Voltage IOH = –4.0 mA
Conditions
Min.
2.4
Max.
Unit
V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
2.0
2.9
2.1
V
V
IOH = –1.0 mA
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage IOH = –100 µA
V
0.4
0.4
V
Output LOW Voltage IOL = 8.0 mA
IOL = 8.0 mA
V
0.2
V
Output LOW Voltage IOL = 100 µA
0.2
V
2.0
1.7
VDD + 0.3
VDD + 0.3
0.7
V
Input HIGH Voltage
Input LOW Voltage
V
V
DDQ = 3.3V
–0.5
–0.3
–5
V
VIL
VDDQ = 2.5V
0.7
V
5
µA
IX
Input Load Current
GND < VIN < VDDQ
Identification Register Definitions
CY7C1366C
CY7C1367C
(512K x18)
Instruction Field
Revision Number (31:29)
(256K x36)
000
Description
Describes the version number.
000
Device Depth (28:24)[6]
01011
01011
Reserved for Internal Use
000110
100110
00000110100
1
000110
010110
00000110100
1
Device Width (23:18)
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Note:
5. All voltages referenced to VSS (GND).
6. Bit #24 is “1” in the Register Definitions for both 2.5v and 3.3v versions of this device.
Document #: 38-05542 Rev. *A
Page 13 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Instruction
3
3
Bypass
1
1
ID
32
71
71
32
71
71
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball fBGA package)
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
SAMPLE/PRELOAD
011
100
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
119-Ball BGA Boundary Scan Order
CY7C1366C (256K x 36)
CY7C1367C (512K x 18)
Signal
BALL
ID
Signal
Signal
Name
A0
A1
A
Signal
Name
BIT#
Name
BIT# BALL ID
BIT# BALL ID
Name
CLK
GW
BIT# BALL ID
1
2
3
4
5
6
7
8
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
37
38
39
40
41
42
43
44
P4
N4
R6
T5
T3
R2
R3
P2
1
2
3
4
5
6
7
8
37
38
39
40
41
42
43
44
P4
N4
R6
T5
T3
R2
R3
A0
A1
A
A
A
K4
H4
M4
F4
B4
A4
G4
C3
K4
H4
M4
F4
B4
A4
G4
C3
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
A
MODE
DQPD
MODE
Internal
Internal
9
B3
D6
H7
G6
E6
D7
E7
F6
G7
H6
A
45
46
47
48
49
50
51
52
53
54
P1
L2
DQD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
Internal
DQC
9
B3
T2
A
45
46
47
48
49
50
51
52
53
54
Internal
Internal
Internal
P2
Internal
Internal
Internal
DQPB
DQB
10
11
12
13
14
15
16
17
18
DQPB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
10
11
12
13
14
15
16
17
18
A
K1
Internal
Internal
Internal
D6
Internal
Internal
Internal
DQPA
DQA
N2
N1
N1
M2
M2
DQB
L1
E7
L1
DQB
K2
F6
DQA
K2
DQB
Internal
H1
G7
DQA
Internal
H1
Internal
DQB
H6
DQA
Document #: 38-05542 Rev. *A
Page 14 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
119-Ball BGA Boundary Scan Order (continued)
CY7C1366C (256K x 36)
Signal
CY7C1367C (512K x 18)
BALL
ID
Signal
Name
Signal
Signal
BIT#
Name
BIT# BALL ID
BIT# BALL ID
Name
BIT# BALL ID
Name
19
T7
K7
L6
ZZ
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
G2
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQPC
A
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
T7
ZZ
DQA
DQA
DQA
DQA
Internal
Internal
Internal
Internal
Internal
A
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
G2
DQB
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQPA
A
E2
K7
E2
DQB
DQB
D1
L6
D1
N6
P7
N7
M6
L7
H2
N6
Internal
Internal
Internal
Internal
Internal
C2
Internal
Internal
Internal
Internal
Internal
A
G1
F2
P7
Internal
Internal
Internal
Internal
Internal
T6
E1
D2
K6
P6
T4
A3
C5
B5
A5
C6
C2
A2
A
A2
A
E4
CE1
E4
CE1
A
B2
CE2
A3
A
B2
CE2
A
L3
BWD
BWC
BWB
BWA
Internal
C5
A
Internal
Internal
G3
Internal
Internal
BWB
A
G3
G5
L5
B5
A
A
A5
A
A
C6
A
L5
BWA
35
36
A6
B6
A
A
Internal
35
36
A6
B6
A
A
Internal
Internal
165-Ball fBGA Boundary Scan Order
CY7C1366C (256K x 36)
Signal
CY7C1367C (512K x 18)
Signal
Signal
Signal
Name
A0
A1
A
BIT# BALL ID Name
BIT# BALL ID
Name
A0
BIT# BALL ID
Name
CLK
BIT# BALL ID
1
B6
CLK
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
R6
1
B6
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
R6
P6
R4
P4
R3
P3
R1
2
B7
GW
P6
A1
A
A
A
2
B7
GW
BWE
OE
ADSC
ADSP
ADV
A
3
A7
BWE
OE
R4
P4
3
A7
4
B8
4
B8
A
A
A
5
A8
ADSC
ADSP
ADV
A
R3
P3
R1
N1
5
A8
6
B9
A
6
B9
7
A9
MODE
DQPD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
Internal
7
A9
MODE
Internal
Internal
Internal
Internal
DQPB
DQB
DQB
DQB
DQB
Internal
8
9
B10
A10
C11
E10
F10
G10
D10
D11
E11
F11
8
9
B10
A10
A11
Internal
Internal
Internal
C11
D11
E11
F11
Internal
Internal
Internal
Internal
N1
A
L2
A
A
10
11
12
13
14
15
16
17
DQPB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
K2
J2
M2
M1
L1
K1
J1
Internal
10
11
12
13
14
15
16
17
Internal
Internal
Internal
DQPA
DQA
DQA
DQA
M1
L1
K1
J1
Internal
Document #: 38-05542 Rev. *A
Page 15 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
165-Ball fBGA Boundary Scan Order (continued)
CY7C1366C (256K x 36)
Signal
CY7C1367C (512K x 18)
Signal
Name
Signal
Signal
Name
BIT# BALL ID Name
BIT# BALL ID
BIT# BALL ID
Name
BIT# BALL ID
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
G11
H11
J10
K10
L10
M10
J11
K11
L11
M11
N11
R11
R10
P10
R9
DQB
ZZ
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
G2
F2
E2
D2
G1
F1
E1
D1
C1
B2
A2
A3
B3
B4
A4
A5
B5
A6
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQPC
A
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
G11
H11
J10
K10
DQA
ZZ
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
G2
F2
E2
D2
Internal
Internal
Internal
Internal
Internal
B2
A2
A3
B3
Internal
Internal
A4
B5
A6
DQB
DQB
DQB
DQB
Internal
Internal
Internal
Internal
Internal
A
A
CE1
CE2
Internal
Internal
BWB
BWA
CE3
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQPA
A
A
A
A
A
A
A
A
DQA
DQA
DQA
DQA
Internal
Internal
Internal
Internal
Internal
A
L10
M10
Internal
Internal
Internal
Internal
Internal
R11
R10
P10
R9
P9
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
A
A
A
A
A
A
A
P9
R8
P8
P11
R8
P8
P11
Document #: 38-05542 Rev. *A
Page 16 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Latch-up Current..................................................... >200 mA
Ambient Temperature with
Operating Range
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Range
Temperature
VDD
VDDQ
DC Voltage Applied to Outputs
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
in three-state....................................... –0.5V to VDDQ + 0.5V
to VDD
Industrial
–40°C to +85°C
DC Input Voltage....................................–0.5V to VDD + 0.5V
[7, 8]
Electrical Characteristics Over the Operating Range
Parameter
VDD
VDDQ
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
3.6
VDD
Unit
V
V
V
V
V
V
V
V
V
V
V
µA
VDDQ = 3.3V
DDQ = 2.5V
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
DDQ = 2.5V, VDD = Min., IOH= –1.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
DDQ = 2.5V, VDD = Min., IOL = 1.0 mA
V
2.625
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[7]
Input LOW Voltage[7]
V
2.0
0.4
0.4
VDD + 0.3V
VDD + 0.3V
0.8
V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
2.0
1.7
–0.3
–0.3
–5
VDDQ = 2.5V
0.7
5
Input Load Current
GND ≤ VI ≤ VDDQ
except ZZ and MODE
Input Current of MODE Input = VSS
Input = VDD
–30
–5
µA
µA
µA
µA
µA
5
Input Current of ZZ
Input = VSS
Input = VDD
30
5
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
–5
VDD Operating Supply VDD = Max., IOUT = 0 mA,
4.4-ns cycle, 225 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
All speeds
250
220
180
50
mA
mA
mA
mA
Current
f = fMAX = 1/tCYC
ISB1
ISB2
ISB3
ISB4
Automatic CE
V
DD = Max, Device Deselected,
Power-down
V
IN ≥ VIH or VIN ≤ VIL
Current—TTL Inputs
f = fMAX = 1/tCYC
Automatic CE
VDD = Max, Device Deselected,
All speeds
30
50
40
mA
mA
mA
Power-down
V
IN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
Automatic CE
VDD = Max, Device Deselected, or All speeds
Power-down
V
IN ≤ 0.3V or VIN > VDDQ – 0.3V
Current—CMOS Inputs f = fMAX = 1/tCYC
Automatic CE
V
DD = Max, Device Deselected,
All Speeds
Power-down
V
IN ≥ VIH or VIN ≤ VIL, f = 0
Current—TTL Inputs
Shaded areas contain advance information.
Notes:
7. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > -2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
< V
DD\
8. TPower-up: Assumes a linear ramp from 0v to V (min.) within 200ms. During this time V < V and V
DDQ
DD
IH
DD
Document #: 38-05542 Rev. *A
Page 17 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Thermal Resistance[9]
TQFP
BGA
fBGA
Parameter
Description
Test Conditions
Package
Package
Package
Unit
ΘJA
Thermal Resistance
Test conditions follow standard
test methods and procedures
for measuring thermal
25
25
27
°C/W
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
9
6
6
°C/W
impedance, per EIA / JESD51.
Capacitance[9]
TQFP
BGA
fBGA
Parameter
CIN
CCLK
Description
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
Test Conditions
Package
Package
Package
Unit
pF
pF
TA = 25°C, f = 1 MHz,
5
5
5
5
5
7
5
5
7
V
DD = 3.3V.
DDQ = 2.5V
V
CI/O
pF
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
5 pF
R = 351Ω
≤ 1ns
≤ 1ns
V = 1.5V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50Ω
0
10%
L
GND
≤ 1ns
5 pF
R =1538Ω
≤ 1ns
V = 1.25V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note:
9. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05542 Rev. *A
Page 18 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Switching Characteristics Over the Operating Range[14, 15]
225 MHz
200 MHz
166 MHz
Parameter
tPOWER
Clock
tCYC
tCH
tCL
Description
Min.
1
Max
Min.
1
Max
Min.
1
Max
Unit
ms
VDD(Typical) to the first Access[10]
Clock Cycle Time
Clock HIGH
4.4
1.8
1.8
5.0
2.0
2.0
6.0
2.4
2.4
ns
ns
ns
Clock LOW
Output Times
tCO
tDOH
tCLZ
tCHZ
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[11, 12, 13]
2.8
3.0
3.5
ns
ns
ns
ns
ns
ns
ns
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
Clock to High-Z[11, 12, 13]
2.8
2.8
3.0
3.0
3.5
3.5
tOEV
OE LOW to Output Valid
LOW to Output Low-Z[11, 12, 13]
OE
tOELZ
tOEHZ
Set-up Times
tAS
tADS
tADVS
tWES
0
0
0
OE HIGH to Output High-Z[11, 12, 13]
2.8
3.0
3.5
Address Set-up Before CLK Rise
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
,
ADSC ADSP Set-up Before CLK Rise
ADV Set-up Before CLK Rise
Set-up Before CLK Rise
GW, BWE, BWX
tDS
tCES
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
Hold Times
tAH
tADH
tADVH
tWEH
tDH
Address Hold After CLK Rise
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
,
Hold After CLK Rise
ADSP ADSC
ADV Hold After CLK Rise
,
,
GW BWE BWX Hold After CLK Rise
Data Input Hold After CLK Rise
tCEH
Chip Enable Hold After CLK Rise
Shaded areas contain advance information.
Notes:
10. This part has a voltage regulator internally; t
can be initiated.
is the time that the power needs to be supplied above V (minimum) initially before a read or write operation
DD
POWER
11. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
12. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
13. This parameter is sampled and not 100% tested.
14. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
15. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05542 Rev. *A
Page 19 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Switching Waveforms
Read Cycle Timing[16]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,BWX
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
OEV
CO
t
t
CHZ
t
t
t
OELZ
OEHZ
DOH
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
Q(A1)
Data Out (DQ)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Notes:
16. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05542 Rev. *A
Page 20 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Switching Waveforms (continued)
Write Cycle Timing[16, 17]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
BWE,
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BW
X
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
Data in (D)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
DON’T CARE
Single WRITE
Extended BURST WRITE
UNDEFINED
Note:
17.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document #: 38-05542 Rev. *A
Page 21 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Switching Waveforms (continued)
Read/Write Cycle Timing[16, 18, 19]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
t
DH
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Back-to-Back READs
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
BURST READ
Back-to-Back
Single WRITE
DON’T CARE
WRITEs
UNDEFINED
Notes:
18.
.
The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by
ADSP or ADSC
19. GW is HIGH.
Document #: 38-05542 Rev. *A
Page 22 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Switching Waveforms (continued)
ZZ Mode Timing [20, 21]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Speed
Package
Operating
Range
(MHz)
Ordering Code
Name
Part and Package Type
225
CY7C1366C-225AXC
CY7C1367C-225AXC
CY7C1366C-225AXI
CY7C1367C-225AXI
CY7C1366C-225BGC
CY7C1367C-225BGC
CY7C1366C-225BGI
CY7C1367C-225BGI
CY7C1366C-225BZC
CY7C1367C-225BZC
CY7C1366C-225BZI
CY7C1367C-225BZI
CY7C1366C-200AXC
CY7C1367C-200AXC
CY7C1366C-200AXI
CY7C1367C-200AXI
CY7C1366C-200BGC
CY7C1367C-200BGC
CY7C1366C-200BGI
CY7C1367C-200BGI
CY7C1366C-200BZC
CY7C1367C-200BZC
CY7C1366C-200BZI
CY7C1367C-200BZI
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
Commercial
3 Chip Enables
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Industrial
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with Commercial
JTAG
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with Industrial
JTAG
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Commercial
3 Chip Enables with JTAG
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Industrial
3 Chip Enables with JTAG
200
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Commercial
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Industrial
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with Commercial
JTAG
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with Industrial
JTAG
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Commercial
3 Chip Enables with JTAG
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Industrial
3 Chip Enables with JTAG
Notes:
20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
21. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05542 Rev. *A
Page 23 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Ordering Information (continued)
Speed
Package
Operating
Range
Commercial
(MHz)
Ordering Code
CY7C1366C-166AXC
CY7C1367C-166AXC
CY7C1366C-166AXI
CY7C1367C-166AXI
CY7C1366C-166BGC
CY7C1367C-166BGC
CY7C1366C-166BGI
CY7C1367C-166BGI
CY7C1366C-166BZC
CY7C1367C-166BGC
CY7C1366C-166BZI
CY7C1367C-166BGI
Name
Part and Package Type
166
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Industrial
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with Commercial
JTAG
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with
JTAG
Industrial
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Commercial
3 Chip Enables with JTAG
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables with JTAG
Industrial
Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.Lead-free BG and BZ packages (Ordering
code:BGX,BZX) will be available in 2005.
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
ꢁ6.00 0.20
ꢁ4.00 0.ꢁ0
ꢁ.40 0.05
ꢁ00
ꢀꢁ
ꢀ0
ꢁ
0.30 0.0ꢀ
0.65
TYP.
ꢁ2° ꢁ°
SEE DETAIL
A
(ꢀX)
30
5ꢁ
3ꢁ
50
0.20 MAX.
ꢁ.60 MAX.
R 0.0ꢀ MIN.
0.20 MAX.
0° MIN.
STAND-OFF
0.05 MIN.
0.ꢁ5 MAX.
SEATING PLANE
0.25
GAUGE PLANE
R 0.0ꢀ MIN.
0.20 MAX.
0°-7°
0.60 0.ꢁ5
ꢁ.00 REF.
0.20 MIN.
51-85050-*A
DETAIL
A
Document #: 38-05542 Rev. *A
Page 24 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05542 Rev. *A
Page 25 of 27
CY7C1366C
CY7C1367C
PRELIMINARY
Package Diagrams (continued)
165 FBGA 13 x 15 x 1.40 MM BB165D
51-85180-**
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05542 Rev. *A
Page 26 of 27
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1366C
CY7C1367C
PRELIMINARY
Document History Page
Document Title: CY7C1366C/CY7C1367C 9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM (Preliminary)
Document Number: 38-05542
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
241690
See ECN
RKF
New data sheet
*A
278969
See ECN
RKF
Changed Boundary Scan order to match the B rev of these devices.
Document #: 38-05542 Rev. *A
Page 27 of 27
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