CY7C1367C-166BZI_技术文档

CY7C1366C

CY7C1367C

9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM

Features

Functional Description^[1]

• Supports bus operation up to 250 MHz

The CY7C1366C/CY7C1367C SRAM integrates 256K x 36

and 512K x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE₁), depth-expansion Chip

Enables (CE₂and CE₃^[2]), Burst Control inputs (ADSC, ADSP,

• Available speed grades are 250, 200, and 166 MHz

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

—Depth expansion without wait state

• 3.3V –5% and +10% core power supply (V_DD

)

• 2.5 V/3.3V I/O power supply (V_DDQ

)

ADV), Write Enables (BW , and BWE), and Global Write

and

X

(GW). Asynchronous inputs include the Output Enable (OE)

and the ZZ pin.

• Fast clock-to-output times

— 2.8 ns (for 250-MHz device)

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

• Asynchronous output enable

• Available in lead-Free 100-Pin TQFP, lead-free and non

lead-free 119-Ball BGA package and 165-Ball FBGA

package

controlled by the byte write control inputs. GW

active

LOW

This device incorporates an

causes all bytes to be written.

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

The CY7C1366C/CY7C1367C operates from a +3.3V core

power supply while all outputs operate with a +3.3V or a +2.5V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

250 MHz

200 MHz

3.0

166 MHz

3.5

Unit

ns

Maximum Access Time

2.8

250

40

Maximum Operating Current

Maximum CMOS Standby Current

220

180

mA

40

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE is for TQFP and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.

3

Cypress Semiconductor Corporation

Document #: 38-05542 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 14, 2006

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CY7C1366C

CY7C1367C

1

Logic Block Diagram – CY7C1366C (256K x 36)

ADDRESS

A0,A1,A

REGISTER

2

A[1:0]

MODE

Q1

ADV

CLK

BURST

COUNTER AND

LOGIC

CLR

Q0

ADSC

ADSP

DQD,DQP

D

DQD,DQP

D

BYTE

BW

D

WRITE REGISTER

WRITE DRIVER

DQ

BYTE

WRITE DRIVER

c,DQPC

DQ

BYTE

WRITE REGISTER

c,DQPC

MEMORY

ARRAY

BW

C

OUTPUT

BUFFERS

OUTPUT

REGISTERS

SENSE

AMPS

DQs

DQP

A

DQ

BYTE

WRITE DRIVER

B,DQPB

E

DQ

BYTE

WRITE REGISTER

B,DQPB

B

C

BW

B

A

DQP

D

DQA,DQP

A

DQA,DQP

A

BYTE

WRITE DRIVER

BYTE

WRITE REGISTER

BWE

INPUT

REGISTERS

GW

ENABLE

REGISTER

PIPELINED

ENABLE

CE

1

2

3

OE

SLEEP

ZZ

CONTROL

2

Logic Block Diagram – CY7C1367C (512K x 18)

ADDRESS

REGISTER

A0, A1, A

2

A[1:0]

MODE

Q1

ADV

CLK

BURST

COUNTER AND

LOGIC

CLR

Q0

ADSC

ADSP

DQB , DQP

BYTE

WRITE DRIVER

B

DQB, DQP

BYTE

WRITE REGISTER

B

OUTPUT

BUFFERS

BW

B

A

OUTPUT

REGISTERS

DQs,

DQP

SENSE

AMPS

MEMORY

ARRAY

A

DQ^A,DQP

BYTE

WRITE DRIVER

A

B

E

DQA , DQP

BYTE

WRITE REGISTER

A

BW

BWE

GW

INPUT

REGISTERS

ENABLE

REGISTER

CE

1

PIPELINED

ENABLE

2

3

OE

SLEEP

ZZ

CONTROL

Document #: 38-05542 Rev. *E

Page 2 of 29

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CY7C1366C

CY7C1367C

Pin Configurations

100-Pin TQFP Pinout (3 Chip Enables)

DQP_C

1

DQP_B

DQ_B

V_DDQ

V_SSQ

DQ_B

V_SSQ

V_DDQ

DQ_B

V_SS

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

NC

V_DDQ

V_SSQ

NC

A

NC

V_DDQ

V_SSQ

NC

DQP_A

DQ_A

V_SSQ

V_DDQ

DQ_A

V_SS

NC

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQ_C

2

DQ_C

V_DDQ

V_SSQ

DQ_C

3

4

5

6

DQ_C

7

NC

DQ_C

8

DQ_B

V_SSQ

V_DDQ

DQ_B

NC

V_DD

NC

V_SS

DQ_B

V_DDQ

V_SSQ

DQ_B

DQP_B

NC

DQ_C

9

10

11

9

V_SSQ

V_DDQ

DQ_C

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

12

DQ_C

13

NC

14

V_DD

15

NC

V_DD

ZZ

CY7C1367C

(512K x 18)

CY7C1366C

(256K X 36)

NC

16

V_DD

ZZ

V_SS

17

DQ_D

18

DQ_A

V_DDQ

V_SSQ

DQ_A

V_SSQ

V_DDQ

DQ_A

DQP_A

DQ_A

V_DDQ

V_SSQ

DQ_A

NC

DQ_D

19

20

21

V_DDQ

V_SSQ

DQ_D

22

DQ_D

23

DQ_D

24

DQ_D

25

26

27

NC

V_SSQ

V_DDQ

DQ_D

29

V_SSQ

V_DDQ

NC

V_SSQ

V_DDQ

NC

28

DQP_D

30

Document #: 38-05542 Rev. *E

Page 3 of 29

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CY7C1366C

CY7C1367C

Pin Configurations (continued)

119-Ball BGA Pinout (2 Chip Enable with JTAG)

CY7C1366C (256K x 36)

1

2

3

4

5

6

7

A

V_DDQ

A

V_DDQ

ADSP

ADSC

V_DD

B

C

NC/288M

NC/144M

CE₂

A

NC/576M

NC/1G

D

E

F

DQ_C

V_DDQ

DQP_C

DQ_C

V_SS

NC

V_SS

DQP_B

DQ_B

CE₁

DQ_C

DQ_B

V_DDQ

OE

G

H

J

DQ_C

V_DDQ

DQ_D

DQ_C

V_DD

BW_C

V_SS

NC

BW_B

V_SS

NC

DQ_B

V_DD

DQ_A

DQ_B

V_DDQ

DQ_A

ADV

GW

V_DD

K

DQ_D

V_SS

CLK

NC

V_SS

L

M

N

DQ_D

V_DDQ

DQ_D

DQ_A

V_DDQ

DQ_A

BW_D

V_SS

BW_A

V_SS

BWE

A1

DQ_D

NC

DQP_D

A

V_SS

A0

V_SS

NC

DQP_A

A

DQ_A

NC

P

R

MODE

V_DD

T

NC

NC/72M

TMS

A

NC/36M

NC

ZZ

V_DDQ

TDI

TCK

TDO

V_DDQ

U

CY7C1367C (512K x 18)

2

A

1

3

A

4

5

A

6

A

7

V_DDQ

NC/576M

NC/1G

NC

V_DDQ

A

B

C

D

E

F

ADSP

NC/288M

NC/144M

DQ_B

CE₂

A

ADSC

V_DD

A

NC

DQ_B

NC

V_SS

NC

V_SS

DQP_A

NC

DQ_A

NC

DQ_A

CE₁

V_DDQ

OE

NC

DQ_B

NC

V_DD

V_SS

NC

DQ_A

V_DD

DQ_A

NC

V_DDQ

G

H

J

BW_B

V_SS

NC

ADV

DQ_B

V_DDQ

GW

V_DD

K

NC

DQ_B

V_SS

CLK

NC

V_SS

NC

DQ_A

L

M

N

P

DQ_B

V_DDQ

DQ_B

NC

DQ_B

NC

V_SS

DQ_A

NC

V_DDQ

NC

BW_A

V_SS

BWE

A1

V_SS

DQ_A

NC

DQP_B

A0

DQ_A

R

T

NC

A

MODE

A

V_DD

NC/36M

TCK

NC

A

NC

ZZ

NC/72M

V_DDQ

TMS

TDI

TDO

NC

V_DDQ

U

Document #: 38-05542 Rev. *E

Page 4 of 29

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CY7C1366C

CY7C1367C

Pin Configurations (continued)

165-ball FBGA Pinout (3 Chip Enable)

CY7C1366C (256K x 36)

11

22

33

44

55

66

77

88

99

11

0

1111

NC/

C/

QPP_CC

N

2

C

88M

A

NNC

A

C

EE₁₁

B

WW_CC

B

WW_BB

CE₃

CLK

ADSC

OE

A

BWE

GW

ADV

ADSP

VV_DD

N

C

/

1

4

4MM

4

AA

CC

EE₂₂

BB

WW_DD

BB

WW_AA

AA

NNCC//557766MM

BB

D

Q

N

C

VV_DDD

VV_SSS

V_SSS

V

NN

C

/

/ 1

1

GG

DDQQPP_BB

CC

D

Q

S

D

DQ

Q

D

QQ_CC

D

QQ_CC

VV_DDD

VV_SSS

VV_DDD

VV_DD

D

QQ_BB

D

QQ_BB

D

Q

D

S

D

DQ

Q

DD

VV_DDD

VV_SSS

VV_DDD

DD

EE

D

Q

D

S

D

Q

DD

VV_DDD

VV_SSS

VV_DDD

DD

FF

D

Q

D

S

D

Q

DD

VV_DDD

VV_SSS

VV_DDD

DD

GG

D

Q

D

S

D

Q

N

NC

C

VV_SSS

NNC

VV_DDD

VV_SSS

VV_DDD

N

C

N

NC

C

ZZZ

HH

V_S

SSS

S

D

S

D

QQ_DD

D

QQ_DD

VV_DDD

VV_SSS

VV_DDD

VV_DD

D

QQ_AA

D

QQ_AA

J

D

Q

D

S

D

DQ

Q

DD

VV_DDD

VV_SSS

VV_DDD

DD

KK

D

Q

D

S

D

Q

DD

VV_DDD

VV_SSS

VV_DDD

DD

LL

D

Q

D

S

D

Q

DD

VV_DDD

VV_SSS

VV_DDD

DD

M

D

Q

D

S

D

Q

D

Q

QPP_DD

NC

OD

NN

CC

VV_DDD

VV_SSS

N

C

NN

C

C/

/

1

8

MM

N

C

VV_SSS

NNC

C

DDQQPP_AA

NN

D

Q

S

D

Q

N

C

N

C

C/

/

7

2

M

AA

T

D

DI

I

A

1

T

D

DO

O

AA

PP

A

A00

M

O

D

E

NN

C

C/

/

3

6

M

AA

T

M

MS

S

T

C

CK

K

AA

RR

CY7C1367C (512K x 18)

1

2

3

4

5

6

7

8

9

10

11

NC/288M

NC/144M

NC

A

NC

A

B

C

D

BW_B

NC

CE₃

CLK

V_SS

CE₁

CE₂

BWE

GW

V_SS

ADSC

OE

ADV

A

BW_A

V_SS

ADSP

A

NC/576M

DQP_A

DQ_A

NC

V_DDQ

V_SS

V_DD

V_SS

V_DDQNC/1G

NC

DQ_B

V_DD

V_DDQ

NC

DQ_B

V_SS

NC

V_DDQ

NC

V_DD

V_SS

‘V_SS

V_SS

V_DD

V_DDQ

NC

DQ_A

ZZ

E

F

NC

G

H

J

NC

DQ_B

V_DDQ

DQ_A

NC

K

L

NC

DQ_B

DQP_B

NC

V_DDQ

A

V_DD

V_SS

A

V_SS

NC

V_SS

NC/18M

A1

V_SS

NC

V_DD

V_SS

A

V_DDQ

A

DQ_A

NC

A

NC

A

M

N

P

NC/72M

TDI

TDO

MODE NC/36M

A

TMS

A0

TCK

A

R

Document #: 38-05542 Rev. *E

Page 5 of 29

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CY7C1366C

CY7C1367C

Pin Definitions

Name

I/O

Description

A₀, A₁, A

Input-

Synchronous

Address Inputs used to select one of the address locations. Sampled at the rising edge of

the CLK if ADSP or ADSC is active LOW, and CE₁, CE₂, and CE₃^{[2 ]}are sampled active. A1: A0

are fed to the two-bit counter.

BW_A,BW_B

BW_C,BW_D

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.

Sampled on the rising edge of CLK.

GW

Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a

global write is conducted (ALL bytes are written, regardless of the values on BW_Xand BWE).

BWE

CLK

CE₁

Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be

asserted LOW to conduct a byte write.

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the

burst counter when ADV is asserted LOW, during a burst operation.

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE₂and CE₃^[2]to select/deselect the device. ADSP is ignored if CE₁is HIGH. CE₁is sampled

only when a new external address is loaded.

CE₂

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

CE₁and CE₃^[2]to select/deselect the device. CE₂is sampled only when a new external address

is loaded.

[2]

CE₃

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE and CE to select/deselect the device.

CE ^[2]is

Not connected for BGA. Where referenced,

3

1

assumed ac²tive throughout this document for BGA.

CE₃is sampled only when a new external address is loaded.

OE

Input-

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When

Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ pins are tri-stated, and act

as input data pins. OE is masked during the first clock of a read cycle when emerging from a

deselected state.

ADV

Input-

Synchronous

Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it

automatically increments the address in a burst cycle.

ADSP

Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When

asserted LOW, addresses presented to the device are captured in the address registers. A1: A0

are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is

recognized. ASDP is ignored when CE₁is deasserted HIGH.

ADSC

ZZ

Input-

Synchronous

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When

asserted LOW, addresses presented to the device are captured in the address registers. A1: A0

are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is

recognized.

Input-

ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical

Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or

left floating. ZZ pin has an internal pull-down.

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by the addresses presented during the previous clock rise of the read cycle. The

direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.

When HIGH, DQs and DQP_Xare placed in a tri-state condition.

DQs,

DQPs

V_DD

Power Supply Power supply inputs to the core of the device.

V_SS

Ground

Ground for the core of the device.

Ground for the I/O circuitry.

V_SSQ

V_DDQ

MODE

I/O Ground

I/O Power Supply Power supply for the I/O circuitry.

Input-

Static

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V_DDor left

floating selects interleaved burst sequence. This is a strap pin and should remain static during

device operation. Mode Pin has an internal pull-up.

Document #: 38-05542 Rev. *E

Page 6 of 29

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CY7C1366C

CY7C1367C

Pin Definitions (continued)

Name

TDO

I/O

Description

JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG

Synchronous

feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP

packages.

TDI

JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is

Synchronous

not being utilized, this pin can be disconnected or connected to V_DD. This pin is not available on

TQFP packages.

TMS

JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is

Synchronous

not being utilized, this pin can be disconnected or connected to V_DD. This pin is not available on

TQFP packages.

TCK

NC

JTAG-

Clock

Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be

connected to V_SS. This pin is not available on TQFP packages.

–

No Connects. Not internally connected to the die.18M, 36M, 72M, 144M, 288M, 576M, and 1G

are address expansion pins and are not internally connected to the die.

outputs are controlled by the OE signal. Consecutive single

read cycles are supported.

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

The CY7C1366C/CY7C1367C is a double-cycle deselect part.

Once the SRAM is deselected at clock rise by the chip select

and either ADSP or ADSC signals, its output will tri-state

immediately after the next clock rise.

The CY7C1366C/CY7C1367C supports secondary cache in

systems utilizing either a linear or interleaved burst sequence.

The interleaved burst order supports Pentium and i486™

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is user

selectable, and is determined by sampling the MODE input.

Accesses can be initiated with either the Processor Address

Strobe (ADSP) or the Controller Address Strobe (ADSC).

Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)

chip select is asserted active. The address presented is

loaded into the address register and the address

advancement logic while being delivered to the memory core.

The write signals (GW, BWE, and BW_X) and ADV inputs are

ignored during this first cycle.

ADSP triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQ_xinputs is written into the corre-

sponding address location in the memory core. If GW is HIGH,

Byte write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW_X) inputs. A Global Write

Enable (GW) overrides all byte write inputs and writes data to

all four bytes. All writes are simplified with on-chip

synchronous self-timed write circuitry.

then the write operation is controlled by BWE and

BW_X

signals. The CY7C1366C/CY7C1367C provides byte write

capability that is described in the Write Cycle Description table.

Asserting the Byte Write Enable input (BWE) with the selected

Byte Write input will selectively write to only the desired bytes.

Bytes not selected during a byte write operation will remain

unaltered. A synchronous self-timed write mechanism has

been provided to simplify the write operations.

[2]

Synchronous Chip Selects CE₁, CE₂, CE₃

and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. ADSP is ignored if CE₁

is HIGH.

Because the CY7C1366C/CY7C1367C is a common I/O

device, the Output Enable (OE) must be deasserted HIGH

before presenting data to the DQ inputs. Doing so will tri-state

the output drivers. As a safety precaution, DQ are automati-

cally tri-stated whenever a write cycle is detected, regardless

of the state of OE.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

chip selects are all asserted active, and (3) the write signals

(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE₁

is HIGH. The address presented to the address inputs is

stored into the address advancement logic and the Address

Register while being presented to the memory core. The corre-

sponding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next clock the data

is allowed to propagate through the output register and onto

the data bus within t_coif OE is active LOW. The only exception

occurs when the SRAM is emerging from a deselected state

to a selected state, its outputs are always tri-stated during the

first cycle of the access. After the first cycle of the access, the

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deasserted HIGH, (3) chip select is asserted active, and (4)

the appropriate combination of the write inputs (GW, BWE,

and

) are asserted active to conduct a write to the desired

BW_X

byte(s). ADSC triggered write accesses require a single clock

cycle to complete. The address presented is loaded into the

address register and the address advancement logic while

being delivered to the memory core. The ADV input is ignored

Document #: 38-05542 Rev. *E

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CY7C1366C

CY7C1367C

during this cycle. If a global write is conducted, the data

presented to the DQ_Xis written into the corresponding address

location in the memory core. If a byte write is conducted, only

the selected bytes are written. Bytes not selected during a byte

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CEs, ADSP, and ADSC must remain

inactive for the duration of t_ZZRECafter the ZZ input returns

LOW.

write operation will remain unaltered.

A synchronous

self-timed write mechanism has been provided to simplify the

write operations.

Because the CY7C1366C/CY7C1367C is a common I/O

device, the Output Enable (OE) must be deasserted HIGH

before presenting data to the DQ_Xinputs. Doing so will tri-state

the output drivers. As a safety precaution, DQ_Xare automati-

cally tri-stated whenever a write cycle is detected, regardless

of the state of OE.

Interleaved Burst Address Table

(MODE = Floating or V_DD

)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

Burst Sequences

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

The CY7C1366C/CY7C1367C provides a two-bit wraparound

counter, fed by A_[1:0], that implements either an interleaved or

linear burst sequence. The interleaved burst sequence is

designed specifically to support Intel Pentium applications.

The linear burst sequence is designed to support processors

that follow a linear burst sequence. The burst sequence is user

selectable through the MODE input. Both read and write burst

operations are supported.

Linear Burst Address Table (MODE = GND)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both read and write burst operations are supported.

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

ZZ Mode Electrical Characteristics

Parameter

I_DDZZ

Description

Sleep mode standby current

Device operation to ZZ

Test Conditions

ZZ > V_DD– 0.2V

Min.

Max.

Unit

mA

ns

50

t_ZZS

ZZ > V_DD– 0.2V

2t_CYC

t_ZZREC

t_ZZI

ZZ recovery time

ZZ < 0.2V

2t_CYC

0

ns

ZZ active to sleep current

ZZ Inactive to exit sleep current

This parameter is sampled

2t_CYC

ns

t_RZZI

ns

Document #: 38-05542 Rev. *E

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CY7C1366C

CY7C1367C

Partial Truth Table for Read/Write^{[5, 10]}

Function (CY7C1366C)

Read

GW

H

L

BWE

H

L

BW_D

X

H

L

BW_C

X

H

L

BW_B

BW_A

X

H

L

X

H

L

Read

Write Byte A – (DQ_Aand DQP_A)

Write Byte B – (DQ_Band DQP_B)

Write Bytes B, A

L

H

L

Write Byte C – (DQ_Cand DQP_C)

Write Bytes C, A

L

H

L

H

L

Write Bytes C, B

L

H

L

Write Bytes C, B, A

Write Byte D – (DQ_Dand DQP_D)

Write Bytes D, A

L

H

L

H

L

H

L

Write Bytes D, B

L

H

L

Write Bytes D, B, A

Write Bytes D, C

L

H

L

H

L

Write Bytes D, C, A

Write Bytes D, C, B

Write All Bytes

L

H

L

Write All Bytes

X

Truth Table for Read/Write^{[5, 10]}

Function (CY7C1367C)

Read

GW

H

BW_E

BW_B

X

BW_A

H

L

X

H

L

Read

H

Write Byte A – (DQ_Aand DQP_A)

Write Byte B – (DQ_Band DQP_B)

Write All Bytes

H

L

H

L

H

L

Write All Bytes

L

X

Document #: 38-05542 Rev. *E

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CY7C1366C

CY7C1367C

Test MODE SELECT (TMS)

IEEE 1149.1 Serial Boundary Scan (JTAG)

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this ball unconnected if the TAP is not used. The ball is

pulled up internally, resulting in a logic HIGH level.

The CY7C1366C/CY7C1367C incorporates a serial boundary

scan test access port (TAP) in the BGA package only. The

TQFP package does not offer this functionality. This part

operates in accordance with IEEE Standard 1149.1-1900, but

doesn’t have the set of functions required for full 1149.1

compliance. These functions from the IEEE specification are

excluded because their inclusion places an added delay in the

critical speed path of the SRAM. Note the TAP controller

functions in a manner that does not conflict with the operation

of other devices using 1149.1 fully compliant TAPs. The TAP

operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.

Test Data-In (TDI)

The TDI ball is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. TDI

is internally pulled up and can be unconnected if the TAP is

unused in an application. TDI is connected to the most signif-

icant bit (MSB) of any register. (See Tap Controller Block

Diagram.)

The CY7C1366C/CY7C1367C contains a TAP controller,

instruction register, boundary scan register, bypass register,

and ID register.

Test Data-Out (TDO)

Disabling the JTAG Feature

The TDO output ball is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine. The output changes on the

falling edge of TCK. TDO is connected to the least significant

bit (LSB) of any register. (See Tap Controller State Diagram.)

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(V_SS) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to V_DDthrough a pull-up resistor. TDO should be

left unconnected. Upon power-up, the device will come up in

a reset state which will not interfere with the operation of the

device.

TAP Controller Block Diagram

0

Bypass Register

TAP Controller State Diagram

2

1

0

TEST-LOGIC

1

Selection

Circuitry

Instruction Register

31 30 29

Identification Register

RESET

0

Selection

TDI

TDO

Circuitr

y

.

. 2 1

1

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

0

x

.

. 2 1

1

CAPTURE-DR

CAPTURE-IR

Boundary Scan Register

0

SHIFT-DR

0

SHIFT-IR

0

1

TCK

TMS

1

EXIT1-DR

EXIT1-IR

TAP CONTROLLER

0

PAUSE-DR

0

PAUSE-IR

0

1

Performing a TAP Reset

0

EXIT2-DR

1

EXIT2-IR

1

A RESET is performed by forcing TMS HIGH (V_DD) for five

rising edges of TCK. This RESET does not affect the operation

of the SRAM and may be performed while the SRAM is

operating.

UPDATE-DR

UPDATE-IR

1

0

1

0

At power-up, the TAP is reset internally to ensure that TDO

comes up in a High-Z state.

TAP Registers

The 0/1 next to each state represents the value of TMS at the

rising edge of TCK.

Registers are connected between the TDI and TDO balls and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time through

the instruction register. Data is serially loaded into the TDI ball

on the rising edge of TCK. Data is output on the TDO ball on

the falling edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

register. This register is loaded when it is placed between the

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CY7C1366C

CY7C1367C

TDI and TDO balls as shown in the Tap Controller Block

Diagram. Upon power-up, the instruction register is loaded

with the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.

through the instruction register through the TDI and TDO balls.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be

executed whenever the instruction register is loaded with all

0s. EXTEST is not implemented in this SRAM TAP controller,

and therefore this device is not compliant to 1149.1. The TAP

controller does recognize an all-0 instruction.

When the TAP controller is in the Capture-IR state, the two

least significant bits are loaded with a binary “01” pattern to

allow for fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

register is a single-bit register that can be placed between the

TDI and TDO balls. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

(V_SS) when the BYPASS instruction is executed.

When an EXTEST instruction is loaded into the instruction

register, the SRAM responds as if a SAMPLE/PRELOAD

instruction has been loaded. There is one difference between

the two instructions. Unlike the SAMPLE/PRELOAD

instruction, EXTEST places the SRAM outputs in a High-Z

state.

Boundary Scan Register

IDCODE

The boundary scan register is connected to all the input and

bidirectional balls on the SRAM.

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO balls and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state.

The boundary scan register is loaded with the contents of the

RAM I/O ring when the TAP controller is in the Capture-DR

state and is then placed between the TDI and TDO balls when

the controller is moved to the Shift-DR state. The EXTEST,

SAMPLE/PRELOAD and SAMPLE Z instructions can be used

to capture the contents of the I/O ring.

The IDCODE instruction is loaded into the instruction register

upon power-up or whenever the TAP controller is given a test

logic reset state.

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI and the LSB is connected to TDO.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO balls when the TAP

controller is in a Shift-DR state. It also places all SRAM outputs

into a High-Z state.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is

possible that during the Capture-DR state, an input or output

will undergo a transition. The TAP may then try to capture a

signal while in transition (metastable state). This will not harm

the device, but there is no guarantee as to the value that will

be captured. Repeatable results may not be possible.

TAP Instruction Set

Overview

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in the

Instruction Codes table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

The TAP controller used in this SRAM is not fully compliant to

the 1149.1 convention because some of the mandatory 1149.1

instructions are not fully implemented.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture set-up plus

hold times (t_CSand t_CH). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE/PRELOAD instruction. If this

is an issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK# captured in the

boundary scan register.

The TAP controller cannot be used to load address data or

control signals into the SRAM and cannot preload the I/O

buffers. The SRAM does not implement the 1149.1 commands

EXTEST or INTEST or the PRELOAD portion of

SAMPLE/PRELOAD; rather, it performs a capture of the I/O

ring when these instructions are executed.

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the

boundary scan register between the TDI and TDO pins.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

Document #: 38-05542 Rev. *E

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CY7C1366C

CY7C1367C

PRELOAD allows an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells

prior to the selection of another boundary scan test operation.

register is placed between the TDI and TDO balls. The

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

The shifting of data for the SAMPLE and PRELOAD phases

can occur concurrently when required—that is, while data

captured is shifted out, the preloaded data can be shifted in.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

BYPASS

When the BYPASS instruction is loaded in the instruction

register and the TAP is placed in a Shift-DR state, the bypass

TAP Timing

1

2

3

4

5

6

Test Clock

(TCK)

t

CYC

TH

TL

t

TMSS

TDIS

TMSH

Test Mode Select

(TMS)

TDIH

Test Data-In

(TDI)

t

TDOV

t

TDOX

Test Data-Out

(TDO)

DON’T CARE

UNDEFINED

TAP AC Switching Characteristics Over the Operating Range^{[3, 4]}

Parameter

Clock

t_TCYC

t_TF

Description

Min.

Max.

Unit

TCK Clock Cycle Time

TCK Clock Frequency

TCK Clock HIGH Time

TCK Clock LOW Time

50

ns

MHz

ns

20

t_TH

20

t_TL

ns

Output Times

t_TDOVTCK Clock LOW to TDO Valid

t_TDOXTCK Clock LOW to TDO Invalid

Set-up Times

t_TMSSTMS Set-up to TCK Clock Rise

t_TDIS

10

ns

0

5

ns

TDI Set-up to TCK Clock Rise

Capture Set-up to TCK Rise

t_CS

Hold Times

t_TMSH

t_TDIH

TMS Hold after TCK Clock Rise

TDI Hold after Clock Rise

5

ns

t_CH

Capture Hold after Clock Rise

Notes:

3. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.

CS

CH

4. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.

R

F

Document #: 38-05542 Rev. *E

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CY7C1366C

CY7C1367C

3.3V TAP AC Test Conditions

2.5V TAP AC Test Conditions

Input pulse levels ............................................... V_SSto 3.3V

Input rise and fall times................................................... 1 ns

Input timing reference levels...........................................1.5V

Output reference levels...................................................1.5V

Test load termination supply voltage...............................1.5V

Input pulse levels ................................................V_SSto 2.5V

Input rise and fall time .....................................................1 ns

Input timing reference levels......................................... 1.25V

Output reference levels ................................................ 1.25V

Test load termination supply voltage ............................ 1.25V

3.3V TAP AC Output Load Equivalent

2.5V TAP AC Output Load Equivalent

1.5V

1.25V

50Ω

TDO

Z_O= 50Ω

20pF

TAP DC Electrical Characteristics And Operating Conditions

(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)^[5]

Parameter

V_OH1

Description

Conditions

V_DDQ= 3.3V

Min.

2.4

2.0

2.9

2.1

Max.

Unit

V

Output HIGH Voltage I_OH= –4.0 mA

I

_OH= –1.0 mA

V_DDQ= 2.5V

V_DDQ= 3.3V

V_DDQ= 2.5V

V_DDQ= 3.3V

V_DDQ= 2.5V

V_DDQ= 3.3V

V

V_OH2

V_OL1

V_OL2

V_IH

Output HIGH Voltage I_OH= –100 µA

V

Output LOW Voltage I_OL= 8.0 mA

0.4

V

I

_OL= 8.0 mA

V

Output LOW Voltage I_OL= 100 µA

0.2

V

V_DDQ= 2.5V

0.2

V

Input HIGH Voltage

V_DDQ= 3.3V

V_DDQ= 2.5V

V_DDQ= 3.3V

2.0

1.7

V_DD+ 0.3

0.7

V

V_IL

Input LOW Voltage

–0.5

–0.3

–5

V

V_DDQ= 2.5V

0.7

V

I_X

Input Load Current

GND < V_IN< V_DDQ

5

µA

Identification Register Definitions

CY7C1366C

CY7C1367C

(512K x18)

Instruction Field

Revision Number (31:29)

Device Depth (28:24)^[6]

(256K x36)

Description

000

Describes the version number.

Reserved for Internal Use

01011

101110

000110

010110

Device Width (23:18) 119-BGA

Device Width (23:18) 165-FBGA

Cypress Device ID (17:12)

Cypress JEDEC ID Code (11:1)

ID Register Presence Indicator (0)

101110

000110

100110

00000110100

1

Defines memory type and architecture

Defines width and density

00000110100 Allows unique identification of SRAM vendor.

Indicates the presence of an ID register.

1

Notes:

5. All voltages referenced to V (GND).

SS

6. Bit #24 is “1” in the Register Definitions for both 2.5V and 3.3V versions of this device.

Document #: 38-05542 Rev. *E

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CY7C1366C

CY7C1367C

Scan Register Sizes

Register Name

Bit Size (x36)

Bit Size (x18)

Instruction

3

Bypass

1

ID

32

71

32

71

Boundary Scan Order (119-ball BGA package)

Boundary Scan Order (165-ball FBGA package)

Identification Codes

Instruction

EXTEST

Code

Description

000

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM outputs to High-Z state.

IDCODE

001

010

Loads the ID register with the vendor ID code and places the register between TDI and

TDO. This operation does not affect SRAM operations.

SAMPLE Z

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED

011

100

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation.

RESERVED

BYPASS

101

110

111

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

Document #: 38-05542 Rev. *E

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CY7C1366C

CY7C1367C

119-Ball BGA Boundary Scan Order

CY7C1366C (256K x 36)

CY7C1367C (512K x 18)

Signal

Name

Signal

Name

Bit # ball ID

Name

CLK

GW

BWE

OE

Bit # ball ID

Bit #

1

ball ID

Name

CLK

GW

Bit #

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

ball ID

1

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

P4

N4

R6

T5

A0

A1

P4

A0

K4

H4

M4

F4

B4

A4

G4

C3

B3

D6

H7

G6

E6

D7

E7

F6

G7

H6

T7

K7

L6

K4

H4

2

N4

A1

3

A

3

M4

BWE

OE

R6

A

4

A

4

F4

T5

A

5

ADSC

ADSP

ADV

A

T3

A

5

B4

ADSC

ADSP

ADV

A

T3

A

6

R2

R3

P2

A

6

A4

R2

A

7

MODE

DQP_D

DQ_D

Internal

DQ_C

DQP_C

A

7

G4

R3

MODE

Internal

DQP_B

DQ_B

8

C3

Internal

P2

9

A

P1

9

B3

A

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

DQP_B

DQ_B

ZZ

L2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

T2

A

K1

Internal

D6

Internal

DQP_A

DQ_A

ZZ

N2

N1

M2

L1

N1

M2

DQ_B

E7

L1

DQ_B

K2

F6

K2

DQ_B

Internal

H1

G2

E2

G7

Internal

H1

Internal

DQ_B

H6

T7

G2

DQ_B

DQ_A

DQP_A

A

K7

DQ_A

Internal

A

E2

DQ_B

D1

H2

G1

F2

L6

D1

DQ_B

N6

P7

N7

M6

L7

N6

Internal

C2

Internal

A

P7

Internal

T6

E1

D2

C2

A2

K6

P6

T4

A3

C5

B5

A5

C6

A6

B6

A

A2

A

E4

CE₁

CE₂

BWD

BW_C

BW_B

BW_A

Internal

E4

CE₁

A

B2

A3

A

B2

CE₂

A

L3

C5

A

Internal

G3

Internal

BW_B

BW_A

Internal

A

G3

G5

L5

B5

A

A5

A

C6

A

L5

A

Internal

A6

A

Internal

A

B6

A

Document #: 38-05542 Rev. *E

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CY7C1366C

CY7C1367C

165-Ball FBGA Boundary Scan Order

CY7C1366C (256K x 36)

CY7C1367C (512K x 18)

Signal

Name

Signal

Name

Signal

Name

Bit # ball ID

Name

CLK

GW

BWE

OE

Bit #

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

ball ID

R6

P6

R4

P4

R3

P3

R1

N1

L2

Bit #

1

ball ID

B6

Bit #

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

ball ID

R6

1

B6

B7

A0

A1

CLK

GW

A0

A1

2

B7

P6

3

A7

A

3

A7

BWE

OE

R4

A

4

B8

A

4

B8

P4

A

5

A8

ADSC

ADSP

ADV

A

5

A8

ADSC

ADSP

ADV

A

R3

A

6

B9

A

6

B9

P3

A

7

A9

MODE

DQP_D

DQ_D

Internal

DQ_C

DQP_C

A

7

A9

R1

MODE

Internal

DQP_B

DQ_B

8

B10

A10

C11

E10

F10

G10

D10

D11

E11

F11

G11

H11

J10

K10

L10

M10

J11

K11

L11

M11

N11

R11

R10

P10

R9

8

B10

Internal

N1

9

A

9

A10

A

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

DQP_B

DQ_B

ZZ

K2

J2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

A11

A

Internal

C11

Internal

DQP_A

DQ_A

ZZ

M2

M1

L1

M1

L1

DQ_B

K1

J1

D11

K1

DQ_B

E11

J1

DQ_B

Internal

G2

F2

F11

Internal

G2

Internal

DQ_B

G11

H11

F2

DQ_B

DQ_A

DQP_A

A

E2

D2

G1

F1

J10

DQ_A

Internal

A

E2

DQ_B

K10

D2

DQ_B

L10

Internal

B2

Internal

A

M10

Internal

R11

E1

D1

C1

B2

A2

A3

B3

B4

A4

A5

B5

A6

A

A2

A

CE₁

CE₂

BW_D

BW_C

BW_B

BW_A

CE₃

A3

CE₁

A

R10

P10

A

B3

CE₂

A

Internal

A4

Internal

BW_B

BW_A

CE₃

A

R9

A

P9

A

P9

A

R8

A

R8

A

B5

P8

A

P8

A

A6

P11

A

P11

A

Document #: 38-05542 Rev. *E

Page 16 of 29

[+] Feedback

CY7C1366C

CY7C1367C

DC Input Voltage ................................... –0.5V to V_DD+ 0.5V

Current into Outputs (LOW)......................................... 20 mA

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Storage Temperature .................................–65°C to +150°C

Latch-up Current.................................................... > 200 mA

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Operating Range

Supply Voltage on V_DDRelative to GND........ –0.5V to +4.6V

Supply Voltage on V_DDQRelative to GND ......–0.5V to +V_DD

Ambient

Temperature

Range

V_DD

V_DDQ

DC Voltage Applied to Outputs

in tri-state ............................................ –0.5V to V_DDQ+ 0.5V

Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%

to V_DD

Industrial

–40°C to +85°C

Electrical Characteristics Over the Operating Range ^{[7, 8]}

Parameter

V_DD

Description

Power Supply Voltage

I/O Supply Voltage

Test Conditions

Min.

3.135

2.375

2.4

Max.

3.6

Unit

V

V_DDQ

for 3.3V I/O

for 2.5V I/O

V_DD

V

2.625

V

V_OH

V_OL

V_IH

V_IL

I_X

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage^[7]

Input LOW Voltage^[7]

for 3.3V I/O, I_OH= −4.0 mA

for 2.5V I/O, I_OH= −1.0 mA

for 3.3V I/O, I_OL= 8.0 mA

for 2.5V I/O, I_OL= 1.0 mA

for 3.3V I/O

V

2.0

V

0.4

V

2.0

1.7

V_DD+ 0.3V

V

for 2.5V I/O

V

_DD+ 0.3V

V

for 3.3V I/O

–0.3

–5

0.8

0.7

5

V

for 2.5V I/O

V

Input Leakage Current GND ≤ V_I≤ V_DDQ

except ZZ and MODE

µA

Input Current of MODE Input = V_SS

Input = V_DD

–30

–5

µA

5

Input Current of ZZ

Input = V_SS

Input = V_DD

µA

30

5

µA

I_OZ

I_DD

Output Leakage Current GND ≤ V_I≤ V_DDQ,Output Disabled

–5

µA

V_DDOperating Supply V_DD= Max., I_OUT= 0 mA,

4-ns cycle, 250 MHz

5-ns cycle, 200 MHz

6-ns cycle, 166 MHz

4-ns cycle, 250 MHz

5-ns cycle, 200 MHz

6-ns cycle, 166 MHz

All speeds

250

220

180

130

120

110

40

mA

Current

f = f_MAX= 1/t_CYC

I_SB1

Automatic CE

Power-down

Current—TTL Inputs

V_DD= Max, Device Deselected,

V_IN≥ V_IHor V_IN≤ V_IL

f = f_MAX= 1/t_CYC

I_SB2

Automatic CE

Power-down

Current—CMOS Inputs f = 0

V_DD= Max, Device Deselected,

V_IN≤ 0.3V or V_IN> V_DDQ– 0.3V,

I_SB3

Automatic CE

Power-down

Current—CMOS Inputs f = f_MAX= 1/t_CYC

V_DD= Max, Device Deselected, or 4-ns cycle, 250 MHz

120

110

100

40

mA

V_IN≤ 0.3V or V_IN> V_DDQ– 0.3V

5-ns cycle, 200 MHz

6-ns cycle, 166 MHz

All Speeds

I_SB4

Automatic CE

Power-down

Current—TTL Inputs

V_DD= Max, Device Deselected,

V_IN≥ V_IHor V_IN≤ V_IL, f = 0

Notes:

7. Overshoot: V (AC) < V +1.5V (Pulse width less than t

/2), undershoot: V (AC) > –2V (Pulse width less than t

/2).

IH

DD

CYC

IL

CYC

8. TPower-up: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V

< V

DD

IH

DD

DDQ

DD.

Document #: 38-05542 Rev. *E

Page 17 of 29

[+] Feedback

CY7C1366C

CY7C1367C

Capacitance^[9]

100 TQFP

Max.

119 BGA

Max.

165 FBGA

Parameter

C_IN

Description

Input Capacitance

Test Conditions

Max.

Unit

pF

T_A= 25°C, f = 1 MHz,

5

7

5

7

V_DD= 3.3V.

C_CLK

Clock Input Capacitance

Input/Output Capacitance

pF

V_DDQ= 2.5V

C_I/O

pF

Thermal Resistance^[9]

100 TQFP

Package

119 BGA

Package

165 FBGA

Package

Parameter

Description

Test Conditions

Unit

Θ_JA

Thermal Resistance

(Junction to Ambient)

Test conditions follow standard

test methods and procedures

for measuring thermal

29.41

34.1

16.8

°C/W

Θ_JC

Thermal Resistance

(Junction to Case)

6.31

14.0

3.0

°C/W

impedance, per EIA/JESD51.

AC Test Loads and Waveforms

3.3V I/O Test Load

R = 317Ω

3.3V

OUTPUT

ALL INPUT PULSES

90%

V_DDQ

90%

10%

Z = 50Ω

0

10%

R = 50Ω

L

GND

5 pF

R = 351Ω

≤ 1ns

V = 1.5V

T

INCLUDING

JIG AND

SCOPE

(c)

(a)

(b)

2.5V I/O Test Load

R = 1667Ω

2.5V

OUTPUT

R = 50Ω

OUTPUT

ALL INPUT PULSES

90%

V_DDQ

GND

90%

10%

Z = 50Ω

0

10%

L

5 pF

R =1538Ω

≤ 1ns

V = 1.25V

T

INCLUDING

JIG AND

SCOPE

(c)

(a)

(b)

Note:

9. Tested initially and after any design or process change that may affect these parameters.

Document #: 38-05542 Rev. *E

Page 18 of 29

[+] Feedback

CY7C1366C

CY7C1367C

Switching Characteristics Over the Operating Range^{[14, 15]}

–250

–200

166 MHz

Parameter

t_POWER

Clock

t_CYC

Description

V_DD(Typical) to the first Access^[10]

Min.

Max.

Min.

Max.

Min.

Max.

Unit

1

ms

Clock Cycle Time

Clock HIGH

4.0

1.8

5.0

2.0

6.0

2.4

ns

t_CH

t_CL

Clock LOW

Output Times

t_CO

Data Output Valid After CLK Rise

Data Output Hold After CLK Rise

Clock to Low-Z^{[11, 12, 13]}

2.8

3.0

3.5

ns

t_DOH

1.25

t_CLZ

t_CHZ

Clock to High-Z^{[11, 12, 13]}

2.8

3.0

3.5

t_OEV

OE LOW to Output Valid

t_OELZ

t_OEHZ

Set-up Times

t_AS

OE LOW to Output Low-Z^{[11, 12, 13]}

OE HIGH to Output High-Z^{[11, 12, 13]}

0

2.8

3.0

3.5

Address Set-up Before CLK Rise

ADSC, ADSP Set-up Before CLK Rise

ADV Set-up Before CLK Rise

1.4

1.5

ns

t_ADS

t_ADVS

t_WES

GW, BWE, BW_XSet-up Before CLK Rise

Data Input Set-up Before CLK Rise

Chip Enable Set-up Before CLK Rise

t_DS

t_CES

Hold Times

t_AH

Address Hold After CLK Rise

ADSP, ADSC Hold After CLK Rise

ADV Hold After CLK Rise

0.4

0.5

ns

t_ADH

t_ADVH

t_WEH

GW, BWE, BW_XHold After CLK Rise

Data Input Hold After CLK Rise

Chip Enable Hold After CLK Rise

t_DH

t_CEH

Notes:

10. This part has a voltage regulator internally; t

is the time that the power needs to be supplied above V (minimum) initially before a read or write operation

DD

POWER

can be initiated.

11. t

, t

,t

, and t

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

CHZ CLZ OELZ

OEHZ

12. At any given voltage and temperature, t

is less than t

and t

is less than t

to eliminate bus contention between SRAMs when sharing the same

CLZ

OEHZ

OELZ

CHZ

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

13. This parameter is sampled and not 100% tested.

14. Timing reference level is 1.5V when V

= 3.3V and is 1.25V when V

= 2.5V.

DDQ

15. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

Document #: 38-05542 Rev. *E

Page 19 of 29

[+] Feedback

CY7C1366C

CY7C1367C

Switching Waveforms

Read Cycle Timing^[16]

t

CYC

CLK

t

CL

CH

t

ADH

ADS

ADSP

ADSC

t

ADH

ADS

t

AH

AS

A1

A2

A3

ADDRESS

Burst continued with

new base address

t

WEH

WES

GW, BWE,BW_X

Deselect

cycle

t

CEH

CES

CE

t

ADVH

ADVS

ADV

OE

ADV suspends burst

t

OEV

CO

t

CHZ

t

OELZ

OEHZ

DOH

CLZ

t

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

Q(A2)

Q(A2 + 1)

Q(A3)

Q(A1)

Data Out (DQ)

High-Z

CO

Burst wraps around

to its initial state

Single READ

BURST READ

DON’T CARE

UNDEFINED

Note:

16. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.

1

2

3

1

2

3

Document #: 38-05542 Rev. *E

Page 20 of 29

[+] Feedback

CY7C1366C

CY7C1367C

Switching Waveforms (continued)

Write Cycle Timing^{[16, 17]}

t

CYC

CLK

t

CL

CH

t

ADH

ADS

ADSP

ADSC

ADSC extends burst

t

ADH

ADS

t

ADH

ADS

t

AH

AS

A1

A2

A3

ADDRESS

BWE,

Byte write signals are ignored for first cycle when

ADSP initiates burst

t

WEH

WES

BW

X

t

WEH

WES

GW

CE

t

CEH

CES

t

ADVH

ADVS

ADV

OE

ADV suspends burst

t

DH

DS

D(A2)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

D(A1)

High-Z

Data in (D)

t

OEHZ

Data Out (Q)

BURST READ

BURST WRITE

DON’T CARE

Single WRITE

Extended BURST WRITE

UNDEFINED

Note:

17.

Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.

X

Document #: 38-05542 Rev. *E

Page 21 of 29

[+] Feedback

CY7C1366C

CY7C1367C

Switching Waveforms (continued)

Read/Write Cycle Timing^{[16, 18, 19]}

t

CYC

CLK

t

CL

CH

t

ADH

ADS

ADSP

ADSC

t

AH

AS

A1

A2

A3

A4

A5

A6

ADDRESS

t

WEH

WES

BWE, BW

X

t

CEH

CES

CE

ADV

OE

t

DH

t

CO

DS

t

OELZ

Data In (D)

High-Z

D(A3)

D(A5)

D(A6)

t

OEHZ

CLZ

Data Out (Q)

Q(A1)

Back-to-Back READs

Q(A2)

Q(A4)

Q(A4+1)

Q(A4+2)

Q(A4+3)

BURST READ

Back-to-Back

Single WRITE

DON’T CARE

WRITEs

UNDEFINED

Notes:

18. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

19. GW is HIGH.

Document #: 38-05542 Rev. *E

Page 22 of 29

[+] Feedback

CY7C1366C

CY7C1367C

Switching Waveforms (continued)

ZZ Mode Timing^{[20, 21]}

CLK

t

ZZ

ZZREC

ZZ

t

ZZI

I

SUPPLY

I

DDZZ

t

RZZI

ALL INPUTS

(except ZZ)

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

Notes:

20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

21. DQs are in high-Z when exiting ZZ sleep mode.

Document #: 38-05542 Rev. *E

Page 23 of 29

[+] Feedback

CY7C1366C

CY7C1367C

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz)

Package

Diagram

Operating

Range

Ordering Code

CY7C1366C-166AXC

CY7C1367C-166AXC

CY7C1366C-166BGC

CY7C1367C-166BGC

Part and Package Type

166

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1366C-166BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1367C-166BGXC

CY7C1366C-166BZC

CY7C1367C-166BZC

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1366C-166BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1367C-166BZXC

CY7C1366C-166AXI

CY7C1367C-166AXI

CY7C1366C-166BGI

CY7C1367C-166BGI

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1366C-166BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1367C-166BGXI

CY7C1366C-166BZI

CY7C1367C-166BZI

CY7C1366C-166BZXI

CY7C1367C-166BZXI

CY7C1366C-200AXC

CY7C1367C-200AXC

CY7C1366C-200BGC

CY7C1367C-200BGC

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

200

Commercial

CY7C1366C-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1367C-200BGXC

CY7C1366C-200BZC

CY7C1367C-200BZC

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1366C-200BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1367C-200BZXC

CY7C1366C-200AXI

CY7C1367C-200AXI

CY7C1366C-200BGI

CY7C1367C-200BGI

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1366C-200BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1367C-200BGXI

CY7C1366C-200BZI

CY7C1367C-200BZI

CY7C1366C-200BZXI

CY7C1367C-200BZXI

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

Document #: 38-05542 Rev. *E

Page 24 of 29

[+] Feedback

CY7C1366C

CY7C1367C

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

250

CY7C1366C-250AXC

CY7C1367C-250AXC

CY7C1366C-250BGC

CY7C1367C-250BGC

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1366C-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1367C-250BGXC

CY7C1366C-250BZC

CY7C1367C-250BZC

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1366C-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1367C-250BZXC

CY7C1366C-250AXI

CY7C1367C-250AXI

CY7C1366C-250BGI

CY7C1367C-250BGI

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1366C-250BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1367C-250BGXI

CY7C1366C-250BZI

CY7C1367C-250BZI

CY7C1366C-250BZXI

CY7C1367C-250BZXI

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

Document #: 38-05542 Rev. *E

Page 25 of 29

[+] Feedback

CY7C1366C

CY7C1367C

Package Diagrams

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)

16.00 0.20

14.00 0.10

1.40 0.05

100

81

80

1

0.30 0.08

0.65

TYP.

12° 1°

(8X)

SEE DETAIL

A

30

51

31

50

0.20 MAX.

1.60 MAX.

R 0.08 MIN.

0.20 MAX.

0° MIN.

SEATING PLANE

STAND-OFF

0.05 MIN.

0.15 MAX.

NOTE:

1. JEDEC STD REF MS-026

0.25

GAUGE PLANE

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

R 0.08 MIN.

0.20 MAX.

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

0°-7°

0.60 0.15

0.20 MIN.

51-85050-*B

1.00 REF.

DETAIL

A

Document #: 38-05542 Rev. *E

Page 26 of 29

[+] Feedback

CY7C1366C

CY7C1367C

Package Diagrams (continued)

119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)

Ø0.05 M C

Ø0.25 M C A B

A1 CORNER

Ø0.75 0.15(119X)

Ø1.00(3X) REF.

1

2

3

4

5

6

7

6

5

4

3

2

1

A

B

C

D

E

A

B

C

D

E

F

G

H

G

H

J

K

L

J

K

L

M

N

P

R

T

M

N

P

R

T

U

1.27

0.70 REF.

A

3.81

12.00

7.62

B

14.00 0.20

0.15(4X)

30° TYP.

51-85115-*B

SEATING PLANE

C

Document #: 38-05542 Rev. *E

Page 27 of 29

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CY7C1366C

CY7C1367C

Package Diagrams (continued)

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D

165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)

BOTTOM VIEW

PIN 1 CORNER

TOP VIEW

Ø0.05 M C

Ø0.25 M C A B

PIN 1 CORNER

-0Ø.060.25 M C A B

Ø0.50 (165X)

+0.14

-0.06

Ø0.50₃

(165X)

1

2

3

4

5

6

7

8

9

10

11

11 10

9

8

7

6

5

4

2

+0.14

1

2

3

4

5

6

7

8

9

10

11

11 10

9

8

7

6

5

4

3

2

1

A

B

A

B

C

D

B

C

D

C

D

C

D

E

F

G

H

J

H

J

H

J

H

J

K

L

M

N

P

R

N

P

R

N

P

R

N

P

R

A

1.00

5.00

A

1.00

5.00

10.00

B

13.00 0.10

B

13.00 0.10

B

13.00 0.10

0.15(4X)

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

PACKAGE WEIGHT : 0.475g

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE WEIGHT : 0.475g

PACKAJEGDEECCORDEEFE:RBEBN0ACEC: MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

SEATING PLANE

C

51-85180-*A

C

51-85180-*A

i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM

Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05542 Rev. *E

Page 28 of 29

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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CY7C1366C

CY7C1367C

Document History Page

Document Title: CY7C1366C/CY7C1367C 9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM

Document Number: 38-05542

Orig. of

REV.

**

ECN NO.

241690

278969

332059

Issue Date

See ECN

Change

Description of Change

RKF

New data sheet

*A

RKF

Changed Boundary Scan order to match the B rev of these devices

*B

PCI

Changed 225-MHz to 250 MHz Speed bins

Changed t_CYCfor 250 MHz from 4.4 ns to 4.0 ns

Unshaded 200 and 166 MHz speed bins in the AC/DC Table and Selection

Guide

Address expansion pins/balls in the pinouts for all packages are modified as

per JEDEC standard

Added Address Expansion pins in the Pin Definitions Table

Changed Device Width (23:18) for 119-BGA from 000110 to 101110

Added separate row for 165 -FBGA Device Width (23:18)

Included ZZ Mode Electrical Characteristics table

Modified V_OL,V_OHtest conditions

Changed I_DDZZfrom 35 mA to 50 mA

Changed I_SB1from 50 mA to 130, 120 and 110 mA for 250, 200 and 166 MHz

Changed I_SB3from 50 mA to 120, 110 and 100 mA for 250, 200 and 166 MHz

^ChangedΘ_JAand Θ_JCfrom 25 and 9 °C/W to 29.41 and 6.31 °C/W respec-

tively for 100 TQFP Package

Changed Θ_JAand Θ_JCfrom 25 and 6 °C/W to 34.1 and 14.0 °C/W respec-

tively for 119 BGA Package

^ChangedΘ_JAandΘ_JCfrom 27 and 6 °C/W to 16.8 and 3.0 °C/W respectively

for 165 FBGA Package

Added lead-free information for 100-pin TQFP, 119 BGA and 165 FBGA

packages

Updated Ordering Information Table

*C

*D

377095

408298

See ECN

PCI

Changed I_SB2from 30 to 40 mA

Modified test condition in note# 8 from V_IH< V_DDto V_IH< V_DD

RXU

Changed address of Cypress Semiconductor Corporation on Page# 1 from

“3901 North First Street” to “198 Champion Court”

Converted from Preliminary to Final

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristics Table

Replaced Package Name column with Package Diagram in the Ordering

Information table

Updated the ordering information

*E

501793

See ECN

VKN

Added the Maximum Rating for Supply Voltage on V_DDQRelative to GND.

Changed t_TH, t_TLfrom 25 ns to 20 ns and t_TDOVfrom 5 ns to 10 ns in TAP AC

Switching Characteristics table.

Updated the Ordering Information table.

Document #: 38-05542 Rev. *E

Page 29 of 29

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型号：	CY7C1367C-166BZI
厂家：	CYPRESS
描述：	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM 9兆位（ 256K ×36 / 512K ×18 ）流水线DCD同步SRAM 静态存储器 CD
文件：	总29页 (文件大小：544K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C1367C-166BZI [CYPRESS]

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