CY7C1380CV25-225AC [CYPRESS]
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; 18兆位（ 512K ×36 / 1M ×18 ）流水线SRAM
| 型号： | CY7C1380CV25-225AC |
| 厂家： | 
CYPRESS |
| 描述： | 18-Mbit (512K x 36/1M x 18) Pipelined SRAM |
| 文件： | 总33页 (文件大小：511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1380CV25
CY7C1382CV25
18-Mbit (512K x 36/1M x 18) Pipelined SRAM
Features
Functional Description[1]
• Supports bus operation up to 250 MHz
The CY7C1380CV25/CY7C1382CV25 SRAM integrates
524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
• Available speed grades are 250, 225, 200,166 and
133 MHz
• Registered inputs and outputs for pipelined operation
• 2.5V core power supply
• Fast clock-to-output times
inputs, address-pipelining Chip Enable
(
), depth-
CE1
[2]
expansion Chip Enables (CE2 and
), Burst Control
CE3
— 2.6 ns (for 250-MHz device)
inputs ( ,
and
ADSC ADSP
,
), Write Enables ( , and
ADV
BWX
— 2.8 ns (for 225-MHz device)
), and Global Write (
BWE
). Asynchronous inputs include
GW
— 3.0 ns (for 200-MHz device)
the Output Enable ( ) and the ZZ pin.
OE
— 3.4 ns (for 166-MHz device)
Addresses and chip enables are registered at rising edge of
— 4.2 ns (for 133-MHz device)
clock when either Address Strobe Processor (
) or
ADSP
Address Strobe Controller (
) are active. Subsequent
ADSC
• Provide high-performance 3-1-1-1 access rate
burst addresses can be internally generated as controlled by
the Advance pin ( ).
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
ADV
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
controlled by the byte write control inputs.
when active
GW
• Single Cycle Chip Deselect
causes all bytes to be written.
LOW
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA
The CY7C1380CV25/CY7C1382CV25 operates from a +2.5V
core power supply. All outputs also operate with a +2.5 supply.
All inputs and outputs are JEDEC-standard JESD8-5-
compatible.
and 165-Ball fBGA packages
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
Selection Guide
250 MHz
225 MHz
2.8
200 MHz
3.0
167 MHz
3.4
133 MHz
4.2
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
2.6
350
70
325
70
300
70
275
70
245
70
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Notes:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE , CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.
3
2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05240 Rev. *C
Revised May 11, 2004
CY7C1380CV25
CY7C1382CV25
1
Logic Block Diagram – CY7C1380CV25 (512K x 36)
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER
AND
CLR
Q0
LOGIC
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D ,DQPD
DQ
BYTE
WRITE DRIVER
D ,DQPD
BW
D
DQC ,DQP
BYTE
WRITE DRIVER
C
DQC ,DQP
BYTE
WRITE REGISTER
C
BW
C
OUTPUT
BUFFERS
OUTPUT
REGISTERS
MEMORY
ARRAY
DQ s
SENSE
AMPS
DQPA
DQB ,DQP
BYTE
WRITE DRIVER
B
E
DQB ,DQP
BYTE
WRITE REGISTER
B
DQP
DQP
B
C
BW
BW
B
A
DQPD
DQ
BYTE
WRITE DRIVER
A ,DQPA
DQ
A ,DQPA
BYTE
WRITE REGISTER
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
2
Logic Block Diagram – CY7C1382CV25 (1M x 18)
ADDRESS
A0, A1, A
REGISTER
A[1:0]
2
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQB,DQP
B
DQB,DQP
WRITE REGISTER
B
WRITE DRIVER
OUTPUT
BUFFERS
BW
B
A
DQs
DQP
DQP
OUTPUT
REGISTERS
SENSE
AMPS
MEMORY
ARRAY
A
B
DQA,DQP
A
E
DQA,DQP
WRITE REGISTER
A
WRITE DRIVER
BW
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE1
CE2
PIPELINED
ENABLE
CE3
OE
ZZ
SLEEP
CONTROL
3
Document #: 38-05240 Rev. *C
Page 2 of 33
CY7C1380CV25
CY7C1382CV25
Pin Configurations
100-pin TQFP Pinout
DQPC
1
DQP
B
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
A
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
DQB
B
2
NC
2
DQc
VDDQ
VSSQ
DQ
3
NC
NC
3
VDDQ
4
VDDQ
VSSQ
NC
VDDQ
VSSQ
NC
4
VSSQ
5
5
DQ
DQ
DQ
C
DQ
DQ
DQ
DQ
B
B
B
B
6
6
C
C
7
NC
DQP
A
7
8
DQ
B
B
DQ
A
A
8
DQ
C
9
DQ
DQ
9
VSSQ
VDDQ
VSSQ
VDDBQ
DQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSSQ
VSSQ
VDDAQ
DQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
DQ
C
DQ
B
B
DQ
C
DQ
B
DQ
DQ
A
NC
VDD
NC
VSS
NC
VDD
ZZ
NC
VDD
NC
VSS
NC
VDD
ZZ
CY7C1382CV25
(1M x 18)
CY7C1380CV25
(512K X 36)
VSDS
VSBS
DQ
DQ
A
DQ
DQ
A
A
DQ
D
DQA
DQ
B
DQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
DQ
D
DQ
DQ
DQ
DQ
A
A
A
A
DQ
B
B
B
DQ
DQ
NC
NC
A
A
DQ
D
DQ
DQ
D
DQP
DQ
D
NC
VSSQ
VDDQ
NC
VSSQ
VDDQ
VSSQ
VDDAQ
DQ
VSSQ
VDDQ
NC
DQ
D
DQ
D
DQA
NC
NC
DQPD
DQP
A
NC
NC
Document #: 38-05240 Rev. *C
Page 3 of 33
CY7C1380CV25
CY7C1382CV25
Pin Configurations (continued)
119-ball BGA (1 Chip Enable with JTAG)
CY7C1380CV25 (512K x 36)
1
2
3
4
5
6
7
VDDQ
A
A
A
A
VDDQ
A
B
C
ADSP
ADSC
VDD
NC
NC
A
A
A
A
A
A
A
A
NC
NC
DQC
DQC
VDDQ
DQPC
DQC
DQC
VSS
VSS
VSS
NC
CE1
VSS
VSS
VSS
DQPB
DQB
DQB
DQB
DQB
VDDQ
D
E
F
OE
DQC
DQC
VDDQ
DQD
DQD
VDDQ
DQD
DQC
DQC
VDD
BWC
VSS
NC
BWB
VSS
NC
DQB
DQB
VDD
DQA
DQA
DQA
DQA
DQB
DQB
VDDQ
DQA
DQA
VDDQ
DQA
G
H
J
ADV
GW
VDD
CLK
NC
BWE
A1
DQD
VSS
VSS
K
L
M
N
DQD
DQD
DQD
BWD
VSS
VSS
BWA
VSS
VSS
P
R
DQD
NC
DQPD
A
VSS
MODE
A0
VDD
VSS
NC
DQPA
A
DQA
NC
T
U
NC
VDDQ
NC / 72M
TMS
A
TDI
A
TCK
A
TDO
NC / 36M
NC
ZZ
VDDQ
CY7C1382CV25 (1M x 18)
2
A
A
1
3
A
A
4
5
A
A
6
A
A
7
A
B
C
D
E
F
VDDQ
NC
NC
DQB
NC
VDDQ
VDDQ
NC
NC
NC
DQA
VDDQ
ADSP
ADSC
VDD
NC
CE1
A
A
A
A
NC
DQB
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQPA
NC
DQA
OE
G
H
J
NC
DQB
VDDQ
DQB
NC
VDD
VSS
VSS
NC
NC
DQA
VDD
DQA
NC
VDDQ
BWB
VSS
NC
ADV
GW
VDD
NC
DQB
VSS
CLK
NC
BWE
A1
VSS
NC
DQA
NC
DQA
NC
DQA
K
L
M
N
P
DQB
VDDQ
DQB
NC
NC
DQB
NC
VSS
VSS
VSS
VSS
NC
VDDQ
NC
BWA
VSS
VSS
VSS
DQPB
A0
DQA
R
T
U
NC
NC / 72M
VDDQ
A
A
TMS
MODE
A
TDI
VDD
NC / 36M
TCK
NC
A
TDO
A
A
NC
NC
ZZ
VDDQ
Document #: 38-05240 Rev. *C
Page 4 of 33
CY7C1380CV25
CY7C1382CV25
Pin Configurations (continued)
165-ball fBGA
CY7C1380CV25 (512K x 36)
1
NC / 288M
NC
DQPC
DQC
2
3
4
5
6
7
8
9
10
11
NC
NC / 144M
DQPB
DQB
A
A
B
C
D
E
F
G
H
J
K
L
CE1
BWC
BWD
VSS
VDD
BWB
BWA
VSS
VSS
CE3
CLK
VSS
VSS
ADSC
A
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A
NC
DQC
DQC
DQC
DQC
VSS
DQD
DQD
DQD
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
A
NC
DQB
DQB
DQB
DQB
NC
DQA
DQA
DQA
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DQC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQB
DQC
DQC
NC
DQD
DQD
DQD
DQB
DQB
ZZ
DQA
DQA
DQA
VDDQ
VDDQ
VDDQ
DQD
DQPD
NC
DQD
NC
NC / 72M
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
A
A1
VSS
NC
TDO
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
A0
MODE NC / 36M
A
A
TMS
TCK
A
A
A
A
R
CY7C1382CV25 (1M x 18)
1
NC / 288M
NC
2
3
CE1
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
4
BWB
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
5
6
7
8
9
10
11
A
A
NC
A
A
CE
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ADSC
OE
VSS
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
3
A
NC
DQB
DQB
DQB
DQB
VSS
NC
NC
NC
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
NC
NC
NC
NC
NC
NC / 144M
DQPA
DQA
B
C
D
E
F
G
H
J
K
L
NC
NC
NC
NC
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DQA
DQA
DQA
ZZ
NC
NC
NC
NC
DQB
DQB
DQB
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
DQB
DQPB
NC
NC
NC
NC / 72M
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
A
A1
VSS
NC
TDO
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
MODE NC / 36M
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05240 Rev. *C
Page 5 of 33
CY7C1380CV25
CY7C1382CV25
CY7C1380CV25–Pin Definitions
Name
TQFP
BGA
fBGA
I/O
Description
A0, A1, A
37,36,32,
33,34,35,
42,43,44,45,
46,47,48,
49,50,81,
82,99,100
P4,N4,
R6,P6,A2,
Input-
Address Inputs used to select one of the
A2,B2,
A10,B2,
Synchronous address locations. Sampled at the rising edge
C2,R2,
B10,N6,P3,P4,
P8,P9,P10,
P11,R3,R4,R8,
R9,R10,R11
of the CLK if
or is active LOW, and
ADSP ADSC
A3,B3,C3,
T3,T4,A5,B5,
C5,
CE1,CE2, andCE3[2]aresampledactive. A1:A0
are fed to the two-bit counter.
.
T5,A6,B6,C6,R6
93,94,95,
96
L5,G5,
B5,A5,A4,
B4
Input-
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
BWA,BWB
BWC,BWD
G3,L3
Synchronous
H4
B7
Input-
Global Write Enable Input, active LOW. When
88
GW
Synchronous asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written,
regardless of the values on BWX and BWE).
87
89
M4
K4
A7
B6
Input-
Byte Write Enable Input, active LOW.
BWE
CLK
Synchronous Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW,
during a burst operation.
98
E4
A3
Input-
Chip Enable 1 Input, active LOW. Sampled on
CE1
Synchronous the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
ADSP is ignored if CE1 is HIGH.
[2]
CE2
97
92
-
-
B3
A6
Input-
Chip Enable 2 Input, active HIGH. Sampled on
Synchronous the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW. Sampled on
[2]
CE3
Synchronous the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.Not
available for AJ package version.
Not connected
for BGA. Where referenced, CE3 is assumed
active throughout this document for BGA.
86
F4
B8
Input-
Output Enable, asynchronous input, active
OE
Asynchronous LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is
masked during the first clock of a read cycle
when emerging from a deselected state.
83
84
G4
A4
A9
B9
Input-
Advance Input signal, sampled on the rising
ADV
Synchronous edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst
cycle.
Input-
Address Strobe from Processor, sampled on
ADSP
Synchronous the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the
devicearecapturedintheaddressregisters. A1:
A0 are also loaded into the burst counter. When
ADSP and ADSC are both asserted, only ADSP
is recognized. ASDP is ignored when CE1 is
deasserted HIGH.
Document #: 38-05240 Rev. *C
Page 6 of 33
CY7C1380CV25
CY7C1382CV25
CY7C1380CV25–Pin Definitions (continued)
Name
TQFP
BGA
fBGA
I/O
Description
B4
A8
Input-
Address Strobe from Controller, sampled on
85
ADSC
Synchronous the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the
devicearecapturedintheaddressregisters. A1:
A0 are also loaded into the burst counter. When
ADSP and ADSC are both asserted, only ADSP
is recognized.
ZZ
64
T7
H11
Input-
ZZ “sleep” Input, active HIGH. When asserted
Asynchronous HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved.
For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.
52,53,56,
57,58,59,
62,63,68,
69,72,73,
74,75,78,
79,2,3,6,7,8,9,
12,13,18,19,22
,
K6,L6,
M6,N6,
K7,L7,
N7,P7,
E6,F6,
G6,H6,
D7,E7,
G7,H7,
D1,E1,
G1,H1,
E2,F2,
G2,H2,
K1,L1,
N1,P1,
K2,L2,
M2,N2,
P6,D6,
D2,P2
M11,L11,
K11,J11,
I/O-
Bidirectional Data I/O lines. As inputs, they
DQs,
Synchronous feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs,
they deliver the data contained in the memory
location specified by the addresses presented
DQPs
J10,K10,
L10,M10,
D10,E10,
F10,G10,
D11,E11,
F11,G11,
D1,E1,F1,
G1,D2,E2,F2,
G2,J1,
during the previous
clock rise of the read cycle.
The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as
outputs. When HIGH, DQs and DQPX are
placed in a three-state condition.
23,24,25,
28,29,51,
80,1,30
K1,L1,M1,
J2,K2,L2,
M2,N11,
C11,C1,N1
VDD
15,41,65,
91
J2,C4,J4,R4,
D4,D8,E4,E8, Power Supply Power supply inputs to the core of the
J6
F4,F8,
G4,G8,H4,H8,
J4,J8,
device.
K4,K8,L4,
L8,M4,M8
VSS
17,40,67,
90
D3,E3,
F3,H3,
K3,M3,
N3,P3,
D5,E5,
F5,H5,
K5,M5,
N5,P5
C4,C5,C6,C7,
C8,D5,D6,D7,
E5,E6,E7,F5,
F6,F7,G5,G6,
G7,H2,H5,H6,
H7,J5,J6,J7,
K5,K6,K7,
Ground
Ground for the core of the device.
L5,L6,L7,
M5,M6,M7,N4,
N8
VSSQ
5,10,21,26,55,
60,71,
-
-
I/O Ground Ground for the I/O circuitry.
76
Document #: 38-05240 Rev. *C
Page 7 of 33
CY7C1380CV25
CY7C1382CV25
CY7C1380CV25–Pin Definitions (continued)
Name
TQFP
BGA
fBGA
I/O
Description
VDDQ
4,11,20,27,54, A1,F1,J1,M1,U1, C3,C9,D3,D9,
I/O Power Power supply for the I/O circuitry.
61,70,
77
A7,F7,J7,M7,U7 E3,E9,F3,F9,G
Supply
3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,N3,
N9
MODE
31
R3
R1
Input-
Static
Selects Burst Order. When tied to GND selects
linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence.
This is a strap pin and should remain static
during device operation. Mode Pin has an
internal pull-up.
TDO
TDI
-
-
-
-
U5
U3
U2
U4
P7
P5
R5
R7
JTAG serial Serial data-out to the JTAG circuit. Delivers
output
data on the negative edge of TCK. If the JTAG
Synchronous feature is not being utilized, this pin should be
disconnected. This pin is not available on TQFP
packages.
JTAG serial Serial data-In to the JTAG circuit. Sampled on
input
the rising edge of TCK. If the JTAG feature is not
Synchronous being utilized, this pin can be disconnected or
connected to VDD. This pin is not available on
TQFP packages.
TMS
JTAG serial Serial data-In to the JTAG circuit. Sampled on
input
the rising edge of TCK. If the JTAG feature is not
Synchronous being utilized, this pin can be disconnected or
connected to VDD. This pin is not available on
TQFP packages.
TCK
NC
JTAG-Clock Clock input to the JTAG circuitry. If the JTAG
feature is not being utilized, this pin must be
connected to VSS. This pin is not available on
TQFP packages.
14,16,66,
39,38
B1,C1,
R1,T1,T2,J3,
D4,
A11,B1,C2,
C10,H1,H3,H9
,H10,
-
No Connects. Not internally connected to the
die
L4,J5,R5,6T,
6U,
N2,N5,N7,N10
,P1,A1,B11,P2
,R2,N6
B7,C7,
R7
CY7C1382CV25–Pin Definitions
Name
A0, A1, A
TQFP
BGA
fBGA
I/O
Input-
Description
37,36,32,
33,34,35,
42,43,44,
45,46,47,
48,49,50,
80,81,82,
99,100
P4,N4,
A2,B2,
C2,R2,
T2,A3,
B3,C3,
T3,A5,
B5,C5,
T5,A6,
B6,C6,
R6,T6
R6,P6,A2,
Address Inputs used to select one of the
A10,A11,
Synchronous address locations. Sampled at the rising
B2,B10,P3,P4,N6,P
8,P9,
edge of the CLK if
or
is active
ADSP ADSC
LOW, and CE1, CE2, and CE3 are sampled
active. A1: A0 are fed to the two-bit counter.
P10,P11,
.
R3,R4,R8,R9,R10,
R11
93,94
G3,L5
B5,A4
Input-
Byte Write Select Inputs, active LOW.
BWA,BWB
Synchronous
Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of CLK
.
Document #: 38-05240 Rev. *C
Page 8 of 33
CY7C1380CV25
CY7C1382CV25
CY7C1382CV25–Pin Definitions (continued)
Name
TQFP
BGA
fBGA
I/O
Description
H4
B7
Input-
Global Write Enable Input, active LOW.
88
GW
Synchronous When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes
are written, regardless of the values on BWX
and BWE).
87
89
M4
K4
A7
B6
Input-
Byte Write Enable Input, active LOW.
BWE
CLK
Synchronous Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Input-
Clock Input. Used to capture all synchronous
inputstothedevice. Alsousedtoincrementthe
burst counter when ADV is asserted LOW,
during a burst operation.
Clock
98
97
92
E4
A3
B3
A6
Input-
Chip Enable 1 Input, active LOW. Sampled
CE1
Synchronous on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the
device. ADSP is ignored if CE1 is HIGH.
Chip Enable 2 Input, active HIGH. Sampled
[2]
CE2
-
-
Input-
Synchronous on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the
device.
Input-
Chip Enable 3 Input, active LOW. Sampled
[2]
CE3
Synchronous on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the
device. Not available for AJ package
version.
Not connected for BGA. Where refer-
enced, CE3 is assumed active throughout this
document for BGA.
86
F4
B8
Input-
Output Enable, asynchronous input, active
OE
Asynchronou LOW. Controls the direction of the I/O pins.
s
When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is
masked during the first clock of a read cycle
when emerging from a deselected state.
83
84
G4
A4
A9
B9
Input-
Advance Input signal, sampled on the
ADV
Synchronous rising edge of CLK, active LOW. When
asserted, it automatically increments the
address in a burst cycle.
Input-
Address Strobe from Processor, sampled
ADSP
Synchronous on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to
the device are captured in the address
registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
P4
A8
Input-
Address Strobe from Controller, sampled
85
ADSC
Synchronous on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to
the device are captured in the address
registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
Document #: 38-05240 Rev. *C
Page 9 of 33
CY7C1380CV25
CY7C1382CV25
CY7C1382CV25–Pin Definitions (continued)
Name
TQFP
BGA
fBGA
I/O
Description
ZZ
64
T7
H11
Input-
ZZ “sleep” Input, active HIGH. When
Asynchronou asserted HIGH places the device in a
s
non-time-critical “sleep” condition with data
integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has
an internal pull-down.
58,59,62,
63,68,69,
72,73,8,9,
12,13,18,
19,22,23,
74,24
P7,K7,
G7,E7,
F6,H6,L6,N6,
D1,
J10,K10,
L10,M10,
I/O-
Bidirectional Data I/O lines. As inputs, they
DQs,
Synchronous feed into an on-chip data register that is
triggeredbytherisingedgeofCLK. Asoutputs,
they deliver the data contained in the memory
location specified by the addresses presented
DQPs
D11,E11,
F11,G11,J1,K1,L1,M
1,D2,E2,F2,
G2,C11,N1
H1,L1,
N1,E2,
G2,K2,
M2,D6,
P2
during the previous
clock rise of the read cycle.
The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave
as outputs. When HIGH, DQs and DQPX are
placed in a three-state condition.
VDD
15,41,65,
91
C4,J2,J4,J6, D4,D8,E4,E8,F4,F8, Power Supply Power supply inputs to the core of the
R4
G4,G8,H4,
H8,J4,J8,
K4,K8,L4,
L8,M4,M8
device.
VSS
17,40,67,
90
D3,D5,
H2,C4,C5,C6,C7,C8
Ground
Ground for the core of the device.
E5,E3,F3,F5, ,D5,D6,D7,E5,E6,E7
G5,
H3,H5,
K3,K5,L3,M3,
M5,
,
F5,F6,F7,
G5,G6,G7,
H5,H6,H7,J5,J6,J7,
K5,K6,K7,
N3,N5,
P3,P5
L5,L6,L7,
M5,M6,M7,N4,N8
VSSQ
5,10,21,26,55,
60,71,
-
-
I/O Ground Ground for the I/O circuitry.
76
VDDQ
4,11,20,27,54, A1,A7,F1,F7, C3,C9,D3,D9,E3,E9 I/O Power Power supply for the I/O circuitry.
61,70,
77
J1,J7,M1,M7,
U1,U7
,
Supply
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,N3,N9
MODE
31
R3
R1
Input-
Static
Selects Burst Order. When tied to GND
selects linear burst sequence. When tied to
V
DD or left floating selects interleaved burst
sequence. This is a strap pin and should
remain static during device operation. Mode
Pin has an internal pull-up.
TDO
TDI
-
-
U5
U3
P7
P5
JTAG serial Serial data-out to the JTAG circuit. Delivers
output
data on the negative edge of TCK. If the JTAG
Synchronous feature is not being utilized, this pin should be
left unconnected. This pin is not available on
TQFP packages.
JTAG serial Serial data-In to the JTAG circuit. Sampled
input
on the rising edge of TCK. If the JTAG feature
Synchronous is not being utilized, this pin can be left floating
or connected to VDD through a pull up resistor.
This pin is not available on TQFP packages.
Document #: 38-05240 Rev. *C
Page 10 of 33
CY7C1380CV25
CY7C1382CV25
CY7C1382CV25–Pin Definitions (continued)
Name
TQFP
BGA
fBGA
I/O
Description
TMS
-
U2
R5
JTAG serial Serial data-In to the JTAG circuit. Sampled
input
on the rising edge of TCK. If the JTAG feature
Synchronous is not being utilized, this pin can be discon-
nected or connected to VDD. This pin is not
available on TQFP packages.
TCK
NC
-
U4
R7
JTAG-Clock ClockinputtotheJTAGcircuitry. IftheJTAG
feature is not being utilized, this pin must be
connected to VSS. This pin is not available on
TQFP packages.
1,2,3,6,7,
14,16,25,
28,29,30,
38,39,
B1,B7,
C1,C7,
A5,B1,B4,
C1,C2,C10,D1,D10,
E1,E10,F1,
F10,G1,
-
No Connects. Not internally connected to the
die.
D2,D4,
D7,E1,
51,52,53,
56,57,66,
75,78,79,
95,96
E6,H2,
G10,H1,H3,H9,H10,
J2,J11,
F2,G1,
G6,H7,
K2,
J3,J5,K1,
K6,L4,L2,L7,
M6,
K11,L2,L1,M2,M11,
N2,N7,N10,
N5,
N2,L7,P1,P6,
R1,
N11,P1,A1,
B11,
R5,R7,
P2,R2
T1,T4,U6
Functional Overview
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.0 ns (200-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single Read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 3.0ns
(200-MHz device).
The CY7C1380CV25/CY7C1382CV25 supports secondary
cache in systems utilizing either a linear or interleaved burst
sequence. The interleaved burst order supports Pentium and
i486 processors. The linear burst sequence is suited for
processors that utilize a linear burst sequence. The burst order
is user selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE1, CE2, CE3 are all asserted active. The address
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BWX) and
ADV inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
then the Write operation is controlled by BWE and BWX
signals. The CY7C1380CV25/CY7C1382CV25 provides Byte
Write capability that is described in the Write Cycle Descrip-
tions table. Asserting the Byte Write Enable input (BWE) with
the selected Byte Write (BWX) input, will selectively write to
only the desired bytes. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
Document #: 38-05240 Rev. *C
Page 11 of 33
CY7C1380CV25
CY7C1382CV25
Write mechanism has been provided to simplify the Write
operations.
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Because the CY7C1380CV25/CY7C1382CV25 is a common
I/O device, the Output Enable (OE) must be deserted HIGH
before presenting data to the DQs inputs. Doing so will
three-state the output drivers. As a safety precaution, DQs are
automatically three-stated whenever a Write cycle is detected,
regardless of the state of OE.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and
(4) the appropriate combination of the Write inputs (GW, BWE,
and BWX) are asserted active to conduct a Write to the desired
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into
the address register and the address advancement logic while
being delivered to the memory array. The ADV input is ignored
during this cycle. If a global Write is conducted, the data
presented to the DQs is written into the corresponding address
location in the memory core. If a Byte Write is conducted, only
the selected bytes are written. Bytes not selected during a
Byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations.
the
“sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Because the CY7C1380CV25/CY7C1382CV25 is a common
I/O device, the Output Enable (OE) must be deserted HIGH
before presenting data to the DQs inputs. Doing so will
three-state the output drivers. As a safety precaution, DQs are
automatically three-stated whenever a Write cycle is detected,
regardless of the state of OE.
Linear Burst Address Table (MODE = GND)
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
Burst Sequences
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
The CY7C1380CV25/CY7C1382CV25 provides a two-bit
wraparound counter, fed by A1: A0, that implements either an
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
Description
Snooze mode standby current
Device operation to ZZ
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
Min.
Max.
60mA
2tCYC
Unit
mA
ns
tZZREC
tZZI
tRZZI
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
2tCYC
0
ns
ns
ns
2tCYC
Document #: 38-05240 Rev. *C
Page 12 of 33
CY7C1380CV25
CY7C1382CV25
Truth Table[ 3, 4, 5, 6, 7, 8]
Operation
Add. Used
None
CE2
X
L
X
L
CE3
X
X
H
X
H
X
L
L
L
L
L
X
X
X
X
X
WRITE
CLK
DQ
CE1
H
L
L
L
L
X
L
L
L
ZZ ADSP ADSC ADV
OE
X
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Snooze Mode, Power-down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue
Burst
WRITE Cycle, Continue
Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle,Suspend Burst Current
WRITE Cycle,Suspend Burst Current
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
X
L
L
H
H
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
L-H three-state
L-H three-state
L-H three-state
L-H three-state
L-H three-state
None
None
None
None
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
X
X
X
X
X
L
H
X
L
H
L
H
L
X
X
L
None
X
X
X
L
L
L
H
H
H
H
H
X
L-H
three-state
Q
External
External
External
External
External
Next
Next
Next
Next
Next
H
H
H
H
H
X
X
X
X
X
L
L-H three-state
L-H
L-H
H
H
H
H
H
X
X
H
D
Q
L
L
L-H three-state
L-H
L-H three-state
L-H
L-H three-state
L-H
L-H
L-H
L-H three-state
L-H
L-H three-state
L-H
L-H
X
X
H
H
X
Q
L
L
L
L
Q
H
X
D
D
Q
Next
H
X
X
L
X
H
L
L
X
Current
Current
Current
Current
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
X
X
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
X
X
Q
D
D
L
Truth Table for Read/Write [5]
Function (CY7C1380CV25)
Read
Read
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
Write Byte C – (DQC and DQPC)
Write Bytes C, A
BWD
X
BWC
X
BWB
BWA
X
H
L
H
L
H
L
H
GW
BWE
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
X
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
L
L
Write Bytes C, B
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the
signal.
is asynchronous and is not sampled with the clock.
OE
OE
6. CE , CE , and CE are available only in the TQFP package. BGA package has only 2 chip selects CE and CE .
1
2
3
1
2
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks
X
after the
or with the assertion of
. As a result,
must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state.
OE
is
ADSC
a don't care for the remainder of the write cycle
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when
OE
ADSP
8.
OE
is
OE
.
is active (LOW)
inactive or when the device is deselected, and all data bits behave as output when
OE
Document #: 38-05240 Rev. *C
Page 13 of 33
CY7C1380CV25
CY7C1382CV25
Truth Table for Read/Write (continued)[5]
Function (CY7C1380CV25)
Write Bytes C, B, A
Write Byte D – (DQD and DQPD)
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
BWD
H
BWC
L
BWB
L
H
H
L
BWA
L
H
L
H
L
H
L
H
L
GW
BWE
H
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
X
L
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
L
X
L
H
H
L
L
X
Write All Bytes
X
Truth Table for Read/Write[5]
Function (CY7C1382CV25)
BWB
X
H
H
L
L
L
X
BWA
GW
BWE
Read
Read
H
H
L
L
L
L
L
X
X
H
L
H
L
L
X
H
H
H
H
H
L
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
Write All Bytes
Write All Bytes
IEEE 1149.1 Serial Boundary Scan (JTAG)
TAP Controller State Diagram
TEST-LOGIC
The CY7C1380CV25/CY7C1382CV25 incorporates a serial
boundary scan test access port (TAP). This port operates in
accordance with IEEE Standard 1149.1-1990 but does not
have the set of functions required for full 1149.1 compliance.
These functions from the IEEE specification are excluded
because their inclusion places an added delay in the critical
speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5V I/O logic levels.
1
RESET
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
0
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
The CY7C1380CV25/CY7C1382CV25 contains
a
TAP
1
1
EXIT1-DR
EXIT1-IR
controller, instruction register, boundary scan register, bypass
register, and ID register.
0
0
PAUSE-DR
0
PAUSE-IR
0
Disabling the JTAG Feature
1
1
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alter-
nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Document #: 38-05240 Rev. *C
Page 14 of 33
CY7C1380CV25
CY7C1382CV25
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure . TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Data-Out (TDO)
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The SRAM has a 75-bit-long
register.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0
Bypass Register
2
1
0
0
0
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
S
election
TDI
TDO
Circuitr
y
.
.
. 2 1
Identification (ID) Register
x
.
.
.
.
. 2 1
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Boundary Scan Register
TCK
TMS
TAP CONTROLLER
TAP Instruction Set
Overview
Performing a TAP Reset
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
The TAP controller cannot be used to load address data or
Registers are connected between the TDI and TDO balls and
control signals into the SRAM and cannot preload the I/O
allow data to be scanned into and out of the SRAM test
Document #: 38-05240 Rev. *C
Page 15 of 33
CY7C1380CV25
CY7C1382CV25
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus
hold time (tCS plus tCH).
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Reserved
These instructions are not implemented but are reserved for
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
future use. Do not use these instructions.
Document #: 38-05240 Rev. *C
Page 16 of 33
CY7C1380CV25
CY7C1382CV25
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the operating Range[9, 10]
Parameter
Description
Min.
Max.
Unit
Clock
tTCYC
tTF
tTH
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
Output Times
100
ns
MHz
ns
10
40
40
tTL
ns
tTDOV
tTDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
Set-up Times
20
ns
ns
0
tTMSS
tTDIS
tCS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
Hold Times
10
10
10
ns
ns
tTMSH
tTDIH
tCH
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
10
10
10
ns
ns
ns
Notes:
t
t
9. CS and CH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1ns.
R
F
Document #: 38-05240 Rev. *C
Page 17 of 33
CY7C1380CV25
CY7C1382CV25
2.5V TAP AC Test Conditions
Input pulse levels ......................................... V to 2.5V
2.5V TAP AC Output Load Equivalent
1.25V
SS
Input rise and fall time..................................................... 1 ns
Input timing reference levels.........................................1.25V
Output reference levels.................................................1.25V
Test load termination supply voltage.............................1.25V
50Ω
TDO
ZO= 50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; Vdd = 2.5V ±0.125V unless
otherwise noted)[11]
Parameter
VOH1
VOH2
VOL1
VOL2
VIH
Description
Description
Conditions
VDDQ = 2.5V
Min.
2.0
2.1
Max.
Unit
V
V
V
V
V
V
µA
Output HIGH Voltage IOH = -1.0 mA
Output HIGH Voltage IOH = -100 µA
Output LOW Voltage IOL = 8.0 mA
Output LOW Voltage IOL = 100 µA
Input HIGH Voltage
VDDQ = 2.5V
VDDQ = 2.5V
VDDQ = 2.5V
VDDQ = 2.5V
VDDQ = 2.5V
0.4
0.2
VDD + 0.3
0.7
1.7
-0.3
-5
VIL
IX
Input LOW Voltage
Input Load Current
5
GND < VIN < VDDQ
Identification Register Definitions
CY7C1380CV25
CY7C1382CV25
Instruction Field
Revision Number (31:29)
Device Depth (28:24)
(512Kx36)
010
(1Mx18)
010
Description
Describes the version number.
Reserved for internal use.
01011
01011
000000
100101
00000110100
1
000000
010101
00000110100
1
Architecture/Memory type(23:18)
Bus Width/Density(17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Defines memory type and architecture.
Defines width and density.
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Instruction
3
3
Bypass
1
1
ID
32
72
32
72
Boundary Scan Order
Identification Codes
Instruction
Code
Description
000
EXTEST
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
001
010
011
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
SAMPLE Z
RESERVED
Note:
Do Not Use: This instruction is reserved for future use.
11. All voltages referenced to VSS (GND).
Document #: 38-05240 Rev. *C
Page 18 of 33
CY7C1380CV25
CY7C1382CV25
Identification Codes (continued)
Instruction
Code
Description
100
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
101
110
111
RESERVED
RESERVED
BYPASS
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
119-Ball BGA Boundary Scan Order
CY7C1380CV25
(512K x 36)
Bit#
1
2
3
4
5
6
7
8
Ball ID
Bit#
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Ball ID
B2
P4
N4
R6
T5
T3
R2
R3
P2
P1
N2
L2
K1
N1
M2
K4
H4
M4
F4
B4
A4
G4
C6
A6
D6
D7
E6
G6
H7
E7
F6
G7
H6
T7
K7
L6
N6
P7
K6
L7
M6
N7
P6
B5
B3
C5
C3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
L1
K2
Not Bonded (Preset to1)
H1
G2
E2
D1
H2
G1
F2
E1
D2
A5
A3
E4
Internal
L3
Document #: 38-05240 Rev. *C
Page 19 of 33
CY7C1380CV25
CY7C1382CV25
119-Ball BGA Boundary Scan Order (continued)
33
34
35
36
C2
A2
T4
B6
69
70
71
72
G3
G5
L5
Internal
CY7C1382CV25 (1M x 18)
Bit#
1
2
3
4
5
6
7
8
Ball ID
Bit#
37
38
39
40
41
42
43
44
45
46
Ball ID
B2
P4
N4
R6
T5
T3
R2
K4
H4
M4
F4
B4
A4
G4
C6
A6
T6
R3
9
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
P2
N1
M2
L1
D6
E7
F6
G7
H6
T7
K7
L6
K2
Not Bonded (Preset to 1)
H1
G2
E2
D1
N6
P7
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
A5
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
B5
A3
E4
Internal
B3
C5
CY7C1382CV25 (1M x 18) (continued)
Bit#
32
33
34
35
Ball ID
Bit#
68
69
70
71
Ball ID
Not Bonded (Preset to 0)
C3
C2
A2
T2
B6
Internal
G3
L5
36
72
Internal
Document #: 38-05240 Rev. *C
Page 20 of 33
CY7C1380CV25
CY7C1382CV25
165-Ball fBGA Boundary Scan Order
CY7C1380CV25 (512K x 36)
Bit#
1
2
3
4
5
6
7
8
Ball ID
B6
B7
A7
B8
A8
B9
A9
Bit#
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
Ball ID
N6
R6
P6
R4
R3
P4
P3
R1
N1
L2
K2
J2
M2
M1
L1
B10
A10
C11
E10
F10
G10
D10
D11
E11
F11
G11
H11
J10
K10
L10
M10
J11
K11
L11
M11
N11
R11
R10
R9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
K1
J1
Not Bonded (Preset to1)
G2
F2
E2
D2
G1
F1
E1
D1
C1
A2
B2
A3
B3
CY7C1380CV25 (512K x 36) (continued)
Bit#
32
Ball ID
R8
Bit#
68
Ball ID
B4
33
34
P10
P9
69
70
A4
A5
35
P8
71
B5
36
P11
72
A6
CY7C1382CV25 (1M x 18)
Bit#
1
2
3
4
Ball ID
Bit#
37
Ball ID
N6
R6
P6
R4
B6
B7
A7
B8
A8
38
39
40
41
5
R3
Document #: 38-05240 Rev. *C
Page 21 of 33
CY7C1380CV25
CY7C1382CV25
165-Ball fBGA Boundary Scan Order (continued)
6
B9
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
P4
P3
R1
7
A9
8
B10
9
A10
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
A11
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
N1
M1
L1
K1
C11
D11
E11
F11
G11
H11
J10
K10
J1
Not Bonded (Preset to 1)
G2
F2
E2
D2
L10
M10
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
A2
B2
A3
B3
R11
R10
R9
R8
P10
P9
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
A4
B5
A6
P8
P11
Document #: 38-05240 Rev. *C
Page 22 of 33
CY7C1380CV25
CY7C1382CV25
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
Static Discharge Voltage.......................................... > 2001V
lines, not tested.)
(per MIL-STD-883, Method 3015)Latch-up Current > 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V
Range
Temperature
VDD
VDDQ
DC Voltage Applied to Outputs
Commercial 0°C to +70°C 2.5V – 5%/+5% 2.5V – 5%
in three-state....................................... –0.5V to VDDQ + 0.5V
to VDD
Industrial
–40°C to +85°C
[12, 13]
Electrical Characteristics Over the Operating Range
Parameter
VDD
VDDQ
VOH
VOL
VIH
Description
Test Conditions
Min.
2.375
2.375
2.0
Max.
2.625
VDD
Unit
V
V
V
V
V
V
µA
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
VDDQ = 2.5V
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
0.4
Input HIGH Voltage[12] VDDQ = 2.5V
1.7 VDD + 0.3V
–0.3
–5
VIL
IX
Input LOW Voltage[12]
VDDQ = 2.5V
GND ≤ VI ≤ VDDQ
0.7
5
Input Load Current
except ZZ and MODE
Input Current of MODE Input = VSS
Input = VDD
–30
–30
–5
µA
µA
µA
µA
µA
5
Input Current of ZZ
Input = VSS
Input = VDD
5
5
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
VDD Operating Supply VDD = Max., IOUT = 0 mA,
4.0-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
7.5-ns cycle, 133 MHz
4.0-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
7.5-ns cycle, 133 MHz
350
325
300
275
245
120
110
100
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Current
f = fMAX = 1/tCYC
ISB1
Automatic CE
VDD = Max, Device Deselected,
Power-down
VIN ≥ VIH or VIN ≤ VIL
Current—TTL Inputs
f = fMAX = 1/tCYC
85
70
ISB2
Automatic CE
VDD = Max, Device Deselected, VIN ≤ All speeds
Power-down
0.3V or VIN > VDDQ – 0.3V, f = 0
Current—CMOS Inputs
ISB3
Automatic CE
V
DD = Max, Device Deselected, or VIN 4.0-ns cycle, 250 MHz
105
100
95
85
80
mA
mA
mA
mA
mA
mA
Power-down
≤ 0.3V or VIN > VDDQ – 0.3V
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
7.5-ns cycle, 133 MHz
All speeds
Current—CMOS Inputs f = fMAX = 1/tCYC
ISB4
Automatic CE
V
DD = Max, Device Deselected,
80
Power-down
V
IN ≥ VIH or VIN ≤ VIL, f = 0
Current—TTL Inputs
Shaded areas contain advance information.
Notes:
12. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > -2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
13. TPower-up: Assumes a linear ramp from 0v to V (min.) within 200ms. During this time V < V and V
< V
.
DD
DD
IH
DD
DDQ
Document #: 38-05240 Rev. *C
Page 23 of 33
CY7C1380CV25
CY7C1382CV25
Thermal Resistance[14]
TQFP
BGA
fBGA
Parameter
Description
Test Conditions
Package
Package
Package
Unit
ΘJA
Thermal Resistance
Test conditions follow standard
test methods and procedures
for measuring thermal
31
45
46
°C/W
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
6
7
3
°C/W
impedence, per EIA / JESD51.
Capacitance[14]
TQFP
BGA
fBGA
Parameter
CIN
CCLK
CI/O
Description
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
Test Conditions
Package
Package
Package
Unit
pF
pF
TA = 25°C, f = 1 MHz,
5
5
5
8
8
8
9
9
9
V
DD = 2.5V.
VDDQ = 2.5V
pF
AC Test Loads and Waveforms
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDD
90%
10%
Z = 50Ω
0
10%
L
GND
≤ 1ns
5 pF
R =1538Ω
≤ 1ns
INCLUDING
JIG AND
SCOPE
V = 1.25V
L
(a)
(b)
(c)
Switching Characteristics Over the Operating Range [19, 20]
250 MHz
225 MHz
200 MHz
167 MHz
133 MHz
Parameter
tPOWER
Clock
tCYC
tCH
tCL
Description
Min. Max. Min. Max. Min. Max. Min. Max Min. Max Unit
VDD(Typical) to the first Access[15]
1
1
1
1
1
ms
Clock Cycle Time
Clock HIGH
4.0
1.7
1.7
4.4
2.0
2.0
5
2.0
2.0
6
2.2
2.2
7.5
2.5
2.5
ns
ns
ns
Clock LOW
Output Times
tCO
tDOH
tCLZ
tCHZ
tOEV
tOELZ
tOEHZ
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[16, 17, 18]
2.6
2.8
3.0
3.4
4.2
ns
ns
ns
ns
ns
ns
ns
1.0
1.0
1.0
1.0
1.3
1.3
1.3
1.3
1.3
1.3
Clock to High-Z[16, 17, 18]
2.6
2.6
2.8
2.8
3.0
3.0
3.4
3.4
3.4
4.2
OE LOW to Output Valid
LOW to Output Low-Z[16, 17, 18]
OE
0
0
0
0
0
OE HIGH to Output High-Z[16, 17, 18]
2.6
2.8
3.0
3.4
4.0
Shaded areas contain advance information.
Notes:
14. Tested initially and after any design or process change that may affect these parameters
15. This part has a voltage regulator internally; t
can be initiated.
is the time that the power needs to be supplied above V (minimum) initially before a read or write operation
DD
POWER
16. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
CHZ CLZ OELZ
17. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
18. This parameter is sampled and not 100% tested.
19. Timing reference level is 1.25V when V
=2.5V.
DDQ
20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05240 Rev. *C
Page 24 of 33
CY7C1380CV25
CY7C1382CV25
Switching Characteristics Over the Operating Range (continued)[19, 20]
250 MHz
225 MHz
200 MHz
167 MHz
133 MHz
Parameter
Set-up Times
tAS
Description
Min. Max. Min. Max. Min. Max. Min. Max Min. Max Unit
Address Set-up Before CLK Rise
1.2
1.2
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
ns
ns
tADS
,
ADSC ADSP Set-up Before CLK
Rise
tADVS
tWES
1.2
1.2
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
ns
ns
ADV Set-up Before CLK Rise
Set-up Before CLK
GW, BWE, BWX
Rise
tDS
tCES
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise 1.2
1.2
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
ns
ns
Hold Times
tAH
tADH
tADVH
tWEH
tDH
Address Hold After CLK Rise
Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
,
ADSP ADSC
ADV Hold After CLK Rise
,
,
GW BWE BWX Hold After CLK Rise
Data Input Hold After CLK Rise
tCEH
Chip Enable Hold After CLK Rise
Document #: 38-05240 Rev. *C
Page 25 of 33
CY7C1380CV25
CY7C1382CV25
Switching Waveforms
Read Cycle Timing[21]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,
BWx
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV
suspends
burst.
t
t
OEV
CO
t
t
OEHZ
t
OELZ
t
CHZ
DOH
t
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Notes:
21. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
22.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document #: 38-05240 Rev. *C
Page 26 of 33
CY7C1380CV25
CY7C1382CV25
Switching Waveforms (continued)
Write Cycle Timing[21, 22]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
ADDRESS
BWE,
t
t
AH
AS
A1
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BW
X
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
Data In (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Document #: 38-05240 Rev. *C
Page 27 of 33
CY7C1380CV25
CY7C1382CV25
Switching Waveforms (continued)
Read/Write Cycle Timing[21, 23, 24]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
BWE,
t
t
WEH
WES
BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
ZZ Mode Timing [25, 26]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
23.
.
The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by
ADSP or ADSC
24. GW is HIGH.
Document #: 38-05240 Rev. *C
Page 28 of 33
CY7C1380CV25
CY7C1382CV25
Ordering Information
Speed
Package
Name
A101
Operating
Range
Commercial
(MHz)
Ordering Code
Part and Package Type
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
250
CY7C1380CV25-250AC
CY7C1382CV25-250AC
CY7C1380CV25-250BGC
CY7C1382CV25-250BGC
BG119 119 PBGA
BB165A 165 fBGA
CY7C1380CV25-250BZC
CY7C1382CV25-250BZC
225
200
CY7C1380CV25-225AC
CY7C1382CV25-225AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
CY7C1380CV25-225BGC
BG119 119 PBGA
BB165A 165 fBGA
CY7C1382CV25-225BGC
CY7C1380CV25-225BZC
CY7C1382CV25-225BZC
CY7C1380CV25-200AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
CY7C1382CV25-200AC
CY7C1380CV25-200BGC
CY7C1382CV25-200BGC
CY7C1380CV25-200BZC
CY7C1382CV25-200BZC
CY7C1380CV25-167AC
CY7C1382CV25-167AC
CY7C1380CV25-167BGC
CY7C1382CV25-167BGC
BG119 119 PBGA
BB165A 165 fBGA
167
133
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
BG119 119 PBGA
BB165A 165 fBGA
CY7C1380CV25-167BZC
CY7C1382CV25-167BZC
CY7C1380CV25-133AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Notes:
25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
26. DQs are in high-Z when exiting ZZ sleep mode.
167
CY7C1380CV25-167AI
CY7C1382CV25-167AI
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Industrial
CY7C1380CV25-167BGI
BG119 119 PBGA
BB165A 165 fBGA
CY7C1382CV25-167BGI
CY7C1380CV25-167BZI
CY7C1382CV25-167BZI
Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.
Document #: 38-05240 Rev. *C
Page 29 of 33
CY7C1380CV25
CY7C1382CV25
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
ꢁ6.00 0.20
ꢁ4.00 0.ꢁ0
ꢁ.40 0.05
ꢁ00
ꢀꢁ
ꢀ0
ꢁ
0.30 0.0ꢀ
0.65
TYP.
ꢁ2° ꢁ°
(ꢀX)
SEE DETAIL
A
30
5ꢁ
3ꢁ
50
0.20 MAX.
ꢁ.60 MAX.
R 0.0ꢀ MIN.
0.20 MAX.
0° MIN.
STAND-OFF
0.05 MIN.
0.ꢁ5 MAX.
SEATING PLANE
0.25
GAUGE PLANE
R 0.0ꢀ MIN.
0.20 MAX.
0°-7°
0.60 0.ꢁ5
0.20 MIN.
ꢁ.00 REF.
51-85050-*A
DETAIL
A
Document #: 38-05240 Rev. *C
Page 30 of 33
CY7C1380CV25
CY7C1382CV25
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05240 Rev. *C
Page 31 of 33
CY7C1380CV25
CY7C1382CV25
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05240 Rev. *C
Page 32 of 33
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1380CV25
CY7C1382CV25
Document History Page
Document Title: CY7C1380CV25/CY7C1382CV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
Document Number: 38-05240
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
116280
08/29/02
SKX
New Data Sheet
*A
121543
11/21/02
DSG
Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85122
(BB165A) to rev. *C
*B
*C
206081
230388
See ECN
See ECN
RKF
VBL
Final data sheet
Update Ordering Info section:
Shade Selection Guide and Characteristics table
Changed the title for 119-BGA pin table for CY7C1382CV25 from
“512K x 18” to “1M x 18”
Modified Identification Register Definitions table: Changed Bit #24 from “0”
to “1” and changed “Device Width” to “Architecture/Memory type”
Document #: 38-05240 Rev. *C
Page 33 of 33
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