CY7C1381D-100BGCT [CYPRESS]
Cache SRAM, 512KX36, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119;
| 型号： | CY7C1381D-100BGCT |
| 厂家： | 
CYPRESS |
| 描述： | Cache SRAM, 512KX36, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 静态存储器 |
| 文件： | 总29页 (文件大小：543K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1381D
CY7C1383D
18-Mbit (512K x 36/1M x 18)
Flow-Through SRAM
Functional Description[1]
Features
• Supports 133-MHz bus operations
• 512K × 36/1M × 18 common I/O
The CY7C1381D/CY7C1383D is a 3.3V, 512K x 36 and 1M x
18 Synchronous Flow-through SRAMs, respectively designed
to interface with high-speed microprocessors with minimum
glue logic. Maximum access delay from clock rise is 6.5 ns
(133-MHz version). A 2-bit on-chip counter captures the first
address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx,
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
• 3.3V core power supply (VDD
)
• 2.5V or 3.3V I/O supply (VDDQ
• Fast clock-to-output time
— 6.5 ns (133-MHz version)
)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
The CY7C1381D/CY7C1383D allows either interleaved or
linear burst sequences, selected by the MODE input pin. A
HIGH selects an interleaved burst sequence, while a LOW
selects a linear burst sequence. Burst accesses can be
initiated with the Processor Address Strobe (ADSP) or the
cache Controller Address Strobe (ADSC) inputs. Address
advancement is controlled by the Address Advancement
(ADV) input.
• Asynchronous output enable
• Available in JEDEC-standard lead-free 100-pin TQFP,
lead-free and non-lead-free 119-ball BGA and 165-ball
FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode option
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1381D/CY7C1383D operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
133 MHz
6.5
100 MHz
8.5
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
210
175
mA
mA
70
70
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE CE are for TQFP and 165 FBGA package only. 119 BGA is offered only in 1 Chip Enable.
3,
2
Cypress Semiconductor Corporation
Document #: 38-05544 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 23, 2006
CY7C1381D
CY7C1383D
1
Logic Block Diagram – CY7C1381D (512K x 36)
ADDRESS
REGISTER
A0, A1, A
A[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
AND LOGIC
Q0
CLR
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D, DQPD
DQ
BYTE
WRITE REGISTER
D, DQPD
BW
D
DQ
BYTE
WRITE REGISTER
C, DQPC
DQ
BYTE
WRITE REGISTER
C, DQPC
BW
C
OUTPUT
BUFFERS
DQs
MEMORY
ARRAY
SENSE
AMPS
DQP
DQP
DQP
A
DQ
BYTE
WRITE REGISTER
B, DQPB
B
C
DQ
BYTE
WRITE REGISTER
B, DQPB
BW
B
DQPD
DQ
BYTE
WRITE REGISTER
A, DQPA
DQ
A, DQPA
BW
A
BYTE
BWE
WRITE REGISTER
INPUT
GW
REGISTERS
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
2
Logic Block Diagram – CY7C1383D (1M x 18)
ADDRESS
REGISTER
A0,A1,A
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B,DQPB
DQ
B,DQPB
WRITE DRIVER
WRITE REGISTER
BW
B
A
MEMORY
ARRAY
OUTPUT
BUFFERS
DQs
DQP
DQP
SENSE
AMPS
A
B
DQ
A,DQPA
DQA,DQPA
WRITE REGISTER
WRITE DRIVER
BW
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
Document #: 38-05544 Rev. *E
Page 2 of 29
CY7C1381D
CY7C1383D
Pin Configurations
100-pin TQFP Pinout (3 Chip Enable)
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQC
VDDQ
VSSQ
DQC
3
4
5
6
DQC
7
NC
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS/DNU
VDD
DQC
9
10
11
9
VSSQ
VDDQ
DQC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
12
DQC
13
VSS/DNU
14
VDD
15
NC
VDD
ZZ
CY7C1383D
(1M x 18)
CY7C1381D
(512K x 36)
NC
16
NC
VSS
VDD
ZZ
VSS
17
DQD
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
20
21
VDDQ
VSSQ
DQD
22
DQD
23
DQD
24
DQD
25
26
27
NC
VSSQ
VDDQ
DQD
DQD
29
VSSQ
VDDQ
NC
NC
NC
28
DQPD
30
Document #: 38-05544 Rev. *E
Page 3 of 29
CY7C1381D
CY7C1383D
Pin Configurations (continued)
119-Ball BGA
Pinout
CY7C1381D (512K x 36)
1
2
3
4
5
6
7
A
VDDQ
A
A
A
A
VDDQ
ADSP
B
C
NC/288M
NC/144M
A
A
A
A
A
A
A
A
NC/576M
NC/1G
ADSC
VDD
D
E
F
DQC
DQC
VDDQ
DQPC
DQC
VSS
VSS
VSS
NC
CE1
OE
VSS
VSS
VSS
DQPB
DQB
DQB
DQB
DQC
DQB
VDDQ
G
H
J
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
ADV
BWC
VSS
NC
BWB
VSS
NC
GW
VDD
K
DQD
VSS
CLK
NC
VSS
L
M
N
DQD
VDDQ
DQD
DQD
DQD
DQD
DQA
DQA
DQA
DQA
VDDQ
DQA
BWD
VSS
VSS
BWA
VSS
VSS
BWE
A1
DQD
NC
DQPD
A
VSS
A0
VSS
NC
DQPA
A
DQA
NC
P
R
MODE
VDD
T
NC
NC/72M
TMS
A
A
A
NC/36M
NC
ZZ
VDDQ
TDI
TCK
TDO
VDDQ
U
CY7C1383D (1M x 18)
2
A
1
3
A
4
5
6
7
VDDQ
NC/576M
NC/1G
NC
VDDQ
A
A
A
B
C
D
E
F
ADSP
NC/288M
NC/144M
DQB
A
A
A
ADSC
VDD
A
A
A
A
A
NC
DQB
NC
VSS
VSS
VSS
NC
VSS
VSS
VSS
NC
VSS
DQPA
NC
NC
DQA
CE1
OE
VDDQ
DQA
VDDQ
NC
DQB
NC
VDD
NC
DQA
VDD
DQA
NC
VDDQ
G
H
J
BWB
VSS
NC
ADV
DQB
VDDQ
GW
VDD
NC
K
NC
DQB
VSS
CLK
NC
VSS
NC
DQA
L
M
N
P
DQB
VDDQ
DQB
NC
NC
DQB
NC
NC
VSS
VSS
VSS
DQA
NC
NC
VDDQ
NC
BWA
VSS
BWE
A1
VSS
VSS
DQA
NC
DQPB
A0
DQA
R
T
NC
A
A
MODE
A
VDD
NC/36M
TCK
NC
A
A
A
NC
ZZ
NC/72M
VDDQ
TMS
TDI
TDO
NC
VDDQ
U
Document #: 38-05544 Rev. *E
Page 4 of 29
CY7C1381D
CY7C1383D
Pin Configurations (continued)
165-Ball FBGA Pinout(3 Chip Enable)
CY7C1381D (512K x 36)
1
2
A
3
CE1
4
BWC
5
BWB
6
CE3
7
8
9
ADV
10
A
11
NC
NC/288M
NC/144M
DQPC
BWE
GW
VSS
VSS
ADSC
A
B
C
D
A
CE2
VDDQ
VDDQ
BWD
VSS
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
ADSP
VDDQ
VDDQ
A
NC/576M
DQPB
DQB
NC
DQC
NC/1G
DQB
DQC
VDD
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
NC/72M
TDI
A1
TDO
A0
MODE NC/36M
A
A
TMS
TCK
A
A
A
A
R
CY7C1383D (1M x 18)
1
2
A
3
CE1
4
BWB
5
NC
6
CE3
7
8
9
ADV
10
A
11
A
NC/288M
NC/144M
NC
BWE
GW
VSS
VSS
ADSC
A
B
C
D
A
CE2
VDDQ
VDDQ
NC
VSS
VDD
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
ADSP
VDDQ
VDDQ
A
NC/576M
DQPA
DQA
NC
NC/1G
NC
NC
DQB
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
DQA
DQA
ZZ
E
F
NC
NC
G
H
J
VSS
DQB
DQB
DQB
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
NC/72M
TDI
A1
TDO
MODE NC/36M
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05544 Rev. *E
Page 5 of 29
CY7C1381D
CY7C1383D
Pin Definitions
Name
I/O
Description
A ,
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge
A ,
A
0
1
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2] are sampled active.
A[1:0] feed the 2-bit counter.
BWA, BWB
BWC, BWD
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
GW
CLK
CE1
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BW[A:D]and BWE).
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is
sampled only when a new external address is loaded.
CE2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled onthe rising edge of CLK. Usedin conjunction
with CE1 and CE3[2] to select/deselect the device. CE2 is sampled only when a new external
address is loaded.
[2]
CE3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external
address is loaded.
OE
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
Asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when
emerging from a deselected state.
ADV
Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automat-
ically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both
.
asserted, only ADSP is recognized
BWE
ZZ
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Input-
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
DQs
memory location specified by the addresses presented during the previous
clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The
outputs are automatically tri-stated during the data portion of a write sequence, during the
first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
I/O-
Synchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs.
During write sequences, DQPX is controlled by BWX correspondingly.
DQPX
MODE
Input-Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD
or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an internal pull-up.
VDD
VDDQ
VSS
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground
Ground for the core of the device.
Document #: 38-05544 Rev. *E
Page 6 of 29
CY7C1381D
CY7C1383D
Pin Definitions (continued)
Name
I/O
Description
VSSQ
TDO
I/O Ground
Ground for the I/O circuitry.
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
Synchronous
JTAG feature is not being utilized, this pin should be left unconnected. This pin is not
available on TQFP packages.
TDI
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not being utilized, this pin can be left floating or connected to VDD through a pull up
resistor. This pin is not available on TQFP packages.
TMS
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TCK
NC
JTAG-
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to VSS. This pin is not available on TQFP packages.
–
No Connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M and 1G
are address expansion pins and are not internally connected to the die.
VSS/DNU
Ground/DNU
This pin can be connected to Ground or should be left floating.
Single Write Accesses Initiated by ADSP
Functional Overview
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (tCDV) is 6.5 ns (133-MHz device).
[2]
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BWX)are ignored during this first clock
cycle. If the write inputs are asserted active (see Write Cycle
Descriptions table for appropriate states that indicate a write)
on the next clock rise, the appropriate data will be latched and
written into the device. Byte writes are allowed. All I/Os are
tri-stated during a byte write.Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless of the state of OE.
The CY7C1381D/CY7C1383D supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3[2] are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active
LOW.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3[2]) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ[A:D] will be
written into the specified address location. Byte writes are
allowed. All I/Os are tri-stated when a write is detected, even
a byte write. Since this is a common I/O device, the
asynchronous OE input signal must be deasserted and the
I/Os must be tri-stated prior to the presentation of data to DQs.
As a safety precaution, the data lines are tri-stated once a write
cycle is detected, regardless of the state of OE.
Single Read Accesses
A single read access is initiated when the following conditions
[2]
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to tCDV after clock
rise. ADSP is ignored if CE1 is HIGH.
Document #: 38-05544 Rev. *E
Page 7 of 29
CY7C1381D
CY7C1383D
Burst Sequences
Interleaved Burst Address Table
(MODE = Floating or VDD
)
The CY7C1381D/CY7C1383D provides an on-chip two-bit
wraparound burst counter inside the SRAM. The burst counter
is fed by A[1:0], and can follow either a linear or interleaved
burst order. The burst order is determined by the state of the
MODE input. A LOW on MODE will select a linear burst
sequence. A HIGH on MODE will select an interleaved burst
order. Leaving MODE unconnected will cause the device to
default to a interleaved burst sequence.
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3[2], ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
ZZ > VDD – 0.2V
Min.
Max.
Unit
mA
ns
80
tZZS
ZZ > VDD – 0.2V
2tCYC
tZZREC
tZZI
ZZ recovery time
ZZ < 0.2V
2tCYC
0
ns
ZZ active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
ns
Truth Table[3, 4, 5, 6, 7]
ADDRESS
Used
Cycle Description
CE1 CE2 CE3 ZZ ADSP
ADSC ADV WRITE OE CLK
DQ
Deselected Cycle,
Power-down
None
None
None
None
None
H
L
L
L
X
X
X
X
H
X
X
L
L
L
L
L
X
L
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
Deselected Cycle,
Power-down
L
L
Deselected Cycle,
Power-down
X
L
L
Deselected Cycle,
Power-down
H
H
Deselected Cycle,
Power-down
X
Sleep Mode, Power-down
Read Cycle, Begin Burst
None
X
L
X
H
X
L
H
L
X
L
X
X
X
X
X
X
X
L
X
Tri-State
Q
External
L-H
Notes:
3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the signal. is asynchronous and is not sampled with the clock.
OE
OE
must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks
X
after the
or with the assertion of
. As a result,
ADSC
is a
OE
OE
ADSP
don't care for the remainder of the write cycle.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when
7.
is
OE
OE
inactive or when the device is deselected, and all data bits behave as output when
is active (LOW).
OE
Document #: 38-05544 Rev. *E
Page 8 of 29
CY7C1381D
CY7C1383D
Truth Table[3, 4, 5, 6, 7] (continued)
ADDRESS
Used
Cycle Description
CE1 CE2 CE3 ZZ
ADSP
L
ADSC ADV WRITE OE CLK
DQ
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
External
External
External
External
Next
L
L
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
X
X
X
X
L
X
L
H
X
L
L-H Tri-State
H
L-H
L-H
D
Q
L
L
H
L
H
H
H
H
H
H
L
L
L
H
L
H
L
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H Tri-State
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
H
L
H
L
Next
X
L
Q
Next
X
L
H
X
X
L
Next
H
L
L-H
L-H
L-H
D
D
Q
Next
X
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L-H Tri-State
L-H
L-H Tri-State
X
Q
X
H
X
X
H
L-H
L-H
D
D
X
L
Partial Truth Table for Read/Write[3, 8]
Function (CY7C1381D)
Read
GW
BWE
BWD
X
BWC
X
BWB
X
BWA
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
Read
H
H
H
H
Write Byte A (DQA, DQPA)
Write Byte B(DQB, DQPB)
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
Write Byte C (DQC, DQPC)
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
H
H
H
L
H
H
L
H
H
H
L
L
H
L
H
H
H
L
H
L
H
L
L
H
Write Bytes C, B, A (DQC, DQB, DQA, DQPC,
DQPB, DQPA)
H
L
L
L
Write Byte D (DQD, DQPD)
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
L
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
L
Write Bytes D, B, A (DQD, DQB, DQA, DQPD,
DQPB, DQPA)
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
H
L
L
L
L
L
L
H
H
H
L
Write Bytes D, B, A (DQD, DQC, DQA, DQPD,
DQPC, DQPA)
Note:
8. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid Appropriate write will be done based on which byte write is active.
X
Document #: 38-05544 Rev. *E
Page 9 of 29
CY7C1381D
CY7C1383D
Truth Table for Read/Write[3,8]
Function (CY7C1383D)
GW
BWE
BWB
BWA
Write Bytes D, C, A (DQD, DQB, DQA, DQPD,
DQPB, DQPA)
H
L
L
L
Write All Bytes
H
L
L
X
H
L
L
X
X
H
H
L
L
X
X
H
L
Write All Bytes
Read
H
H
H
H
H
L
Read
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write All Bytes
L
L
H
L
L
L
Write All Bytes
X
X
X
Document #: 38-05544 Rev. *E
Page 10 of 29
CY7C1381D
CY7C1383D
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1381D/CY7C1383D incorporates a serial boundary
scan test access port (TAP).This part is fully compliant with
1149.1. The TAP operates using JEDEC-standard 3.3V or
2.5V I/O logic levels.
The CY7C1381D/CY7C1383D contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
TAP Controller Block Diagram
0
Bypass Register
2
1
0
0
0
TAP Controller State Diagram
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
Selection
TDI
TDO
TEST-LOGIC
1
Circuitr
y
.
.
. 2 1
RESET
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
x
.
.
.
.
. 2 1
0
0
Boundary Scan Register
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
TCK
TMS
1
1
TAP CONTROLLER
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
0
Performing a TAP Reset
1
1
0
0
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
Document #: 38-05544 Rev. *E
Page 11 of 29
CY7C1381D
CY7C1383D
Bypass Register
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required - that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST Output Bus Tri-State
IDCODE
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The boundary scan register has a special bit located at bit #85
(for 119-BGA package) or bit #89 (for 165-fBGA package).
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
Document #: 38-05544 Rev. *E
Page 12 of 29
CY7C1381D
CY7C1383D
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter
Description
Min.
Max.
Unit
Clock
tTCYC
tTF
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
tTH
20
20
tTL
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
10
ns
ns
tTDOX
0
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
5
5
5
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tTDIH
tCH
Capture Hold after Clock Rise
Notes:
9. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
10. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document #: 38-05544 Rev. *E
Page 13 of 29
CY7C1381D
CY7C1383D
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ................................................ VSS to 3.3V
Input rise and fall times................................................... 1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels......................................... 1.25V
Output reference levels ................................................ 1.25V
Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
ZO= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)[11]
Parameter
VOH1
Description
Output HIGH Voltage IOH = –4.0 mA
OH = –1.0 mA
Conditions
VDDQ = 3.3V
Min.
2.4
2.0
2.9
2.1
Max.
Unit
V
I
VDDQ = 2.5V
VDDQ = 3.3V
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
IOH = –100 µA
V
VDDQ = 2.5V
V
IOL = 8.0 mA
IOL = 8.0 mA
IOL = 100 µA
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
0.4
0.4
V
V
0.2
V
V
DDQ = 2.5V
VDDQ = 3.3V
DDQ = 2.5V
VDDQ = 3.3V
DDQ = 2.5V
0.2
V
2.0
1.7
VDD + 0.3
VDD + 0.3
0.8
V
V
V
VIL
–0.3
–0.3
–5
V
V
0.7
V
IX
GND < VIN < VDDQ
5
µA
Document #: 38-05544 Rev. *E
Page 14 of 29
CY7C1381D
CY7C1383D
Identification Register Definitions
CY7C1381D
CY7C1383D
(1M × 18)
Instruction Field
Revision Number (31:29)
Device Depth (28:24)[12]
(512K × 36)
Description
000
000
Describes the version number.
Reserved for Internal Use
01011
01011
Device Width (23:18) 119-BGA
Device Width (23:18) 165-FBGA
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
101001
000001
100101
00000110100
1
101001
000001
010101
Defines memory type and architecture
Defines memory type and architecture
Defines width and density
00000110100 Allows unique identification of SRAM vendor.
1
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (×36)
Bit Size (×18)
Instruction Bypass
3
3
Bypass
ID
1
1
32
85
89
32
85
89
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball fBGA package)
Identification Codes
Instruction
EXTEST
Code
Description
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Notes:
11. All voltages referenced to V (GND).
SS
12. Bit #24 is “1” in the Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: 38-05544 Rev. *E
Page 15 of 29
CY7C1381D
CY7C1383D
119-Ball BGA Boundary Scan Order [13, 14]
Bit #
1
Ball ID
Bit #
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Ball ID
F6
Bit #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Ball ID
G4
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
Bit #
Ball ID
L1
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
H4
T4
T5
T6
R5
L5
2
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
B6
D4
B4
F4
M2
N1
3
4
P1
5
K1
6
L2
7
R6
U6
R7
T7
P6
N7
M6
L7
N2
P2
8
9
R3
10
11
12
13
14
15
16
17
18
19
20
21
22
T1
R1
T2
L3
R2
K6
P7
N6
L6
G1
H2
D1
E2
G2
H1
J3
T3
L4
N4
P4
K7
J5
M4
A5
K4
E4
Internal
H6
G7
2K
Notes:
13. Balls which are NC (No Connect) are pre-set LOW.
14. Bit# 85 is pre-set HIGH.
Document #: 38-05544 Rev. *E
Page 16 of 29
CY7C1381D
CY7C1383D
165-Ball BGA Boundary Scan Order [13, 15]
Bit #
1
Ball ID
N6
Bit #
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Ball ID
D10
C11
A11
B11
A10
B10
A9
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
G1
D2
E2
2
N7
3
N10
P11
P8
4
F2
5
G2
H1
H3
J1
6
R8
7
R9
8
P9
B9
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
C10
A8
K1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
L1
B8
M1
J2
A7
B7
K2
B6
L2
A6
M2
N1
N2
P1
B5
A5
A4
B4
R1
R2
P3
B3
A3
A2
R3
P2
H10
G11
F11
E11
D11
G10
F10
E10
B2
C2
R4
P4
B1
A1
N5
P6
C1
D1
R6
Internal
E1
F1
Note:
15. Bit# 89 is pre-set HIGH.
Document #: 38-05544 Rev. *E
Page 17 of 29
CY7C1381D
CY7C1383D
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current.....................................................> 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V
Supply Voltage on VDDQ Relative to GND ......–0.3V to +VDD
Ambient
Temperature
Range
VDD
VDDQ
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5%
to VDD
Industrial
–40°C to +85°C
Electrical Characteristics Over the Operating Range [16, 17]
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
3.6
Unit
V
VDDQ
for 3.3V I/O
for 2.5V I/O
VDD
V
2.625
V
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
for 3.3V I/O, IOH = –4.0 mA
for 2.5V I/O, IOH = –1.0 mA
for 3.3V I/O, IOL = 8.0 mA
for 2.5V I/O, IOL = 1.0 mA
V
2.0
V
0.4
0.4
V
V
Input HIGH Voltage[16] for 3.3V I/O
2.0
1.7
VDD + 0.3V
VDD + 0.3V
0.8
V
for 2.5V I/O
V
Input LOW Voltage[16]
for 3.3V I/O
for 2.5V I/O
–0.3
–0.3
–5
V
0.7
V
Input Leakage Current GND ≤ VI ≤ VDDQ
except ZZ and MODE
5
µA
Input Current of MODE Input = VSS
Input = VDD
–30
–5
µA
µA
µA
µA
µA
mA
mA
mA
5
Input Current of ZZ
Input = VSS
Input = VDD
30
5
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled
–5
VDD Operating Supply VDD = Max., IOUT = 0 mA,
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
210
175
140
120
Current
f = fMAX = 1/tCYC
ISB1
ISB2
ISB3
ISB4
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
inputs switching
Automatic CE
Power-down
Current—CMOS Inputs f = 0, inputs static
Max. VDD, Device Deselected,
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
All speeds
70
mA
Automatic CE
Power-down
Current—CMOS Inputs f = fMAX, inputs switching
Max. VDD, Device Deselected,
VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V,
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
130
110
mA
mA
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
All Speeds
80
mA
Notes:
16. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
17. T
: Assumes a linear ramp from 0v to V (min.) within 200 ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
Document #: 38-05544 Rev. *E
Page 18 of 29
CY7C1381D
CY7C1383D
Capacitance[19]
100 TQFP
Package
119 BGA
Package
165 FBGA
Parameter
Description
Test Conditions
Package
Unit
pF
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
DD = 3.3V.
VDDQ = 2.5V
5
5
5
8
8
8
9
9
9
V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
pF
Thermal Resistance[19]
100 TQFP
Package
119 BGA
Package
165 FBGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per
EIA/JESD51.
28.66
23.8
20.7
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
4.08
6.2
4.0
°C/W
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
INCLUDING
JIG AND
SCOPE
V = 1.5V
T
(a)
(b)
(c)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R = 1538Ω
≤ 1 ns
≤ 1 ns
INCLUDING
JIG AND
SCOPE
V = 1.25V
T
(a)
(b)
(c)
Note:
18. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05544 Rev. *E
Page 19 of 29
CY7C1381D
CY7C1383D
Switching Characteristics Over the Operating Range [23, 24]
133 MHz
100 MHz
Parameter
tPOWER
Description
VDD(Typical) to the first Access[19]
Min.
Max.
Min.
Max.
Unit
1
1
ms
Clock
tCYC
Clock Cycle Time
Clock HIGH
7.5
2.1
2.1
10
2.5
2.5
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCDV
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[20, 21, 22]
6.5
8.5
ns
ns
ns
ns
ns
ns
ns
tDOH
2.0
2.0
0
2.0
2.0
0
tCLZ
tCHZ
Clock to High-Z[20, 21, 22]
4.0
3.2
5.0
3.8
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
Set-up Times
tAS
OE LOW to Output Low-Z[20, 21, 22]
OE HIGH to Output High-Z[20, 21, 22]
0
0
4.0
5.0
Address Set-up Before CLK Rise
ADSP, ADSC Set-up Before CLK Rise
ADV Set-up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BW[A:D] Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-up
tDS
tCES
Hold Times
tAH
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tADH
ADSP, ADSC Hold After CLK Rise
GW, BWE, BW[A:D] Hold After CLK Rise
ADV Hold After CLK Rise
tWEH
tADVH
tDH
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tCEH
Notes:
19. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially, before a read or write operation
DD
POWER
can be initiated.
20. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
CHZ CLZ OELZ
21. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
OEHZ
OELZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system condition.
22. This parameter is sampled and not 100% tested.
23. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
24. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05544 Rev. *E
Page 20 of 29
CY7C1381D
CY7C1383D
Timing Diagrams
Read Cycle Timing[25]
t
CYC
t
CLK
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
X
Deselect Cycle
t
t
CES
CEH
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note:
25. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05544 Rev. *E
Page 21 of 29
CY7C1381D
CY7C1383D
Timing Diagrams (continued)
Write Cycle Timing[25, 26]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW
X
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
DON’T CARE
UNDEFINED
Note:
26.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document #: 38-05544 Rev. *E
Page 22 of 29
CY7C1381D
CY7C1383D
Timing Diagrams (continued)
Read/Write Cycle Timing[25, 27, 28]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
Back-to-Back READs
Single WRITE
BURST READ
WRITEs
DON’T CARE
UNDEFINED
Notes:
27. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
28.
GW is HIGH.
Document #: 38-05544 Rev. *E
Page 23 of 29
CY7C1381D
CY7C1383D
Timing Diagrams (continued)
ZZ Mode Timing[29, 30]
CLK
ZZ
t
t
ZZ
ZZREC
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
29. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
30. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05544 Rev. *E
Page 24 of 29
CY7C1381D
CY7C1383D
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Part and Package Type
133 CY7C1381D-133AXC
CY7C1383D-133AXC
CY7C1381D-133BGC
CY7C1383D-133BGC
CY7C1381D-133BGXC
CY7C1383D-133BGXC
CY7C1381D-133BZC
CY7C1383D-133BZC
CY7C1381D-133BZXC
CY7C1383D-133BZXC
CY7C1381D-133AXI
CY7C1383D-133AXI
CY7C1381D-133BGI
CY7C1383D-133BGI
CY7C1381D-133BGXI
CY7C1383D-133BGXI
CY7C1381D-133BZI
CY7C1383D-133BZI
CY7C1381D-133BZXI
CY7C1383D-133BZXI
100 CY7C1381D-100AXC
CY7C1383D-100AXC
CY7C1381D-100BGC
CY7C1383D-100BGC
CY7C1381D-100BGXC
CY7C1383D-100BGXC
CY7C1381D-100BZC
CY7C1383D-100BZC
CY7C1381D-100BZXC
CY7C1383D-100BZXC
CY7C1381D-100AXI
CY7C1383D-100AXI
CY7C1381D-100BGI
CY7C1383D-100BGI
CY7C1381D-100BGXI
CY7C1383D-100BGXI
CY7C1381D-100BZI
CY7C1383D-100BZI
CY7C1381D-100BZXI
CY7C1383D-100BZXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
lndustrial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
lndustrial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
Document #: 38-05544 Rev. *E
Page 25 of 29
CY7C1381D
CY7C1383D
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
A
Document #: 38-05544 Rev. *E
Page 26 of 29
CY7C1381D
CY7C1383D
Package Diagrams (continued)
119-ball BGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
Document #: 38-05544 Rev. *E
Page 27 of 29
CY7C1381D
CY7C1383D
Package Diagrams (continued)
165-ball FBGA (13 x 15 x 1.4 mm) (51-85180)
BOTTOM VIEW
PIN 1 CORNER
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
-0.06
Ø0.50
(165X)
+0.14
1
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
A
B
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00
5.00
10.00
13.00 0.10
B
B
13.00 0.10
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDECREFERENCE: MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
SEATING PLANE
C
51-85180-*A
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05544 Rev. *E
Page 28 of 29
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1381D
CY7C1383D
Document History Page
Document Title: CY7C1381D/CY7C1383D 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
Document Number: 38-05544
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
254518
288531
See ECN
See ECN
RKF
SYT
New data sheet
*A
Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
non-compliance with 1149.1
Removed 117-MHz Speed Bin
Added lead-free information for 100-Pin TQFP, 119 BGA and 165 FBGA
package
Added comment of ‘Lead-free BG packages availability’ below the Ordering
Information
*B
326078
See ECN
PCI
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Added description on EXTEST Output Bus Tri-State
Changed description on the Tap Instruction Set Overview and Extest
Changed Device Width (23:18) for 119-BGA from 000001 to 101001
Added separate row for 165 -FBGA Device Width (23:18)
Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to 28.66 and
4.08 °C/W respectively
Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to 23.8 and 6.2
°C/W respectively
Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to 20.7 and
4.0 °C/W respectively
Modified VOL, VOH test conditions
Removed comment of ‘Lead-free BG packages availability’ below the
Ordering Information
Updated Ordering Information Table
Changed from Preliminary to Final
*C
*D
351895
416321
See ECN
See ECN
PCI
Updated Ordering Information Table
NXR
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed the description of IX from Input Load Current to Input Leakage
Current on page# 18
Changed the IX current values of MODE on page # 18 from –5 µA and 30 µA
to –30 µA and 5 µA
Changed the IX current values of ZZ on page # 18 from –30 µA and 5 µA
to –5 µA and 30 µA
Changed VIH < VDD to VIH < VDDon page # 18
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
*E
475009
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP
AC Switching Characteristics table.
Updated the Ordering Information table.
Document #: 38-05544 Rev. *E
Page 29 of 29
相关型号：
CY7C1381D-100BGIT
Cache SRAM, 512KX36, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CYPRESS
CY7C1381D-100BZIT
Standard SRAM, 512KX36, 8.5ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CYPRESS
CY7C1381D-117AI
Cache SRAM, 512KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
CY7C1381D-117BGI
Cache SRAM, 512KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CYPRESS
CY7C1381D-117BZI
Cache SRAM, 512KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165
CYPRESS
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