CY7C1381KV33-133AXC [CYPRESS]
18-Mbit (512K Ã 36/1M Ã 18) Flow-Through SRAM (With ECC);
| 型号： | CY7C1381KV33-133AXC |
| 厂家： | 
CYPRESS |
| 描述： | 18-Mbit (512K Ã 36/1M Ã 18) Flow-Through SRAM (With ECC) 静态存储器 |
| 文件： | 总34页 (文件大小：1120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
18-Mbit (512K × 36/1M × 18)
Flow-Through SRAM (With ECC)
18-Mbit (512K
× 36/1M × 18) Flow-Through SRAM (With ECC)
Features
Functional Description
■ Supports 133 MHz bus operations
■ 512K × 36 and 1M × 18 common I/O
The CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/
CY7C1383KVE33 are a 3.3 V, 512K × 36 and 1M × 18
synchronous flow through SRAMs, designed to interface with
high speed microprocessors with minimum glue logic. Maximum
access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit
on-chip counter captures the first address in a burst and
increments the address automatically for the rest of the burst
access. All synchronous inputs are gated by registers controlled
by a positive edge triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address pipelining
chip enable (CE1), depth-expansion chip enables (CE2 and
CE3), burst control inputs (ADSC, ADSP, and ADV), write
enables (BWx, and BWE), and global write (GW). Asynchronous
inputs include the output enable (OE) and the ZZ pin.
■ 3.3 V core power supply (VDD
)
■ 2.5 V or 3.3 V I/O supply (VDDQ
)
■ Fast clock-to-output time
❐ 6.5 ns (133 MHz version)
■ Provides high performance 2-1-1-1 access rate
■ User selectable burst counter supporting interleaved or linear
burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/
The
CY7C1383KVE33
allows interleaved or linear burst sequences,
selected by the MODE input pin. A HIGH selects an interleaved
burst sequence, while a LOW selects a linear burst sequence.
Burst accesses can be initiated with the processor address
strobe (ADSP) or the cache controller address strobe (ADSC)
inputs. Address advancement is controlled by the address
advancement (ADV) input.
■ Asynchronous output enable
■ CY7C1381KV33/CY7C1381KVE33
available
in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free 165-ball
FBGA package. CY7C1383KV33/CY7C1383KVE33 available
in JEDEC-standard Pb-free 100-pin TQFP.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as controlled by the advance pin (ADV).
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ ZZ sleep mode option.
CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/
■ On-chip error correction code (ECC) to reduce soft error rate
(SER)
CY7C1383KVE33 operates from a +3.3 V core power supply
while all outputs operate with a +2.5 V or +3.3 V supply. All inputs
and outputs are JEDEC-standard and JESD8-5-compatible.
Selection Guide
Description
Maximum access time
133 MHz
6.5
100 MHz Unit
8.5
114
134
ns
Maximum operating current
× 18
× 36
129
mA
mA
149
Cypress Semiconductor Corporation
Document Number: 001-97888 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 16, 2018
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Logic Block Diagram – CY7C1381KV33
(512K × 36)
ADDRESS
REGISTER
A0, A1, A
A
[1:0]
MODE
ADV
CLK
Q1
Q0
BURST
COUNTER
AND LOGIC
CLR
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D, DQP D
DQ
BYTE
WRITE REGISTER
D, DQP D
BW
D
DQ C , DQP C
DQ C , DQP C
BW
C
WRITE REGISTER
DQ DQP
OUTPUT
BUFFERS
DQs
DQP
DQP
DQP
DQP
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
A
B
B
,
B
DQ B, DQP B
BW
B
C
D
WRITE REGISTER
DQ DQP
WRITE REGISTER
A
,
BYTE
DQ
BYTE
WRITE REGISTER
A, DQP A
BW
A
WRITE REGISTER
BWE
INPUT
GW
REGISTERS
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
Logic Block Diagram – CY7C1381KVE33
(512K × 36)
ADDRESS
REGISTER
A0, A1, A
A[1:0]
MODE
ADV
CLK
Q1
Q0
BURST
COUNTER
AND LOGIC
CLR
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D, DQPD
DQ
BYTE
WRITE REGISTER
D, DQPD
BWD
DQ
BYTE
WRITE REGISTER
C, DQPC
DQ
BYTE
WRITE REGISTER
C, DQPC
BW
C
ECC
DECODER
OUTPUT
BUFFERS
DQs
MEMORY
ARRAY
SENSE
AMPS
DQP
DQP
DQP
A
DQ
BYTE
WRITE REGISTER
B, DQPB
B
C
DQ
BYTE
WRITE REGISTER
B, DQPB
BW
B
DQP
D
DQ
BYTE
WRITE REGISTER
A, DQPA
DQ
BYTE
WRITE REGISTER
A, DQPA
BW
A
BWE
ECC
ENCODER
INPUT
REGISTERS
GW
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
Document Number: 001-97888 Rev. *F
Page 2 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Logic Block Diagram – CY7C1383KV33
(1M × 18)
ADDRESS
REGISTER
A0,A1,A
A[1:0]
MODE
ADV
Q1
COUNTER AND
BURST
Q0
DQ
B
,DQP
B
DQ
DQ
B
,DQP
,DQP
B
WRITE DRIVER
BW
BW
B
MEMORY
ARRAY
OUTPUT
BUFFERS
DQs
DQP
DQP
SENSE
AMPS
A
B
DQ
A,DQP A
A
A
WRITE DRIVER
A
BWE
GW
INPUT
REGISTERS
ENABLE
CE
CE
1
2
CE
3
OE
SLEEP
CONTROL
Logic Block Diagram – CY7C1383KVE33
(1M × 18)
Document Number: 001-97888 Rev. *F
Page 3 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Contents
Pin Configurations ...........................................................5
Pin Definitions ..................................................................7
Functional Overview ........................................................9
Single Read Accesses ................................................9
Single Write Accesses Initiated by ADSP ...................9
Single Write Accesses Initiated by ADSC ...................9
Burst Sequences .........................................................9
Sleep Mode .................................................................9
Interleaved Burst Address Table ...............................10
Linear Burst Address Table .......................................10
ZZ Mode Electrical Characteristics ............................10
Truth Table ......................................................................11
Truth Table for Read/Write ............................................12
Truth Table for Read/Write ............................................12
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................13
Disabling the JTAG Feature ......................................13
Test Access Port (TAP) .............................................13
PERFORMING A TAP RESET ..................................13
TAP REGISTERS ......................................................13
TAP Instruction Set ...................................................14
TAP Controller State Diagram .......................................15
TAP Controller Block Diagram ......................................16
TAP Timing ......................................................................17
TAP AC Switching Characteristics ...............................17
3.3 V TAP AC Test Conditions .......................................18
3.3 V TAP AC Output Load Equivalent .........................18
2.5 V TAP AC Test Conditions .......................................18
2.5 V TAP AC Output Load Equivalent .........................18
TAP DC Electrical Characteristics
and Operating Conditions .............................................18
Identification Register Definitions ................................19
Scan Register Sizes .......................................................19
Instruction Codes ...........................................................19
Boundary Scan Order ....................................................20
Maximum Ratings ...........................................................21
Operating Range .............................................................21
Neutron Soft Error Immunity .........................................21
Electrical Characteristics ...............................................21
Capacitance ....................................................................23
Thermal Resistance ........................................................23
AC Test Loads and Waveforms .....................................23
Switching Characteristics ..............................................24
Timing Diagrams ............................................................25
Ordering Information ......................................................29
Ordering Code Definitions .........................................29
Package Diagrams ..........................................................30
Acronyms ........................................................................32
Document Conventions .................................................32
Units of Measure .......................................................32
Document History Page .................................................33
Sales, Solutions, and Legal Information ......................34
Worldwide Sales and Design Support .......................34
Products ....................................................................34
PSoC® Solutions ......................................................34
Cypress Developer Community .................................34
Technical Support .....................................................34
Document Number: 001-97888 Rev. *F
Page 4 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3-Chip Enable)
CY7C1381KV33/CY7C1381KVE33 (512K × 36) CY7C1383KV33/CY7C1383KVE33 (1M × 18)
Document Number: 001-97888 Rev. *F
Page 5 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Pin Configurations (continued)
Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout (3-Chip Enable)
CY7C1381KV33 (512K × 36)
1
2
3
4
5
6
7
8
9
10
A
11
NC
NC/288M
NC/144M
DQPC
A
B
C
D
CE1
BWC
BWD
VSS
VDD
BWB
BWA
VSS
VSS
CE3
CLK
VSS
VSS
ADSC
OE
A
BWE
GW
VSS
VSS
ADV
ADSP
VDDQ
VDDQ
A
CE2
VDDQ
VDDQ
A
NC/576M
DQPB
DQB
NC
VSS
VDD
NC/1G
DQB
DQC
DQC
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
NC/72M
TDI
A1
TDO
A0
MODE NC/36M
A
A
TMS
TCK
A
A
A
A
R
Document Number: 001-97888 Rev. *F
Page 6 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Pin Definitions
Name
A ,
I/O
Description
Input
Synchronous
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK
if ADSP or ADSC is active LOW, and CE1, CE2, andCE3 are sampled active. A[1:0] feed the 2-bit counter.
A ,
A
0
1
BWA, BWB,
Input
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
BWC, BWD Synchronous
on the rising edge of CLK.
GW
CLK
CE1
Input
Synchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write is
conducted (all bytes are written, regardless of the values on BW[A:D] and BWE).
Input
Clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Input
Synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
CE3
OE
Input
Synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
Input
Synchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
Input
Asynchronou
s
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input
Synchronous
Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically increments
the address in a burst cycle.
ADSP
Input
Synchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
Input
Synchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
.
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized
BWE
ZZ
Input
Synchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
LOW to conduct a byte write.
Input
Asynchronou
s
ZZ sleep input. This active HIGH input places the device in a non time critical sleep condition with data
integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal
pull down.
I/O
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
DQs
Synchronous
addresses presented during the previous
read cycle. The direction of the pins is
clock rise of the
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tristate condition.The outputs are automatically tristated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
I/O
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
sequences, DQPX is controlled by BWX correspondingly.
DQPX
Synchronous
Document Number: 001-97888 Rev. *F
Page 7 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Pin Definitions (continued)
Name
MODE
I/O
Description
Input Static Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode pin has an internal pull-up.
VDD
PowerSupply Power supply inputs to the core of the device.
VDDQ
I/O Power Power supply for the I/O circuitry.
Supply
VSS
Ground
Ground for the core of the device.
VSSQ
TDO
I/O Ground Ground for the I/O circuitry.
JTAG Serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is
Output
Synchronous
not being used, this pin can be left unconnected. This pin is not available on TQFP packages.
TDI
JTAG Serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
Input
used, this pin can be left floating or connected to VDD through a pull-up resistor. This pin is not available
on TQFP packages.
Synchronous
TMS
JTAG Serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
Input
used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
Synchronous
TCK
JTAG
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be connected
to VSS. This pin is not available on TQFP packages.
NC
–
No connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
VSS/DNU
Ground/DNU This pin can be connected to ground or can be left floating.
Document Number: 001-97888 Rev. *F
Page 8 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
clock rise, the appropriate data is latched and written into the
device. Byte writes are allowed. All I/O are tristated during a byte
write. As this is a common I/O device, the asynchronous OE
input signal must be deasserted and the I/O must be tristated
prior to the presentation of data to DQs. As a safety precaution,
the data lines are tristated when a write cycle is detected,
regardless of the state of OE.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (tCDV) is 6.5 ns (133 MHz device).
CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/CY7C138
3KVE33 supports secondary cache in systems using a linear or
interleaved burst sequence. The linear burst sequence is suited
for processors that use a linear burst sequence. The burst order
is user selectable, and is determined by sampling the MODE
input. Accesses can be initiated with the processor address
strobe (ADSP) or the controller address strobe (ADSC). Address
advancement through the burst sequence is controlled by the
ADV input. A two-bit on-chip wraparound burst counter captures
the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter, the control logic, or both, and delivered to
the memory core The information presented to DQ[A:D] is written
into the specified address location. Byte writes are allowed. All
I/O are tristated when a write is detected, even a byte write.
Because this is a common I/O device, the asynchronous OE
input signal must be deasserted and the I/O must be tristated
prior to the presentation of data to DQs. As a safety precaution,
the data lines are tristated when a write cycle is detected,
regardless of the state of OE.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE1 is
HIGH.
Burst Sequences
Single Read Accesses
CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/CY7C138
3KVE33 provides an on-chip two-bit wraparound burst counter
inside the SRAM. The burst counter is fed by A[1:0], and can
follow either a linear or interleaved burst order. The burst order
is determined by the state of the MODE input. A LOW on MODE
selects a linear burst sequence. A HIGH on MODE selects an
interleaved burst order. Leaving MODE unconnected causes the
device to default to a interleaved burst sequence.
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP or ADSC is asserted LOW (if the access is
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter and/or
control logic, and later presented to the memory core. If the OE
input is asserted LOW, the requested data is available at the data
outputs with a maximum to tCDV after clock rise. ADSP is ignored
if CE1 is HIGH.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CE1, CE2, CE3,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active,
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BWX) are ignored during this first clock cycle. If the write
inputs are asserted active (see Truth Table for Read/Write on
page 12 for appropriate states that indicate a write) on the next
Document Number: 001-97888 Rev. *F
Page 9 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Interleaved Burst Address Table
(MODE = Floating or VDD
Linear Burst Address Table
)
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min
Max
65
Unit
mA
ns
ZZ > VDD– 0.2 V
–
tZZS
ZZ > VDD – 0.2 V
ZZ < 0.2 V
–
2tCYC
–
2tCYC
–
tZZREC
tZZI
ns
ZZ active to sleep current
This parameter is sampled
2tCYC
–
ns
tRZZI
ZZ inactive to exit sleep current This parameter is sampled
0
ns
Document Number: 001-97888 Rev. *F
Page 10 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Truth Table
The truth table for CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/CY7C1383KVE33 follows. [1, 2, 3, 4, 5]
Cycle Description
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Sleep Mode, Power Down
Read Cycle, Begin Burst
Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
None
None
H
L
X
L
X
X
H
X
H
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L–H Tri-State
L–H Tri-State
L–H Tri-State
L–H Tri-State
L–H Tri-State
None
L
X
L
L
None
L
H
H
X
L
None
X
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
X
X
L
X
Tri-State
Q
External
External
External
External
External
Next
L–H
Read Cycle, Begin Burst
L
L
L
H
X
L
L–H Tri-State
Write Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L–H
L–H
D
Q
Read Cycle, Begin Burst
L
L
L
H
H
H
H
H
H
L
Read Cycle, Begin Burst
L
L
L
H
L
L–H Tri-State
L–H
L–H Tri-State
L–H
L–H Tri-State
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L–H
L–H
L–H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L–H Tri-State
L–H
L–H Tri-State
Q
H
X
X
L–H
L–H
D
D
L
Notes
1. X = Don't Care, H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the signal. is asynchronous and is not sampled with the clock.
OE
OE
must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate.
4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks after the
X
or with the assertion of
. As a result,
is a don't care for the
OE
ADSC
OE
ADSP
remainder of the write cycle.
5.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when
is
inactive
OE
or when the device is deselected, and all data bits behave as output when
OE
is active (LOW).
OE
Document Number: 001-97888 Rev. *F
Page 11 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Truth Table for Read/Write
The truth table for CY7C1381KV33/CY7C1381KVE33 read/write follows. [6, 7]
Function (CY7C1381KV33/CY7C1381KVE33)
Read
GW
H
BWE
BWD
X
BWC
X
BWB
X
BWA
X
H
L
L
L
L
L
L
L
L
Read
H
H
H
H
H
Write Byte A (DQA, DQPA)
H
H
H
H
L
Write Byte B(DQB, DQPB)
H
H
H
L
H
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
Write Byte C (DQC, DQPC)
H
H
H
L
L
H
H
L
H
H
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
H
H
L
H
L
H
H
L
L
H
Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB,
DQPA)
H
H
L
L
L
Write Byte D (DQD, DQPD)
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
L
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
L
Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
H
L
L
L
L
L
L
H
H
H
L
Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC,
DQPA)
Truth Table for Read/Write
The truth table for CY7C1383KV33/CY7C1383KVE33 read/write follows. [6, 7]
Function (CY7C1383KV33/CY7C1383KVE33)
GW
BWE
BWB
BWA
Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
L
Write All Bytes
H
L
L
X
H
L
L
X
X
H
H
L
L
X
X
H
L
Write All Bytes
Read
H
H
H
H
H
L
Read
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write All Bytes
L
L
H
L
L
L
Write All Bytes
X
X
X
Notes
6. X=Don't Care, H = Logic HIGH, L = Logic LOW.
7. The table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write is done based on which byte write is active.
X
Document Number: 001-97888 Rev. *F
Page 12 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
TAP Registers
IEEE 1149.1 Serial Boundary Scan (JTAG)
Registers are connected between the TDI and TDO balls and
allow data to be scanned in and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI ball on
the rising edge of TCK. Data is output on the TDO ball on the
falling edge of TCK.
The CY7C1381KV33 incorporates a serial boundary scan test
access port (TAP). This part is fully compliant with 1149.1. The
TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic
levels.
CY7C1381KV33 contains a TAP controller, instruction register,
boundary scan register, bypass register, and ID register.
Instruction Register
Disabling the JTAG Feature
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 16. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
may be left unconnected. At power up, the device comes up in a
reset state, which does not interfere with the operation of the
device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to allow for
fault isolation of the board level serial test path.
Test Access Port (TAP)
Bypass Register
Test Clock (TCK)
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
SRAM with minimal delay. The bypass register is set LOW (VSS
)
when the BYPASS instruction is executed.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
Test Data-In (TDI)
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram on page 15. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
The Boundary Scan Order on page 20 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Instruction Codes on page 19).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Identification (ID) Register
The ID register is loaded with a vendor-specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 19.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high Z state.
Document Number: 001-97888 Rev. *F
Page 13 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
TAP Instruction Set
Overview
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in Instruction
Codes on page 19. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail below.
Instructions are loaded into the TAP controller during the Shift-IR
state, when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction when it is shifted in, the TAP controller needs to
be moved into the Update-IR state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the Shift-DR controller state.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required; that is, while data captured is
shifted out, the preloaded data is shifted in.
BYPASS
IDCODE
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
The IDCODE instruction causes a vendor-specific 32-bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
EXTEST Output Bus Tri-State
IEEE standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
SAMPLE Z
The boundary scan register has a special bit located at bit #89
(for 165-ball FBGA package). When this scan cell, called the
“extest output bus tristate,” is latched into the preload register
during the Update-DR state in the TAP controller, it directly
controls the state of the output (Q-bus) pins, when the EXTEST
is entered as the current instruction. When HIGH, it enables the
output buffers to drive the output bus. When LOW, this bit places
the output bus into a high Z condition.
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. The SAMPLE Z command places
all SRAM outputs into a high Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-97888 Rev. *F
Page 14 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
1
1
1
RUN-TEST/
0
SELECT
DR-SCAN
SELECT
IR-SCAN
IDLE
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
1
0
PAUSE-IR
1
0
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 001-97888 Rev. *F
Page 15 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
TAP Controller Block Diagram
0
Bypass Register
2
1
0
0
0
Selection
Circuitry
Instruction Register
31 30 29 .
Selection
TDI
TDO
Circuitr
y
.
. 2 1
Identification Register
x
.
.
.
.
. 2 1
Boundary Scan Register
TCK
TMS
TAP CONTROLLER
Document Number: 001-97888 Rev. *F
Page 16 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
TAP Timing
Figure 3. TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range
Parameter [8, 9]
Clock
Description
Min
Max
Unit
tTCYC
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH Time
TCK Clock LOW Time
50
–
–
20
–
ns
MHz
ns
tTF
tTH
20
20
tTL
–
ns
Output Times
tTDOV
tTDOX
Setup Times
tTMSS
tTDIS
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
–
0
10
–
ns
ns
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture Hold after Clock Rise
Notes
8.
t
and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS CH
9. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
Document Number: 001-97888 Rev. *F
Page 17 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input rise and fall times (Slew Rate) ........................... 2 V/ns
Input timing reference levels ......................................... 1.5 V
Output reference levels ................................................ 1.5 V
Test load termination supply voltage ............................ 1.5 V
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall time (Slew Rate) ............................. 2 V/ns
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50 Ω
20pF
ZO= 50 Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted)
Parameter [10]
Description
Test Conditions
VDDQ = 3.3 V
Min
2.4
2.0
2.9
2.1
–
Max
–
Unit
V
VOH1
Output HIGH Voltage
IOH = –4.0 mA
IOH = –1.0 mA
IOH = –100 µA
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
–
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
–
V
–
V
IOL = 8.0 mA
IOL = 8.0 mA
IOL = 100 µA
0.4
0.4
0.2
0.2
V
–
V
–
V
–
V
2.0
1.7
–0.3
–0.3
–5
VDD + 0.3
V
VDD + 0.3
V
VIL
0.8
0.7
5
V
V
IX
GND < VIN < VDDQ
µA
Note
10. All voltages referenced to V (GND).
SS
Document Number: 001-97888 Rev. *F
Page 18 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Identification Register Definitions
CY7C1381KV33
(512K × 36)
Instruction Field
Description
Revision Number (31:29)
Device Depth (28:24) [11]
000
Describes the version number.
Reserved for internal use.
01011
Device Width (23:18)
165-ball FBGA
000001
Defines the memory type and architecture.
Cypress Device ID (17:12)
100101
Defines the width and density.
Cypress JEDEC ID Code
(11:1)
00000110100
Allows unique identification of SRAM vendor.
ID Register Presence
Indicator (0)
1
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (× 36)
Instruction Bypass
3
1
Bypass
ID
32
89
Boundary Scan Order (165-ball FBGA package)
Instruction Codes
Instruction
EXTEST
Code
Description
000
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM outputs to high Z state.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a high Z state.
RESERVED
011
100
Do Not Use. This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use. This instruction is reserved for future use.
Do Not Use. This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
11. Bit #24 is “1” in the register definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 001-97888 Rev. *F
Page 19 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Boundary Scan Order
165-ball FBGA [12, 13]
Bit #
1
Ball ID
Bit #
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Ball ID
D10
C11
A11
B11
A10
B10
A9
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
G1
D2
E2
N6
N7
2
3
N10
P11
P8
4
F2
5
G2
H1
H3
J1
6
R8
7
R9
8
P9
B9
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
C10
A8
K1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
L1
B8
M1
J2
A7
B7
K2
B6
L2
A6
M2
N1
N2
P1
B5
A5
A4
B4
R1
R2
P3
B3
A3
A2
R3
P2
H10
G11
F11
E11
D11
G10
F10
E10
B2
C2
B1
R4
P4
A1
N5
P6
C1
D1
E1
R6
Internal
F1
Notes
12. Balls which are NC (No Connect) are pre-set LOW.
13. Bit# 89 is pre-set HIGH.
Document Number: 001-97888 Rev. *F
Page 20 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Maximum Ratings
Operating Range
Ambient
Temperature
Exceeding the maximum ratings may impair the useful life of the
device. For user guidelines, not tested.
Range
VDD
VDDQ
Commercial
Industrial
0 °C to +70 °C
3.3 V– 5% / 2.5 V – 5% to
Storage Temperature ............................... –65 °C to +150 °C
+ 10%
VDD
–40 °C to +85 °C
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
Neutron Soft Error Immunity
Test
Parameter Description
Conditions
Typ Max* Unit
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
LSBU
Logical
Single-Bit
Upsets
25 °C
<5
5
FIT/
Mb
DC Input Voltage ................................–0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
(Device
without
ECC)
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ..........................> 2001 V
LSBU
(Device with
ECC)
0
0
0
0.01 FIT/
Mb
Latch-up Current ....................................................> 200 mA
LMBU
SEL
Logical
Multi-Bit
Upsets
25 °C
85 °C
0.01 FIT/
Mb
Single Event
Latch up
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
2
statistical , 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”.
Electrical Characteristics
Over the Operating Range
Parameter [14, 15]
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min
3.135
3.135
2.375
2.4
Max
Unit
V
VDD
3.6
VDDQ
for 3.3 V I/O
for 2.5 V I/O
VDD
V
2.625
V
VOH
VOL
VIH
VIL
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[14]
Input LOW Voltage[14]
for 3.3 V I/O, IOH = –4.0 mA
for 2.5 V I/O, IOH = –1.0 mA
for 3.3 V I/O, IOL = 8.0 mA
for 2.5 V I/O, IOL = 1.0 mA
for 3.3 V I/O
–
V
2.0
–
0.4
V
–
V
–
0.4
V
2.0
VDD + 0.3 V
VDD + 0.3 V
0.8
V
for 2.5 V I/O
1.7
V
for 3.3 V I/O
–0.3
–0.3
V
for 2.5 V I/O
0.7
V
Notes
14. Overshoot: V
< V + 1.5 V (Pulse width less than t
/2), undershoot: V
> –2 V (Pulse width less than t
/2).
IH(AC)
DD
CYC
IL(AC)
CYC
15. T
: Assumes a linear ramp from 0 V to V
of at least 200 ms. During this time V < V and V
<V
.
Power-up
DD(min.)
IH
DD
DDQ
DD
Document Number: 001-97888 Rev. *F
Page 21 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Electrical Characteristics (continued)
Over the Operating Range
Parameter [14, 15]
Description
Test Conditions
Min
Max
Unit
IX
Input Leakage Current except ZZ GND VI VDDQ
and MODE
–5
5
A
Input Current of MODE
Input = VSS
–30
–
–
5
Input = VDD
Input Current of ZZ
Input = VSS
–5
–
–
Input = VDD
30
5
IOZ
IDD
Output Leakage Current
VDD Operating Supply
GND VI VDDQ, Output Disabled
–5
–
A
VDD = Max.,
IOUT = 0 mA,
f = fMAX = 1/tCYC
100 MHz
133 MHz
100 MHz
133 MHz
× 18
× 36
× 18
× 36
× 18
× 36
× 18
× 36
× 18
× 36
114
134
129
149
75
80
75
80
65
70
mA
–
–
–
ISB1
Automatic CE Power-down
Current – TTL Inputs
Max. VDD
,
–
mA
Device Deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
–
–
–
ISB2
Automatic CE Power-down
Current – CMOS Inputs
Max. VDD
,
All speed
grades
–
mA
mA
Device Deselected,
VIN 0.3 V or
VIN > VDDQ 0.3 V,
f = 0
–
ISB3
Automatic CE Power-down
Current – CMOS Inputs
Max. VDD
,
100 MHz
133 MHz
× 18
× 36
× 18
× 36
× 18
× 36
–
–
–
–
–
–
75
80
75
80
65
70
Device Deselected,
VIN 0.3 V or
VIN > VDDQ 0.3 V,
f = fMAX = 1/tCYC
ISB4
Automatic CE Power-down
Current – TTL Inputs
Max. VDD
,
All speed
grades
mA
Device Deselected,
VIN VIH or VIN VIL,
f = 0
Document Number: 001-97888 Rev. *F
Page 22 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Capacitance
100-pin TQFP 165-ballFBGA
Parameter
Description
Test Conditions
Unit
Package
Package
CIN
Input capacitance
TA = 25 °C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
5
5
5
5
5
5
pF
pF
pF
CCLK
CIO
Clock input capacitance
Input/Output capacitance
Thermal Resistance
100-pin TQFP 165-ballFBGA
Parameter
Description
Test Conditions
Unit
Package
Package
17.34
14.33
12.63
8.95
JA
Thermal resistance
(junction to ambient)
Test conditions follow With Still Air (0 m/s)
37.95
C/W
C/W
C/W
C/W
standard
methods
test
and
With Air Flow (1 m/s)
33.19
procedures
measuring
impedance,
EIA/JESD51.
for With Air Flow (3 m/s)
thermal
per
30.44
JB
JC
Thermal resistance
(junction to board)
--
24.07
Thermal resistance
(junction to case)
8.36
3.50
C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50
0
10%
L
GND
5 pF
R = 351
1 ns
1 ns
INCLUDING
JIG AND
SCOPE
V = 1.5 V
T
(a)
(b)
(c)
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50
0
10%
L
GND
5 pF
R = 1538
1 ns
1 ns
INCLUDING
JIG AND
SCOPE
V = 1.25 V
T
(a)
(b)
(c)
Document Number: 001-97888 Rev. *F
Page 23 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Switching Characteristics
Over the Operating Range
133 MHz
Max
100 MHz
Max
Parameter [16, 17]
Description
Unit
Min
Min
tPOWER
Clock
tCYC
VDD(typical) to the first access [18]
1
–
1
–
ms
Clock cycle time
Clock HIGH
7.5
2.1
2.1
–
–
–
10
2.5
2.5
–
–
–
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCDV
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z [19, 20, 21]
–
2.0
2.0
0
6.5
–
–
2.0
2.0
0
8.5
–
ns
ns
ns
ns
ns
ns
ns
tDOH
tCLZ
–
–
tCHZ
Clock to high Z [19, 20, 21]
4.0
3.2
–
5.0
3.8
–
tOEV
OE LOW to output valid
–
–
tOELZ
tOEHZ
Setup Times
tAS
OE LOW to output low Z [19, 20, 21]
OE HIGH to output high Z [19, 20, 21]
0
0
–
4.0
–
5.0
Address setup before CLK rise
ADSP, ADSC setup before CLK rise
ADV setup before CLK rise
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BW[A:D] setup before CLK rise
Data input setup before CLK rise
Chip enable setup
tDS
tCES
Hold Times
tAH
Address hold after CLK rise
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADH
ADSP, ADSC hold after CLK rise
GW, BWE, BW[A:D] hold after CLK rise
ADV hold after CLK rise
tWEH
tADVH
tDH
Data input hold after CLK rise
Chip enable hold after CLK rise
tCEH
Notes
16. Timing reference level is 1.5 V when V
= 3.3 V and is 1.25 V when V
= 2.5 V.
DDQ
DDQ
17. Test conditions shown in (a) of Figure 4 on page 23 unless otherwise noted.
18. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V
initially, before a read or write operation can be
POWER
DD(minimum)
initiated.
19. t
, t
, t
, and t
are specified with AC test conditions shown in part (b) of Figure 4 on page 23. Transition is measured ±200 mV from steady-state voltage
OEHZ
CHZ CLZ OELZ
20. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
OEHZ
OELZ
CHZ
CLZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system condition.
21. This parameter is sampled and not 100% tested.
Document Number: 001-97888 Rev. *F
Page 24 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Timing Diagrams
Figure 5. Read Cycle Timing [22]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
X
Deselect Cycle
t
t
CES
CEH
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2
+
3)
Q(A2)
Q(A2
+
1)
Q(A2
+
2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
.
Note
22. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document Number: 001-97888 Rev. *F
Page 25 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Timing Diagrams (continued)
Figure 6. Write Cycle Timing [23, 24]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BWX
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2
+
1)
D(A2
+
1)
D(A2
+
2)
D(A2
+
3)
D(A3)
D(A3
+
1)
D(A3 + 2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
DON’T CARE
UNDEFINED
.
Notes
23. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
24.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document Number: 001-97888 Rev. *F
Page 26 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Timing Diagrams (continued)
Figure 7. Read/Write Cycle Timing [25, 26, 27]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
Back-to-Back READs
Single WRITE
BURST READ
DON’T CARE
UNDEFINED
.
Notes
25. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
26. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.
27. GW is HIGH.
Document Number: 001-97888 Rev. *F
Page 27 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Timing Diagrams (continued)
Figure 8. ZZ Mode Timing [28, 29]
CLK
ZZ
t
t
ZZ
ZZREC
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
28. Device must be deselected when entering ZZ mode. See Truth Table on page 11 for all possible signal conditions to deselect the device.
29. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 001-97888 Rev. *F
Page 28 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a
worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit
us at t http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Part and Package Type
133 CY7C1381KV33-133AXC
CY7C1383KV33-133AXC
CY7C1381KVE33-133AXI
CY7C1381KV33-133AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
lndustrial
CY7C1383KVE33-133AXI
CY7C1383KV33-133AXI
100 CY7C1381KV33-100AXC
CY7C1381KV33-100BZXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
Commercial
lndustrial
Ordering Code Definitions
-
33
E
CY
7
C
13XX
KV
XXX XX
X X
Temperature range: X = C or I
C = Commercial = 0 °C to +70 °C; I = Industrial = -40 °C to +85 °C
X = Pb-free; X Absent = Leaded
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Speed Grade: XXX = 100 MHz or 133 MHz
33 = 3.3 V VDD
E = Device with ECC; E Absent = Device without ECC
Process Technology: K =65 nm
Part Identifier: 13XX = 1381 or 1383
1381 = FT, 512Kb × 36 (18Mb)
1383 = FT, 1Mb × 18 (18Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-97888 Rev. *F
Page 29 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Package Diagrams
Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
ș 2
ș
1
ș
DIMENSIONS
MIN. NOM. MAX.
1.60
NOTE:
SYMBOL
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
MOLD PROTRUSION/END FLASH SHALL
A
0.05
0.15
A1
A2
D
1.35 1.40 1.45
15.80 16.00 16.20
13.90 14.00 14.10
21.80 22.00 22.20
19.90 20.00 20.10
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
D1
E
E1
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
0.08
0.08
0°
R
R
ș
0.20
0.20
7°
1
2
ș 1
ș 2
c
0°
11° 12° 13°
0.20
0.22 0.30 0.38
0.45 0.60 0.75
1.00 REF
b
L
L1
L 2
L 3
e
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Document Number: 001-97888 Rev. *F
Page 30 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Package Diagrams (continued)
Figure 10. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *G
Document Number: 001-97888 Rev. *F
Page 31 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CE
Chip Enable
Symbol
°C
Unit of Measure
CMOS
EIA
Complementary Metal Oxide Semiconductor
Electronic Industries Alliance
Fine-Pitch Ball Grid Array
Input/Output
degree Celsius
megahertz
microampere
milliampere
millimeter
millisecond
millivolt
MHz
µA
mA
mm
ms
mV
ns
FBGA
I/O
JEDEC
JTAG
LMBU
LSB
Joint Electron Devices Engineering Council
Joint Test Action Group
Logical Multi-Bit Upsets
Least Significant Bit
nanosecond
ohm
LSBU
MSB
OE
Logical Single-Bit Upsets
Most Significant Bit
%
percent
Output Enable
pF
V
picofarad
volt
SEL
Single Event Latch Up
Static Random Access Memory
Test Access Port
SRAM
TAP
W
watt
TCK
TDI
Test Clock
Test Data-In
TDO
TMS
TQFP
TTL
Test Data-Out
Test Mode Select
Thin Quad Flat Pack
Transistor-Transistor Logic
Document Number: 001-97888 Rev. *F
Page 32 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document History Page
Document Title: CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/CY7C1383KVE33, 18-Mbit (512K × 36/1M × 18)
Flow-Through SRAM (With ECC)
Document Number: 001-97888
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*C
4983482
DEVM
10/26/2015 Changed status from Preliminary to Final.
*D
*E
5085859
5333612
DEVM
PRIT
01/14/2016 Post to external web.
07/01/2016 Updated Truth Table:
Updated details in “CE3” column corresponding to fifth row of “Deselected
Cycle, Power Down”.
Updated Neutron Soft Error Immunity:
Updated values in “Typ” and “Max” columns corresponding to LSBU (Device
without ECC) parameter.
Updated to new template.
*F
6073260
CNX
02/16/2018 Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *G.
Updated to new template.
Document Number: 001-97888 Rev. *F
Page 33 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
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cypress.com/arm
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© Cypress Semiconductor Corporation, 2015-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-97888 Rev. *F
Revised February 16, 2018
Page 34 of 34
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