CY7C1383B-133BGC [CYPRESS]
Standard SRAM, 1MX18, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119;
| 型号： | CY7C1383B-133BGC |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 1MX18, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119 静态存储器 |
| 文件： | 总30页 (文件大小：844K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY7C1381B
CY7C1381B
CY7C1383B
PRELIMINARY
512K x 36 / 1 Mb x 18 Flow-Thru SRAM
nal burst operation. All synchronous inputs are gated by reg-
isters controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), Burst Control In-
Features
• Fast access times: 6.5, 7.5, 8.5 ns
• Fast clock speed: 133, 117, 100 MHz
• Provide high-performance 3-1-1-1 access rate
• Optimal for depth expansion
puts (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,
BWc, BWd, and BWe), and Global Write (GW).
• 3.3V (–5% / +10%) power supply
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Chip enable for address pipeline
• Address, data and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• High-density, high-speed packages
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or address status controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQ1-DQ8 and DQP1. BWb controls DQ9-DQ16 and
DQP2. BWc controls DQ17-DQ24and DQP3. BWd controls
DQ25-DQ32 and DQP4. BWa, BWb BWc, and BWd can be
active only with BWe being LOW. GW being LOW causes all
bytes to be written. WRITE pass-through capability allows writ-
ten data available at the output for the immediately next READ
cycle. This device also incorporates pipelined enable circuit for
easy depth expansion without penalizing system performance.
• JTAG boundary scan for BGA packaging version
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced sin-
gle-layer polysilicon, triple-layer metal technology. Each mem-
ory cell consists of six transistors.
The CY7C1381B and CY7C1383A SRAMs integrate
524,288x36 and 1,048,576x18 SRAM cells with advanced
synchronous peripheral circuitry and a 2-bit counter for inter-
All inputs and outputs of the CY7C1381B and the CY7C1383A
are JEDEC standard JESD8-5 compatible.
Selection Guide
-133 MHz
6.5
-117 MHz
7.5
-100 MHz
8.5
Maximum Access Time (ns)
Maximum Operating Current (mA)
200
175
150
Maximum CMOS Standby Current (mA)
30
30
30
Shaded areas contain advance information
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 2, 2001
CY7C1381B
CY7C1383B
PRELIMINARY
Functional Block Diagram
Logic Block Diagram x18:
MODE
2
(A ,A )
0
1
Q
CLK
ADV
ADSC
0
BURST
COUNTER
CE
Q1
Q
CLR
ADSP
18
20
ADDRESS
REGISTER
CE
D
1 Mb X 18
A
[19:0]
20
18
MEMORY
ARRAY
GW
DQb[15:8],DP1
D
Q
Q
BYTEWRITE
BWE
REGISTERS
BWS
b
D DQa[7:0],DP0
BYTEWRITE
REGISTERS
BWS
a
18
18
CE
CE
CE
1
2
3
D
CE
ENABLE
Q
REGISTER
CLK
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
DP
[15:0]
[1:0]
Logic Block Diagram x36:
MODE
2
(A ,A )
0
1
Q
CLK
ADV
ADSC
0
Q1
Q
BURST
COUNTER
CE
CLR
ADSP
17
19
ADDRESS
REGISTER
CE
D
512K X 36
A
[18:0]
19
17
MEMORY
ARRAY
GW
DQd[31:24],DP3
D
D
Q
BYTEWRITE
REGISTERS
BWE
BWS
d
DQc[23:16],DP2
Q
BYTEWRITE
REGISTERS
BWS
BWS
c
D
D
DQb[15:8],DP1
Q
BYTEWRITE
REGISTERS
b
DQa[7:0],DP0Q
BWS
BYTEWRITE
a
REGISTERS
36
36
CE
CE
CE
1
2
3
D
ENABLE
Q
CE REGISTER
CLK
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
DP
[31:0]
[3:0]
2
CY7C1381B
CY7C1383B
PRELIMINARY
Pin Configurations
100-Pin TQFP
NC
NC
NC
VDDQ
VSSQ
NC
NC,DPc
1
A
NC
NC
VDDQ
VSSQ
NC
DPa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC,DPb
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DQb
DQb
VSSQ
VDDQ
DQb
DQb
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc
2
DQc
VDDQ
VSSQ
DQc
3
4
5
6
NC
DQc
7
DQb
DQb
VSSQ
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DPb
NC
DQc
8
DQc
9
9
10
11
VSSQ
VDDQ
DQc
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
12
DQc
13
NC
14
VDD
15
NC
VDD
ZZ
CY7C1381B
(512K X 36)
CY7C1383B
(1 Mb x 18)
NC
16
VDD
ZZ
VSS
17
DQd
18
DQa
DQa
VDDQ
VSSQ
DQa
DQa
NC
DQa
DQa
VDDQ
VSSQ
DQa
DQa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
NC,DPa
DQd
19
20
21
VDDQ
VSSQ
DQd
22
DQd
23
DQd
24
DQd
NC
25
26
27
VSSQ
VDDQ
NC
NC
NC
VSSQ
VDDQ
DQd
DQd
29
VSSQ
VDDQ
NC
NC
NC
28
NC,DPd
30
3
CY7C1381B
CY7C1383B
PRELIMINARY
Pin Configurations (continued)
119-Ball BGA
CY7C1381B (512K x 36)
2
A
1
3
A
4
5
A
6
A
7
A
B
C
D
E
F
VDDQ
ADSP
ADSC
VDD
NC
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
NC
DQc
DQc
VDDQ
DQPc
DQc
DQc
VSS
VSS
VSS
VSS
VSS
VSS
DQPb
DQb
DQb
DQb
DQb
VDDQ
CE1
OE
G
H
J
DQc
DQc
VDDQ
DQc
DQc
VDD
BWc
VSS
NC
ADV
GW
VDD
BWb
VSS
NC
DQb
DQb
VDD
DQb
DQb
VDDQ
K
L
DQd
DQd
DQd
DQd
DQd
VSS
BWd
VSS
CLK
NC
VSS
BWa
VSS
DQa
DQa
DQa
DQa
DQa
M
VDDQ
BWE
VDDQ
N
P
R
T
DQd
DQd
NC
DQd
VSS
VSS
MODE
A
A1
A0
VSS
VSS
NC
A
DQa
DQPa
A
DQa
DQa
NC
DQPd
VDD
A
A
NC
NC
NC
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
U
CY7C1383B (1M x 18)
2
A
1
3
A
4
5
A
6
A
7
VDDQ
NC
ADSP
ADSC
VDD
NC
VDDQ
NC
A
B
C
D
E
F
A
A
A
A
NC
A
A
A
A
NC
DQb
NC
NC
DQb
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQPa
NC
DQa
NC
CE1
OE
DQa
VDDQ
VDDQ
G
H
J
NC
DQb
VDDQ
NC
DQb
NC
BWb
VSS
NC
ADV
GW
VDD
CLK
NC
VSS
VSS
NC
NC
DQb
VDD
NC
DQa
NC
VDD
DQb
NC
VDDQ
DQa
NC
VSS
VSS
VSS
BWa
K
L
DQb
DQa
M
VDDQ
DQb
NC
DQb
NC
VSS
VSS
VSS
BWE
A1
VSS
VSS
VSS
NC
DQa
NC
VDDQ
NC
N
P
DQPb
A0
DQa
R
T
NC
NC
A
A
MODE
A
VDD
NC
NC
A
A
A
NC
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
U
4
CY7C1381B
CY7C1383B
PRELIMINARY
Pin Definitions
Name
I/O
Description
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and
CE3 are sampled active. A[1:0] feed the 2-bit counter.
BWa
BWb
BWc
BWd
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising
edge of CLK, a global write is conducted (ALL bytes are written, regardless of
the values on BWa,b,c,d and BWE).
BWE
CLK
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
CE1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ig-
nored if CE1 is HIGH.
CE2
CE3
OE
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE3 to select/deselect the device.(TQFP Only)
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE2 to select/deselect the device. (TQFP Only)
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the
I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH,
I/O pins are three-stated, and act as input data pins. OE is masked during the
first clock of a read cycle when emerging from a deselected state.
ADV
Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK. When asserted, it
automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK. When
asserted LOW, A is captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK. When
asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized.
MODE
ZZ
Input-
Static
Selects burst order. When tied to GND selects linear burst sequence. When
tied to VDDQ or left floating selects interleaved burst sequence. This is a strap
pin and should remain static during device operation.
Input-
Asynchronous
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical
“sleep” condition with data integrity preserved.
DQa, DQPa
DQb, DQPb
DQc, DQPc
DQd, DQPd
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A during the previous clock rise
of the read cycle. The direction of the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs. When HIGH, DQa–DQd and DQ-
Pa–DQPd are placed in a three-state condition.
TDO
JTAG serial
output
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK
(BGA Only).
Synchronous
5
CY7C1381B
CY7C1383B
PRELIMINARY
Pin Definitions
Name
I/O
Description
TDI
JTAG serial
input
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK (BGA
Only).
Synchronous
TMS
TCK
VDD
Test Mode Select
Synchronous
This pin controls the Test Access Port state machine. Sampled on the rising
edge of TCK (BGA Only).
JTAG serial
clock
Serial clock to the JTAG circuit (BGA Only).
Power Supply
Power supply inputs to the core of the device. Should be connected to 2.5V
power supply.
VSS
Ground
Ground for the core of the device. Should be connected to ground of the sys-
tem.
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry. Should be connected to a 2.5V power supply.
VSSQ
NC
I/O Ground
-
Ground for the I/O circuitry. Should be connected to ground of the system.
No Connects.
6
CY7C1381B
CY7C1383B
PRELIMINARY
will remain unaltered. All I/Os are three-stated during a byte
write because the CY7C1381B/CY7C1383B is a common I/O
device, the Output Enable (OE) must be deasserted HIGH be-
fore presenting data to the DQx inputs. Doing so will
three-state the output drivers. As a safety precaution, DQx are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Functional Description
Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip enable (CE1, CE2, CE3 on TQFP, CE1 on BGA) asserted
active, and (3) the write signals (GW, BWE) are all deasserted
HIGH. ADSP is ignored if CE1 is HIGH. The address presented
to the address inputs is stored into the address advancement
logic and the Address Register while being presented to the
memory core. If the OE input is asserted LOW, the requested
data will be available at the data outputs a maximum to tCDV
after clock rise. ADSP is ignored if CE1 is HIGH.
Burst Sequences
The CY7C1381B/CY7C1383B provides a two-bit wraparound
counter, fed by A[1:0], that implements either an interleaved or
linear burst sequence. to support processors that follow a lin-
ear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
Chip Enable asserted active. The address presented is loaded
into the address register and the address advancement logic
while being delivered to the RAM core. The write signals (GW,
BWE, and BWx) and ADV inputs are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
latched
and
written
into
the
device.
The
CY7C1381B/CY7C1383B provides byte write capability that is
described in the Write Cycle Description table. Asserting the
Byte Write Enable input (BWE) with the selected Byte Write
(BWa,b,c,d for CY7C1381B and BWa,b for CY7C1383B) input
will selectively write to only the desired bytes. Bytes not select-
ed during a byte write operation will remain unaltered. All I/Os
are three-stated during a byte write.
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
Because the CY7C1381B/CY7C1383B is a common I/O de-
vice, the Output Enable (OE) must be deasserted HIGH before
presenting data to the DQxinputs. Doing so will three-state the
output drivers. As a safety precaution, DQx are automatically
three-stated whenever a write cycle is detected, regardless of
the state of OE.
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) Chip Enable (CE1, CE2, CE3 on TQFP,
CE1 on BGA) asserted active, and (4) the appropriate combi-
nation of the write inputs (GW, BWE, and BWx) are asserted
active to conduct a write to the desired byte(s). ADSC is ig-
nored if ADSP is active LOW.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed. Ac-
cesses pending when entering the “sleep” mode are not con-
sidered valid nor is the completion of the operation guaran-
teed. The device must be deselected prior to entering the
“sleep” mode. Chip Enable (CE1, CE2, CE3, on TQFP, CE1 on
BGA), ADSP and ADSC must remain inactive for the duration
of tZZREC after the ZZ input returns LOW. Leaving ZZ uncon-
nected defaults the device into an active state.
The address presented to A[17:0] is loaded into the address
register and the address advancement logic while being deliv-
ered to the RAM core. The ADV input is ignored during this
cycle. If a global write is conducted, the data presented to the
DQx is written into the corresponding address location in the
RAM core. If a byte write is conducted, only the selected bytes
are written. Bytes not selected during a byte write operation
7
CY7C1381B
CY7C1383B
PRELIMINARY
ZZ Mode Electrical Characteristics
Parameter
ICCZZ
Description
Test Conditions
Min.
Max.
Unit
Snooze mode
standby current
ZZ > VDD − 0.2V
15
mA
tZZS
Deviceoperationto
ZZ
ZZ > VDD − 0.2V
ZZ < 0.2V
2tCYC
ns
ns
tZZREC
ZZ recovery time
2tCYC
Cycle Descriptions[1, 2, 3]
Next Cycle
Unselected
Add. Used
None
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
CE3
X
1
CE2
X
X
0
CE1
1
ADSP
X
0
ADSC
ADV
X
X
X
X
X
X
X
0
OE
X
X
X
X
X
X
X
1
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Write
X
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
X
Unselected
None
0
X
Unselected
None
X
1
0
0
X
Unselected
None
X
0
0
1
X
Unselected
None
X
0
0
1
X
Begin Read
External
External
Next
1
0
0
X
Begin Read
0
1
0
1
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
X
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
1
X
X
1
1
Next
1
0
0
Next
X
X
1
0
1
Hi-Z
DQ
Next
1
0
0
Current
Current
Current
Current
Current
Current
External
Next
X
X
1
1
1
Hi-Z
DQ
1
1
0
X
X
1
1
1
Hi-Z
DQ
1
1
0
X
1
1
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Begin Write
X
1
1
Begin Write
0
X
0
Continue Write
Continue Write
Suspend Write
Suspend Write
X
X
X
X
X
X
X
X
X
X
X
1
1
Next
X
1
0
Current
Current
None
X
1
1
X
X
1
ZZ “sleep”
X
X
Note:
1. X =”Don't Care”, 1 = HIGH, 0 = LOW.
2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWx. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a “Don't Care” for the remainder of the write cycle.
3. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ = High-Z when OE is inactive
or when the device is deselected, and DQ = data when OE is active.
8
CY7C1381B
CY7C1383B
PRELIMINARY
Write Cycle Description[1, 2, 3]
Function (CY7C1381B)
Read
GW
1
BWE
BWd
X
1
BWc
X
1
BWb
BWa
X
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X
Read
1
Write Byte 0 - DQa
Write Byte 1 - DQb
Write Bytes 1, 0
Write Byte 2 - DQc
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 - DQd
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
1
1
1
0
1
1
1
1
1
1
1
0
1
1
0
1
1
1
0
0
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
1
0
0
1
1
0
0
0
Write All Bytes
0
X
X
X
Function (CY7C1383B)
Read
GW
BWE
BWb
BWa
1
1
1
1
1
0
1
0
0
0
0
X
X
1
1
0
0
X
X
1
0
1
0
X
Read
Write Byte 0 - DQa and DPa
Write Byte 1 - DQb and DPb
Write All Bytes
Write All Bytes
9
CY7C1381B
CY7C1383B
PRELIMINARY
ry. Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI pin on
the rising edge of TCK. Data is output on the TDO pin on the
falling edge of TCK.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1381B/CY7C1383B incorporates a serial boundary
scan Test Access Port (TAP) in the FBGA package only. The
TQFP package does not offer this functionality. This port oper-
ates in accordance with IEEE Standard 1149.1-1900, but does
not have the set of functions required for full 1149.1 compli-
ance. These functions from the IEEE specification are exclud-
ed because their inclusion places an added delay in the critical
speed path of the SRAM. Note that the TAP controller func-
tions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP op-
erates using JEDEC standard 3.3V I/O logic levels.
Instruction Register
Three-bit instructions can be serially loaded into the instruc-
tion register. This register is loaded when it is placed between
the TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as de-
scribed in the previous section.
Disabling the JTAG Feature
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary "01" pattern to allow
for fault isolation of the board level serial test path.
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port (TAP) - Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a xx-bit-long regis-
ter, and the x18 configuration has a yy-bit-long register.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the regis-
ters and can be connected to the input of any of the registers.
The register between TDI and TDO is chosen by the instruc-
tion that is loaded into the TAP instruction register. For infor-
mation on loading the instruction register, see the TAP Control-
ler State Diagram. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is con-
nected to the Most Significant Bit (MSB) on any register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
Test Data Out (TDO)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register Defi-
nitions table.
The TDO output pin is used to serially clock data-out from the
registers. The e output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power-up, the TAP is reset internally to ensure that TDO
comes up in a high-Z state.
Eight different instructions are possible with the three-bit in-
struction register. All combinations are listed in the Instruction
Code table. Three of these instructions are listed as RE-
SERVED and should not be used. The other five instructions
are described in detail below.
TAP Registers
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller can-
not be used to load address, data or control signals into the
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test circuit-
10
CY7C1381B
CY7C1383B
PRELIMINARY
SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE / PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
When the SAMPLE / PRELOAD instructions loaded into the
instruction register and the TAP controller in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible
that during the Capture-DR state, an input or output will under-
go a transition. The TAP may then try to capture a signal while
in transition (metastable state). This will not harm the device,
but there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP control-
ler needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be ex-
ecuted whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in the TAP controller, and there-
fore this device is not compliant to the 1149.1 standard.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (TCS and TCH). The SRAM clock input might not
be captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE / PRELOAD instruction. If
this is an issue, it is still possible to capture all other signals
and simply ignore the value of the CK and CK captured in the
boundary scan register.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE / PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE / PRELOAD instruction, EX-
TEST places the SRAM outputs in a High-Z state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP con-
troller enters the Shift-DR state. The IDCODE instruction is
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE / PRELOAD in-
struction will have the same effect as the Pause-DR command.
loaded into the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
Bypass
When the BYPASS instruction is loaded in the instruction reg-
ister and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The advan-
tage of the BYPASS instruction is that it shortens the boundary
scan path when multiple devices are connected together on a
board.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Reserved
SAMPLE / PRELOAD
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
SAMPLE / PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant.
11
CY7C1381B
CY7C1383B
PRELIMINARY
TAP Controller State Diagram
TEST-LOGIC
1
RESET
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
CAPTURE-DR
0
1
1
CAPTURE-DR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
12
CY7C1381B
CY7C1383B
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
0
TDO
TDI
Instruction Register
29
Identification Register
31 30
.
.
2
1
1
0
0
.
x
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[4, 5]
Parameter
VOH1
VOH2
VOL1
VOL2
VIH
Description
Test Conditions
Min.
1.7
Max.
Unit
V
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
IOH = –2.0 mA
IOH = –100 mA
IOL = 2.0 mA
IOL = 100 mA
2.1
V
0.7
0.2
V
V
1.7
–0.3
–5
VDD+0.3
0.7
V
VIL
V
IX
GND < VI < VDDQ
5
mA
4. All Voltage referenced to Ground.
5. Overshoot: VIH(AC)<VDD+1.5V for t<tTCYC/2. Undershoot:VIL(AC)<0.5V for t<tTCYC/2. Power-up: VIH<2.6V and VDD<2.4V and VDDQ<1.4V for t<200 ms.
13
CY7C1381B
CY7C1383B
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range[6, 7]
Parameters
tTCYC
Description
Min.
Max.
Unit
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
100
tTF
10
MHz
ns
tTH
40
40
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
10
10
10
ns
ns
ns
tTDIH
tCH
Capture Hold after Clock Rise
Output Times
tTDOV
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
20
ns
ns
tTDOX
0
Notes:
6. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
7. Test conditions are specified using the load in TAP AC test conditions. Tr/Tf = 1 ns.
14
CY7C1381B
CY7C1383B
PRELIMINARY
TAP Timing and Test Conditions
1.25V
50Ω
ALL INPUT PULSES
1.50V
TDO
3.3V
Z =50Ω
0
C =20 pF
L
0V
GND
(a)
tTL
tTH
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
15
CY7C1381B
CY7C1383B
PRELIMINARY
Identification Register Definitions
Instruction Field
Revision Number
512K x 36
1 Mb x 18
Description
xxxx
xxxx
Reserved for version number.
(31:28)
Device Depth
(27:23)
00111
00100
01000
00011
Defines depth of SRAM. 512K or 1 Mb
Defines with of the SRAM. x36 or x18
Reserved for future use.
Device Width
(22:18)
Cypress Device ID
(17:12)
xxxxx
xxxxx
Cypress JEDEC ID
(11:1)
00011100100
1
00011100100
1
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
ID Register Presence
(0)
Scan Register Sizes
Register Name
Instruction
Bit Size (x18)
Bit Size (x36)
3
1
3
1
Bypass
ID
32
70
32
51
Boundary Scan
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents. Places the boundary scan register
between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register be-
tween TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
Captures the Input/Output contents. Places the boundary scan register be-
tween TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction
does not implement 1149.1 preload function and is therefore not 1149.1
compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
16
CY7C1381B
CY7C1383B
PRELIMINARY
Boundary Scan Order (512K X 18)
Boundary Scan Order (1 Mb X 18)
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Bit #
Bit #
36
Bit #
Bit #
36
1
A
2R
A
6B
1
A
2R
DQb
2E
2
A
3T
4T
5T
6R
3B
5B
6P
7N
6M
7L
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
BWa#
BWb#
BWc#
BWd#
A
5L
2
A
2T
3T
5T
6R
3B
5B
7P
6N
6L
7K
7T
6H
7G
6F
7E
6D
6T
6A
5A
4G
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
DQb
DQb
NC
2G
1H
5R
2K
1L
3
A
5G
3G
3L
3
A
4
A
4
A
5
A
5
A
DQb
DQb
DQb
DQb
DQb
MODE
A
6
A
2B
4E
3A
2A
2D
1E
2F
1G
1D
1D
2E
2G
1H
5R
2K
1L
6
A
7
A
CE#
A
7
A
2M
1N
2P
3R
2C
3C
5C
6C
4N
4P
8
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
8
DQa
DQa
DQa
DQa
ZZ
9
A
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
6K
7P
6N
6L
A
DQa
DQa
DQa
DQa
DQa
A
A
A
A1
7K
7T
6H
7G
6F
7E
6D
7H
6G
6E
7D
6A
5A
4G
A0
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
A
A
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
MODE
A
A
ADV#
2M
1N
2P
1K
2L
ADSP# 4A
ADSC# 4B
OE#
BWE#
GW#
CLK
A
4F
4M
4H
4K
6B
5L
2N
1P
3R
2C
3C
5C
6C
4N
4P
A
ADV#
BWa#
BWb#
A
ADSP# 4A
ADSC# 4B
3G
2B
4E
3A
2A
1D
A
OE#
4F
4M
4H
4K
A
CE#
A
BWE#
GW#
CLK
A
A1
A
A0
DQb
17
CY7C1381B
CY7C1383B
PRELIMINARY
Static Discharge Voltage >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature −65°C to +150°C
Ambient Temperature with
Power Applied−55°C to +125°C
Latch-Up Current >200 mA
Operating Range
Ambient
Range
Temp.[9]
VDD
VDDQ
Supply Voltage on VDD Relative to GND−0.3V to +4.6V
DC Voltage Applied to Outputs
Com’l
0 − 70°C 3.3V +10%/–5%
2.375V–VDD
in High Z State[8]−0.5V to VDDQ + 0.5V
DC Input Voltage[8]−0.5V to VDDQ + 0.5V
Current into Outputs (LOW)20 mA
Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Test Conditions
Min.
3.135
2.375
2.4
Max.
3.6
Unit
V
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
3.3V range
3.3V range
VDDQ
VDD
V
VOH
VDD = Min., IOH = −1.0 mA
3.3V
2.5V
3.3V
2.5V
3.3V
2.5V
3.3V
2.5V
V
1.7
V
VOL
VIH
VIL
IX
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[8]
VDD = Min., IOL = 1.0 mA
0.4
0.7
V
1.8
1.7
V
V
−0.3
–0.3
−5
0.8
0.7
5
Input Load Current
GND ≤ VI ≤ VDDQ
µA
except ZZ and MODE
Input Current of MODE
Input Current of ZZ
−30
−5
30
µA
µA
IZZ
Input = VSS
Note:
8. Minimum voltage equals –2.0V for pulse durations of less than 20 ns
9. TA is the temperature.
18
CY7C1381B
CY7C1383B
PRELIMINARY
Electrical Characteristics Over the Operating Range (continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
IOZ
Output Leakage
Current
GND ≤ VI ≤ VDDQ, Output Disabled
−2
2
µA
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5-ns cycle, 133 MHz
200
175
150
100
85
mA
mA
mA
mA
mA
mA
mA
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
7.5-ns cycle, 133 MHz
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
All Speeds
ISB1
ISB2
ISB3
ISB4
Automatic CS
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselect-
ed, VIN ≥ VIH or
VIN ≤ VIL
f = fMAX = 1/tCYC
70
Automatic CS
Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselect-
ed, VIN ≤ 0.3V or
VIN > VDDQ – 0.3V, f = 0
30
Automatic CS
Power-Down
Current—CMOS Inputs VIN > VDDQ – 0.3V
Max. VDD, Device
Deselected, or VIN ≤ 0.3V or
7.5-ns cycle, 133 MHz
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
All Speeds
70
60
50
40
mA
mA
mA
mA
f = fMAX = 1/tCYC
Automatic CS
Power-Down
Max. VDD, Device
Deselected,
Current—TTL Inputs
VIN ≥ VIH or VIN ≤ VIL,f = 0
19
CY7C1381B
CY7C1383B
PRELIMINARY
Capacitance[10]
Parameter
Description
Test Conditions
Max.
Unit
pF
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
DD = 3.3V,
DDQ = 2.5V
3
3
3
V
V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
pF
AC Test Loads and Waveforms[11]
R=1667Ω
2.5V
OUTPUT
[10]
OUTPUT
ALL INPUT PULSES
90%
2.5V
GND
90%
10%
Z =50Ω
0
R =50Ω
10%
L
5 pF
R=1538Ω
≤ 1 V/ns
≤ 1V/ns
= 1.25V
VTH
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note:
10. Tested initially and after any design or process changes that may affect these parameters.
11. Input waveform should have a slew rate of 1 V/ns.
20
CY7C1381B
CY7C1383B
PRELIMINARY
Switching Characteristics Over the Operating Range[12, 13, 14]
-133
Max.
-117
Max.
-100
Max.
Parameter
tCYC
Description
Min.
7.5
3.0
3.0
2.0
0.5
Min.
8.5
3.0
3.0
2.0
0.5
Min.
10.0
3.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Time
Clock HIGH
tCH
tCL
Clock LOW
3.0
tAS
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
BWE, GW, BWx Set-Up Before CLK Rise
BWE, GW, BWx Hold After CLK Rise
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
2.0
tAH
0.5
tCO
6.5
7.5
8.5
tDOH
tADS
tADH
tWES
tWEH
tADVS
tADVH
tDS
1.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
0
1.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
0
1.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
0
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip enable Set-Up
tDH
tCES
tCEH
tCHZ
tCLZ
tEOHZ
tEOLZ
tEOV
Chip enable Hold After CLK Rise
Clock to High-Z[13]
Clock to Low-Z[13]
OE HIGH to Output High-Z[13, 14]
OE LOW to Output Low-Z[13, 14]
OE LOW to Output Valid[13]
4.0
3.5
3.5
4.0
3.5
3.5
5.0
4.0
4.0
0
0
0
0
0
0
Shaded areas contain advance information.
Notes:
12. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
13. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from
steady-state voltage.
14. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ
.
21
CY7C1381B
CY7C1383B
PRELIMINARY
1
Switching Waveforms
Write Cycle Timing[15,16]
Single Write
tCYC
tADH
Burst Write
Pipelined Write
tCH
Unselected
CLK
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
ADSC
ADV
tADH
tADS
ADSC initiated write
tADVH
tADVS
tAS
ADV Must Be Inactive for ADSP Write
WD3
ADD
GW
WE
WD1
WD2
tAH
tWH
tWH
tWS
tWS
tCES
tCEH
CE1 masks ADSP
CE
1
tCEH
tCES
Unselected with CE2
CE
2
CE
3
tCES
tCEH
OE
tDH
tDS
High-Z
High-Z
Data In
3a
2a
2d
= DON’T CARE
1a
2b
2c
= UNDEFINED
Notes:
15. WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Descriptions table).
16. WDx stands for Write Data to Address X.
22
CY7C1381B
CY7C1383B
PRELIMINARY
Switching Waveforms (continued)
Read Cycle Timing[15, 17]
Burst Read
Single Read
Unselected
tCYC
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC initiated read
ADSC
ADV
tADVS
tADH
Suspend Burst
tADVH
tAS
ADD
GW
RD1
RD3
RD2
tAH
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
OE
tCEH
tEOV
tCES
tOEHZ
tDOH
tCDV
3a
Data Out
2d
2a
2b
2c
1a
tCLZ
tCHZ
= DON’T CARE
= UNDEFINED
Note:
17. RDx stands for Read Data from Address X.
23
CY7C1381B
CY7C1383B
PRELIMINARY
Switching Waveforms (continued)
Read/Write Cycle Timing[15, 16, 17]
Read/Write Timing
tCYC
tCL
tCH
CLK
tAH
tAS
A
D
B
C
ADD
tADH
tADS
ADSP
tADH
tADS
ADSC
tADVH
tADVS
ADV
tCEH
tCES
CE1
CE
tCEH
tCES
tWES
tWEH
WE
OE
ADSP ignored
with CE1 HIGH
tEOHZ
tCLZ
Data
Q
(B+3)
D
(C+1)
D
(C+2)
D
(C+3)
Q
(B+2)
Q
(B+1)
Q(B)
Q(B)
D(C)
Q(D)
Q(A)
In/Out
tCDV
tDOH
tCHZ
Device originally
deselected
WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Description table).
CE is the combination of CE2 and CE3. All chip selects need to be active in order to select
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
= UNDEFINED
= DON’T CARE
24
CY7C1381B
CY7C1383B
PRELIMINARY
Switching Waveforms (continued)
Pipeline Timing[18, 19]
tCYC
tCL
tCH
CLK
tAS
WD1
WD2
WD3
WD4
RD1
RD2
RD3
RD4
ADD
tADS
tADH
ADSC initiated Reads
ADSC
ADSP initiated Reads
ADSP
ADV
tCEH
tCES
CE1
CE
tWES
tWEH
WE
OE
ADSP ignored
with CE1 HIGH
tCLZ
Data In/Out
tCDV
1a
In
1a
2a
3a
4a
2a
In
3a
In
4a
Out Out Out Out
In
tDOH
Back to Back Reads
tCHZ
Back to Back Writes
= UNDEFINED
= DON’T CARE
25
CY7C1381B
CY7C1383B
PRELIMINARY
Switching Waveforms (continued)
Notes:
18. Device originally deselected.
19. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device.
OE Switching Waveforms
OE
tEOV
tEOHZ
Three-State
I/Os
tEOLZ
26
CY7C1381B
CY7C1383B
PRELIMINARY
Switching Waveforms (continued)
ZZ Mode Timing [18, 20]
CLK
ADSP
HIGH
ADSC
CE1
LOW
CE2
HIGH
CE3
ZZ
tZZS
ICC
ICC(active)
tZZREC
ICCZZ
I/Os
Three-state
Note:
20. I/Os are in three-state when exiting ZZ sleep mode.
27
CY7C1381B
CY7C1383B
PRELIMINARY
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
133
117
100
133
117
100
133
117
100
133
117
100
Ordering Code
Package Type
100-Lead Thin Quad Flat Pack
CY7C1381B-133AC
CY7C1381B-117AC
CY7C1381B-100AC
CY7C1383B-133AC
CY7C1383B-117AC
CY7C1383B-100AC
CY7C1381B-133BGC
CY7C1381B-117BGC
CY7C1381B-100BGC
CY7C1383B-133BGC
CY7C1383B-117BGC
CY7C1383B-100BGC
A101
Commercial
BG119
119 Ball BGA
Document #: 38-01077-*A
28
CY7C1381B
CY7C1383B
PRELIMINARY
Pin Configurations
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
29
CY7C1381B
CY7C1383B
PRELIMINARY
Pin Configurations (continued)
119-Lead FBGA (14 x 22 x 2.4 mm) BG119
51-85115
Revision History
Document Title: CY7C1381B/CY7C1383B 512K x36/1M x18 Sync. Flowthrough
Document Number:38-01077
ORIG. OF
REV.
**
ECN NO.
ISSUE DATE
9/30/2000
05/04/01
CHANGE
DESCRIPTION OF CHANGE
1. New Data sheet
MPR
*A
3772
PKS
1. Changed Icc/Vih/Vil values
2. Changed Pin capacitance values
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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