CY7C1399BL-12VC [CYPRESS]
32K x 8 3.3V Static RAM; 32K ×8 3.3V静态RAM
| 型号： | CY7C1399BL-12VC |
| 厂家： | 
CYPRESS |
| 描述： | 32K x 8 3.3V Static RAM |
| 文件： | 总10页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
C1399B
CY7C1399B
32K x 8 3.3V Static RAM
active LOW Output Enable (OE) and three-state drivers. The
device has an automatic power-down feature, reducing the
power consumption by more than 95% when deselected.
Features
• Single 3.3V power supply
• Ideal for low-voltage cache memory applications
• High speed
An active LOW Write Enable signal (WE) controls the writing/
reading operation of the memory. When CE and WE inputs are
both LOW, data on the eight data input/output pins (I/O0
through I/O7) is written into the memory location addressed by
the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins is present on the eight data input/output pins.
— 10/12/15 ns
• Low active power
— 216 mW (max.)
• Low-power alpha immune 6T cell
• Plastic SOJ and TSOP packaging
Functional Description[1]
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The CY7C1399B is available in 28-pin standard
300-mil-wide SOJ and TSOP Type I packages.
The CY7C1399B is a high-performance 3.3V CMOS Static
RAM organized as 32,768 words by 8 bits. Easy memory ex-
pansion is provided by an active LOW Chip Enable (CE) and
Logic Block Diagram
Pin Configurations
SOJ
Top View
A
A
V
CC
28
27
26
1
2
3
4
5
6
5
WE
6
A
A
7
A
4
A
3
8
25
24
A
9
A
2
A
10
A
11
A
12
23
22
A
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
8
9
10
11
12
13
OE
A
0
0
1
2
3
4
5
6
21
20
19
18
17
INPUT BUFFER
A
13
A
14
CE
I/O
A
0
7
I/O
I/O
I/O
I/O
I/O
A
1
0
1
2
6
5
4
A
2
16
15
A
3
I/O
I/O
A
4
GND
14
3
32K x 8
ARRAY
A
5
A
6
A
7
A
8
A
9
CE
WE
POWER
DOWN
COLUMN
DECODER
I/O
7
OE
Selection Guide
1399B-10
1399B-12
1399B-15
1399B-20
Maximum Access Time (ns)
10
60
12
55
15
50
20
45
Maximum Operating Current (mA)
Maximum CMOS Standby Current (µA)
500
50
500
50
500
50
500
50
L
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05071 Rev. *C
Revised June 19, 2001
CY7C1399B
Pin Configuration
TSOP
Top View
21
20
OE
1
22
23
A
CE
I/O
I/O
I/O
I/O
I/O
0
A
A
19
18
17
16
24
2
7
A
25
26
27
28
1
3
4
6
5
4
3
A
WE
15
14
13
V
CC
A
5
GND
I/O
A
2
3
6
2
A7
12
11
I/O
I/O
A
1
0
A
4
5
8
10
9
A
9
14
13
12
A
A
A
6
7
10
11
8
A
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
DC Voltage Applied to Outputs
3.3V ±300 mV
3.3V ±300 mV
in High Z State[2] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[2].................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range[1]
7C1399B-10
7C1399B-12
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
Min.
Max.
Min.
Max.
Unit
V
VCC = Min., IOH = –2.0 mA
VCC = Min., IOL = 4.0 mA
2.4
2.4
VOL
0.4
0.4
V
VIH
2.2
VCC
2.2
VCC
V
+0.3V
+0.3V
VIL
IIX
Input LOW Voltage[2]
Input Load Current
–0.3
–1
0.8
+1
+5
–0.3
–1
0.8
+1
+5
V
µA
µA
IOZ
Output Leakage
Current
GND ≤ VI ≤ VCC
Output Disabled
,
–5
–5
IOS
ICC
ISB1
Output Short
VCC = Max., VOUT = GND
–300
60
–300
55
mA
mA
Circuit Current[3]
VCC Operating
Supply Current
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
Automatic CE Power-Down
Current — TTL Inputs
Max. VCC, CE ≥ VIH,
5
4
5
4
mA
mA
µA
VIN ≥ VIH, or VIN ≤ VIL,f = fMAX
L
L
ISB2
Automatic CE Power-Down
Current — CMOS Inputs[4]
Max. VCC, CE ≥ VCC – 0.3V, V
≥
500
50
500
50
IN
VCC – 0.3V, or VIN ≤ 0.3V,
WE ≥VCC – 0.3V or WE ≤0.3V,
f = fMAX
µA
Notes:
2. Minimum voltage is equal to –2.0V for pulse durations of less than 20 ns.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Device draws low standby current regardless of switching on the addresses.
Document #: 38-05071 Rev. *C
Page 2 of 10
CY7C1399B
Electrical Characteristics Over the Operating Range (continued)
1399B-15
1399B-20
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
VCC = Min., IOH = –2.0 mA
VCC = Min., IOL = 4.0 mA
Min.
Max.
Min.
Max.
Unit
V
2.4
2.4
VOL
VIH
0.4
0.4
V
2.2
VCC
2.2
VCC
V
+0.3V
+0.3V
VIL
IIX
Input LOW Voltage
Input Load Current
Output Leakage Current
–0.3
–1
0.8
+1
+5
–0.3
–1
0.8
+1
+5
V
µA
µA
IOZ
GND ≤ VI ≤ VCC
,
–5
–5
Output Disabled
IOS
ICC
ISB1
Output Short Circuit
Current[3]
VCC = Max., VOUT = GND
–300
50
–300
45
mA
mA
VCC Operating
Supply Current
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
AutomaticCEPower-Down Max. VCC, CE ≥ VIH,
Current — TTL Inputs IN ≥ VIH, or VIN ≤ VIL,
f = fMAX
5
4
5
4
mA
mA
V
L
L
ISB2
AutomaticCEPower-Down Max. VCC, CE ≥ VCC–0.3V, VIN
Current — CMOS Inputs[4] VCC – 0.3V, or VIN ≤ 0.3V,
WE≥VCC–0.3V or WE≤ 0.3V,
≥
500
50
500
50
µA
µA
f=fMAX
Capacitance[5]
Parameter
Description
Test Conditions
Max.
Unit
CIN: Addresses
CIN: Controls
COUT
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = 3.3V
5
6
6
pF
pF
pF
Output Capacitance
AC Test Loads and Waveforms
R1 317Ω
3.3V
ALL INPUT PULSES
90%
OUTPUT
3.0V
90%
10%
10%
R2
351Ω
C
GND
L
≤ 3 ns
≤ 3 ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05071 Rev. *C
Page 3 of 10
CY7C1399B
Switching Characteristics Over the Operating Range[6]
1399B-10
1399B-12
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
10
3
12
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[7]
OE HIGH to High Z[7, 8]
CE LOW to Low Z[7]
CE HIGH to High Z[7, 8]
CE LOW to Power-Up
CE HIGH to Power-Down
10
12
tOHA
tACE
10
5
12
5
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
0
3
0
0
3
0
5
5
5
6
tPD
10
12
Write Cycle[9, 10]
tWC
Write Cycle Time
10
8
12
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tAW
7
8
tHA
0
0
tSA
0
0
tPWE
tSD
7
8
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[9]
5
7
tHD
0
0
tHZWE
7
7
tLZWE
WE HIGH to Low Z[7]
3
3
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
OL/IOH and capacitance CL = 30 pF.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8.
I
tHZOE, tHZCE, tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05071 Rev. *C
Page 4 of 10
CY7C1399B
Switching Characteristics Over the Operating Range[6] (Continued)
1399B-15
1399B-20
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
15
3
20
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[7]
OE HIGH to High Z[7, 8]
CE LOW to Low Z[7]
CE HIGH to High Z[7, 8]
CE LOW to Power-Up
CE HIGH to Power-Down
15
20
tOHA
tACE
15
6
20
7
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
0
3
0
0
3
0
6
7
6
7
tPD
15
20
Write Cycle[9, 10]
tWC
Write Cycle Time
15
10
10
0
20
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tAW
tHA
tSA
0
0
tPWE
tSD
10
8
12
10
0
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[9]
tHD
0
tHZWE
tLZWE
7
7
WE HIGH to Low Z[7]
3
3
Data Retention Characteristics (Over the Operating Range - L version only)
Parameter
Description
VCC for Data Retention
Data Retention Current
Conditions
Min.
2.0
0
Max.
Unit
VDR
V
ICCDR
tCDR
Com’l VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
20
µA
ns
Chip Deselect to Data
Retention Time
0
tR
Operation Recovery Time
tRC
ns
Document #: 38-05071 Rev. *C
Page 5 of 10
CY7C1399B
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
CC
DR
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No. 1[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2[12, 13]
t
RC
CE
t
ACE
OE
t
t
HZOE
t
DOE
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
V
ICC
CC
SUPPLY
CURRENT
50%
50%
ISB
Notes:
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05071 Rev. *C
Page 6 of 10
CY7C1399B
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[9, 14, 15]
t
WC
ADDRESS
CE
t
t
AW
HA
t
SA
t
PWE
WE
OE
t
SD
t
HD
NOTE 16
DATA VALID
IN
DATA I/O
t
HZOE
Write Cycle No. 2 (CE Controlled)[9, 14, 15]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
WE
t
t
HD
SD
DATA I/O
DATA VALID
IN
Write Cycle No. 3 (WE Controlled, OE LOW)[10, 15]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
WE
t
t
HD
SD
DATA VALID
DATA I/O
NOTE 16
IN
t
t
LZWE
HZWE
Notes:
14. Data I/O is high impedance if OE = VIH
.
15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
16. During this period, the I/Os are in the output state and input signals should not be applied.
Document #: 38-05071 Rev. *C
Page 7 of 10
CY7C1399B
Truth Table
CE
H
L
WE
X
OE
X
Input/Output
High Z
Mode
Deselect/Power-Down
Power
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
H
L
Data Out
Data In
High Z
Read
)
L
L
X
Write
)
L
H
H
Deselect, Output Disabled
)
l
product and comany names mentioned in this document may be the trademarks of their respective holders.
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
CY7C1399B-10VC
CY7C1399B-10ZC
CY7C1399BL-10VC
CY7C1399BL-10ZC
CY7C1399B-12VC
CY7C1399B-12ZC
CY7C1399BL-12VC
CY7C1399BL-12ZC
CY7C1399B-12VI
CY7C1399B-12ZI
CY7C1399B-15VC
CY7C1399B-15ZC
CY7C1399BL-15VC
CY7C1399BL-15ZC
CY7C1399B-15VI
CY7C1399B-15ZI
CY7C1399B-20VC
CY7C1399B-20ZC
CY7C1399BL-20VC
CY7C1399BL-20ZC
CY7C1399B-20VI
CY7C1399B-20ZI
Name
V21
Z28
V21
Z28
V21
Z28
V21
Z28
V21
Z28
V21
Z28
V21
Z28
V21
Z28
V21
Z28
V21
Z28
V21
Z28
Package Type
28-Lead Molded SOJ
10
Commercial
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
12
15
20
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
Industrial
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
Commercial
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
Industrial
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
Commercial
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
Industrial
28-Lead Thin Small Outline Package
Document #: 38-05071 Rev. *C
Page 8 of 10
CY7C1399B
Package Diagrams
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
28-Lead Thin Small Outline Package Type 1 (8x13.4 mm) Z28
51-85071-*G
Document #: 38-05071 Rev. *C
Page 9 of 10
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1399B
Document History Page
Document Title: CY7C1399B 32K x 8 3.3V Static RAM
Document Number: 38-05071
ISSUE
DATE
ORIG. OF
CHANGE
REV.
**
ECN NO.
107264
107533
116472
224340
DESCRIPTION OF CHANGE
Change from Spec #: 38-01102 to 38-05071
05/25/01
06/28/01
09/17/02
See ECN
SZV
MAX
CEA
RKF
*A
Add Low Power
*B
Add applications foot note to data sheet, page 1.
*C
Option 1 of the Orientation ID on TSOP-I Package Diagram [Page #9]
removed
Document #: 38-05071 Rev. *C
Page 10 of 10
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