CY7C1412BV18 [CYPRESS]
36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture; 36 - Mbit的QDR - II⑩ SRAM 2字突发架构
| 型号： | CY7C1412BV18 |
| 厂家： | 
CYPRESS |
| 描述： | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| 文件： | 总26页 (文件大小：1096K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
36-Mbit QDR-II™ SRAM 2-Word Burst
Architecture
Features
Functional Description
• Separate Independent Read and Write data ports
— Supports concurrent transactions
• 250-MHz clock for high bandwidth
• 2-Word Burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 500 MHz) @ 250 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
The CY7C1410BV18, CY7C1425BV18, CY7C1412BV18 and
CY7C1414BV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II architecture. QDR-II architecture
consists of two separate ports to access the memory array.
The Read port has dedicated Data Outputs to support Read
operations and the Write Port has dedicated Data Inputs to
support Write operations. QDR-II architecture has separate
data inputs and data outputs to completely eliminate the need
to “turn-around” the data bus required with common I/O
devices. Access to each port is accomplished through a
common address bus. The Read address is latched on the
rising edge of the K clock and the Write address is latched on
the rising edge of the K clock. Accesses to the QDR-II Read
and Write ports are completely independent of one another. In
order to maximize data throughput, both Read and Write ports
are equipped with Double Data Rate (DDR) interfaces. Each
address location is associated with two 8-bit words
(CY7C1410BV18) or 9-bit words (CY7C1425BV18) or 18-bit
words (CY7C1412BV18) or 36-bit words (CY7C1414BV18)
that burst sequentially into or out of the device. Since data can
be transferred into and out of the device on every rising edge
of both input clocks (K and K and C and C), memory bandwidth
is maximized while simplifying system design by eliminating
bus “turn-arounds.”
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• QDR-II operates with 1.5 cycle read latency when DLL
is enabled
• Operates like a QDR I device with 1 cycle read latency
in DLL off mode
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
• Available in x8, x9, x18, and x36 configurations
• Full data coherency, providing most current data
• Core VDD = 1.8V (±0.1V); I/O VDDQ = 1.4V to VDD
• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
• Offered in both lead-free and non lead-free packages
• Variable drive HSTL output buffers
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1410BV18 – 4M x 8
CY7C1425BV18 – 4M x 9
CY7C1412BV18 – 2M x 18
CY7C1414BV18 – 1M x 36
Selection Guide
250 MHz
200 MHz
200
167 MHz
167
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
250
1065
870
740
Cypress Semiconductor Corporation
Document #: 001-07036 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 20, 2006
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Logic Block Diagram (CY7C1410BV18)
D
[7:0]
8
Write
Reg
Write
Reg
Address
Register
A
(20:0)
21
Address
Register
A
(20:0)
21
RPS
C
K
K
Control
Logic
CLK
Gen.
DOFF
Read Data Reg.
16
CQ
CQ
C
8
V
REF
8
Reg.
Reg.
Reg.
WPS
NWS
Control
Logic
8
8
[1:0]
Q
[7:0]
8
Logic Block Diagram (CY7C1425BV18)
D
[8:0]
9
Write
Reg
Write
Reg
Address
Register
A
(20:0)
21
Address
Register
A
(20:0)
21
RPS
K
K
Control
Logic
CLK
Gen.
C
C
DOFF
Read Data Reg.
18
CQ
CQ
V
REF
Reg.
Reg.
Reg.
WPS
BWS
9
Control
Logic
9
[0]
9
Q
[8:0]
9
9
Document #: 001-07036 Rev. *B
Page 2 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Logic Block Diagram (CY7C1412BV18)
D
[17:0]
18
Write
Reg
Write
Reg
Address
Register
A
(19:0)
20
Address
Register
A
(19:0)
20
RPS
C
K
K
Control
Logic
CLK
Gen.
DOFF
Read Data Reg.
36
CQ
CQ
C
18
V
REF
18
Reg.
Reg.
Reg.
18
WPS
BWS
Control
Logic
18
[1:0]
Q
[17:0]
18
Logic Block Diagram (CY7C1414BV18)
D
[35:0]
36
Write
Reg
Write
Reg
Address
Register
A
(18:0)
19
Address
Register
A
(18:0)
19
RPS
K
K
Control
Logic
CLK
Gen.
C
C
DOFF
Read Data Reg.
72
CQ
CQ
36
V
REF
36
Reg.
Reg.
Reg.
WPS
BWS
Control
Logic
36
[3:0]
36
Q
[35:0]
36
Document #: 001-07036 Rev. *B
Page 3 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Pin Configurations
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1410BV18 (4M x 8)
2
3
8
9
10
11
4
WPS
A
5
NWS1
NC/288M
A
6
7
1
NC/72M
CQ
NC
NC
NC
NC
NC
NC
RPS
A
A
K
NC/144M
NWS0
A
A
A
CQ
Q3
A
B
C
D
NC
NC
NC
NC
NC
NC
K
A
NC
NC
NC
VSS
VSS
VSS
VSS
NC
NC
D3
D4
VSS
VSS
VSS
NC
NC
NC
D5
Q4
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
D2
NC
Q2
NC
NC
ZQ
D1
NC
Q0
E
F
Q5
NC
NC
G
H
J
VREF
NC
NC
Q6
VDDQ
NC
VDDQ
NC
VREF
Q1
DOFF
NC
NC
NC
NC
NC
NC
NC
NC
NC
K
L
D6
NC
NC
NC
D7
NC
NC
NC
Q7
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
NC
D0
NC
NC
M
N
P
C
A
A
A
A
A
A
A
A
A
TDO
TCK
A
TMS
TDI
R
C
CY7C1425BV18 (4M x 9)
1
2
NC/72M
NC
3
4
WPS
A
5
NC
6
K
7
8
9
10
A
11
CQ
NC
NC
NC
NC
NC
NC
A
NC/144M RPS
A
CQ
Q4
D4
NC
A
NC
NC
NC
NC/288M
A
K
A
NC
NC
NC
NC
NC
NC
B
C
D
BWS0
NC
VSS
VSS
A
A
VSS
VSS
D5
VSS
VSS
VSS
NC
NC
D6
Q5
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
D3
NC
Q3
NC
NC
ZQ
D2
NC
Q1
E
F
Q6
NC
NC
G
H
J
VREF
NC
NC
Q7
VDDQ
NC
VDDQ
NC
VREF
Q2
DOFF
NC
NC
NC
NC
NC
NC
NC
NC
NC
K
L
D7
NC
NC
NC
D8
NC
NC
NC
Q8
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
D0
D1
NC
Q0
M
N
P
C
A
A
A
A
A
A
A
A
A
TDO
TCK
A
TMS
TDI
R
C
Document #: 001-07036 Rev. *B
Page 4 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Pin Configurations (continued)
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1412BV18 (2M x 18)
1
2
NC/144M
Q9
3
4
5
BWS1
NC
6
K
7
NC/288M
BWS0
A
8
RPS
A
9
10
NC/72M
NC
11
CQ
Q8
D8
D7
Q6
CQ
NC
NC
NC
NC
NC
NC
A
WPS
A
A
A
B
C
D
D9
D10
Q10
NC
NC
NC
K
NC
VSS
VSS
A
A
VSS
VSS
Q7
D11
VSS
VSS
VSS
NC
NC
Q12
D13
VREF
NC
Q11
D12
Q13
VDDQ
D14
Q14
D15
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
D6
NC
NC
VREF
Q4
E
F
VDD
VDD
VDD
VDD
VDD
VSS
Q5
D5
ZQ
D4
Q3
Q2
NC
G
H
J
VDDQ
NC
DOFF
NC
NC
NC
NC
NC
NC
NC
NC
D3
K
L
Q15
NC
NC
NC
D17
NC
D16
Q16
Q17
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
Q1
NC
D0
D2
D1
Q0
M
N
P
C
A
A
A
A
A
A
A
A
A
TDO
TCK
A
TMS
TDI
R
C
CY7C1414BV18 (1M x 36)
1
2
3
5
6
7
8
9
10
NC/144M
Q17
11
CQ
Q8
D8
D7
Q6
4
WPS
A
CQ
Q27
D27
D28
NC/288M NC/72M
BWS2
BWS3
A
K
BWS1
BWS0
A
RPS
A
A
A
B
C
D
Q18
Q28
D20
D18
D19
Q19
D17
D16
Q16
K
A
VSS
VSS
VSS
VSS
Q7
VSS
VSS
VSS
VSS
D15
Q29
Q30
D30
D29
Q21
D22
VREF
Q31
D32
Q24
Q20
D21
Q22
VDDQ
D23
Q23
D24
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
Q15
D14
D6
Q14
D13
VREF
Q4
E
F
VDD
VDD
VDD
VDD
VDD
VSS
Q5
D5
ZQ
D4
Q3
Q2
Q13
VDDQ
D12
G
H
J
DOFF
D31
Q32
Q33
D33
D34
Q35
Q12
D11
D3
K
L
Q11
Q34
D26
D35
D25
Q25
Q26
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
D10
Q10
Q9
Q1
D9
D0
D2
D1
Q0
M
N
P
A
C
A
A
A
A
A
A
A
TDO
TCK
A
A
TMS
TDI
R
C
Document #: 001-07036 Rev. *B
Page 5 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
Input-
Synchronous
Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.
CY7C1410BV18 - D[7:0]
CY7C1425BV18 - D[8:0]
CY7C1412BV18 - D[17:0]
CY7C1414BV18 - D[35:0]
WPS
Input-
Synchronous
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When
asserted active, a Write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D[x:0] to be ignored.
NWS0,NWS1
Nibble Write Select 0, 1 − active LOW. (CY7C1410BV18 Only) Sampled on the rising
edge of the K and K clocks during Write operations. Used to select which nibble is written
into the device during the current portion of the Write operations.Nibbles not written
remain unaltered. NWS0 controls D[3:0] and NWS1 controls D[7:4]. All Nibble Write Selects
are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause
the corresponding nibble of data to be ignored and not written into the device.
BWS0, BWS1,
BWS2, BWS3
Input-
Synchronous
Byte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and
K clocks during Write operations. Used to select which byte is written into the device
during the current portion of the Write operations. Bytes not written remain unaltered.
CY7C1425BV18 − BWS0 controls D[8:0]
CY7C1412BV18 − BWS0 controls D[8:0], BWS1 controls D[17:9]
.
CY7C1414BV18 − BWS0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18]
and BWS3 controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte
Write Select will cause the corresponding byte of data to be ignored and not written into
the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K (Read address) and K (Write
address) clocks during active Read and Write operations. These address inputs are
multiplexed for both Read and Write operations. Internally, the device is organized as 4M
x 8 (2 arrays each of 2M x 8) for CY7C1410BV18, 4M x 9 (2 arrays each of 2M x 9) for
CY7C1425BV18, 2M x 18 (2 arrays each of 1M x 18) for CY7C1412BV18 and 1M x 36
(2 arrays each of 512K x 36) for CY7C1414BV18. Therefore, only 21 address inputs are
needed to access the entire memory array of CY7C1410BV18 and CY7C1425BV18, 20
address inputs for CY7C1412BV18 and 19 address inputs for CY7C1414BV18. These
inputs are ignored when the appropriate port is deselected.
Q[x:0]
Outputs-
Synchronous
Data Output signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations or K and K when in single clock mode. When the Read port is deselected,
Q[x:0] are automatically tri-stated.
CY7C1410BV18 − Q[7:0]
CY7C1425BV18 − Q[8:0]
CY7C1412BV18 − Q[17:0]
CY7C1414BV18 − Q[35:0]
RPS
Input-
Synchronous
Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the output
drivers are automatically tri-stated following the next rising edge of the C clock. Each
read access consists of a burst of two sequential transfers.
C
C
Input-Clock
Input-Clock
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the
Read data from the device. C and C can be used together to deskew the flight times of
various devices on the board back to the controller. See application example for further
details.
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the
Read data from the device. C and C can be used together to deskew the flight times of
various devices on the board back to the controller. See application example for further
details.
Document #: 001-07036 Rev. *B
Page 6 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Pin Definitions (continued)
Pin Name
I/O
Pin Description
K
Input-Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q[x:0] when in single clock mode. All accesses
are initiated on the rising edge of K.
K
Input-Clock
Echo Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented
to the device and to drive out data through Q[x:0] when in single clock mode.
CQ
CQ is referenced with respect to C. This is a free running clock and is synchronized
to the Input clock for output data (C) of the QDR-II. In the single clock mode, CQ is
generated with respect to K. The timings for the echo clocks are shown in the AC Timing
table.
CQ
ZQ
CQ is referenced with respect to C. This is a free running clock and is synchronized
to the Input clock for output data (C) of the QDR-II. In the single clock mode, CQ is
generated with respect to K. The timings for the echo clocks are shown in the AC Timing
table.
Echo Clock
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the
system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ,
where RQ is a resistor connected between ZQ and ground. Alternatively, this pin can be
connected directly to VDDQ, which enables the minimum impedance mode. This pin
cannot be connected directly to GND or left unconnected.
DOFF
Input
DLL Turn Off - Active LOW. Connecting this pin to ground will turn off the DLL inside
the device. The timings in the DLL turned off operation will be different from those listed
in this data sheet. For normal operation, this pin can be connected to a pull-up through
a 10-Kohm or less pull-up resistor. The device will behave in DDR-I mode when the DLL
is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with QDR-I timing.
TDO
Output
Input
Input
Input
N/A
TDO for JTAG.
TCK
TCK pin for JTAG.
TDI
TDI pin for JTAG.
TMS
TMS pin for JTAG.
NC
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
NC/72M
NC/144M
NC/288M
VREF
N/A
N/A
N/A
Input-
Reference Voltage Input. Static input used to set the reference level for HSTL inputs
Reference
and Outputs as well as AC measurement points.
VDD
VSS
Power Supply
Ground
Power supply inputs to the core of the device.
Ground for the device.
VDDQ
Power Supply
Power supply inputs for the outputs of the device.
CY7C1425BV18,two 18-bit data transfers in the case of
CY7C1412BV18 and two 36-bit data transfers in the case of
CY7C1414BV18, in one clock cycle.
Functional Overview
The CY7C1410BV18, CY7C1425BV18, CY7C1412BV18 and
CY7C1414BV18 are synchronous pipelined Burst SRAMs
equipped with both a Read port and a Write port. The Read
port is dedicated to Read operations and the Write port is
dedicated to Write operations. Data flows into the SRAM
through the Write port and out through the Read port. These
devices multiplex the address inputs in order to minimize the
number of address pins required. By having separate Read
and Write ports, the QDR-II completely eliminates the need to
“turn-around” the data bus and avoids any possible data
contention, thereby simplifying system design. Each access
consists of two 8-bit data transfers in the case of
CY7C1410BV18, two 9-bit data transfers in the case of
This device operates with a read latency of one and half cycles
when DOFF pin is tied HIGH. When DOFF pin is set LOW or
connected to VSS then device will behave in QDR-I mode with
a read latency of one clock cycle.
Accesses for both ports are initiated on the rising edge of the
positive Input Clock (K). All synchronous input timings are
referenced from the rising edge of the input clocks (K and K)
and all output timings are referenced to the rising edge of
output clocks (C and C or K and K when in single clock mode).
All synchronous data inputs (D[x:0]) inputs pass through input
registers controlled by the input clocks (K and K). All
Document #: 001-07036 Rev. *B
Page 7 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
synchronous data outputs (Q[x:0]) outputs pass through output
registers controlled by the rising edge of the output clocks (C
and C or K and K when in single clock mode).
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power on. This function is
a strap option and not alterable during device operation.
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the
input clocks (K and K).
Concurrent Transactions
The Read and Write ports on the CY7C1412BV18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans-
action on the other port. Also, reads and writes can be started
in the same clock cycle. If the ports access the same location
at the same time, the SRAM will deliver the most recent infor-
mation associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.
CY7C1412BV18 is described in the following sections. The
same basic descriptions apply to CY7C1410BV18,
CY7C1425BV18, and CY7C1414BV18.
Read Operations
The CY7C1412BV18 is organized internally as 2 arrays of
1Mx18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the Positive Input Clock (K).
The address is latched on the rising edge of the K Clock. The
address presented to Address inputs is stored in the Read
address register. Following the next K clock rise the corre-
sponding lowest order 18-bit word of data is driven onto the
Depth Expansion
The CY7C1412BV18 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Q
[17:0] using C as the output timing reference. On the subse-
quent rising edge of C, the next 18-bit data word is driven onto
the Q[17:0]. The requested data will be valid 0.45 ns from the
rising edge of the output clock (C and C or K and K when in
single clock mode).
Synchronous internal circuitry will automatically tri-state the
outputs following the next rising edge of the Output Clocks
(C/C). This will allow for a seamless transition between
devices without the insertion of wait states in a depth
expanded memory.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5x the
value of the intended line impedance driven by the SRAM. The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K). On the same K
clock rise, the data presented to D[17:0] is latched and stored
into the lower 18-bit Write Data register provided BWS[1:0] are
both asserted active. On the subsequent rising edge of the
Negative Input Clock (K), the address is latched and the infor-
mation presented to D[17:0] is stored into the Write Data
register provided BWS[1:0] are both asserted active. The 36
bits of data are then written into the memory array at the
specified location. When deselected, the write port will ignore
all inputs after the pending Write operations have been
completed.
V
DDQ = 1.5V.The output impedance is adjusted every 1024
cycles upon power-up to account for drifts in supply voltage
and temperature.
Echo Clocks
Echo clocks are provided on the QDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the QDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are
free-running clocks and are synchronized to the output clock
(C/C) of the QDR-II. In the single clock mode, CQ is generated
with respect to K and CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC Timing table.
Byte Write Operations
Byte Write operations are supported by the CY7C1412BV18.
A Write operation is initiated as described in the Write Opera-
tions section above. The bytes that are written are determined
by BWS0 and BWS1, which are sampled with each 18-bit data
word. Asserting the appropriate Byte Write Select input during
the data portion of a Write will allow the data being presented
to be latched and written into the device. Deasserting the Byte
Write Select input during the data portion of a write will allow
the data stored in the device for that byte to remain unaltered.
This feature can be used to simplify Read/Modify/Write opera-
tions to a Byte Write operation.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. During power-up, when the DOFF is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K
for a minimum of 30 ns. However, it is not necessary for the
DLL to be specifically reset in order to lock the DLL to the
desired frequency. The DLL will automatically lock 1024 clock
cycles after a stable clock is presented. The DLL may be
disabled by applying ground to the DOFF pin. When the DLL
is turned off, the device will behave in QDR-I mode (with one
cycle latency and a longer access time). For information refer
to the application note “DLL Considerations in QDRII/DDRII”.
Single Clock Mode
The CY7C1412BV18 can be used with a single clock that
controls both the input and output registers. In this mode, the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
Document #: 001-07036 Rev. *B
Page 8 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Application Example[1]
R = 250οηµσ
SRAM #1
SRAM #4
R = 250οηµσ
ZQ
CQ/CQ#
Q
ZQ
CQ/CQ#
Q
R W
R
P
S
#
B
W
S
W
B
W
S
Vt
R
P
S
#
P
S
#
P
S
#
D
A
D
A
C
C#
K
K#
C C# K
K#
#
#
DATA IN
DATA OUT
Address
RPS#
WPS#
BWS#
CLKIN/CLKIN#
Vt
Vt
R
BUS
MASTER
(CPU
or
Source K
Source K#
ASIC)
Delayed K
Delayed K#
R
R = 50οηµσ
Vt = Vddq/2
Truth Table for DDR-II[2, 3, 4, 5, 6, 7]
Operation
K
RPS
WPS
DQ
D(A + 0) at K(t) ↑
DQ
D(A + 1) at K(t) ↑
Write Cycle:
L-H
X
L
Load address on the rising edge of K clock; input
write data on K and K rising edges.
Read Cycle:
L-H
L-H
L
X
Q(A + 0) at C(t + 1) ↑ Q(A + 1) at C(t + 2) ↑
Load address on the rising edge of K clock; wait one
and a half cycle; read data on C and C rising edges.
NOP: No Operation
H
X
H
X
D = X
Q = High-Z
D = X
Q = High-Z
Standby: Clock Stopped
Stopped
Previous State
Previous State
Notes:
1. The above application shows four QDR-II being used.
2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW, ↑represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 00, A + 01 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
Document #: 001-07036 Rev. *B
Page 9 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Write Cycle Descriptions (CY7C1410BV18 and CY7C1412BV18) [2, 8]
BWS NWS
BWS NWS
1
K
K
/
/
Comments
0
0
1
L
L
L
L
L-H
–
During the Data portion of a Write sequence:
CY7C1410BV18 − both nibbles (D[7:0]) are written into the device,
CY7C1412BV18 − both bytes (D[17:0]) are written into the device.
L
–
L-H During the Data portion of a Write sequence:
CY7C1410BV18 − both nibbles (D[7:0]) are written into the device,
CY7C1412BV18 − both bytes (D[17:0]) are written into the device.
H
L-H
–
During the Data portion of a Write sequence:
CY7C1410BV18 − only the lower nibble (D[3:0]) is written into the device.
D[7:4] will remain unaltered,
CY7C1412BV18 − only the lower byte (D[8:0]) is written into the device.
D[17:9] will remain unaltered.
L
H
H
H
L
L
–
L-H
–
L-H During the Data portion of a Write sequence:
CY7C1410BV18 − only the lower nibble (D[3:0]) is written into the device.
D[7:4] will remain unaltered,
CY7C1412BV18 − only the lower byte (D[8:0]) is written into the device.
D[17:9] will remain unaltered.
–
During the Data portion of a Write sequence:
CY7C1410BV18 − only the upper nibble (D[7:4]) is written into the device.
D[3:0] will remain unaltered,
CY7C1412BV18 − only the upper byte (D[17:9]) is written into the device.
D[8:0] will remain unaltered.
L-H During the Data portion of a Write sequence:
CY7C1410BV18 − only the upper nibble (D[7:4]) is written into the device.
D[3:0] will remain unaltered,
CY7C1412BV18 − only the upper byte (D[17:9]) is written into the device.
D[8:0] will remain unaltered.
H
H
H
H
L-H
–
–
No data is written into the devices during this portion of a Write operation.
L-H No data is written into the devices during this portion of a Write operation.
Write Cycle Descriptions (CY7C1425BV18) [2, 8]
BWS0
K
K
Comments
L
L-H
–
During the Data portion of a Write sequence:
CY7C1425BV18 - the single byte (D[8:0]) is written into the device
L
–
L-H
During the Data portion of a Write sequence:
CY7C1425BV18 - the single byte (D[8:0]) is written into the device
H
H
L-H
–
–
No data is written into the devices during this portion of a Write operation.
No data is written into the devices during this portion of a Write operation.
L-H
Note:
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS , NWS , BWS , BWS , BWS and BWS can be altered on different
0
1
0
1
2
3
portions of a Write cycle, as long as the set-up and hold requirements are achieved.
Document #: 001-07036 Rev. *B
Page 10 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
[2, 8]
Write Cycle Descriptions (CY7C1414BV18)
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L-H
-
During the Data portion of a Write sequence, all four bytes (D[35:0]) are
written into the device.
L
L
L
L
-
L-H
-
L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) are
written into the device.
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
-
During the Data portion of a Write sequence, only the lower byte (D[8:0]
is written into the device. D[35:9] will remain unaltered.
)
L
L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]
is written into the device. D[35:9] will remain unaltered.
)
H
H
H
H
H
H
L-H
-
-
During the Data portion of a Write sequence, only the byte (D[17:9]) is
written into the device. D[8:0] and D[35:18] will remain unaltered.
L
L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is
written into the device. D[8:0] and D[35:18] will remain unaltered.
H
H
H
H
L-H
-
-
During the Data portion of a Write sequence, only the byte (D[26:18]) is
written into the device. D[17:0] and D[35:27] will remain unaltered.
L
L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is
written into the device. D[17:0] and D[35:27] will remain unaltered.
H
H
L-H
-
During the Data portion of a Write sequence, only the byte (D[35:27]) is
written into the device. D[26:0] will remain unaltered.
L
L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is
written into the device. D[26:0] will remain unaltered.
H
H
H
H
H
H
H
H
L-H
-
-
No data is written into the device during this portion of a Write operation.
L-H No data is written into the device during this portion of a Write operation.
Document #: 001-07036 Rev. *B
Page 11 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-2001. The TAP operates using
JEDEC standard 1.8V I/O logic levels.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
Test Access Port—Test Clock
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in TAP Controller Block Diagram.
Document #: 001-07036 Rev. *B
Page 12 of 26
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CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
SAMPLE Z
BYPASS
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
SAMPLE/PRELOAD
EXTEST
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit
#108. When this scan cell, called the “extest output bus
tri-state,” is latched into the preload register during the
“Update-DR” state in the TAP controller, it will directly control
the state of the output (Q-bus) pins, when the EXTEST is
entered as the current instruction. When HIGH, it will enable
the output buffers to drive the output bus. When LOW, this bit
will place the output bus into a High-Z condition.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set LOW to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
Document #: 001-07036 Rev. *B
Page 13 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
TAP Controller State Diagram[9]
TEST-LOGIC
1
RESET
0
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 001-07036 Rev. *B
Page 14 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
1
0
TDO
TDI
Instruction Register
29
31 30
.
.
2
0
0
Identification Register
108
.
.
.
.
2
1
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[10, 14, 17]
Parameter
VOH1
Description
Output HIGH Voltage
Test Conditions
IOH = −2.0 mA
Min.
1.4
Max.
Unit
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
IOH = −100 µA
IOL = 2.0 mA
IOL = 100 µA
1.6
V
0.4
0.2
V
V
0.65VDD
–0.3
VDD + 0.3
0.35VDD
5
V
VIL
Input LOW Voltage
V
IX
Input and OutputLoad Current
GND ≤ VI ≤ VDD
−5
µA
Notes:
10. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
Document #: 001-07036 Rev. *B
Page 15 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range[11, 12]
Parameter
tTCYC
Description
Min.
Max.
Unit
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
50
tTF
20
MHz
ns
tTH
20
20
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
tTDIS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
5
5
5
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Capture Hold after Clock Rise
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
10
ns
ns
0
TAP Timing and Test Conditions[12]
0.9V
50Ω
ALL INPUT PULSES
0.9V
1.8V
TDO
Z = 50Ω
0
0V
C = 20 pF
L
tTL
tTH
GND
(a)
tTCYC
Test Clock
TCK
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Notes:
11. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
12. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
Document #: 001-07036 Rev. *B
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Identification Register Definitions
Value
Instruction Field
CY7C1410BV18
CY7C1425BV18
001
CY7C1412BV18
001
CY7C1414BV18
001
Description
Revision Number
(31:29)
001
Version number.
Cypress Device ID
(28:12)
11010011010000111 11010011010001111 11010011010010111 11010011010100111 Defines the type of
SRAM.
Cypress JEDEC ID
(11:1)
00000110100
00000110100
00000110100
00000110100
Unique identifi-
cation of SRAM
vendor.
ID Register Presence
(0)
1
1
1
1
Indicates the
presence of an ID
register.
Scan Register Sizes
Register Name
Instruction
Bit Size
3
1
Bypass
ID
32
109
Boundary Scan Cells
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the Input/Output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operation.
Document #: 001-07036 Rev. *B
Page 17 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Boundary Scan Order
Bit #
0
Bump ID
6R
Bit #
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Bump ID
Bit #
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Bump ID
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
Bit #
84
Bump ID
1J
10G
9G
1
6P
85
2J
2
6N
11F
11G
9F
86
3K
3
7P
87
3J
4
7N
88
2K
5
7R
10F
11E
10E
10D
9E
89
1K
6
8R
90
2L
7
8P
91
3L
8
9R
92
1M
1L
9
11P
10P
10N
9P
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
10C
11D
9C
94
3N
95
3M
1N
96
10M
11N
9M
9D
97
2M
3P
11B
11C
9B
98
99
2N
9N
100
101
102
103
104
105
106
107
108
2P
11L
11M
9L
10B
11A
10A
9A
1P
3R
4R
10L
11K
10K
9J
4P
8B
5P
7C
3F
5N
6C
1G
1F
5R
9K
8A
Internal
10J
11J
11H
7A
3G
2G
1H
7B
6B
Document #: 001-07036 Rev. *B
Page 18 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Power-up Sequence in QDR-II SRAM[13]
QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
DLL Constraints
• DLL uses K clock as its synchronizing input. The input
should have low phase jitter, which is specified as tKC Var
.
• The DLL will function at frequencies down to 80 MHz.
Power-Up Sequence
• If the input clock is unstable and the DLL is enabled, then
the DLL may lock onto an incorrect frequency, causing
unstableSRAMbehavior. Toavoidthis, provide1024cycles
stable clock to relock to the desired clock frequency
• Apply power with DOFF tied HIGH (All other inputs can be
HIGH or LOW)
— Apply VDD before VDDQ
— Apply VDDQ before VREF or at the same time as VREF
• Provide stable power and clock (K, K) for 1024 cycles to
lock the DLL.
Power-up Waveforms
K
K
Unstable Clock
> 1024 Stable clock
Start Normal
Operation
/
V
Clock Start (Clock Starts after V
Stable)
DDQ
DD
Stable (< +/- 0.1V DC per 50ns )
/
/
V
DDQ
VDDQ
V
DD
VDD
Fix High (or tied to V
)
DDQ
DOFF
Notes:
13. During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.
Document #: 001-07036 Rev. *B
Page 19 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired.)
Storage Temperature .................................–65°C to +150°C
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied...............................................–10°C to +85°C
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V
Supply Voltage on VDDQ Relative to GND ......–0.5V to +VDD
Ambient
[18]
[18]
Range Temperature (TA)
VDD
VDDQ
1.4V to VDD
Com’l
Ind’l
0°C to +70°C
1.8 ± 0.1V
DC Voltage Applied to Outputs
in High-Z State .................................... –0.5V to VDDQ + 0.3V
–40°C to +85°C
DC Input Voltage[17] ...............................–0.5V to VDD + 0.3V
Electrical Characteristics Over the Operating Range[14, 18]
DC Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
1.7
Typ.
1.8
Max.
Unit
V
1.9
VDDQ
VOH
1.4
1.5
VDD
V
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[17]
Input LOW Voltage[17]
Input Leakage Current
Output Leakage Current
Note 15
Note 16
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
VSS
VDDQ/2 + 0.12
V
VOL
VDDQ/2 + 0.12
V
VOH(LOW)
VOL(LOW)
VIH
IOH = −0.1 mA, Nominal Impedance
VDDQ
0.2
V
IOL = 0.1 mA, Nominal Impedance
V
VREF + 0.1
–0.3
VDDQ+0.3
VREF – 0.1
5
V
VIL
V
IX
GND ≤ VI ≤ VDDQ
−5
µA
µA
V
IOZ
GND ≤ VI ≤ VDDQ, Output Disabled
−5
5
VREF
IDD
Input Reference Voltage[19] Typical Value = 0.75V
0.68
0.75
0.95
740
VDD Operating Supply
VDD = Max., IOUT = 0 167 MHz
mA
mA
mA
mA
mA
mA
mA, f = fMAX = 1/tCYC
200 MHz
250 MHz
870
1065
270
ISB1
Automatic Power-down
Current
Max. VDD, Both Ports 167 MHz
Deselected, VIN ≥ VIH
200 MHz
300
or VIN ≤ VIL, f = fMAX
=
250 MHz
350
1/tCYC, Inputs Static
AC Input Requirements Over the Operating Range
Parameter
VIH
VIL
Description
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min.
VREF + 0.2
–
Typ.
Max.
–
Unit
V
–
–
VREF – 0.2
V
Capacitance[20]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
DD = 1.8V
DDQ = 1.5V
Max.
Unit
pF
CIN
Input Capacitance
5
4
5
V
V
CCLK
Clock Input Capacitance
Output Capacitance
pF
CO
pF
Notes:
14. All voltage referenced to Ground.
15. Output are impedance controlled. I = –(V
/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs.
OH
DDQ
16. Output are impedance controlled. I = (V
/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.
OL
DDQ
17. Overshoot: V (AC) < V
+0.85V (Pulse width less than t
/2), Undershoot: V (AC) > –1.5V (Pulse width less than t
/2).
IH
DDQ
CYC
IL
CYC
18. Power-up: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
DD
IH
DD
DDQ
DD
19. V
(Min.) = 0.68V or 0.46V
, whichever is larger, V
(Max.) = 0.95V or 0.54V
, whichever is smaller.
REF
DDQ
REF
DDQ
20. Tested initially and after any design or process change that may affect these parameters.
Document #: 001-07036 Rev. *B
Page 20 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Thermal Resistance[20]
165 FBGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
17.2
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
3.2
°C/W
AC Test Loads and Waveforms
VREF = 0.75V
0.75V
VREF
VREF
0.75V
R = 50Ω
OUTPUT
[21]
ALL INPUT PULSES
Z = 50Ω
0
OUTPUT
1.25V
Device
R = 50Ω
L
0.75V
Under
Device
Under
0.25V
Test
5 pF
VREF = 0.75V
Slew Rate = 2 V/ns
ZQ
Test
ZQ
RQ =
RQ =
250Ω
250Ω
INCLUDING
JIG AND
SCOPE
(a)
(b)
Note:
21. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, V
= 1.5V, input
DDQ
pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC Test Loads.
OL OH
Document #: 001-07036 Rev. *B
Page 21 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Switching Characteristics Over the Operating Range [21, 22]
250 MHz
200 MHz
167 MHz
Cypress Consortium
Parameter Parameter
Description
VDD(Typical) to the first Access[23]
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
Min. Max. Min. Max. Min. Max. Unit
tPOWER
1
1
1
ms
ns
ns
ns
ns
tCYC
tKH
tKHKH
tKHKL
tKLKH
tKHKH
4.0
1.6
1.6
6.3
–
5.0
2.0
2.0
2.2
7.9
–
6.0
2.4
2.4
2.7
8.4
–
tKL
–
–
–
tKHKH
K Clock Rise to K Clock Rise and C to C Rise (rising 1.8
edge to rising edge)
–
–
–
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge to rising
edge)
0
1.8
0
2.2
0
2.7
ns
Set-up Times
tSA
tAVKH
tIVKH
tIVKH
Address Set-up to K Clock Rise
0.35
0.35
0.35
–
–
–
0.4
0.4
0.4
–
–
–
0.5
0.5
0.5
–
–
–
ns
ns
ns
tSC
Control Set-up to K Clock Rise (RPS, WPS)
tSCDDR
Double Data Rate Control Set-up to Clock
(K/K) Rise (BWS0, BWS1, BWS3, BWS4)
[24]
tSD
tDVKH
D[X:0] Set-up to Clock (K/K) Rise
0.35
–
0.4
–
0.5
–
ns
Hold Times
tHA
tKHAX
tKHIX
tKHIX
Address Hold after K Clock Rise
0.35
0.35
0.35
–
–
–
0.4
0.4
0.4
–
–
–
0.5
0.5
0.5
–
–
–
ns
ns
ns
tHC
Control Hold after K Clock Rise (RPS, WPS)
tHCDDR
Double Data Rate Control Hold after Clock (K/K) Rise
(BWS0, BWS1, BWS3, BWS4)
tHD
tKHDX
D[X:0] Hold after Clock (K/K) Rise
0.35
–
–
0.4
–
0.5
–
ns
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in Single Clock Mode) to Data
Valid
0.45
–
–
0.45
–
–
0.50
–
ns
ns
tDOH
tCHQX
Data Output Hold after Output C/C Clock Rise (Active –0.45
to Active)
-0.45
-0.50
tCCQO
tCQOH
tCQD
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCQHCQL
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Valid
–
0.45
–
–
0.45
–
–
0.50
–
ns
ns
ns
ns
ns
ns
–0.45
–
–0.45
–
–0.50
–
0.30
–
0.35
–
0.40
–
tCQDOH
tCQH
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH[25]
CQ Clock Rise to CQ Clock Rise[25]
(rising edge to rising edge)
–0.30
1.55
1.55
–0.35
1.95
1.95
–0.40
2.45
2.45
–
–
–
tCQHCQH tCQHCQH
–
–
–
tCHZ
tCLZ
tCHQZ
Clock (C/C) Rise to High-Z (Active to High-Z)[26,27]
Clock (C/C) Rise to Low-Z[26,27]
–
0.45
–
–
0.45
–
–
0.50
–
ns
ns
tCHQX1
–0.45
–0.45
–0.50
DLL Timing
tKC Var tKC Var
tKC lock tKC lock
Clock Phase Jitter
–
0.20
–
–
0.20
–
–
0.20
–
ns
cycles
ns
DLL Lock Time (K, C)
K Static to DLL Reset
1024
30
1024
30
1024
30
tKC Reset tKC Reset
–
–
–
Notes:
22. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
23. This part has a voltage regulator internally; t
can be initiated.
is the time that the power needs to be supplied above V minimum initially before a read or write operation
DD
POWER
24. For D2 data signal on CY7C1425BV18 device, t is 0.5ns for 200MHz, and 250MHz frequencies.
SD
25. These parameters are extrapolated from the input timing parameters (t
- 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t
) ia already
KHKH
KC Var
included in the t
). These parameters are only guaranteed by design and are not tested in production.
KHKH
26. t
, t
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
CHZ CLZ
27. At any given voltage and temperature t
is less than t
and t
less than t
.
CHZ
CLZ
CHZ
CO
Document #: 001-07036 Rev. *B
Page 22 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Switching Waveforms[28, 29, 30]
READ
WRITE
2
READ
3
WRITE
4
WRITE
6
WRITE
8
NOP
READ
NOP
7
1
5
9
10
K
t
t
KHKH
t
t
CYC
KH
KL
K
RPS
t
t
SC
HC
WPS
A
A2
A3
A4
A0
A1
A5
A6
t
t
t
t
SA HA
SA HA
D
Q
D31
t
D10
D11
D30
D50
D51
D60
D61
t
t
t
SD
HD
SD
HD
Q20
CQDOH
Q00
Q01
DOH
Q21
Q40
Q41
t
t
CLZ
t
t
CHZ
t
KHCH
t
t
KL
t
CO
CQD
t
C
C
KH
t
t
KHKH
CYC
t
KHCH
t
CCQO
t
CQOH
t
CQ
CQ
t
t
CCQO
CQHCQH
CQH
t
CQOH
DON’T CARE
UNDEFINED
Notes:
28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1.
29. Outputs are disabled (High-Z) one clock cycle after a NOP.
30. In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole
diagram.
Document #: 001-07036 Rev. *B
Page 23 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Ordering Information
“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered”.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
250 CY7C1410BV18-250BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Commercial
CY7C1425BV18-250BZC
CY7C1412BV18-250BZC
CY7C1414BV18-250BZC
250 CY7C1410BV18-250BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free Commercial
CY7C1425BV18-250BZXC
CY7C1412BV18-250BZXC
CY7C1414BV18-250BZXC
250 CY7C1410BV18-250BZI
CY7C1425BV18-250BZI
CY7C1412BV18-250BZI
CY7C1414BV18-250BZI
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
250 CY7C1410BV18-250BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free Industrial
CY7C1425BV18-250BZXI
CY7C1412BV18-250BZXI
CY7C1414BV18-250BZXI
200 CY7C1410BV18-200BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Commercial
CY7C1425BV18-200BZC
CY7C1412BV18-200BZC
CY7C1414BV18-200BZC
200 CY7C1410BV18-200BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free Commercial
CY7C1425BV18-200BZXC
CY7C1412BV18-200BZXC
CY7C1414BV18-200BZXC
200 CY7C1410BV18-200BZI
CY7C1425BV18-200BZI
CY7C1412BV18-200BZI
CY7C1414BV18-200BZI
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
200 CY7C1410BV18-200BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free Industrial
CY7C1425BV18-200BZXI
CY7C1412BV18-200BZXI
CY7C1414BV18-200BZXI
167 CY7C1410BV18-167BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Commercial
CY7C1425BV18-167BZC
CY7C1412BV18-167BZC
CY7C1414BV18-167BZC
167 CY7C1410BV18-167BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free Commercial
CY7C1425BV18-167BZXC
CY7C1412BV18-167BZXC
CY7C1414BV18-167BZXC
Document #: 001-07036 Rev. *B
Page 24 of 26
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Ordering Information
“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered”.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
167 CY7C1410BV18-167BZI
CY7C1425BV18-167BZI
CY7C1412BV18-167BZI
CY7C1414BV18-167BZI
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
167 CY7C1410BV18-167BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free Industrial
CY7C1425BV18-167BZXI
CY7C1412BV18-167BZXI
CY7C1414BV18-167BZXI
Package Diagram
165-ball FBGA (15 x 17 x 1.40 mm) (51-85195)
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QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and
Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 001-07036 Rev. *B
Page 25 of 26
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
PRELIMINARY
Document History Page
Document Title: CY7C1410BV18/CY7C1425BV18/CY7C1412BV18/CY7C1414BV18 36-Mbit QDR-II™ SRAM 2-Word
Burst Architecture
Document Number: 001-07036
Orig. of
REV.
**
ECN No. Issue Date Change
Description of Change
433267
462004
See ECN
See ECN
NXR
NXR
New Data Sheet
Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH
*A
,
t
TDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP
AC Switching Characteristics table
Modified Power-Up waveform
*B
503690
See ECN
VKN
Minor change: Moved data sheet to web
Document #: 001-07036 Rev. *B
Page 26 of 26
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