CY7C1441AV25-133BZXIT [CYPRESS]
Standard SRAM, 1MX36, 6.5ns, CMOS, PBGA165;
| 型号： | CY7C1441AV25-133BZXIT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 1MX36, 6.5ns, CMOS, PBGA165 时钟 静态存储器 内存集成电路 |
| 文件： | 总33页 (文件大小：1379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1441AV25
CY7C1447AV25
36-Mbit (1M × 36/512K × 72)
Flow-Through SRAM
36-Mbit (1M
× 36/512K × 72) Flow-Through SRAM
Features
Functional Description
■ Supports 133 MHz bus operations
■ 1M × 36/512K × 72 common I/O
■ 2.5 V core power supply
The CY7C1441AV25/CY7C1447AV25 are 2.5 V, 1M × 36/512K × 72
Synchronous Flow-Through SRAMs, designed to interface with
high speed microprocessors with minimum glue logic. Maximum
access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit
on-chip counter captures the first address in a burst and
increments the address automatically for the rest of the burst
access. All synchronous inputs are gated by registers controlled
■ 2.5 V I/O power supply
■ Fast clock-to-output times
❐ 6.5 ns (133 MHz version)
by
a
positive edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address pipelining Chip Enable (CE1), depth expansion Chip
Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and
ADV), Write Enables (BWx and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the ZZ
pin.
■ Provide high performance 2-1-1-1 access rate
■ User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self timed write
The CY7C1441AV25/CY7C1447AV25 allows either interleaved
or linear burst sequences, selected by the MODE input pin. A
HIGH selects an interleaved burst sequence and a LOW selects
a linear burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
■ Asynchronous output enable
■ CY7C1441AV25 available in Pb-free 165-ball FBGA package.
CY7C1447AV25 available in non Pb-free 209-ball FBGA
package.
■ JTAG boundary scan for FBGA package
■ ZZ sleep mode option
Addresses and chip enables are registered at rising edge of
clock when either ADSP or ADSC are active. Subsequent burst
addresses can be internally generated as controlled by the ADV.
operates from a
+2.5 V core power supply while all outputs may operate with
either +2.5 supply. All inputs and outputs are
The CY7C1441AV25/CY7C1447AV25
a
V
JEDEC-standard JESD8-5 compatible.
For a complete list of related documentation, click here.
Selection Guide
Description
Maximum Access Time
133 MHz Unit
6.5
270
120
ns
Maximum Operating Current
mA
mA
Maximum CMOS Standby Current
Cypress Semiconductor Corporation
Document Number: 001-75380 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 7, 2016
CY7C1441AV25
CY7C1447AV25
Logic Block Diagram – CY7C1441AV25
ADDRESS
REGISTER
A0, A1,
A
A
[1:0]
MODE
ADV
CLK
Q1
Q0
BURST
COUNTER
AND LOGIC
CLR
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D, DQP D
DQ
BYTE
WRITE REGISTER
D, DQP D
BW
D
DQ
BYTE
WRITE REGISTER
C, DQP C
DQ
BYTE
WRITE REGISTER
C, DQP C
BW
C
OUTPUT
BUFFERS
DQ s
MEMORY
ARRAY
SENSE
AMPS
DQP
DQP
DQP
DQP
A
DQ
BYTE
WRITE REGISTER
B, DQP B
B
C
D
DQ
BYTE
WRITE REGISTER
B, DQP B
BW
B
DQ
BYTE
WRITE REGISTER
A, DQP A
DQ
A, DQPA
BW
A
BYTE
BWE
WRITE REGISTER
INPUT
GW
REGISTERS
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
Document Number: 001-75380 Rev. *F
Page 2 of 33
CY7C1441AV25
CY7C1447AV25
Logic Block Diagram – CY7C1447AV25
ADDRESS
REGISTER
A0, A1,A
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER
AND LOGIC
CLR
Q0
ADSC
ADSP
DQ
H
,
DQP
H
DQ
H, DQPH
BW
BW
H
G
WRITE REGISTER
WRITE DRIVER
DQ
G, DQPG
DQ
F, DQPF
WRITE DRIVER
WRITE REGISTER
DQ
F, DQPF
DQ
F, DQPF
BW
BW
BW
BW
F
E
WRITE DRIVER
WRITE REGISTER
DQ E
E
,
DQP
DQ
E, DQPE
WRITE DRIVER
WRITE REGISTER
MEMORY
ARRAY
DQ
D, DQPD
DQ
D, DQPD
D
WRITE REGISTER
WRITE DRIVER
DQ
C, DQPC
DQ
C, DQPC
C
WRITE DRIVER
WRITE REGISTER
OUTPUT
BUFFERS
DQs
DQP
DQP
DQP
DQP
DQP
DQP
DQP
DQP
SENSE
AMPS
A
B
C
D
E
DQ
B, DQPB
DQ
B, DQPB
WRITE DRIVER
BW
BW
B
WRITE REGISTER
DQ
A, DQPA
F
DQ A, DQPA
WRITE REGISTER
WRITE DRIVER
G
H
A
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
Document Number: 001-75380 Rev. *F
Page 3 of 33
CY7C1441AV25
CY7C1447AV25
Contents
Pin Configurations ...........................................................5
Pin Definitions ..................................................................7
Functional Overview ........................................................8
Single Read Accesses ................................................8
Single Write Accesses Initiated by ADSP ...................8
Single Write Accesses Initiated by ADSC ...................8
Burst Sequences .........................................................9
Sleep Mode .................................................................9
Interleaved Burst Address Table .................................9
Linear Burst Address Table .........................................9
ZZ Mode Electrical Characteristics ..............................9
Truth Table ......................................................................10
Partial Truth Table for Read/Write ................................11
Partial Truth Table for Read/Write ................................11
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................12
Disabling the JTAG Feature ......................................12
Test Access Port (TAP) .............................................12
Performing a TAP Reset ...........................................12
TAP Registers ...........................................................12
TAP Instruction Set ...................................................12
Tap Controller State Diagram ........................................14
Tap Controller Block Diagram .......................................15
TAP Timing ......................................................................15
TAP AC Switching Characteristics ...............................16
2.5 V TAP AC Test Conditions .......................................17
2.5 V TAP AC Output Load Equivalent .........................17
TAP DC Electrical Characteristics
Identification Register Definitions ................................18
Scan Register Sizes .......................................................18
Identification Codes .......................................................18
Boundary Scan Order ....................................................19
Boundary Scan Order ....................................................20
Maximum Ratings ...........................................................21
Operating Range .............................................................21
Electrical Characteristics ...............................................21
Capacitance ....................................................................22
Thermal Resistance ........................................................22
AC Test Loads and Waveforms .....................................22
Switching Characteristics ..............................................23
Timing Diagrams ............................................................24
Ordering Information ......................................................28
Ordering Code Definitions .........................................28
Package Diagrams ..........................................................29
Acronyms ........................................................................31
Document Conventions .................................................31
Units of Measure .......................................................31
Document History Page .................................................32
Sales, Solutions, and Legal Information ......................33
Worldwide Sales and Design Support .......................33
Products ....................................................................33
PSoC® Solutions ......................................................33
Cypress Developer Community .................................33
Technical Support .....................................................33
and Operating Conditions .............................................17
Document Number: 001-75380 Rev. *F
Page 4 of 33
CY7C1441AV25
CY7C1447AV25
Pin Configurations
Figure 1. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1441AV25 (1M × 36)
1
2
A
3
CE1
4
BWC
5
BWB
6
CE3
7
8
9
ADV
10
A
11
NC
NC/288M
NC/144M
DQPC
BWE
GW
VSS
VSS
ADSC
A
B
C
D
A
CE2
VDDQ
VDDQ
BWD
VSS
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
ADSP
VDDQ
VDDQ
A
NC/576M
DQPB
DQB
NC
DQC
NC/1G
DQB
DQC
VDD
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
NC/72M
TDI
A1
TDO
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
Document Number: 001-75380 Rev. *F
Page 5 of 33
CY7C1441AV25
CY7C1447AV25
Pin Configurations (continued)
Figure 2.
209-ball FBGA (14 × 22 × 1.76 mm) pinout
CY7C1447AV25 (512K × 72)
1
2
3
4
5
6
7
8
9
10
11
DQG
DQG
DQG
A
B
C
D
E
F
DQG
DQG
CE3
DQB
DQB
CE2
ADSP
ADV
A
DQB
DQB
ADSC
BW
A
A
BWSB
NC/288M
NC/144M
BWSC
BWSH
VSS
BWSF
BWSG
BWSD
DQG
DQG
NC/576M
GW
BWSE
NC
CE1
OE
BWSA DQB
DQB
DQB
DQG
NC/1G
VSS
NC
DQB
DQPG DQPC
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
NC
NC
NC
NC
VSS
NC
NC
VDD
VSS
VDD
DQPF DQPB
DQC
DQC
VSS
DQF
DQF
VSS
VDDQ
VSS
VSS
G
H
J
DQC
DQC
DQC
VDDQ
VSS
VDDQ
VSS
DQF
DQF
DQF
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
A
VSS
DQC
DQC
NC
DQF
DQF
NC
VDDQ
DQC
NC
VDDQ
VDDQ
NC
VDDQ
CLK
DQF
NC
K
L
NC
VDDQ
VSS
NC
DQH
DQH
DQH VDDQ
VDDQ
VDDQ
VSS
DQA
DQA
DQA
M
N
P
R
T
VSS
VSS
VDDQ
VSS
VDDQ
NC
DQH
VSS
VDD
VSS
DQA
DQA
DQA
VDDQ
DQH
DQH
DQPD
DQD
DQD
VDDQ
DQH
VDDQ
VSS
NC
ZZ
DQA
DQA
DQPA
DQE
DQE
DQH
VSS
VSS
VDDQ
VSS
A
VDDQ
VDD
NC
A
DQPH
DQD
DQD
DQD
DQD
VDDQ
VDD
DQPE
DQE
DQE
DQE
DQE
VSS
NC
A
MODE
A
U
V
W
A
NC/72M
A
A
A1
A
DQD
DQD
A
A
A
A
DQE
DQE
TDI
TDO
TCK
A0
A
TMS
Document Number: 001-75380 Rev. *F
Page 6 of 33
CY7C1441AV25
CY7C1447AV25
Pin Definitions
Name
I/O
Description
Address Inputs. Used to select one of the address locations. Sampled at the rising edge of the CLK if
A0, A1, A
Input-
Synchronous ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter.
Input- Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
BWA,
BWB,
BWC,
BWD,
BWE,BWF,
BWG, BWH
GW
CLK
CE1
Input-
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write
Synchronous is conducted (ALL bytes are written, regardless of the values on BWX and BWE).
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW during a burst operation.
Input-
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when
a new external address is loaded.
CE2
CE3
OE
Input-
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
Input- Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
Input- Output Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronou the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated and act as input data
s
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input-
Advance Input Signal. Sampled on the rising edge of CLK. When asserted, it automatically increments
Synchronous the address in a burst cycle.
ADSP
Input-
Address Strobe from Processor. Sampled on the rising edge of CLK, active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when
CE1 is deasserted HIGH.
ADSC
Input-
Address Strobe from Controller. Sampled on the rising edge of CLK, active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
BWE
ZZ
Input-
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
Input-
ZZ Sleep Input, Active HIGH. When asserted HIGH places the device in a non time-critical “sleep”
Asynchronou condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ
s
pin has an internal pull down.
I/O-
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
DQs
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a
write sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
I/O-
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
DQPX
Synchronous sequences, DQPx is controlled by BWX correspondingly.
MODE
Input-Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode pin has an internal pull up.
Document Number: 001-75380 Rev. *F
Page 7 of 33
CY7C1441AV25
CY7C1447AV25
Pin Definitions (continued)
Name
VDD
I/O
Description
Power Supply Inputs to the Core of the Device.
Power
Supply
VDDQ
I/O Power Power Supply for I/O Circuitry.
Supply
VSS
Ground
I/O Ground Ground for I/O Circuitry.
JTAG Serial Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG feature
Ground for the Core of the Device.
VSSQ
TDO
Output
is not utilized, this pin should be left unconnected.
Synchronous
TDI
JTAG Serial Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not
Input
utilized, this pin can be left floating or connected to VDD through a pull up resistor.
Synchronous
TMS
JTAG Serial Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not
Input
utilized, this pin can be disconnected or connected to VDD.
Synchronous
TCK
NC
JTAG-
Clock
Clock Input to the JTAG Circuitry. If the JTAG feature is not utilized, this pin must be connected to VSS
.
–
–
No Connects. Not internally connected to the die.
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
No Connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M, and NC/1G
are address expansion pins and are not internally connected to the die.
active and (2) ADSP or ADSC is asserted LOW (if the access is
initiated by ADSC, the write inputs must be deasserted during
Functional Overview
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter or control
logic and presented to the memory core. If the OE input is
asserted LOW, the requested data is available as the data
outputs a maximum to tCDV after clock rise. ADSP is ignored if
CE1 is HIGH.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (tCDV) is 6.5 ns (133 MHz device).
The CY7C1441AV25/CY7C1447AV25 supports secondary
cache in systems utilizing either a linear or interleaved burst
sequence. The interleaved burst order supports Pentium and
i486™ processors. The linear burst sequence is suited for
processors that utilize a linear burst sequence. The burst order
is user selectable and is determined by sampling the MODE
input. Accesses are initiated with either ADSP or ADSC. Address
advancement through the burst sequence is controlled by the
ADV input. A two-bit on-chip wraparound burst counter captures
the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BWX) are ignored during this first clock cycle. If the write
inputs are asserted active (see Truth Table on page 10 for
appropriate states that indicate a write) on the next clock rise, the
appropriate data is latched and written into the device. Byte
writes are allowed. All I/Os are tri-stated during a byte write.
Because this is a common I/O device, the asynchronous OE
input signal must be deasserted and the I/Os must be tri-stated
prior to the presentation of data to DQs. As a safety precaution,
the data lines are tri-stated when a write cycle is detected,
regardless of the state of OE.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWx) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous self
timed write circuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1 is
HIGH.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
Document Number: 001-75380 Rev. *F
Page 8 of 33
CY7C1441AV25
CY7C1447AV25
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
deselected prior to entering the sleep mode. CE1, CE2, CE3,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
The addresses presented are loaded into the address register
and the burst counter or control logic and delivered to the
memory core. The information presented to DQS is written into
the specified address location. Byte writes are allowed. All I/Os
are tri-stated when a write is detected, even a byte write.
Because this is a common I/O device, the asynchronous OE
input signal must be deasserted and the I/Os must be tri-stated
prior to the presentation of data to DQs. As a safety precaution,
the data lines are tri-stated when a write cycle is detected,
regardless of the state of OE.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Burst Sequences
The CY7C1441AV25/CY7C1447AV25 provides an on-chip
two-bit wraparound burst counter inside the SRAM. The burst
counter is fed by A[1:0], and can follow either a linear or inter-
leaved burst order. The burst order is determined by the state of
the MODE input. A LOW on MODE selects a linear burst
sequence. A HIGH on MODE selects an interleaved burst order.
Leaving MODE unconnected causes the device to default to a
interleaved burst sequence.
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. When in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min
Max
100
2tCYC
–
Unit
mA
ns
ZZ > VDD– 0.2 V
–
tZZS
ZZ > VDD – 0.2 V
ZZ < 0.2 V
–
2tCYC
–
tZZREC
tZZI
ns
ZZ active to sleep current
This parameter is sampled
2tCYC
–
ns
tRZZI
ZZ Inactive to exit sleep current This parameter is sampled
0
ns
Document Number: 001-75380 Rev. *F
Page 9 of 33
CY7C1441AV25
CY7C1447AV25
Truth Table
The truth table for CY7C1441AV25/CY7C1447AV25 follows. [1, 2, 3, 4, 5]
Cycle Description
Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Sleep Mode, Power Down
Read Cycle, Begin Burst
None
None
H
L
X
L
X
X
H
X
X
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L–H Tri-State
L–H Tri-State
L–H Tri-State
L–H Tri-State
L–H Tri-State
None
L
X
L
L
None
L
H
H
X
L
None
X
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
X
X
L
X
Tri-State
Q
External
External
External
External
External
Next
L–H
Read Cycle, Begin Burst
L
L
L
H
X
L
L–H Tri-State
Write Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L–H
L–H
D
Q
Read Cycle, Begin Burst
L
L
L
H
H
H
H
H
H
L
Read Cycle, Begin Burst
L
L
L
H
L
L–H Tri-State
L–H
L–H Tri-State
L–H
L–H Tri-State
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L–H
L–H
L–H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L–H Tri-State
L–H
L–H Tri-State
Q
H
X
X
L–H
L–H
D
D
L
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks after the
X
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for
the remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 001-75380 Rev. *F
Page 10 of 33
CY7C1441AV25
CY7C1447AV25
Partial Truth Table for Read/Write
The partial truth table for read/write for CY7C1441AV25 follows. [6, 7]
Function (CY7C1441AV25)
GW
BWE
BWD
BWC
BWB
BWA
Read
Read
H
H
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
H
L
Write Byte A (DQA, DQPA)
Write Byte B(DQB, DQPB)
H
L
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
Write Byte C (DQC, DQPC)
L
H
H
L
H
L
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
L
L
H
L
Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB,
DQPA)
L
L
Write Byte D (DQD, DQPD)
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
L
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
L
Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
H
L
L
L
L
L
L
H
H
H
L
Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC,
DQPA)
Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
L
L
H
Write All Bytes
Write All Bytes
H
L
L
L
L
L
L
X
X
X
X
X
Partial Truth Table for Read/Write
The partial truth table for read/write for CY7C1447AV25 follows. [6, 8]
Function (CY7C1447AV25)
GW
H
BWE
BWx
Read
H
L
L
L
X
X
Read
H
All BW = H
Write Byte x – (DQx and DQPx)
Write All Bytes
H
L
All BW = L
X
H
Write All Bytes
L
Notes
6. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
7. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write is done based on which byte write is active.
X
8. BWx represents any byte write signal BW .To enable any byte write BW a logic LOW signal should be applied at clock rise. Any number of bye writes can be enabled
X
x,
at the same time for any given write.
Document Number: 001-75380 Rev. *F
Page 11 of 33
CY7C1441AV25
CY7C1447AV25
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1441AV25/CY7C1447AV25 incorporates a serial
boundary scan test access port (TAP). This part is fully compliant
with 1149.1. The TAP operates using JEDEC-standard 2.5 V I/O
logic level.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the Tap Controller Block Diagram on
page 15. On power up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
The
CY7C1441AV25/CY7C1447AV25 contains
a
TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor. TDO
must be left unconnected. On power up, the device comes up in
a reset state, which does not interfere with the operation of the
device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to allow fault
isolation of the board level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that is placed between the TDI and
TDO balls. This allows data to be shifted through the SRAM with
minimal delay. The bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This ball can be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state.
It is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions are used to
capture the contents of the I/O ring.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see Tap Controller State Diagram
on page 14. TDI is internally pulled up and can be unconnected
if the TAP is unused in an application. TDI is connected to the
most significant bit (MSB) of any register.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 18.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data out from the
registers. The output is active depending on the current state of
the TAP state machine (see Identification Codes on page 18).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Overview
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Eight different instructions are possible with the three bit
instruction register.All combinations are listed in the Identification
Codes on page 18. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Document Number: 001-75380 Rev. *F
Page 12 of 33
CY7C1441AV25
CY7C1447AV25
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
IDCODE
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
The IDCODE instruction causes a vendor specific, 32-bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
The IDCODE instruction is loaded into the instruction register on
power up or whenever the TAP controller is given a test logic
reset state.
SAMPLE Z
EXTEST
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High Z state until the next command is given
during the “Update IR” state.
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the Shift-DR controller state.
SAMPLE/PRELOAD
EXTEST OUTPUT BUS TRI-STATE
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #138
(for 209-ball FBGA package). When this scan cell, called the
“extest output bus tri-state”, is latched into the preload register
during the Update-DR state in the TAP controller, it directly
controls the state of the output (Q-bus) pins when the EXTEST
is entered as the current instruction. When HIGH, it enables the
output buffers to drive the output bus. When LOW, this bit places
the output bus into a High Z condition.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output may undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
This bit can be set by entering the SAMPLE/PRELOAD, or
EXTEST command and then shifting the desired bit into that cell
during the Shift-DR state. During Update-DR, the value loaded
into that shift register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up and also when the TAP
controller is in the Test-Logic-Reset” state.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
When the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Document Number: 001-75380 Rev. *F
Page 13 of 33
CY7C1441AV25
CY7C1447AV25
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
1
0
PAUSE-IR
1
0
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 001-75380 Rev. *F
Page 14 of 33
CY7C1441AV25
CY7C1447AV25
TAP Controller Block Diagram
TAP Timing
Figure 3. TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Document Number: 001-75380 Rev. *F
Page 15 of 33
CY7C1441AV25
CY7C1447AV25
TAP AC Switching Characteristics
Over the Operating Range
Parameter [9, 10]
Clock
Parameter
Min
Max
Unit
tTCYC
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
–
–
20
–
ns
MHz
ns
tTF
tTH
20
20
tTL
–
ns
Output Times
tTDOV
tTDOX
Setup Times
tTMSS
tTDIS
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
–
0
10
–
ns
ns
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture SetUp to TCK Rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture Hold after Clock Rise
Notes
9.
t
and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS CH
10. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document Number: 001-75380 Rev. *F
Page 16 of 33
CY7C1441AV25
CY7C1447AV25
2.5 V TAP AC Test Conditions
2.5 V TAP AC Output Load Equivalent
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall time ....................................................1 ns
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage .......................... 1.25 V
1.25V
50Ω
TDO
ZO = 50Ω
20p F
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 2.5 V ± 0.125 V unless otherwise noted)
Parameter [11]
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Description
IOH = –1.0 mA
Conditions
VDDQ = 2.5 V
Min
Max
Unit
V
VOH1
VOH2
VOL1
VOL2
VIH
2.0
2.1
–
–
IOH = –100 µA
IOL = 1.0 mA
IOL = 100 µA
VDDQ = 2.5 V
VDDQ = 2.5 V
VDDQ = 2.5 V
VDDQ = 2.5 V
VDDQ = 2.5 V
–
0.4
V
V
–
0.2
V
1.7
–0.3
–5
VDD + 0.3
0.7
V
VIL
V
IX
GND < VIN < VDDQ
5
µA
Note
11. All voltages referenced to V (GND).
SS
Document Number: 001-75380 Rev. *F
Page 17 of 33
CY7C1441AV25
CY7C1447AV25
Identification Register Definitions
Bit Configuration
Bit Configuration
Instruction Field
Description
CY7C1441AV25 (1M × 36) CY7C1447AV25 (512K × 72)
Revision Number (31:29)
Device Depth (28:24)
000
000
Describes the version number.
Reserved for internal use.
01011
000001
01011
000001
Architecture and Memory Type
(23:18)
Defines memory type and
architecture.
Bus Width and Density (17:12)
Cypress JEDEC ID Code (11:1)
100111
110111
Defines width and density.
00000110100
00000110100
Allows unique identification of
SRAM vendor.
ID Register Presence Indicator (0)
1
1
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size (× 36)
Bit Size (× 72)
Instruction Bypass
3
1
3
1
Bypass
ID
32
89
–
32
–
Boundary Scan Order (165-ball FBGA package)
Boundary Scan Order (209-ball FBGA package)
138
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a High Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document Number: 001-75380 Rev. *F
Page 18 of 33
CY7C1441AV25
CY7C1447AV25
Boundary Scan Order
165-ball FBGA [12, 13]
CY7C1441AV25 (1M × 36)
Bit #
1
Ball ID
Bit #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Ball ID
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
A9
Bit #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Ball ID
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
Bit #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
N1
N6
N7
2
N2
3
N10
P11
P8
P1
4
R1
5
R2
6
R8
P3
7
R9
R3
8
P9
P2
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
R4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P4
G1
D2
E2
F2
N5
P6
B9
R6
C10
A8
Internal
G2
H1
H3
J1
B8
A7
B7
B6
K1
L1
A6
M1
J2
B5
A5
A4
B4
B3
H10
G11
F11
K2
L2
M2
Notes
12. Balls which are NC (No Connect) are preset LOW.
13. Bit# 89 is preset HIGH.
Document Number: 001-75380 Rev. *F
Page 19 of 33
CY7C1441AV25
CY7C1447AV25
Boundary Scan Order
209-ball FBGA [14, 15]
CY7C1447AV25 (512K × 72)
Bit #
1
Ball ID
Bit #
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Ball ID
F6
Bit #
71
Ball ID
Bit #
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
Ball ID
K3
W6
V6
H6
C6
B6
A6
A5
B5
C5
D5
D4
C4
A4
B4
C3
B3
A3
A2
A1
B2
B1
C2
C1
D2
D1
E1
E2
F2
F1
G1
G2
H2
H1
J2
2
K8
72
K4
3
U6
K9
73
K6
4
W7
V7
K10
J11
J10
H11
H10
G11
G10
F11
F10
E10
E11
D11
D10
C11
C10
B11
B10
A11
A10
C9
74
K2
5
75
L2
6
U7
76
L1
7
T7
77
M2
M1
N2
N1
P2
8
V8
78
9
U8
79
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
T8
80
V9
81
U9
82
P1
P6
83
R2
R1
T2
W11
W10
V11
V10
U11
U10
T11
T10
R11
R10
P11
P10
N11
N10
M11
M10
L11
L10
K11
M6
84
85
86
T1
87
U2
U1
V2
88
89
90
V1
91
W2
W1
T6
92
93
B9
94
U3
V3
A9
95
D7
96
T4
C8
97
T5
B8
98
U4
V4
A8
99
D8
100
101
102
103
104
105
5W
5V
C7
B7
5U
Internal
A7
J1
L6
D6
K1
N6
J6
G6
Notes
14. Balls which are NC (No Connect) are preset LOW.
15. Bit# 138 is preset HIGH.
Document Number: 001-75380 Rev. *F
Page 20 of 33
CY7C1441AV25
CY7C1447AV25
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ..........................> 2001 V
Storage Temperature ............................... –65 °C to +150 °C
Latch Up Current ...................................................> 200 mA
Ambient Temperature
with Power Applied .................................. –55 °C to +125 °C
Operating Range
Supply Voltage on VDD Relative to GND .....–0.3 V to +3.6 V
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
Ambient
Temperature
Range
VDD
VDDQ
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
Industrial
–40 °C to +85 °C 2.5 V+ 5% 1.7 V to VDD
Electrical Characteristics
Over the Operating Range
Parameter[16, 17]
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min
2.375
2.375
2.0
Max
2.625
2.625
–
Unit
V
VDD
VDDQ
VOH
VOL
VIH
for 2.5 V I/O
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage [16]
Input LOW Voltage [16]
for 2.5 V I/O, IOH = –1.0 mA
for 2.5 V I/O, IOL = 1.0 mA
for 2.5 V I/O
V
–
0.4
V
1.7
VDD + 0.3
0.7
V
VIL
for 2.5 V I/O
–0.3
–5
V
IX
Input Leakage Current except ZZ GND VI VDDQ
and MODE
5
A
Input Current of MODE
Input = VSS
–30
–
–
5
A
A
A
A
A
mA
Input = VDD
Input Current of ZZ
Input = VSS
–5
–
–
Input = VDD
30
5
IOZ
IDD
Output Leakage Current
GND VI VDDQ, Output Disabled
–5
–
VDD Operating Supply Current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5 ns cycle,
133 MHz
270
ISB1
ISB2
ISB3
ISB4
Automatic CE Power Down
Current – TTL Inputs
Max VDD, Device Deselected,
7.5 ns cycle,
133 MHz
–
–
–
–
150
120
150
135
mA
mA
mA
mA
VIN VIH or VIN VIL, f = fMAX
,
Inputs Switching
Automatic CE Power Down
Current – CMOS Inputs
Max VDD, Device Deselected,
VIN VDD – 0.3 V or VIN 0.3 V, 133 MHz
f = 0, Inputs Static
7.5 ns cycle,
Automatic CE Power Down
Current – CMOS Inputs
Max VDD, Device Deselected,
VIN VDDQ – 0.3 V or VIN 0.3 V, 133 MHz
f = fMAX, Inputs Switching
7.5 ns cycle,
Automatic CE Power Down
Current – TTL Inputs
Max VDD, Device Deselected,
VIN VDD – 0.3 V or VIN 0.3 V, 133 MHz
f = 0, Inputs Static
7.5 ns cycle,
Notes
16. Overshoot: V
< V +1.5 V (Pulse width less than t
/2), undershoot: V
> –2 V (Pulse width less than t
/2).
CYC
IH(AC)
DD
CYC
IL(AC)
17. T
: Assumes a linear ramp from V to V
within 200 ms. During this time V < V and V
< V
.
Power-up
DD(min)
IH
DD
DDQ
DD
Document Number: 001-75380 Rev. *F
Page 21 of 33
CY7C1441AV25
CY7C1447AV25
Capacitance
165-ball FBGA 209-ball FBGA
Parameter [18]
Description
Input capacitance
Test Conditions
Unit
Max
Max
CIN
TA = 25 C, f = 1 MHz, VDD = 2.5 V,
VDDQ = 2.5 V
7
7
6
5
5
7
pF
pF
pF
CCLK
CI/O
Clock input capacitance
Input/Output capacitance
Thermal Resistance
165-ballFBGA 209-ballFBGA
Parameter [18]
Description
Test Conditions
Unit
Package
Package
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
20.8
25.31
°C/W
JC
Thermal resistance
(junction to case)
3.2
4.48
°C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
2.5 V I/O Test Load
R = 1667
2.5V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50
0
10%
L
GND
5 pF
INCLUDING
R = 1538
1 ns
1 ns
V = 1.25V
T
JIG AND
SCOPE
(a)
(b)
(c)
Note
18. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-75380 Rev. *F
Page 22 of 33
CY7C1441AV25
CY7C1447AV25
Switching Characteristics
Over the Operating Range
-133
Unit
Parameter [19, 20]
Description
VDD(typical) to the first access [21]
Min
Max
tPOWER
Clock
tCYC
1
–
ms
Clock cycle time
Clock HIGH
7.5
2.5
2.5
–
–
–
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCDV
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z [22, 23, 24]
–
2.5
2.5
–
6.5
–
ns
ns
ns
ns
ns
ns
ns
tDOH
tCLZ
–
tCHZ
Clock to high Z [22, 23, 24]
3.8
3.0
–
tOEV
OE LOW to output valid
–
tOELZ
tOEHZ
Setup Times
tAS
OE LOW to output low Z [22, 23, 24]
OE HIGH to output high Z [22, 23, 24]
0
–
3.0
Address setup before CLK rise
ADSP, ADSC setup before CLK rise
ADV setup before CLK rise
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BWX setup before CLK rise
Data input setup before CLK rise
Chip enable setup
tDS
tCES
Hold Times
tAH
Address hold after CLK rise
ADSP, ADSC hold after CLK rise
GW, BWE, BWX hold after CLK rise
ADV hold after CLK rise
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADH
tWEH
tADVH
tDH
Data input hold after CLK rise
Chip enable hold after CLK rise
tCEH
Notes
19. Timing reference level is 1.25 V when V
= 2.5 V.
DDQ
20. Test conditions shown in (a) of Figure 4 on page 22 unless otherwise noted.
21. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V
initially, before a read or write operation can
POWER
DD(minimum)
be initiated.
22. t
, t
, t
, and t
are specified with AC test conditions shown in part (b) of Figure 4 on page 22. Transition is measured ±200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
23. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
CLZ
OEHZ
OELZ
CHZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z prior to Low Z under the same system conditions.
24. This parameter is sampled and not 100% tested.
Document Number: 001-75380 Rev. *F
Page 23 of 33
CY7C1441AV25
CY7C1447AV25
Timing Diagrams
Figure 5. Read Cycle Timing [25]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
X
Deselect Cycle
t
t
CES
CEH
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2
+
1)
Q(A2
+
2)
Q(A2
+
3)
Q(A2)
Q(A2
+
1)
Q(A2
+
2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note
25. In this diagram, when CE is LOW: CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document Number: 001-75380 Rev. *F
Page 24 of 33
CY7C1441AV25
CY7C1447AV25
Timing Diagrams (continued)
Figure 6. Write Cycle Timing [26, 27]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BWX
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2
+
1)
D(A2
+
1)
D(A2
+
2)
D(A2
+
3)
D(A3)
D(A3
+
1)
D(A3 + 2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
DON’T CARE
UNDEFINED
Notes
26. In this diagram, when CE is LOW: CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
27.
Full width write is initiated by either GW LOW; or by GW HIGH, BWE LOW, and BW LOW.
X
Document Number: 001-75380 Rev. *F
Page 25 of 33
CY7C1441AV25
CY7C1447AV25
Timing Diagrams (continued)
Figure 7. Read/Write Cycle Timing [28, 29, 30]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
Back-to-Back READs
Single WRITE
BURST READ
DON’T CARE
UNDEFINED
Notes
28. In this diagram, when CE is LOW: CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
29.
30.
.
The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by
GW is HIGH.
ADSP or ADSC
Document Number: 001-75380 Rev. *F
Page 26 of 33
CY7C1441AV25
CY7C1447AV25
Timing Diagrams (continued)
Figure 8. ZZ Mode Timing [31, 32]
CLK
ZZ
t
t
ZZ
ZZREC
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
31. Device must be deselected when entering ZZ mode. See Truth Table on page 10 for all possible signal conditions to deselect the device.
32. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 001-75380 Rev. *F
Page 27 of 33
CY7C1441AV25
CY7C1447AV25
Ordering Information
Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
MPN
Package
Operating
Range
Ordering Code
Part and Package Type
Status Diagram
133 CY7C1441AV25-133BZXI [33]
NRND 51-85195 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
lndustrial
Ordering Code Definitions
CY
7
C 144X
A V25 -
I
X
XX
133
Temperature Grade:
I = Industrial
Pb-free
Package Type: XX = BZ
BZ = 165-ball FBGA
Speed Grade: 133 MHz
V25 = 2.5 V
Die Revision
Part Identifier: 144X = 1441
1441 = FT, 1M × 36 (36 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Note
33. This MPN is not recommended for new designs.
Document Number: 001-75380 Rev. *F
Page 28 of 33
CY7C1441AV25
CY7C1447AV25
Package Diagrams
Figure 9. 165-ball FBGA (15 × 17 × 1.40 mm) (0.50 Ball Diameter) Package Outline, 51-85195
51-85195 *D
Document Number: 001-75380 Rev. *F
Page 29 of 33
CY7C1441AV25
CY7C1447AV25
Package Diagrams (continued)
Figure 10. 209-ball FBGA (14 × 22 × 1.76 mm) BB209A Package Outline, 51-85167
51-85167 *C
Document Number: 001-75380 Rev. *F
Page 30 of 33
CY7C1441AV25
CY7C1447AV25
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CE
Chip Enable
Symbol
°C
Unit of Measure
CMOS
EIA
Complementary Metal Oxide Semiconductor
Electronic Industries Alliance
Fine-Pitch Ball Grid Array
Input/Output
degree Celsius
megahertz
microampere
milliampere
millimeter
millisecond
millivolt
MHz
µA
mA
mm
ms
mV
ns
FBGA
I/O
JEDEC
JTAG
OE
Joint Electron Devices Engineering Council
Joint Test Action Group
Output Enable
nanosecond
ohm
SRAM
TAP
Static Random Access Memory
Test Access Port
%
percent
TCK
TDI
Test Clock
pF
V
picofarad
volt
Test Data-In
TDO
TMS
TTL
Test Data-Out
W
watt
Test Mode Select
Transistor-Transistor Logic
Document Number: 001-75380 Rev. *F
Page 31 of 33
CY7C1441AV25
CY7C1447AV25
Document History Page
Document Title: CY7C1441AV25/CY7C1447AV25, 36-Mbit (1M × 36/512K × 72) Flow-Through SRAM
Document Number: 001-75380
Orig. of
Change
Rev.
ECN No.
Issue Date
Description of Change
**
3534404
3606230
02/28/2012
05/02/2012
GOPA
New data sheet.
*A
PRIT /
GOPA
Updated Features (Included CY7C1441AV25 related information).
Updated Functional Description (Included CY7C1441AV25 related
information).
Included Logic Block Diagram – CY7C1441AV25.
Updated Pin Configurations (Included CY7C1441AV25 related information,
included 165-ball FBGA package related information).
Updated Functional Overview (Included CY7C1441AV25 related information).
Updated Truth Table (Included CY7C1441AV25 related information).
Added Partial Truth Table for Read/Write (Corresponding to CY7C1441AV25).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Included
CY7C1441AV25 related information).
Updated Identification Register Definitions (Included CY7C1441AV25 related
information).
Updated Scan Register Sizes (Included 165-ball FBGA package related
information, added Bit Size (× 36) column).
Added Boundary Scan Order (Corresponding to CY7C1441AV25).
Updated Capacitance (Included 165-ball FBGA package related information).
Updated Thermal Resistance (Included 165-ball FBGA package related
information).
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams (Included 165-ball FBGA package related
information (spec 51-85165)).
*B
*C
*D
3925180
4575392
4675874
03/07/2013
11/20/2014
03/04/2015
PRIT
PRIT
PRIT
Updated Package Diagrams:
spec 51-85167 – Changed revision from *B to *C.
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
Removed spec 51-85165 *D.
Added spec 51-85195 *C.
Updated to new template.
*E
4908404
09/04/2015
PRIT
Removed 1.8 V TAP AC Test Conditions.
Removed 1.8 V TAP AC Output Load Equivalent.
Updated TAP DC Electrical Characteristics and Operating Conditions:
Removed details corresponding to Test Condition “VDDQ = 1.8 V” for all
parameters.
Updated Electrical Characteristics:
Removed details corresponding to Test Condition “for 1.8 V I/O” for all
parameters.
Updated Package Diagrams:
spec 51-85195 – Changed revision from *C to *D.
*F
5164560
03/07/2016
PRIT
Added watermark “Not Recommended for New Designs.” across the
document.
Updated Ordering Information:
No change in part numbers.
Added a column “MPN Status”.
Added Note 33 and referred the same note in “CY7C1441AV25-133BZXI”.
Updated to new template.
Completing Sunset Review.
Document Number: 001-75380 Rev. *F
Page 32 of 33
CY7C1441AV25
CY7C1447AV25
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
cypress.com/psoc
cypress.com/psoc
Automotive
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Clocks & Buffers
Interface
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Lighting & Power Control
Memory
Technical Support
cypress.com/support
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation 2012-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify
and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software
is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole
or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify
and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-75380 Rev. *F
Revised March 7, 2016
Page 33 of 33
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation.
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CYPRESS
CY7C1441AV33-100BZXI
Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
CYPRESS
CY7C1441AV33-133AXCT
Cache SRAM, 1MX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100
CYPRESS
CY7C1441AV33-133BZC
Cache SRAM, 1MX36, 6.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
CYPRESS
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