CY7C1441AV33-100BZC [CYPRESS]
Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165;
| 型号： | CY7C1441AV33-100BZC |
| 厂家： | 
CYPRESS |
| 描述： | Cache SRAM, 1MX36, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165 时钟 静态存储器 内存集成电路 |
| 文件： | 总31页 (文件大小：906K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
36-Mbit (1M x 36/2M x 18/512K x 72)
Flow-Through SRAM
Features
Functional Description
■ Supports 133-MHz bus operations
■ 1M x 36/2M x 18/512K x 72 common IO
■ 3.3V core power supply
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are
3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-through
SRAMs, respectively designed to interface with high-speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE1), depth-expansion Chip Enables (CE2 and
■ 2.5V or 3.3V IO power supply
■ Fast clock-to-output times
❐ 6.5 ns (133-MHz version)
■ Provide high-performance 2-1-1-1 access rate
■ User-selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BWx, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the ZZ
pin.
■ Separate processor and controller address strobes
■ Synchronous self-timed write
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows
either interleaved or linear burst sequences, selected by the
MODE input pin. A HIGH selects an interleaved burst sequence,
while a LOW selects a linear burst sequence. Burst accesses
can be initiated with the Processor Address Strobe (ADSP) or the
cache Controller Address Strobe (ADSC) inputs. Address
advancement is controlled by the Address Advancement (ADV)
input.
■ Asynchronous output enable
■ CY7C1441AV33, CY7C1443AV33 available in
JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and
non-lead-free 165-ball FBGA package. CY7C1447AV33
available in Pb-free and non-lead-free 209-ball FBGA package
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ “ZZ” Sleep Mode option
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
operates from a +3.3V core power supply while all outputs may
operate with either a +2.5 or +3.3V supply. All inputs and outputs
are JEDEC-standard JESD8-5-compatible.
Selection Guide
Description
Maximum Access Time
133 MHz
6.5
100 MHz
8.5
Unit
ns
Maximum Operating Current
310
290
mA
mA
Maximum CMOS Standby Current
120
120
Note
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05357 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 09, 2008
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Logic Block Diagram – CY7C1441AV33 (1M x 36)
ADDRESS
REGISTER
A0, A1,
A
A
[1:0]
MODE
ADV
CLK
Q1
Q0
BURST
COUNTER
AND LOGIC
CLR
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D, DQP D
DQ
BYTE
WRITE REGISTER
D, DQP D
BW
D
DQ
BYTE
WRITE REGISTER
C, DQP C
DQ
BYTE
WRITE REGISTER
C, DQP C
BW
C
OUTPUT
BUFFERS
DQ s
MEMORY
ARRAY
SENSE
AMPS
DQP
DQP
DQP
DQP
A
DQ
BYTE
WRITE REGISTER
B, DQP B
B
C
D
DQ
BYTE
WRITE REGISTER
B, DQP B
BW
B
DQ
BYTE
WRITE REGISTER
A, DQP A
DQ
A, DQPA
BW
A
BYTE
BWE
WRITE REGISTER
INPUT
GW
REGISTERS
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1443AV33 (2Mx 18)
ADDRESS
REGISTER
A0,A1,A
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B,DQP B
DQ
B,DQP B
WRITE DRIVER
WRITE REGISTER
BW
B
MEMORY
ARRAY
OUTPUT
BUFFERS
DQs
DQP
DQP
SENSE
AMPS
A
B
DQ
A,DQP A
DQ A,DQP A
WRITE REGISTER
WRITE DRIVER
BW
A
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE
CE
1
2
3
CE
OE
SLEEP
CONTROL
ZZ
Document #: 38-05357 Rev. *G
Page 2 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Logic Block Diagram – CY7C1447AV33 (512K x 72)
ADDRESS
REGISTER
A0, A1,A
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER
AND LOGIC
CLR
Q0
ADSC
ADSP
DQ
H
,
DQP
H
DQ
H, DQPH
BW
BW
H
G
WRITE REGISTER
WRITE DRIVER
DQ
G, DQPG
DQ
F, DQPF
WRITE DRIVER
WRITE REGISTER
DQ
F, DQPF
DQ
F, DQPF
BW
BW
BW
BW
F
E
WRITE DRIVER
WRITE REGISTER
DQ E
E
,
DQP
DQ
E, DQPE
WRITE DRIVER
WRITE REGISTER
MEMORY
ARRAY
DQ
D, DQPD
DQ
D, DQPD
D
WRITE REGISTER
WRITE DRIVER
DQ
C, DQPC
DQ
C, DQPC
C
WRITE DRIVER
WRITE REGISTER
OUTPUT
BUFFERS
DQs
SENSE
AMPS
DQP
DQP
DQP
DQP
DQP
DQP
DQP
DQP
A
B
C
D
E
DQ
B, DQPB
DQ
B, DQPB
WRITE DRIVER
BW
BW
B
WRITE REGISTER
DQ
A, DQPA
F
DQ A, DQPA
WRITE REGISTER
WRITE DRIVER
G
H
A
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
Document #: 38-05357 Rev. *G
Page 3 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Pin Configurations
Figure 1. 100-Pin TQFP Pinout
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQC
VDDQ
VSSQ
DQC
3
4
5
6
DQC
7
NC
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
DQC
9
10
11
9
VSSQ
VDDQ
DQC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
12
DQC
13
NC
14
VDD
15
NC
VDD
ZZ
CY7C1443AV33
(2M x 18)
CY7C1441AV33
(1Mx 36)
NC
16
VDD
ZZ
VSS
17
DQD
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
20
21
VDDQ
VSSQ
DQD
22
DQD
23
DQD
24
DQD
25
26
27
NC
VSSQ
VDDQ
DQD
DQD
29
VSSQ
VDDQ
NC
NC
NC
VSSQ
VDDQ
NC
NC
NC
28
DQPD
30
Document #: 38-05357 Rev. *G
Page 4 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Pin Configurations (continued)
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1441AV33 (1M x 36)
1
2
A
3
CE1
4
BWC
5
BWB
6
CE3
7
8
9
ADV
10
A
11
NC
NC/288M
NC/144M
DQPC
BWE
GW
VSS
VSS
ADSC
A
B
C
D
A
CE2
VDDQ
VDDQ
BWD
VSS
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
ADSP
VDDQ
VDDQ
A
NC/576M
DQPB
DQB
NC
DQC
NC/1G
DQB
DQC
VDD
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
NC/72M
TDI
A1
TDO
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
CY7C1443AV33 (2M x 18)
1
2
A
3
CE1
4
BWB
5
NC
6
CE3
7
8
9
ADV
10
A
11
A
NC/288M
NC/144M
NC
BWE
GW
VSS
VSS
ADSC
A
B
C
D
A
CE2
VDDQ
VDDQ
NC
VSS
VDD
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
ADSP
VDDQ
VDDQ
A
NC/576M
DQPA
DQA
NC
NC/1G
NC
NC
DQB
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
DQA
DQA
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
V
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
DD
NC
VDD
VDD
VDD
VSS
A
NC
K
L
NC
NC
DQB
DQPB
NC
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
NC/72M
TDI
A1
TDO
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05357 Rev. *G
Page 5 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Pin Configurations (continued)
209-ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1447AV33 (512K × 72)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
DQG
DQG
DQG
DQG
A
CE2
A
DQB
DQB
DQB
ADSP ADSC
ADV
A
CE3
DQB
DQB
BWSB
NC288M
NC/144M
BWSC
BWSH
VSS
BW
BWSF
BWSA
VSS
BWSG
BWSD
DQG
DQG
DQG
DQG
NC/576M
GW
BWSE
NC
CE1
DQB
DQB
NC/1G OE
NC
DQB
DQPG DQPC
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
VDD
VSS
VDD
DQPF DQPB
DQC
DQC
DQF
DQF
VSS
VDDQ
VSS
NC
NC
NC
NC
VSS
NC
NC
VSS
G
H
J
DQC
DQC
DQC
VDDQ
VSS
VDDQ
VSS
DQF
DQF
DQF
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
A
DQC
DQC
NC
DQF
DQF
NC
VDDQ
DQC
NC
VDDQ
VDDQ
CLK
VDDQ
NC
DQF
NC
K
L
NC
NC
DQH
DQH
DQH
VDDQ
VSS
VDDQ
VSS
VDDQ
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
DQA
DQA
DQA
M
N
P
R
T
VSS
VDDQ
VSS
VDDQ
NC
DQH
DQH
DQH
VSS
VDD
VSS
DQA
DQA
DQA
VDDQ
DQH
DQH
DQPD
DQD
DQD
NC
ZZ
DQA
DQA
DQPA
DQE
DQE
VSS
VDDQ
VSS
A
VDDQ
VDD
NC
A
DQPH
DQD
DQD
DQD
DQD
VDDQ
VDD
DQPE
DQE
DQE
DQE
DQE
VSS
NC
A
MODE
A
U
V
W
A
NC/72M
A
A
A1
A
DQD
DQD
A
A
A
A
DQE
DQE
TDI
TDO
TCK
A0
A
TMS
Document #: 38-05357 Rev. *G
Page 6 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Pin Definitions
Name
IO
Description
A0, A1, A
Input-
Synchronous
Address Inputs Used to Select One of the Address Locations. Sampled
at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2,
and CE3 are sampled active. A[1:0] feed the 2-bit counter.
BWA, BWB
BWC, BWD,
BWE, BWF,
BWG, BWH
Input-
Synchronous
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.
GW
CLK
CE1
Input-
Synchronous
Global Write Enable Input, Active LOW. When asserted LOW on the rising
edge of CLK, a global write is conducted (ALL bytes are written, regardless
of the values on BWX and BWE).
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
Input-
Synchronous
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE2 and CE3 to select/deselect the device. ADSP is
ignored if CE1 is HIGH. CE1 is sampled only when a new external address is
loaded.
CE2
CE3
Input-
Synchronous
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled
only when a new external address is loaded.
Input-
Synchronous
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE2 to select/deselect the device. CE3 is
assumed active throughout this document for BGA. CE3 is sampled only when
a new external address is loaded.
OE
Input-
Asynchronous
Output Enable, Asynchronous Input, Active LOW. Controls the direction
of the IO pins. When LOW, the IO pins behave as outputs. When deasserted
HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during
the first clock of a read cycle when emerging from a deselected state.
ADV
Input-
Synchronous
Advance Input Signal, Sampled on the Rising Edge of CLK. When
asserted, it automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, Sampled on the Rising Edge of CLK,
Active LOW. When asserted LOW, addresses presented to the device are
captured in the address registers. A[1:0] are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP
is ignored when
CE1 is deasserted HIGH
ADSC
Input-
Synchronous
Address Strobe from Controller, Sampled on the Rising Edge of CLK,
Active LOW. When asserted LOW, addresses presented to the device are
captured in the address registers. A[1:0] are also loaded into the burst counter.
.
When ADSP and ADSC are both asserted, only ADSP is recognized
BWE
ZZ
Input-
Synchronous
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK.
This signal must be asserted LOW to conduct a byte write.
Input-
Asynchronous
ZZ “sleep” Input, Active HIGH. When asserted HIGH places the device in
a non-time-critical “sleep” condition with data integrity preserved. For normal
operation, this pin must be LOW or left floating. ZZ pin has an internal pull
down.
Document #: 38-05357 Rev. *G
Page 7 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Pin Definitions (continued)
Name
IO
Description
IO-
Bidirectional Data IO lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by the addresses presented during
the previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH,
DQs and DQPX are placed in a tri-state condition.The outputs are automati-
cally tri-stated during the data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
DQs
Synchronous
IO-
Bidirectional Data Parity IO Lines. Functionally, these signals are identical
to DQs. During write sequences, DQPx is controlled by BW[A:H] correspond-
ingly.
DQPX
Synchronous
MODE
Input-Static
Selects Burst Order. When tied to GND selects linear burst sequence. When
tied to VDD or left floating selects interleaved burst sequence. This is a strap
pin and should remain static during device operation. Mode Pin has an internal
pull up.
VDD
Power Supply
IO Power Supply
Ground
Power Supply Inputs to the Core of the Device.
Power Supply for the IO Circuitry.
Ground for the Core of the Device.
Ground for the IO Circuitry.
VDDQ
VSS
VSSQ
TDO
IO Ground
JTAG serial output
Synchronous
Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of
TCK. If the JTAG feature is not being utilized, this pin should be left uncon-
nected. This pin is not available on TQFP packages.
TDI
JTAG serial
input
Synchronous
Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If
the JTAG feature is not being utilized, this pin can be left floating or connected
to VDD through a pull up resistor. This pin is not available on TQFP packages.
TMS
TCK
NC
JTAG serial
input
Synchronous
Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If
the JTAG feature is not being utilized, this pin can be disconnected or
connected to VDD. This pin is not available on TQFP packages.
JTAG-Clock
Clock Input to the JTAG Circuitry. If the JTAG feature is not being utilized,
this pin must be connected to VSS. This pin is not available on TQFP
packages.
-
-
No Connects. Not internally connected to the die. 72M, 144M and 288M are
address expansion pins are not internally connected to the die.
NC/72M, NC/144M,
NC/288M, NC/576M
NC/1G
No Connects. Not internally connected to the die. NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins are not internally
connected to the die.
Document #: 38-05357 Rev. *G
Page 8 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Single Write Accesses Initiated by ADSC
Functional Overview
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (tCDV) is 6.5 ns (133-MHz device).
The
CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
supports secondary cache in systems utilizing either a linear or
interleaved burst sequence. The interleaved burst order
supports Pentium and i486™ processors. The linear burst
sequence is suited for processors that utilize a linear burst
sequence. The burst order is user-selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the Processor Address Strobe (ADSP) or the Controller
Address Strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQS is written into the
specified address location. Byte writes are allowed. All IOs are
tri-stated when a write is detected, even a byte write. Since this
is a common IO device, the asynchronous OE input signal must
be deasserted and the IOs must be tri-stated prior to the presen-
tation of data to DQs. As a safety precaution, the data lines are
tri-stated once a write cycle is detected, regardless of the state
of OE.
Burst Sequences
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWx) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
provides an on-chip two-bit wraparound burst counter inside the
SRAM. The burst counter is fed by A[1:0], and can follow either a
linear or interleaved burst order. The burst order is determined
by the state of the MODE input. A LOW on MODE selects a linear
burst sequence. A HIGH on MODE selects an interleaved burst
order. Leaving MODE unconnected causes the device to default
to a interleaved burst sequence.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1 is
HIGH.
Interleaved Burst Address Table
Single Read Accesses
(MODE = Floating or V )
DD
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP or ADSC is asserted LOW (if the access is
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter/control
logic and presented to the memory core. If the OE input is
asserted LOW, the requested data is available at the data
outputs a maximum to tCDV after clock rise. ADSP is ignored if
CE1 is HIGH.
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active,
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BWX)are ignored during this first clock cycle. If the write
inputs are asserted active (see Write Cycle Descriptions table for
appropriate states that indicate a write) on the next clock rise, the
appropriate data is latched and written into the device. Byte
writes are allowed. All IOs are tri-stated during a byte write.Since
this is a common IO device, the asynchronous OE input signal
must be deasserted and the IOs must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless of
the state of OE.
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
CE3, ADSP, and ADSC must remain inactive for the duration of
tZZREC after the ZZ input returns LOW.
Document #: 38-05357 Rev. *G
Page 9 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
ZZ > VDD – 0.2V
Min.
Max.
100
Unit
mA
ns
tZZS
ZZ > VDD – 0.2V
2tCYC
tZZREC
tZZI
ZZ recovery time
ZZ < 0.2V
2tCYC
0
ns
2tCYC
ZZ active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
ns
tRZZI
ns
Truth Table
tThe truth table for CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 follows.[2, 3, 4, 5, 6]
ADDRESS
Cycle Description
CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Used
None
None
None
None
None
None
Deselected Cycle, Power down
Deselected Cycle, Power down
Deselected Cycle, Power down
Deselected Cycle, Power down
Deselected Cycle, Power down
Sleep Mode, Power down
H
L
X
L
X
X
H
X
X
X
L
L
L
L
L
H
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L
X
L
L
L
H
H
X
X
X
X
X
L
X
X
Tri-State
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
External
External
External
External
External
Next
L
L
H
H
H
H
H
X
X
X
L
L
L
L
L
X
X
X
L
L
L
L
L
L
L
L
L
L
X
X
L
X
X
X
X
X
L
X
X
L
L
H
X
L
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Q
Tri-State
L
H
H
H
H
H
X
D
Q
L
L
H
H
H
H
H
Tri-State
L
L
H
L
X
X
H
H
H
H
Q
Tri-State
Next
L
H
L
Next
L
Q
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Next
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
X
H
X
H
H
X
X
H
X
H
H
H
H
H
H
H
H
H
L
L
H
L
H
X
X
L
L-H Tri-State
Next
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H Tri-State
L-H
L-H Tri-State
Q
H
X
X
L-H
L-H
D
D
L
Notes
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks after
X
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care
for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05357 Rev. *G
Page 10 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Partial Truth Table for Read/Write
Function (CY7C1441AV33)[2, 7]
GW
H
BWE
BWD
X
BWC
X
BWB
X
BWA
X
Read
H
L
L
L
L
L
L
L
L
Read
H
H
H
H
H
Write Byte A (DQA, DQPA)
Write Byte B(DQB, DQPB)
H
H
H
H
L
H
H
H
L
H
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
Write Byte C (DQC, DQPC)
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
H
H
H
L
L
H
H
L
H
H
H
H
L
H
L
H
H
L
L
H
Write Bytes C, B, A (DQC, DQB, DQA, DQPC,
DQPB, DQPA)
H
H
L
L
L
Write Byte D (DQD, DQPD)
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
L
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
L
Write Bytes D, B, A (DQD, DQB, DQA, DQPD,
DQPB, DQPA)
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
H
L
L
L
L
L
L
H
H
H
L
Write Bytes D, B, A (DQD, DQC, DQA, DQPD,
DQPC, DQPA)
Write Bytes D, C, A (DQD, DQB, DQA, DQPD,
DQPB, DQPA)
H
L
L
L
L
H
Write All Bytes
Write All Bytes
H
L
L
L
L
L
L
X
X
X
X
X
Truth Table for Read/Write
Function (CY7C1443AV33)[2]
Read
GW
H
BWE
BWB
X
BWA
H
L
L
L
L
X
X
H
L
Read
H
H
Write Byte A - (DQA and DQPA)
Write Byte B - (DQB and DQPB)
Write All Bytes
H
H
H
L
H
L
H
L
Write All Bytes
L
X
X
Truth Table for Read/Write
Function (CY7C1447AV33)[2, 8]
GW
H
BWE
BWX
Read
H
L
L
L
X
X
Read
H
All BW = H
Write Byte x – (DQx and DQPx)
Write All Bytes
H
L
All BW = L
X
H
Write All Bytes
L
Notes
7. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid Appropriate write is done based on which byte write is active.
X
8. BWx represents any byte write signal BW
.To enable any byte write BW a Logic LOW signal should be applied at clock rise.Any number of bye writes can be
[A..H]
x,
enabled at the same time for any given write.
Document #: 38-05357 Rev. *G
Page 11 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 incor-
porates a serial boundary scan test access port (TAP). This part
is fully compliant with 1149.1. The TAP operates using
JEDEC-standard 3.3V or 2.5V IO logic levels.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an appli-
cation. TDI is connected to the most significant bit (MSB) of any
register. (See Tap Controller Block Diagram.)
The
CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull up resistor. TDO should be
left unconnected. Upon power up, the device comes up in a reset
state which does not interfere with the operation of the device.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register. (See Tap Controller State Diagram.)
TAP Controller State Diagram
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
TEST-LOGIC
1
RESET
0
1
1
1
RUN-TEST/
IDLE
SELECT
SELECT
0
DR-SCAN
IR-SCAN
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
1
1
CAPTURE-DR
CAPTURE-IR
0
0
0
0
SHIFT-DR
0
SHIFT-IR
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
1
1
EXIT1-DR
EXIT1-IR
1
1
EXIT1-DR
EXIT1-IR
0
0
0
0
PAUSE-DR
1
0
PAUSE-IR
1
0
PAUSE-DR
1
0
PAUSE-IR
1
0
0
0
EXIT2-DR
1
EXIT2-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
UPDATE-DR
UPDATE-IR
1
0
1
0
1
0
1
0
Performing a TAP Reset
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Test Access Port (TAP)
At power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
TAP Registers
Registers are connected between the TDI and TDO balls and
scan data into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction register.
Data is serially loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
Document #: 38-05357 Rev. *G
Page 12 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Instruction Register
IDCODE
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the Tap Controller Block Diagram.
Upon power up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO balls and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High-Z state until the next command is given during the
“Update IR” state.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This shifts data through the SRAM with
minimal delay. The bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
The boundary scan register is loaded with the contents of the
RAM IO ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the IO ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions
table.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells prior to the selection
of another boundary scan test operation.
TAP Instruction Set
Overview
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data can be shifted in.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in this section in detail.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller must be
moved into the Update-IR state.
Document #: 38-05357 Rev. *G
Page 13 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
EXTEST
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High-Z condition.
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the shift-DR controller state.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is pre-set HIGH
to enable the output when the device is powered-up, and also
when the TAP controller is in the “Test-Logic-Reset” state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #89
(for 165-FBGA package) or bit #138 (for 209-FBGA package).
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the “Update-DR” state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Document #: 38-05357 Rev. *G
Page 14 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
TAP AC Switching Characteristics
Over the Operating Range[9, 10]
Parameter
Clock
tTCYC
tTF
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
tTH
20
20
tTL
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
10
ns
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
Setup Times
tTMSS
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tTDIH
tCH
Capture Hold after Clock Rise
Notes
9.
t
and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS CH
10. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document #: 38-05357 Rev. *G
Page 15 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels.................................................VSS to 3.3V
Input rise and fall times....................................................1 ns
Input timing reference levels........................................... 1.5V
Output reference levels .................................................. 1.5V
Test load termination supply voltage .............................. 1.5V
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels......................................... 1.25V
Output reference levels ................................................ 1.25V
Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO = 50Ω
ZO = 50Ω
20p F
20p F
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)[11]
Parameter
VOH1
Description
Description
Conditions
VDDQ = 3.3V
Min.
2.4
2.0
2.9
2.1
Max.
Unit
V
Output HIGH Voltage IOH = –4.0 mA
IOH = –1.0 mA
VDDQ = 2.5V
VDDQ = 3.3V
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage IOH = –100 µA
V
VDDQ = 2.5V
V
Output LOW Voltage IOL = 8.0 mA
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
0.4
0.4
V
I
OL = 1.0 mA
V
Output LOW Voltage IOL = 100 µA
0.2
V
0.2
V
Input HIGH Voltage
2.0
1.7
VDD + 0.3
VDD + 0.3
0.8
V
V
DDQ = 2.5V
VDDQ = 3.3V
DDQ = 2.5V
V
VIL
Input LOW Voltage
–0.3
–0.3
–5
V
V
0.7
V
IX
Input Load Current
GND < VIN < VDDQ
5
µA
Note
11. All voltages referenced to V (GND).
SS
Document #: 38-05357 Rev. *G
Page 16 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Identification Register Definitions
CY7C1441AV33 CY7C1443AV33 CY7C1447AV33
Instruction Field
(1M x 36)
Description
(2M x 18)
(512K x 72)
Revision Number (31:29)
Device Depth (28:24)
000
000
000
Describes the version number.
Reserved for Internal Use
01011
000001
01011
01011
Architecture/Memory
Type(23:18)[12]
000001
000001
Defines memory type and architecture
Bus Width/Density(17:12)
100111
010111
110111
Defines width and density
Cypress JEDEC ID Code (11:1)
00000110100
00000110100
00000110100 Allows unique identification of SRAM
vendor.
ID Register Presence Indicator (0)
1
1
1
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Bit Size (x18)
Instruction
3
3
3
Bypass
ID
1
32
89
-
1
32
89
-
1
32
-
Boundary Scan Order (165-ball FBGA package)
Boundary Scan Order (209-ball FBGA package)
138
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures IO ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: 38-05357 Rev. *G
Page 17 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
165-ball FBGA Boundary Scan Order[13,14]
CY7C1441AV33 (1M x 36), CY7C1443AV33 (2M x 18)
Bit #
1
Ball ID
Bit #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Ball ID
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
A9
Bit #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Ball ID
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
Bit #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
N1
N6
N7
N10
P11
P8
2
N2
3
P1
4
R1
5
R2
6
R8
P3
7
R9
R3
8
P9
P2
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
R4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P4
G1
D2
E2
F2
N5
P6
B9
R6
C10
A8
Internal
G2
H1
H3
J1
B8
A7
B7
B6
K1
L1
A6
M1
J2
B5
A5
A4
B4
B3
H10
G11
F11
K2
L2
M2
Notes
13. Balls which are NC (No Connect) are preset LOW.
14. Bit# 89 is preset HIGH.
Document #: 38-05357 Rev. *G
Page 18 of 31
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CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-up Current..................................................... >200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND ........–0.3V to +4.6V
Supply Voltage on VDDQ Relative to GND...... –0.3V to +VDD
Ambient
Temperature
Range
VDD
VDDQ
Commercial
Industrial
0°C to +70°C 3.3V –5%/+10% 2.5V –5%
DC Voltage Applied to Outputs
in Tri-State ...........................................–0.5V to VDDQ + 0.5V
to VDD
–40°C to +85°C
Electrical Characteristics Over the Operating Range[15, 16]
DC Electrical Characteristics Over the Operating Range
Parameter
Description
Power Supply Voltage
IO Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
Unit
V
V
3.6
DD
V
V
V
V
V
I
for 3.3V IO
for 2.5V IO
V
V
DDQ
DD
2.625
V
Output HIGH Voltage
Output LOW Voltage
for 3.3V IO, I = –4.0 mA
V
OH
OL
IH
OH
for 2.5V IO, I = –1.0 mA
2.0
V
OH
for 3.3V IO, I = 8.0 mA
0.4
0.4
V
OL
for 2.5V IO, I = 1.0 mA
V
OL
[15]
Input HIGH Voltage
for 3.3V IO
for 2.5V IO
for 3.3V IO
for 2.5V IO
GND ≤ V ≤ V
2.0
1.7
V
V
+ 0.3V
V
DD
DD
+ 0.3V
V
[15]
Input LOW Voltage
–0.3
–0.3
–5
0.8
V
IL
0.7
5
V
Input Leakage Current
except ZZ and MODE
μA
X
I
DDQ
Input Current of MODE
Input = V
Input = V
Input = V
Input = V
–30
–5
μA
μA
μA
μA
μA
mA
mA
mA
SS
DD
SS
DD
5
Input Current of ZZ
30
5
I
I
Output Leakage Current
GND ≤ V ≤ V
Output Disabled
–5
OZ
I
DDQ,
V
Operating Supply
V
= Max., I
= 0 mA,
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
All Speeds
310
290
180
DD
DD
DD
OUT
= 1/t
MAX CYC
Current
f = f
I
I
I
I
Automatic CE
Max. V , Device Deselected,
DD
SB1
Power down
V ≥ V or V ≤ V , f = f
IN IH IN IL MAX,
Current—TTL Inputs
inputs switching
Automatic CE
Max. V , Device Deselected,
All speeds
All Speeds
All Speeds
120
180
135
mA
mA
mA
SB2
SB3
SB4
DD
Power down
V ≥ V – 0.3V or V ≤ 0.3V,
IN DD IN
Current—CMOS Inputs
f = 0, inputs static
Automatic CE
Max. V , Device Deselected,
DD
Power down
V
≥ V
– 0.3V or V ≤ 0.3V,
DDQ IN
IN
Current—CMOS Inputs
f = f
, inputs switching
MAX
Automatic CE
Max. V , Device Deselected,
DD
Power down
V ≥ V – 0.3V or V ≤ 0.3V,
IN DD IN
Current—TTL Inputs
f = 0, inputs static
Notes
15. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t /2).
CYC
IH
DD
CYC
IL
16. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
Power-up
DD
IH
DD
DDQ DD.
Document #: 38-05357 Rev. *G
Page 19 of 31
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CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Capacitance
Parameter[17]
100 TQFP
Max.
165 FBGA 209 FBGA
Description
Test Conditions
Unit
Max.
Max.
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
6.5
3
7
7
6
5
5
7
pF
pF
pF
V
DD = 3.3V
CCLK
CIO
Clock Input Capacitance
Input/Output Capacitance
VDDQ = 2.5V
5.5
Thermal Resistance
100 TQFP
Package
165 FBGA 209 FBGA
Parameter[17]
Description
Test Conditions
Unit
Package
Package
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA/JESD51.
25.21
20.8
25.31
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
2.28
3.2
4.48
°C/W
Figure 2. AC Test Loads and Waveforms
3.3V IO Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
GND
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
V = 1.5V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V IO Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R = 1538Ω
≤ 1 ns
≤ 1 ns
V = 1.25V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note
17. Tested initially and after any design or process change that may affect these parameters
Document #: 38-05357 Rev. *G
Page 20 of 31
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CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Switching Characteristics
Over the Operating Range[22, 23]
–133
–100
Description
Unit
Parameter
Min.
Max.
Min.
Max.
tPOWER
Clock
tCYC
VDD (Typical) to the first Access[18]
1
1
ms
Clock Cycle Time
Clock HIGH
7.5
2.5
2.5
10
3.0
3.0
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCDV
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[19, 20, 21]
6.5
8.5
ns
ns
ns
ns
ns
ns
ns
tDOH
2.5
2.5
2.5
2.5
0
tCLZ
tCHZ
Clock to High-Z[19, 20, 21]
3.8
3.0
4.5
3.8
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
Setup Times
tAS
OE LOW to Output Low-Z[19, 20, 21]
OE HIGH to Output High-Z[19, 20, 21]
0
0
3.0
4.0
Address Setup Before CLK Rise
ADSP, ADSC Setup Before CLK Rise
ADV Setup Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BWX Setup Before CLK Rise
Data Input Setup Before CLK Rise
Chip Enable Setup
tDS
tCES
Hold Times
tAH
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
GW, BWE, BWX Hold After CLK Rise
ADV Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tADH
tWEH
tADVH
tDH
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tCEH
Notes
18. This part has a voltage regulator internally; t
is the time that the power must be supplied above V (minimum) initially, before a read or write operation can be
DD
POWER
initiated.
19. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of “AC Test Loads and Waveforms” on page 20. Transition is measured ± 200 mV
OEHZ
CHZ CLZ OELZ
from steady-state voltage.
20. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
CLZ
OEHZ
OELZ
CHZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High-Z prior to Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
22. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
23. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05357 Rev. *G
Page 21 of 31
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CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Timing Diagrams
Figure 3. Read Cycle Timing[24]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
X
Deselect Cycle
t
t
CES
CEH
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2
+
1)
Q(A2
+
2)
Q(A2
+
3)
Q(A2)
Q(A2
+
1)
Q(A2
+
2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
.
Note
24. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05357 Rev. *G
Page 22 of 31
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CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Timing Diagrams (continued)
Figure 4. Write Cycle Timing[24, 25]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BWX
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2
+
1)
D(A2
+
1)
D(A2
+
2)
D(A2
+
3)
D(A3)
D(A3
+
1)
D(A3 + 2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
DON’T CARE
UNDEFINED
.
Note
25.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW
X
Document #: 38-05357 Rev. *G
Page 23 of 31
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CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Timing Diagrams (continued)
Figure 5. Read/Write Cycle Timing[24, 26, 27]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
Back-to-Back READs
Single WRITE
BURST READ
DON’T CARE
UNDEFINED
.
Note
26. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
27.
GW is HIGH
Document #: 38-05357 Rev. *G
Page 24 of 31
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CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Timing Diagrams (continued)
Figure 6. ZZ Mode Timing[28, 29]
CLK
ZZ
t
t
ZZ
ZZREC
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Note
28. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
29. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05357 Rev. *G
Page 25 of 31
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CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
133 CY7C1441AV33-133AXC
CY7C1443AV33-133AXC
CY7C1441AV33-133BZC
CY7C1443AV33-133BZC
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
Commercial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1441AV33-133BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
CY7C1443AV33-133BZXC
CY7C1447AV33-133BGC
CY7C1447AV33-133BGXC
CY7C1441AV33-133AXI
CY7C1443AV33-133AXI
CY7C1441AV33-133BZI
CY7C1443AV33-133BZI
CY7C1441AV33-133BZXI
CY7C1443AV33-133BZXI
CY7C1447AV33-133BGI
CY7C1447AV33-133BGXI
100 CY7C1441AV33-100AXC
CY7C1443AV33-100AXC
CY7C1441AV33-100BZC
CY7C1443AV33-100BZC
51-85167 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
lndustrial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
51-85167 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
Commercial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1441AV33-100BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
CY7C1443AV33-100BZXC
CY7C1447AV33-100BGC
CY7C1447AV33-100BGXC
CY7C1441AV33-100AXI
CY7C1443AV33-100AXI
CY7C1441AV33-100BZI
CY7C1443AV33-100BZI
CY7C1441AV33-100BZXI
CY7C1443AV33-100BZXI
CY7C1447AV33-100BGI
CY7C1447AV33-100BGXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
lndustrial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
51-85167 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-free
Document #: 38-05357 Rev. *G
Page 26 of 31
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CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Package Diagrams
Figure 1. 100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
1.00 REF.
DETAIL
A
51-85050-*B
Document #: 38-05357 Rev. *G
Page 27 of 31
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CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Package Diagrams (continued)
Figure 2. 165-ball FBGA (15 x 17 x 1.4 mm) (51-85165)
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
Ø0.45 0.05(165X)
1
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
1.00
5.00
10.00
B
15.00 0.10
0.15(4X)
SEATING PLANE
C
51-85165-*A
Document #: 38-05357 Rev. *G
Page 28 of 31
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CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Package Diagrams (continued)
Figure 3. 209-ball FBGA (14 x 22 x1.76 mm) (51-85167)
51-85167-**
Document #: 38-05357 Rev. *G
Page 29 of 31
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CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Document History Page
Document Title: CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM
Document Number: 38-05357
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
124459
254910
03/06/03
See ECN
CJM
SYT
New Data Sheet
*A
Part number changed from previous revision. New and old part number differ by
the letter “A”
Modified Functional Block diagrams
Modified switching waveforms
Added Footnote #13 (32-Bit Vendor I.D Code changed)
Added Boundary scan information
Added IDD, IX and ISB values in the DC Electrical Characteristics
Added tPOWER specifications in Switching Characteristics table
Removed 119 PBGA Package
Changed 165 FBGA Package from BB165C (15 x 17 x 1.20 mm) to BB165
(15 x 17 x 1.40 mm)
Changed 209-Lead PBGA BG209 (14 x 22 x 2.20 mm) to BB209A
(14 x 22 x 1.76 mm)
*B
*C
300131
320813
See ECN
See ECN
SYT
SYT
Removed 150 and 117 MHz Speed Bins
Changed ΘJA and ΘJC from TBD to 25.21 and 2.58 °C/W respectively for TQFP
Package on Pg # 21
Added lead-free information for 100-pin TQFP, 165 FBGA and 209 BGA
Packages.
Added comment of ‘Lead-free BG and BZ packages availability’ below the
Ordering Information
Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209 FBGA
Changed the test condition from VDD = Min. to VDD = Max for VOL in the Electrical
Characteristics table.
Replaced the TBD’s for IDD, ISB1, ISB2, ISB3 and ISB4 to their respective values.
Replaced TBD’s for ΘJA and ΘJC to their respective values for 165 fBGA and 209
fBGA packages on the Thermal Resistance table.
Changed CIN,CCLK and CIO to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP
Package.
Removed “Lead-free BG and BZ packages availability” comment below the
Ordering Information
*D
331551
See ECN
SYT
Modified Address Expansion balls in the pinouts for 165 FBGA and 209 BGA
Packages as per JEDEC standards and updated the Pin Definitions accordingly
Modified VOL, VOH test conditions
Replaced TBD to 100 mA for IDDZZ
Changed CIN, CCLK and CIO to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA
Package.
Added Industrial Temperature Grade
Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively
Updated the Ordering Information by shading and unshading MPNs as per avail-
ability
Document #: 38-05357 Rev. *G
Page 30 of 31
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CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Document Title: CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM
Document Number: 38-05357
Orig. of
REV.
ECN NO. Issue Date Change
Description of Change
Converted from Preliminary to Final.
*E
417547
See ECN
RXU
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”.
Changed IX current value in MODE from –5 & 30 μA to –30 & 5 μA respectively
and also Changed IX current value in ZZ from –30 & 5 μA to –5 & 30 μA respec-
tively on page# 19.
Modified test condition in note# 8 from VIH < VDD to VIH < VDD.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information.
*F
473650
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC
Switching Characteristics table.
Updated the Ordering Information table.
*G
2447027
See ECN VKN/AESA Corrected typo in the Ordering Information table
Corrected typo in the CY7C1447AV33 ‘s Logic Block diagram
Updated the x72 block diagram
© Cypress Semiconductor Corporation, 2003-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05357 Rev. *G
Revised May 09, 2008
Page 31 of 31
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
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