CY7C1463AV25-133BZXC [CYPRESS]
36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM with NoBL⑩ Architecture; 36兆位（ 1M ×36 / 2M ×18 / 512K X 72 ）流通型SRAM与NoBL⑩架构
| 型号： | CY7C1463AV25-133BZXC |
| 厂家： | 
CYPRESS |
| 描述： | 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM with NoBL⑩ Architecture |
| 文件： | 总29页 (文件大小：460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
36-Mbit (1M x 36/2M x 18/512K x 72)
Flow-Through SRAM with NoBL™ Architecture
Functional Description[1]
Features
• No Bus Latency™ (NoBL™) architecture eliminates
dead cycles between write and read cycles
The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 are
2.5V, 1M × 36/2M × 18/512K × 72 Synchronous Flow-through
Burst SRAMs designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
• Can support up to 133-MHz bus operations with zero
wait states
wait
states.
The
CY7C1461AV25/CY7C1463AV25/
— Data is transferred on every clock
CY7C1465AV25 is equipped with the advanced No Bus
Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write-Read transitions.
• Pin-compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
• 2.5V/1.8V I/O power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
• Clock Enable (CEN) pin to enable clock and suspend
operation
• Synchronous self-timed writes
• Asynchronous Output Enable
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
• CY7C1461AV25, CY7C1463AV25 available in
JEDEC-standard lead-free 100-pin TQFP package,
lead-free and non-lead-free 165-ball FBGA package.
CY7C1465AV25 available in lead-free and non-lead-free
209-ball FBGA package.
• Three chip enables for simple depth expansion
• Automatic Power-down feature available using ZZ
mode or CE deselect
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst Capability—linear or interleaved burst order
• Low standby power
Selection Guide
133 MHz
6.5
100 MHz
8.5
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
270
250
mA
mA
120
120
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05355 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 22, 2006
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Logic Block Diagram – CY7C1461AV25 (1M × 36)
ADDRESS
A0, A1, A
A1
A1'
A0'
REGISTER
D1
A0
Q1
Q0
D0
MODE
BURST
LOGIC
CE
ADV/LD
C
CLK
CEN
C
WRITE ADDRESS
REGISTER
O
U
T
P
U
T
D
A
T
S
E
N
S
ADV/LD
A
B
U
F
MEMORY
ARRAY
BWA
BWB
BWC
BWD
WRITE
DRIVERS
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
T
E
E
R
I
DQs
DQP
DQP
DQP
DQP
A
B
C
D
A
M
P
F
E
R
S
S
WE
E
N
G
INPUT
REGISTER
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
1
Logic Block Diagram – CY7C1463AV25 (2M × 18)
ADDRESS
A0, A1, A
A1
A1'
A0'
REGISTER
D1
A0
Q1
Q0
D0
MODE
BURST
LOGIC
CE
ADV/LD
C
CLK
CEN
C
WRITE ADDRESS
REGISTER
O
U
T
P
U
T
D
A
T
S
E
N
S
ADV/LD
A
B
U
F
MEMORY
ARRAY
BW
A
B
WRITE
DRIVERS
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
T
E
E
R
I
DQs
DQP
DQP
BW
A
B
A
M
P
F
E
R
S
S
WE
E
N
G
INPUT
REGISTER
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
ZZ
CONTROL
Document #: 38-05355 Rev. *E
Page 2 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
2
Logic Block Diagram – CY7C1465AV25 (512K × 72)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
U
T
P
O
U
T
S
E
N
S
P
U
T
D
A
T
U
T
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
BW
BW
BW
a
R
E
G
I
MEMORY
ARRAY
E
B
U
F
DQs
DQP
DQP
DQP
DQP
DQP
DQP
DQP
DQP
WRITE
DRIVERS
b
S
T
E
E
R
I
A
M
P
a
b
c
d
e
f
c
F
S
T
E
R
S
BW
d
E
R
S
S
BW
e
BW
BW
f
N
G
g
E
E
BW
h
g
h
WE
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
Sleep
Control
ZZ
Document #: 38-05355 Rev. *E
Page 3 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Pin Configurations
100-pin TQFP Pinout
DQPC
DQC
DQC
VDDQ
VSS
80
1
DQPB
DQB
DQB
VDDQ
VSS
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
4
5
DQC
6
DQB
DQB
DQB
DQB
VSS
BYTE C
BYTE B
DQC
DQC
DQC
VSS
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
DQC
DQC
NC
VDDQ
DQB
DQB
VSS
CY7C1461AV25
VDD
NC
NC
VDD
ZZ
VSS
DQD
DQD
VDDQ
VSS
DQA
DQA
VDDQ
VSS
DQD
DQA
DQA
DQA
DQA
VSS
DQD
BYTE D
BYTE A
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
VDDQ
DQA
DQA
DQPA
Document #: 38-05355 Rev. *E
Page 4 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Pin Configurations (continued)
100-pin TQFP Pinout
NC
1
80
A
NC
2
NC
3
VDDQ
4
VSS
5
NC
6
NC
7
DQB
8
DQB
9
VSS
10
VDDQ
11
DQB
12
DQB
13
NC
14
VDD
15
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
CY7C1463AV25
BYTE A
BYTE B
NC
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
ZZ
VSS
DQB
DQB
VDDQ
VSS
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
DQB
DQB
DQPB
NC
NC
VSS
VSS
VDDQ
NC
VDDQ
NC
NC
NC
NC
NC
Document #: 38-05355 Rev. *E
Page 5 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Pin Configurations (continued)
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1461AV25 (1M × 36)
1
2
A
3
4
5
6
7
8
ADV/LD
OE
9
A
10
A
11
NC
NC/576M
NC/1G
DQPc
A
B
C
D
CE1
CE2
BWc
BWb
CE3
CLK
VSS
VSS
CEN
WE
A
A
A
NC
BWd
VSS
VDD
BWa
VSS
VSS
NC
DQc
VDDQ
VDDQ
VSS
VSS
VSS
VDDQ
VDDQ
NC
DQb
DQPb
DQb
DQc
VDD
DQc
DQc
DQc
NC
DQc
DQc
DQc
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQb
DQb
DQb
NC
DQb
DQb
DQb
ZZ
E
F
G
H
J
DQd
DQd
DQd
DQd
DQd
DQd
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
DQa
DQa
DQa
K
L
DQd
DQd
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
DQa
DQPa
M
N
P
DQPd
NC/144M NC/72M
TDI
TDO
NC/288M
A
MODE
A
A
TMS
A0
TCK
A
A
A
A
R
CY7C1463AV25 (2M × 18)
1
NC/576M
NC/1G
NC
2
A
3
4
5
NC
6
7
8
9
A
10
A
11
A
A
B
C
D
CE3
CLK
VSS
VSS
CE1
CE2
BWb
NC
CEN
ADV/LD
NC
A
A
A
BWa
VSS
VSS
WE
VSS
VSS
OE
VSS
VDD
NC
DQb
VDDQ
VDDQ
VSS
VDD
VDDQ
VDDQ
NC
NC
DQPa
DQa
NC
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQa
DQa
DQa
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
NC
NC
NC
K
L
NC
NC
DQb
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
NC
NC
M
N
P
DQPb
NC/144M NC/72M
TDI
TDO
NC/288M
A
MODE
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05355 Rev. *E
Page 6 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Pin Configurations (continued)
209-ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1465AV25 (512K × 72)
1
2
3
4
5
6
7
8
9
10
DQb
DQb
11
A
B
C
D
E
F
DQg
DQg
A
A
A
CE3
A
DQb
DQb
DQb
DQb
DQPb
DQf
DQg
DQg
CE2
ADV/LD
WE
A
BWSb
NC
BWSc
BWSh
VSS
BWSf
BWSg
BWSd
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
NC/576M
NC
NC
BWSe
NC
CE1
BWSa DQb
NC/1G
OE
VSS
NC
DQb
DQPg
DQc
VDDQ
VDDQ
VDDQ
DQPf
VDDQ
VSS
VDDQ
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
NC
VDD
VSS
VDD
VSS
DQf
VSS
VDDQ
VSS
VSS
G
H
J
DQc
DQc
VDDQ
VSS
NC
VDDQ
VSS
DQf
DQf
DQf
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
A
DQc
DQc
NC
NC
DQf
DQf
NC
VDDQ
DQc
NC
VDDQ
VDDQ
CLK
VDDQ
NC
NC
DQf
NC
K
L
CEN
NC
NC
NC
DQh
DQh
DQh
VDDQ
VSS
VDDQ
VSS
VDDQ
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
DQa
DQa
DQa
M
N
P
R
T
NC
VSS
VDDQ
VSS
VDDQ
NC
DQh
DQh
DQh
VSS
VDD
VSS
DQa
DQa
DQa
VDDQ
DQh
DQh
DQPd
DQd
DQd
NC
ZZ
DQa
DQa
DQPa
DQe
DQe
VSS
VDDQ
VDDQ
VDD
NC
DQPh
DQd
DQd
DQd
DQd
VDDQ
VDD
DQPe
DQe
DQe
DQe
DQe
VSS
VSS
NC
A
MODE
A
U
V
W
NC/72M
A
NC/288M
NC/144M
A
A
A1
A
DQd
DQd
A
A
A
A
DQe
DQe
TDI
TDO
TCK
A0
A
TMS
Pin Definitions
Pin Name
I/O Type
Pin Description
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
BWa
BWb
BWc
BWd
BWe
BWf
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,
BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf
controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.
BWg
BWh
WE
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Synchronous
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Document #: 38-05355 Rev. *E
Page 7 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
CE1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
CE2
CE3
OE
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
Input-
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state
and when the device has been deselected.
CEN
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
DQa
DQb
DQc
DQd
DQe
DQf
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by AX during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQa–DQd are placed in a tri-state condition. The outputs are automat-
ically tri-stated during the data portion of a write sequence, during the first clock when emerging
from a deselected state, and when the device is deselected, regardless of the state of OE.
DQg
DQh
DQPa
DQPb
DQPc
DQPd
DQPe
DQPf
DQPg
DQPh
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During
write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by
BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf,
DQPg is controlled by BWg, DQPh is controlled by BWh.
MODE
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
TDO
TDI
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Synchronous
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
Synchronous
TMS
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous
TCK
VDD
JTAG-Clock
Clock input to the JTAG circuitry.
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
VDDQ
VSS
Ground
N/A
Ground for the device. Should be connected to ground of the system.
NC
No connects. This pin is not connected to the die.
NC/72M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/144M
NC/288M
NC/576M
NC/1G
N/A
N/A
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
N/A
Not connected to the die. Can be tied to any voltage level.
N/A
Not connected to the die. Can be tied to any voltage level.
ZZ
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous with data integrity preserved. During normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.
Document #: 38-05355 Rev. *E
Page 8 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Therefore, the type of access (Read or Write) is maintained
throughout the burst sequence.
Functional Overview
The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 is a
synchronous flow-through burst SRAM designed specifically
to eliminate wait states during Write-Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (tCDV) is 6.5 ns (133-MHz
device).
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically tri-stated regardless of the state of the OE input
signal. This allows the external logic to present the data on
DQs and DQPX.
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BWX can be used to
conduct byte write operations.
On the next clock rise the data presented to DQs and DQPX
(or a subset for byte write operations, see truth table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by BWX
signals. The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25
providesbyte write capability that is described in the truth table.
Asserting the Write Enable input (WE) with the selected Byte
Write Select input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations. Byte write
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
Because the CY7C1461AV25/CY7C1463AV25/CY7C1465AV25
is a common I/O device, data should not be driven into the
device while the outputs are active. The Output Enable (OE)
can be deasserted HIGH before presenting data to the DQs
and DQPX inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs and DQPX are automatically
tri-stated during the data portion of a write cycle, regardless of
the state of OE.
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be tri-stated
immediately.
Burst Write Accesses
The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 has
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four Write opera-
tions without reasserting the address inputs. ADV/LD must be
driven LOW in order to load the initial address, as described
in the Single Write Access section above. When ADV/LD is
driven HIGH on the subsequent clock rise, the Chip Enables
(CE1, CE2, and CE3) and WE inputs are ignored and the burst
counter is incremented. The correct BWX inputs must be
driven in each cycle of the burst write, in order to write the
correct bytes of data.
Burst Read Accesses
The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 has
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four Reads without
reasserting the address inputs. ADV/LD must be driven LOW
in order to load a new address into the SRAM, as described in
the Single Read Access section above. The sequence of the
burst counter is determined by the MODE input signal. A LOW
input on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and
A1 in the burst sequence, and will wrap around when incre-
mented sufficiently. A HIGH input on ADV/LD will increment
the internal burst counter regardless of the state of chip enable
inputs or WE. WE is latched at the beginning of a burst cycle.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Document #: 38-05355 Rev. *E
Page 9 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Sleep Mode
Linear Burst Address Table (MODE = GND)
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > VDD – 0.2V
Min.
Max.
100
Unit
mA
ns
tZZS
ZZ > VDD – 0.2V
2tCYC
tZZREC
tZZI
ZZ < 0.2V
2tCYC
0
ns
ZZ active to sleep current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
ns
Truth Table[2, 3, 4, 5, 6, 7, 8]
Address
Used
Operation
Deselect Cycle
CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
DQ
None
None
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L->H
L->H
L->H
L->H
Tri-State
Tri-State
Tri-State
Tri-State
Deselect Cycle
Deselect Cycle
None
L
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/Write Abort (Begin Burst)
Write Abort (Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
None
X
H
X
H
X
H
X
H
X
X
X
H
L
External
Next
L->H Data Out (Q)
L->H Data Out (Q)
X
L
X
L
H
L
L
External
Next
H
H
X
X
X
X
X
X
L->H
L->H
Tri-State
Tri-State
X
L
X
L
H
L
External
Next
L->H Data In (D)
L->H Data In (D)
X
L
X
L
H
L
X
L
L
None
H
H
X
X
L->H
L->H
L->H
X
Tri-State
Tri-State
–
Next
X
X
X
X
X
X
H
X
X
X
X
X
Current
None
Tri-State
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BW = L signifies at least one Byte Write Select is active, BW = Valid signifies that the desired byte write
X
X
selects are asserted, see truth table for details.
3. Write is defined by BW , and WE. See truth table for Read/Write.
X
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQs and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
X
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP = Tri-state when OE
X
is inactive or when the device is deselected, and DQs and DQP = data when OE is active.
X
Document #: 38-05355 Rev. *E
Page 10 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Truth Table for Read/Write[2, 3, 9]
Function (CY7C1461AV25)
Read
WE
H
L
BWA
X
BWB
X
BWC
X
BWD
X
Write No bytes written
H
H
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Byte C – (DQC and DQPC)
Write Byte D – (DQD and DQPD)
Write All Bytes
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
Truth Table for Read/Write[2, 3, 9]
Function (CY7C1463AV25)
WE
BWB
BWA
Read
H
L
L
L
L
X
H
H
L
X
H
L
Write – No Bytes Written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Both Bytes
H
L
L
Truth Table for Read/Write[2, 3, 9]
WE
H
BWX
Function (CY7C1465AV25)
Read
X
Write – No Bytes Written
Write Byte X − (DQx and DQPx)
Write All Bytes
L
H
L
L
L
All BW = L
Note:
9. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid Appropriate write will be done based on which byte write is active.
X
Document #: 38-05355 Rev. *E
Page 11 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Test Data-In (TDI)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 incor-
porates a serial boundary scan test access port (TAP). This
part is fully compliant with 1149.1. The TAP operates using
JEDEC-standard 2.5V/1.8V I/O logic level.
The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 contains
a TAP controller, instruction register, boundary scan register,
bypass register, and ID register.
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0
Bypass Register
TAP Controller State Diagram
2
1
0
0
0
Selection
Circuitry
TEST-LOGIC
1
Instruction Register
31 30 29
Identification Register
Selection
RESET
0
TDI
TDO
Circuitr
y
.
.
. 2 1
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
x
.
.
.
.
. 2 1
1
1
CAPTURE-DR
CAPTURE-IR
Boundary Scan Register
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
TCK
TMS
1
1
TAP CONTROLLER
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
0
1
1
Performing a TAP Reset
0
0
EXIT2-DR
1
EXIT2-IR
1
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
UPDATE-DR
UPDATE-IR
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Document #: 38-05355 Rev. *E
Page 12 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the in-
struction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The length of the Boundary
Scan Register for the SRAM in different packages is listed in
the Scan Register Sizes table.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possi-
ble that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
TAP Instruction Set
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
The boundary scan register has a special bit located at bit #89
(for 165-FBGA package) or bit #138 (for 209 FBGA package).
Document #: 38-05355 Rev. *E
Page 13 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[10, 11]
Parameter
Clock
tTCYC
tTF
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
tTH
20
20
tTL
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise
tTDIS
10
ns
ns
0
5
5
5
ns
ns
ns
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Capture Hold after Clock Rise
Notes:
10. .t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
11. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document #: 38-05355 Rev. *E
Page 14 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
1.8V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels .................................... 0.2V to VDDQ – 0.2
Input rise and fall time..................................................... 1 ns
Input timing reference levels...........................................0.9V
Output reference levels...................................................0.9V
Test load termination supply voltage...............................0.9V
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels......................................... 1.25V
Output reference levels ................................................ 1.25V
Test load termination supply voltage ............................ 1.25V
2.5V TAP AC Output Load Equivalent
1.8V TAP AC Output Load Equivalent
1.25V
0.9V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
ZO= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 2.375 to 2.625 unless otherwise noted)[12]
Parameter
VOH1
Description
Test Conditions
Min.
2.0
Max.
Unit
V
Output HIGH Voltage IOH = –1.0 mA, VDDQ = 2.5V
VOH2
Output HIGH Voltage IOH = –100 µA
VDDQ = 2.5V
DDQ = 1.8V
2.1
V
V
1.6
V
VOL1
VOL2
Output LOW Voltage IOL = 1.0 mA
Output LOW Voltage IOL = 100 µA
VDDQ = 2.5V
VDDQ = 2.5V
0.4
0.2
V
V
V
DDQ = 1.8V
VDDQ = 2.5V
DDQ = 1.8V
0.2
V
VIH
VIL
IX
Input HIGH Voltage
Input LOW Voltage
1.7
1.26
–0.3
–0.3
–5
VDD + 0.3
VDD + 0.3
0.7
V
V
V
VDDQ = 2.5V
VDDQ = 1.8V
V
0.36
V
Input Load Current
GND < VIN < VDDQ
5
µA
Identification Register Definitions
CY7C1461AV25 CY7C1463AV25 CY7C1465AV25
Instruction Field
Revision Number (31:29)
Device Depth (28:24)
(1M × 36)
(2M × 18)
(512K × 72)
Description
000
000
000
Describes the version number
Reserved for internal use
01011
01011
01011
Architecture/Memory Type (23:18)
001001
001001
001001
Defines memory type and archi-
tecture
Bus Width/Density(17:12)
100111
010111
110111
Defines width and density
Cypress JEDEC ID Code (11:1)
00000110100
00000110100
00000110100 Allows unique identification of
SRAM vendor
ID Register Presence Indicator (0)
1
1
1
Indicates the presence of an ID
register
Note:
12. All voltages referenced to V (GND).
SS
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CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Scan Register Sizes
Register Name
Bit Size (×36)
Bit Size (×18)
Bit Size (×72)
Instruction
3
1
3
1
3
1
Bypass
ID
32
89
–
32
89
–
32
–
Boundary Scan Order (165-ball FBGA package)
Boundary Scan Order (209-ball FBGA package)
138
Identification Codes
Instruction
EXTEST
Code
Description
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document #: 38-05355 Rev. *E
Page 16 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
165-ball FBGA Boundary Scan Order [13]
CY7C1461AV25 (1M × 36), CY7C1463AV25 (2M × 18)
Bit#
1
Ball ID
N6
Bit#
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Ball ID
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
A9
Bit#
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Ball ID
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
Bit#
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
N1
2
N7
N2
3
N10
P11
P8
P1
4
R1
5
R2
6
R8
P3
7
R9
R3
8
P9
P2
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
R4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P4
G1
D2
E2
F2
N5
P6
B9
R6
C10
A8
Internal
G2
H1
H3
J1
B8
A7
B7
B6
K1
L1
A6
B5
M1
J2
A5
H10
G11
F11
A4
K2
L2
B4
B3
M2
Note:
13. Bit# 89 is preset HIGH.
Document #: 38-05355 Rev. *E
Page 17 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
209-ball BGA Boundary Scan Order [13, 14]
CY7C1465V25 (512K x 72)
Bit#
1
Ball ID
W6
V6
Bit#
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Ball ID
F6
Bit#
71
Ball ID
H6
C6
B6
A6
A5
B5
C5
D5
D4
C4
A4
B4
C3
B3
A3
A2
A1
B2
B1
C2
C1
D2
D1
E1
E2
F2
Bit#
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
Ball ID
K3
2
K8
72
K4
3
U6
K9
73
K6
4
W7
V7
K10
J11
J10
H11
H10
G11
G10
F11
F10
E10
E11
D11
D10
C11
C10
B11
B10
A11
A10
C9
74
K2
5
75
L2
6
U7
76
L1
7
T7
77
M2
M1
N2
N1
P2
8
V8
78
9
U8
79
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
T8
80
V9
81
U9
82
P1
P6
83
R2
R1
T2
W11
W10
V11
V10
U11
U10
T11
T10
R11
R10
P11
P10
N11
N10
M11
M10
L11
L10
K11
M6
84
85
86
T1
87
U2
U1
V2
88
89
90
V1
91
W2
W1
T6
92
93
B9
94
U3
V3
A9
95
D8
96
T4
C8
97
F1
T5
B8
98
G1
G2
H2
H1
J2
U4
V4
A8
99
D7
100
101
102
103
104
105
W5
V5
C7
B7
U5
Internal
A7
J1
L6
D6
K1
N6
J6
G6
Note:
14. Bit# 138 is preset HIGH.
Document #: 38-05355 Rev. *E
Page 18 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current..................................................... >200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V
Supply Voltage on VDDQ Relative to GND ......–0.5V to +VDD
Ambient
Temperature
Range
VDD
VDDQ
Commercial 0°C to +70°C 2.5V –5%/+5% 1.7V to VDD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Industrial
–40°C to +85°C
Electrical Characteristics Over the Operating Range[15, 16]
DC Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
2.375
2.375
1.7
Max.
2.625
VDD
Unit
V
VDDQ
for 2.5V I/O
for 1.8V I/O
V
1.9
V
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
for 2.5V I/O, IOH = −1.0 mA
for 1.8V I/O, IOH = –100 µA
for 2.5V I/O, IOL = 1.0 mA
for 1.8V I/O, IOL = 100 µA
2.0
V
1.6
V
0.4
0.2
V
V
Input HIGH Voltage[15] for 2.5V I/O
1.7
1.26
–0.3
–0.3
–5
VDD + 0.3V
VDD + 0.3V
0.7
V
for 1.8V I/O
V
Input LOW Voltage[15]
for 2.5V I/O
for 1.8V I/O
V
0.36
V
Input Leakage Current GND ≤ VI ≤ VDDQ
except ZZ and MODE
5
µA
Input Current of MODE Input = VSS
Input = VDD
–30
–5
µA
µA
µA
µA
µA
mA
mA
mA
5
Input Current of ZZ
Input = VSS
Input = VDD
30
5
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
–5
VDD Operating Supply VDD = Max., IOUT = 0 mA,
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
270
250
150
Current
f = fMAX = 1/tCYC
ISB1
ISB2
ISB3
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected, All speeds
VIN ≥ VIH or VIN ≤ VIL
f = fMAX, inputs switching
Automatic CE
Power-down
Current—CMOS Inputs f = 0, inputs static
VDD = Max, Device Deselected, All speeds
VIN ≤ 0.3V or VIN > VDD – 0.3V,
120
150
135
mA
mA
mA
Automatic CE
Power-down
Current—CMOS Inputs f = fMAX, inputs switching
VDD = Max, Device Deselected, or All speeds
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
ISB4
Automatic CE
VDD = Max, Device Deselected, All Speeds
Power-down
Current—TTL Inputs
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
Notes:
15. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse widthless than t
/2)
CYC
IH
DD
CYC
IL
16. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
Document #: 38-05355 Rev. *E
Page 19 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Capacitance[17]
100 TQFP 165 FBGA 209 FBGA
Parameter
Description
Input Capacitance
Test Conditions
Max.
6.5
3
Max.
Max.
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
7
7
6
5
5
7
VDD = 2.5V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
VDDQ = 2.5V
5.5
pF
Thermal Resistance[17]
100 TQFP
Package
165 FBGA 209 FBGA
Parameter
Description
Test Conditions
Package
Package
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard
test methods and procedures
for measuring thermal
25.21
20.8
25.31
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
2.28
3.2
4.48
°C/W
impedance, per EIA/JESD51.
AC Test Loads and Waveforms
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
GND
5 pF
INCLUDING
R = 1538Ω
≤ 1ns
≤ 1ns
V = 1.25V
T
JIG AND
SCOPE
(a)
(b)
(c)
1.8V I/O Test Load
R = 14 KΩ
1.8V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ - 0.2
0.2
90%
10%
Z = 50Ω
0
10%
L
5 pF
R = 14 KΩ
≤ 1ns
≤ 1ns
INCLUDING
V = 0.9V
T
JIG AND
SCOPE
(a)
(b)
(c)
Note:
17. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05355 Rev. *E
Page 20 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Switching Characteristics Over the Operating Range [22, 23]
–133
–100
Parameter
Description
Min.
Max.
Min.
Max.
Unit
[18]
tPOWER
1
1
ms
Clock
tCYC
Clock Cycle Time
Clock HIGH
7.5
2.5
2.5
10
3.0
3.0
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCDV
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[19, 20, 21]
6.5
8.5
ns
ns
ns
ns
ns
ns
ns
tDOH
2.5
2.5
2.5
2.5
0
tCLZ
tCHZ
Clock to High-Z[19, 20, 21]
3.8
3.0
4.5
3.8
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
Set-up Times
tAS
OE LOW to Output Low-Z[19, 20, 21]
OE HIGH to Output High-Z[19, 20, 21]
0
0
3.0
4.0
Address Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
WE, BWX Set-up Before CLK Rise
CEN Set-up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tALS
tWES
tCENS
tDS
Data Input Set-up Before CLK Rise
Chip Enable Set-up Before CLK Rise
tCES
Hold Times
tAH
Address Hold After CLK Rise
ADV/LD Hold After CLK Rise
WE, BWX Hold After CLK Rise
CEN Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tALH
tWEH
tCENH
tDH
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tCEH
Notes:
18. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially, before a read or write operation
DD
POWER
can be initiated.
19. t
, t
,t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
20. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
22. Timing reference level is 1.25V when V
= 2.5V and is 0.9V when V
= 1.8V.
DDQ
DDQ
23. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05355 Rev. *E
Page 21 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Switching Waveforms
Read/Write Waveforms[24, 25, 26]
t
1
2
3
4
5
6
7
8
9
10
CYC
t
CLK
CEN
t
t
t
t
t
CENS
CES
CENH
CEH
CL
CH
CE
ADV/LD
WE
BW
X
A1
A2
A4
A3
A5
A6
A7
ADDRESS
DQ
t
CDV
t
t
AS
AH
t
t
t
t
CHZ
DOH
OEV
CLZ
D(A1)
t
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
t
OEHZ
t
DS
DH
t
DOH
t
OELZ
OE
COMMAND
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes:
For this waveform ZZ is tied LOW.
24.
25. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
26. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05355 Rev. *E
Page 22 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Switching Waveforms (continued)
NOP, STALL and DESELECT Cycles[24, 25, 27]
t
1
2
3
4
5
6
7
8
9
10
CYC
CLK
CEN
t
t
t
t
t
t
CENS
CES
CENH
CEH
CL
CH
CE
ADV/LD
WE
BW
X
A1
A2
A4
A3
A5
A6
A7
ADDRESS
DQ
t
CDV
t
t
AS
AH
t
t
t
t
CHZ
DOH
OEV
CLZ
D(A1)
t
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
t
OEHZ
t
DS
DH
t
DOH
t
OELZ
OE
COMMAND
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Note:
27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document #: 38-05355 Rev. *E
Page 23 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Switching Waveforms (continued)
ZZ Mode Timing[28, 29]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
28. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
29. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05355 Rev. *E
Page 24 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Part and Package Type
133 CY7C1461AV25-133AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1463AV25-133AXC
Commercial
CY7C1461AV25-133BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1463AV25-133BZC
CY7C1461AV25-133BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1463AV25-133BZXC
CY7C1465AV25-133BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1465AV25-133BGXC
CY7C1461AV25-133AXI
CY7C1463AV25-133AXI
CY7C1461AV25-133BZI
CY7C1463AV25-133BZI
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
lndustrial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1461AV25-133BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1463AV25-133BZXI
CY7C1465AV25-133BGI
CY7C1465AV25-133BGXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
100 CY7C1461AV25-100AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1463AV25-100AXC
Commercial
CY7C1461AV25-100BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1463AV25-100BZC
CY7C1461AV25-100BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1463AV25-100BZXC
CY7C1465AV25-100BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1465AV25-100BGXC
CY7C1461AV25-100AXI
CY7C1463AV25-100AXI
CY7C1461AV25-100BZI
CY7C1463AV25-100BZI
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
lndustrial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1461AV25-100BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1463AV25-100BZXI
CY7C1465AV25-100BGI
CY7C1465AV25-100BGXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
Document #: 38-05355 Rev. *E
Page 25 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Package Diagrams
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00 0.20
1.40 0.05
14.00 0.10
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
0.25
1. JEDEC STD REF MS-026
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
A
Document #: 38-05355 Rev. *E
Page 26 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Package Diagrams (continued)
165-ball FBGA (15 x 17 x 1.4 mm) (51-85165)
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
Ø0.45 0.05(165X)
1
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
1.00
5.00
10.00
B
15.00 0.10
0.15(4X)
SEATING PLANE
C
51-85165-*A
Document #: 38-05355 Rev. *E
Page 27 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Package Diagrams (continued)
209-ball FBGA (14 x 22 x 1.76 mm) (51-85167)
51-85167-**
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05355 Rev. *E
Page 28 of 29
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Document History Page
Document Title: CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through
SRAM with NoBL™ Architecture
Document Number: 38-05355
Orig. of
REV.
ECN NO. Issue Date Change
Description of Change
**
254911
See ECN
SYT
New data sheet
Changed part number from previous revision. New and old part number differ
by the letter “A”
*A
*B
300131
See ECN
SYT
Removed 150- and 177-MHz speed bins
Changed ΘJA and ΘJC from TBD to 25.21 and 2.58 °C/W, respectively, for
TQFP Package
Added lead-free information for 100-pin TQFP, 165 FBGA and 209 BGA
packages
Added “Lead-free BG and BZ packages availability” below the Ordering Infor-
mation
320813
See ECN
SYT
Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209
FBGA
Changed the test condition from VDD = Min. to VDD = Max for VOL in the
Electrical Characteristics table
Replaced the TBD’s for IDD, ISB1, ISB2, ISB3 and ISB4 to their respective values
Replaced TBD’s for ΘJA and ΘJC to their respective values for 165 FBGA
and 209 FBGA packages on the Thermal Resistance table
Changed CIN, CCLK and CI/O to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP
Package
Removed “Lead-free BG and BZ packages availability” comment below the
Ordering Information
*C
*D
*E
331551
See ECN
SYT
Modified Address Expansion balls in the pinouts for 165 FBGA and 209 BGA
Packages as per JEDEC standards and updated the Pin Definitions accord-
ingly
Changed typo from (-0.5V+4.6V) to (-0.5V+3.6V) for Supply Voltage on VDD
Relative to GND under the Maximum Ratings Section
Modified VOL, VOH test conditions
Replaced TBD to 100 mA for IDDZZ
Changed CIN, CCLK and CI/O to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA
Package
Added Industrial Temperature Grade
Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively
Updated the Ordering Information by shading and unshading MPNs as per
availability
417547
See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed IX current value in MODE from –5 & 30 µA to –30 & 5 µA respec-
tively and also Changed IX current value in ZZ from –30 & 5 µA to –5 & 30
µA respectively on page# 20
Modified test condition from VIH < VDD to VIH < VDD
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information Table
473650
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP
AC Switching Characteristics table.
Updated the Ordering Information table.
Document #: 38-05355 Rev. *E
Page 29 of 29
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