CY7C1464AV33-250 [CYPRESS]
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL⑩ Architecture; 36兆位（ 1M ×36 / 2M ×18 / 512K X 72 ）流水线SRAM与NOBL ™架构
| 型号： | CY7C1464AV33-250 |
| 厂家： | 
CYPRESS |
| 描述： | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL⑩ Architecture |
| 文件： | 总27页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
SRAM with NoBL™ Architecture
Features
Functional Description
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V,
1 Mbit x 36 / 2 Mbit x 18 / 512K x72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They
are designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1460AV33/
CY7C1462AV33/CY7C1464AV33 are equipped with the
advanced (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent Write/Read transitions.The
• Internally self-timed output buffer control to eliminate the
need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33
compatible and functionally equivalent to ZBT devices.
are
pin
• Single 3.3V power supply
• 3.3V/2.5V I/O power supply
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 3.2 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock input
is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the Byte Write Selects
(BWa–BWh for CY7C1464AV33, BWa–BWd for CY7C1460AV33
and BWa–BWb for CY7C1462AV33) and a Write Enable (WE)
input. All writes are conducted with on-chip synchronous
self-timed write circuitry.
• CY7C1460AV33 and CY7C1462AV33 are available in
lead-free 100-pin TQFP and 165-Ball fBGA packages;
CY7C1464AV33 available in 209-Ball fBGA package
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Logic Block Diagram-CY7C1460AV33 (1 Mbit x 36)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD
A
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
R
E
G
I
MEMORY
ARRAY
B
U
F
S
T
E
E
R
I
DQs
DQP
DQP
DQP
DQP
WRITE
DRIVERS
BW
BW
a
a
b
c
d
A
M
P
b
BW
BW
c
S
T
E
R
S
F
d
E
R
S
S
WE
E
E
N
G
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
Cypress Semiconductor Corporation
Document #: 38-05353 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 19, 2004
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Logic Block Diagram-CY7C1462AV33 (2 Mbit x 18)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
R
E
G
I
S
T
E
R
S
MEMORY
ARRAY
E
B
DQs
U
WRITE
DRIVERS
BW
BW
a
S
T
E
E
R
I
A
M
P
F
F
E
R
S
DQP
DQP
a
b
b
S
N
G
WE
E
E
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
Sleep
Control
ZZ
Logic Block Diagram-CY7C1464AV33 (512K x 72)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
O
U
T
P
U
T
P
S
D
A
T
U
T
E
N
S
U
T
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
BW
BW
BW
a
R
E
G
I
S
T
E
R
S
MEMORY
ARRAY
E
B
U
F
DQs
WRITE
DRIVERS
b
S
T
E
E
R
I
A
M
P
DQP
DQP
DQP
DQP
DQP
DQP
DQP
DQP
a
b
c
d
e
f
c
F
BW
d
E
R
S
S
BW
e
BW
BW
f
N
G
g
E
E
BW
h
g
h
WE
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
Sleep
Control
ZZ
Selection Guide
CY7C1460AV33-250
CY7C1462AV33-250
CY7C1464AV33-250
CY7C1460AV33-200
CY7C1462AV33-200
CY7C1464AV33-200
CY7C1460AV33-167
CY7C1462AV33-167
CY7C1464AV33-167
Unit
ns
Maximum Access Time
2.6
475
100
3.2
425
100
3.4
375
100
Maximum Operating Current
mA
mA
Maximum CMOS Standby
Current
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05353 Rev. *A
Page 2 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Pin Configurations
100-pin TQFP Packages
DQPc
DQc
DQc
1
2
3
4
5
6
7
8
NC
NC
NC
DDQ
1
2
3
4
5
6
7
8
A
NC
NC
78
DQPb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
79
V
V
DDQ
VDDQ
VSS
V
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
SS
V
V
SS
SS
DQc
DQc
NC
NC
DQb
NC
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
DQPa
DQa
DQa
DQc
DQc
9
DQb
9
V
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
V
V
DDQ
DDQ
V
DQa
DQa
DDQ
DQc
DQc
NC
DQb
DQb
NC
V
CY7C1462AV33
(2 Mbit × 18)
CY7C1460AV33
(1 Mbit × 36)
SS
V
V
DD
DD
NC
NC
NC
VDD
ZZ
DQa
DQa
V
DD
V
V
SS
SS
ZZ
DQd
DQb
DQb
DQa
DQa
DQd
V
V
DDQ
DDQ
VDDQ
VSS
DQa
DQa
V
DDQ
V
V
SS
SS
V
SS
DQd
DQd
DQd
DQd
DQb
DQb
DQa DQPb
DQa
DQa
NC
DQa
VSS
VDDQ
DQa
DQa
DQPa
NC
NC
V
SS
V
V
SS
SS
V
V
DDQ
DQd
DDQ
V
DDQ
NC
NC
NC
NC
NC
NC
DQd
DQPd
Document #: 38-05353 Rev. *A
Page 3 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Pin Configurations (continued)
165-Ball fBGA Pinout
CY7C1460AV33 (1 Mbit × 36)
1
NC/288M
NC
2
A
3
4
5
6
7
8
9
A
10
A
11
NC
ADV/LD
A
B
C
D
CE1
BWc
BWb
CE3
CLK
VSS
VSS
CEN
WE
VSS
VSS
A
CE2
VDDQ
VDDQ
OE
VSS
VDD
A
A
NC/144M
DQPb
DQb
BWd
VSS
VDD
BWa
VSS
VSS
DQPc
DQc
NC
DQc
VDDQ
VDDQ
NC
DQb
DQc
DQc
DQc
DQc
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQb
DQb
DQb
NC
DQb
E
F
DQc
DQc
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQb
DQb
ZZ
G
H
J
DQd
DQd
DQd
DQd
DQd
DQd
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
DQa
DQa
DQa
K
L
DQd
DQPd
NC
DQd
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
DQa
DQPa
NC
M
N
P
NC/72M
TDI
TDO
A
MODE
A
A
TMS
A0
TCK
A
A
A
A
R
CY7C1462AV33 (2 Mbit × 18)
1
NC/288M
NC
2
A
3
4
5
NC
6
CE3
7
8
9
A
10
A
11
A
A
B
C
D
CE1
BWb
NC
CEN
ADV/LD
NC/144M
A
CE2
VDDQ
VDDQ
BWa
VSS
VSS
CLK
VSS
VSS
A
A
WE
VSS
VSS
OE
VSS
VDD
NC
NC
DQb
VSS
VDD
VDDQ
VDDQ
NC
NC
DQPa
DQa
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQa
E
F
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQa
DQa
ZZ
NC
G
H
J
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
NC
NC
NC
NC
K
L
NC
DQb
DQPb
NC
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
NC
NC
NC
M
N
P
NC/72M
TDI
TDO
A
MODE
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05353 Rev. *A
Page 4 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Pin Configurations (continued)
209-Ball PBGA
CY7C1464AV33 (512K x 72)
1
DQg
DQg
DQg
2
3
4
5
6
7
8
9
10
DQb
11
A
B
C
D
E
F
DQg
DQg
CE3
CE2
ADV/LD
WE
DQb
DQb
A
A
A
A
A
BWSb
DQb
DQb
NC
NC
BWSc
BWSh
VSS
BWSf
BWSa
VSS
BWSg
BWSd
DQg
DQg
DQPc
DQc
DQc
NC
NC
BWSe
NC
CE1
DQb
DQb
DQPb
DQf
DQg
NC
OE
NC
DQb
DQPg
DQc
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
NC
VDD
VSS
VDD
DQPf
DQf
VSS
VDDQ
VSS
VSS
G
H
J
DQc
DQc
VDDQ
VSS
VDDQ
VSS
NC
DQf
DQf
DQf
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
A
DQc
DQc
NC
NC
DQf
DQf
NC
VDDQ
DQc
NC
VDDQ
VDDQ
CLK
VDDQ
NC
NC
DQf
NC
K
L
CEN
NC
NC
NC
DQh
DQh
DQh
VDDQ
VSS
VDDQ
VSS
VDDQ
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
DQa
DQa
DQa
M
N
P
R
T
NC
VSS
VDDQ
VSS
VDDQ
NC
DQh
DQh
DQh
VSS
VDD
VSS
DQa
DQa
DQa
VDDQ
DQh
DQh
DQPd
DQd
DQd
NC
ZZ
DQa
DQa
DQPa
DQe
DQe
VSS
VDDQ
VSS
NC
VDDQ
VDD
NC
DQPh
DQd
DQd
DQd
DQd
VDDQ
VDD
DQPe
DQe
DQe
DQe
DQe
VSS
NC
A
MODE
A
U
V
W
NC/72M
A
NC
A
A
A1
A
DQd
DQd
A
A
A
A
DQe
DQe
TDI
TDO
TCK
A0
A
TMS
Pin Definitions
Pin Name
I/O Type
Pin Description
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
BWa
BWb
BWc
BWd
BWe
BWf
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,
BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf
controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.
BWg
BWh
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
WE
Input-
Synchronous
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
ADV/LD
Document #: 38-05353 Rev. *A
Page 5 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
CE1
CE2
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous
CE1 and CE3 to select/deselect the device.
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
CE3
OE
Input-
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state
and when the device has been deselected.
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
CEN
DQa
DQb
DQc
DQd
DQe
DQf
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by AX during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQa–DQd are placed in a tri-state condition. The outputs are automat-
ically tri-stated during the data portion of a write sequence, during the first clock when emerging
from a deselected state, and when the device is deselected, regardless of the state of OE.
DQg
DQh
DQPa
DQPb
DQPc
DQPd
DQPe
DQPf
DQPg
DQPh
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During
write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by
BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf,
DQPg is controlled by BWg, DQPh is controlled by BWh.
MODE
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
TDO
TDI
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Synchronous
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
Synchronous
TMS
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous
TCK
JTAG-Clock
Clock input to the JTAG circuitry.
VDD
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
VDDQ
VSS
Ground
N/A
Ground for the device. Should be connected to ground of the system.
NC
No connects. This pin is not connected to the die.
NC/72M
NC/144M
NC/288M
ZZ
N/A
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
N/A
N/A
Input-
Asynchronous with data integrity preserved. During normal operation, this pin can be connected to Vss or left
floating.
Document #: 38-05353 Rev. *A
Page 6 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
A1 in the burst sequence, and will wrap-around when incre-
mented sufficiently. A HIGH input on ADV/LD will increment
the internal burst counter regardless of the state of chip
enables inputs or WE. WE is latched at the beginning of a burst
cycle. Therefore, the type of access (Read or Write) is
maintained throughout the burst sequence.
Introduction
Functional Overview
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are
synchronous-pipelined Burst NoBL SRAMs designed specifi-
cally to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(tCO) is 2.6 ns (250-MHz device).
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to the address inputs
is loaded into the Address Register. The write signals are
latched into the Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BW[x] can be used to
conduct byte write operations.
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
for
CY7C1464AV33,
DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b
for CY7C1462AV33). In addition, the address for the subse-
quent access (Read/Write/Deselect) is latched into the
Address Register (provided the appropriate control signals are
asserted).
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
for
CY7C1464AV33,
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 & DQa,b/DQPa,b for
CY7C1462AV33) (or a subset for byte write operations, see
Write Cycle Description table for details) inputs is latched into
the device and the write is complete.
The data written during the Write operation is controlled by BW
(BWa,b,c,d,e,f,g,h
for
CY7C1464AV33,
BWa,b,c,d
for
Single Read Accesses
CY7C1460AV33 and BWa,b for CY7C1462AV33) signals. The
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 provides
byte write capability that is described in the Write Cycle
Description table. Asserting the Write Enable input (WE) with
the selected Byte Write Select (BW) input will selectively write
to only the desired bytes. Bytes not selected during a byte
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.6 ns
(250-MHz device) provided OE is active LOW. After the first
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will tri-state following the
next clock rise.
write operation will remain unaltered.
A synchronous
self-timed write mechanism has been provided to simplify the
write operations. Byte write capability has been included in
order to greatly simplify Read/Modify/Write sequences, which
can be reduced to simple byte write operations.
Because
the
are
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33
common I/O devices, data should not be driven into the device
while the outputs are active. The Output Enable (OE) can be
deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
for
CY7C1464AV33,
DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b
for CY7C1462AV33) inputs. Doing so will tri-state the output
drivers. As a safety precaution, DQ and DQP (DQa,b,c,d,e,f,g,h
/
DQPa,b,c,d,e,f,g,h for CY7C1464AV33, DQa,b,c,d/ DQPa,b,c,d for
CY7C1460AV33 and DQa,b/DQPa,b for CY7C1462AV33) are
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Read Accesses
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 have
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four Reads without
reasserting the address inputs. ADV/LD must be driven LOW
in order to load a new address into the SRAM, as described in
the Single Read Access section above. The sequence of the
burst counter is determined by the MODE input signal. A LOW
input on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and
Burst Write Accesses
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 has
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four WRITE opera-
tions without reasserting the address inputs. ADV/LD must be
driven LOW in order to load the initial address, as described
in the Single Write Access section above. When ADV/LD is
Document #: 38-05353 Rev. *A
Page 7 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
driven HIGH on the subsequent clock rise, the chip enables
Interleaved Burst Address Table
(MODE = Floating or VDD
(CE1, CE2, and CE3) and WE inputs are ignored and the burst
counter is incremented. The correct BW (BWa,b,c,d,e,f,g,h for
CY7C1464AV33 , BWa,b,c,d for CY7C1460AV33 and BWa,b for
CY7C1462AV33) inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
00
A1,A0
01
A1,A0
10
A1,A0
11
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
00
A1,A0
01
A1,A0
10
A1,A0
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > VDD − 0.2V
Min.
Max
Unit
100
mA
tZZS
ZZ > VDD − 0.2V
2tCYC
ns
ns
ns
ns
tZZREC
tZZI
ZZ < 0.2V
2tCYC
0
ZZ active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2tCYC
tRZZI
Truth Table[1, 2, 3, 4, 5, 6, 7]
Address
Used
Operation
CE
H
ZZ
L
ADV/LD WE BWx
OE
CEN CLK
DQ
Deselect Cycle
None
L
X
X
X
X
X
L
L
L-H
L-H
Tri-State
Tri-State
Continue
None
X
L
H
X
Deselect Cycle
Read Cycle
(Begin Burst)
External
Next
L
X
L
L
L
L
L
L
L
L
L
L
H
L
H
X
H
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Data Out (Q)
Data Out (Q)
Tri-State
Read Cycle
(Continue Burst)
L
NOP/Dummy Read External
(Begin Burst)
H
H
X
X
X
X
Dummy Read
(Continue Burst)
Next
X
L
H
L
Tri-State
Write Cycle
(Begin Burst)
External
Next
Data In (D)
Data In (D)
Tri-State
Write Cycle
(Continue Burst)
X
L
H
L
X
L
L
NOP/WRITE ABORT None
(Begin Burst)
H
H
WRITE ABORT
(Continue Burst)
Next
X
H
X
Tri-State
Document #: 38-05353 Rev. *A
Page 8 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Truth Table[1, 2, 3, 4, 5, 6, 7]
Address
Used
Operation
CE
ZZ
ADV/LD WE BWx
OE
CEN CLK
DQ
IGNORE CLOCK
EDGE
Current
X
L
X
X
X
X
H
L-H
-
(Stall)
SLEEP MODE
None
X
H
X
X
X
X
X
X
Tri-State
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BW . See Write Cycle Description table for details.
X
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ and DQP = Tri-state when OE is
s
X
inactive or when the device is deselected, and DQ =data when OE is active.
s
Document #: 38-05353 Rev. *A
Page 9 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Partial Write Cycle Description[1, 2, 3, 8]
Function (CY7C1460AV33)
BWd
X
H
H
H
H
H
H
H
H
L
BWc
X
BWb
X
H
H
L
BWa
X
H
L
WE
H
L
Read
Write – No bytes written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Bytes b, a
H
H
H
H
L
L
L
H
L
L
L
Write Byte c – (DQc and DQPc)
Write Bytes c, a
L
H
H
L
H
L
L
L
Write Bytes c, b
L
LL
L
H
L
Write Bytes c, b, a
L
L
Write Byte d – (DQd and DQPd)
Write Bytes d, a
L
H
H
H
H
L
H
H
L
H
L
L
L
Write Bytes d, b
L
L
H
L
Write Bytes d, b, a
L
L
L
Write Bytes d, c
L
L
H
H
L
H
L
Write Bytes d, c, a
L
L
L
Write Bytes d, c, b
L
L
L
H
L
Write All Bytes
L
L
L
L
Function (CY7C1462AV33)[2,8]
WE
BWb
BWa
Read
H
L
L
L
L
x
H
H
L
x
H
L
Write – No Bytes Written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Both Bytes
H
L
L
Function (CY7C1464AV33)[2,8]
WE
BWx
Read
H
L
L
L
x
Write – No Bytes Written
Write Byte X − (DQx and DQPx)
H
L
Write All Bytes
All BW = L
Note:
8. Table only lists a partial listing of the byte write combinations. Any combinaion of BW
is valid. Appropriate write will be done based on which byte write is active.
[a:d]
Document #: 38-05353 Rev. *A
Page 10 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Test Data-In (TDI)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure . TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 incor-
porates a serial boundary scan test access port (TAP). This
part is fully compliant with 1149.1. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic level.
The
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alter-
nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
0
Bypass Register
TEST-LOGIC
1
RESET
0
2
1
0
0
0
Selection
Circuitry
1
1
1
Instruction Register
31 30 29
Identification Register
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
S
election
0
TDI
TDO
Circuitr
y
.
.
. 2 1
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
x
.
.
.
.
. 2 1
SHIFT-DR
0
SHIFT-IR
0
Boundary Scan Register
1
1
1
1
EXIT1-DR
EXIT1-IR
TCK
TMS
0
0
TAP CONTROLLER
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
UPDATE-DR
UPDATE-IR
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Instruction Register
Test MODE SELECT (TMS)
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Document #: 38-05353 Rev. *A
Page 11 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
When the TAP controller is in the Capture-IR state, the two
SAMPLE Z
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
SAMPLE/PRELOAD
SAMPLE / PRELOAD is a 1149.1 mandatory instruction.
When the SAMPLE / PRELOAD instructions are loaded into
the instruction register and the TAP controller is in the Cap-
ture-DR state, a snapshot of data on the inputs and output pins
is captured in the boundary scan register.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The length of the Boundary
Scan Register for the SRAM in different packages is listed in
the Scan Register Sizes table.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE / PRELOAD instruction. If
this is an issue, it is still possible to capture all other signals
and simply ignore the value of the CK and CK# captured in the
boundary scan register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
TAP Instruction Set
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required - that is, while data
captured is shifted out, the preloaded data can be shifted in.
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
The boundary scan register has a special bit located at bit #89
( for 165-FBGA package) or bit #138 ( for 209 BGA package).
Document #: 38-05353 Rev. *A
Page 12 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR,” the value
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter
Clock
tTCYC
tTF
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
tTH
25
25
tTL
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise
tTDIS
5
ns
ns
0
5
5
5
ns
ns
ns
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
tCS
Hold Times
tTMSH
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tTDIH
tCH
Capture Hold after Clock Rise
Notes:
t
t
9. CS and CH refer to the set-up and hold time requirements of latching data from the boundary scan register.
10.Test conditions are specified using the load in TAP AC test Conditions. t /t = 1ns.
R
F
Document #: 38-05353 Rev. *A
Page 13 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ................................................ VSS to 3.3V
Input rise and fall times..................... ..............................1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Input pulse levels ........................................ VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels................... ......................1.25V
Output reference levels .................. ..............................1.25V
Test load termination supply voltage .................... ........1.25V
2.5V TAP AC Output Load Equivalent
3.3V TAP AC Output Load Equivalent
1.25V
1.5V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
20pF
ZO= 50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; Vdd =3.135V to 3.6V unless otherwise noted)[11]
Parameter
VOH1
Description
Output HIGH Voltage IOH = -4.0 mA,VDDQ = 3.3V
OH = -1.0 mA,VDDQ = 2.5V
Test Conditions
Min.
2.4
2.0
2.9
2.1
Max.
Unit
V
I
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage IOH = -100 µA
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
V
V
Output LOW Voltage IOL = 8.0 mA
0.4
0.4
V
I
OL = 1.0 mA
V
Output LOW Voltage IOL = 100 µA
0.2
V
VDDQ = 2.5V
0.2
V
Input HIGH Voltage
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
2.0
1.7
-0.3
-0.3
-5
VDD + 0.3
VDD + 0.3
0.8
V
V
VIL
Input LOW Voltage
V
VDDQ = 2.5V
0.7
V
IX
Input Load Current
GND < VIN < VDDQ
5
µA
Identification Register Definitions
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33
Instruction Field
Revision Number (31:29)
Device Depth (28:24)[12]
(1 Mbit ×36)
(2 Mbit ×18)
(512K ×72)
Description
000
000
000
Describes the version number.
Reserved for Internal Use
01011
01011
01011
Architecture/Memory Type(23:18)
001000
001000
001000
Defines memory type and archi-
tecture
Bus Width/Density(17:12)
100111
010111
110111
Defines width and density
Cypress JEDEC ID Code (11:1)
00000110100
00000110100
00000110100 Allows unique identification of
SRAM vendor.
ID Register Presence Indicator (0)
1
1
1
Indicates the presence of an ID
register.
Notes:
11. All voltages referenced to VSS (GND).
12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: 38-05353 Rev. *A
Page 14 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Scan Register Sizes
Register Name
Bit Size (×36)
Bit Size (×18)
Bit Size (×72)
Instruction
3
1
3
1
3
1
Bypass
ID
32
89
-
32
89
-
32
-
Boundary Scan Order-165FBGA
Boundary Scan Order- 209BGA
138
Identification Codes
Instruction
EXTEST
Code
Description
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document #: 38-05353 Rev. *A
Page 15 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
165-Ball fBGA Boundary Scan Order [13]
CY7C1460AV33 (1 Mbit x 36)
CY7C1460AV33 (1 Mbit x 36)
Bit#
1
Ball ID
N6
Bit#
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
Ball ID
A7
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
Bit#
83
84
85
86
87
88
89
Ball ID
P2
2
N7
R4
3
N10
P11
P8
P4
4
N5
5
P6
6
R8
R6
7
R9
Internal
8
P9
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
CY7C1462AV33 (2 Mbit x 18)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
1
N6
N7
2
3
10N
P11
P8
4
5
6
R8
7
R9
8
P9
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
G1
D2
E2
F2
H10
G11
F11
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
A9
G2
H1
H3
J1
K1
L1
M1
J2
K2
L2
H10
G11
F11
E11
D11
G10
F10
E10
D10
C11
M2
N1
N2
P1
R1
R2
P3
R3
B9
C10
A8
B8
Note:
13. Bit# 89 is preset HIGH.
Document #: 38-05353 Rev. *A
Page 16 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
165-Ball fBGA Boundary Scan Order [13]
CY7C1462AV33 (2 Mbit x 18)
Bit#
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Ball ID
A11
B11
A10
B10
A9
Bit#
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
G1
D2
E2
F2
G2
H1
H3
J1
B9
C10
A8
B8
K1
A7
L1
B7
M1
J2
B6
A6
K2
B5
L2
A5
M2
N1
N2
P1
A4
B4
B3
A3
R1
R2
P3
A2
B2
C2
B1
R3
P2
A1
R4
P4
C1
D1
E1
N5
P6
F1
R6
Internal
Document #: 38-05353 Rev. *A
Page 17 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
209-Ball BGA Boundary Scan Order [13, 14]
CY7C1464AV33 (512K x 72)
CY7C1464AV33 (512K x 72)
Bit#
1
Ball ID
W6
V6
Bit#
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Ball ID
J6
Bit#
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
Ball ID
D6
G6
H6
C6
B6
A6
A5
B5
C5
D5
D4
C4
A4
B4
C3
B3
A3
A2
A1
B2
B1
C2
C1
D2
D1
E1
E2
F2
Bit#
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
Ball ID
K1
2
F6
N6
K3
3
U6
K8
4
W7
V7
K9
K4
5
K10
J11
J10
H11
H10
G11
G10
F11
F10
E10
E11
D11
D10
C11
C10
B11
B10
A11
A10
C9
K6
6
U7
K2
7
T7
L2
8
V8
L1
9
U8
M2
M1
N2
N1
P2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
T8
V9
U9
P6
W11
W10
V11
V10
U11
U10
T11
T10
R11
R10
P11
P10
N11
N10
M11
M10
L11
L10
K11
M6
P1
R2
R1
T2
T1
U2
U1
V2
V1
W2
W1
T6
B9
A9
U3
V3
D8
C8
T4
B8
F1
T5
A8
G1
G2
H2
H1
J2
U4
V4
D7
C7
W5
V5
B7
L6
A7
U5
Internal
J1
Note:
14. Bit# 138 is preset HIGH.
Document #: 38-05353 Rev. *A
Page 18 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Temperature
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
DC to Outputs in Tri-State................... –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Range
VDD
VDDQ
Commercial 0°C to +70°C 3.3V–5%/+10% 2.5V –5% to
VDD
Electrical Characteristics Over the Operating Range[15, 16]
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
3.6
Unit
V
VDDQ
VOH
VOL
VIH
VIL
VDDQ = 3.3V
VDDQ = 2.5V
VDD
V
2.625
V
Output HIGH Voltage
Output LOW Voltage
VDD = Min., IOH = −4.0 mA, VDDQ = 3.3V
VDD = Min., IOH= −1.0 mA, VDDQ = 2.5V
VDD = Max., IOL= 8.0 mA, VDDQ = 3.3V
VDD = Max., IOL= 1.0 mA, VDDQ = 2.5V
V
2.0
V
0.4
V
0.4
VDD + 0.3V
VDD + 0.3V
0.8
V
Input HIGH Voltage[15] VDDQ = 3.3V
2.0
1.7
V
VDDQ = 2.5V
V
Input LOW Voltage[15] VDDQ = 3.3V
VDDQ = 2.5V
–0.3
–0.3
–5
V
0.7
V
IX
Input Load Current ex- GND ≤ VI ≤ VDDQ
cept ZZ and MODE
5
µA
Input Current of MODE Input = VSS
Input = VDD
–5
–30
–5
µA
µA
30
Input Current of ZZ
Input = VSS
Input = VDD
µA
5
µA
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
5
µA
VDD Operating Supply VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz
475
425
375
225
225
225
100
mA
mA
mA
mA
mA
mA
mA
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
ISB1
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz
VIN ≥ VIH or VIN ≤ VIL, f = fMAX =
1/tCYC
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
ISB2
Automatic CE
Power-down
Current—CMOS Inputs f = 0
Max. VDD, Device Deselected, All speed grades
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
ISB3
Automatic CE
Power-down
Current—CMOS Inputs f = fMAX = 1/tCYC
Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz
200
200
200
110
mA
mA
mA
mA
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
ISB4
Automatic CE
Max. VDD, Device Deselected, All speed grades
Power-down
Current—TTL Inputs
VIN ≥ VIH or VIN ≤ VIL, f = 0
Shaded areas contain advance information.
Notes:
15. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2).
16. T : Assumes a linear ramp from 0V to VDD (min.) within 200ms. During this time VIH < VDD and VDDQ < VDD.
Power-up
Document #: 38-05353 Rev. *A
Page 19 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Capacitance[17]
Parameter
Description
Test Conditions
100 TQFP
165 FBGA
209 FBGA
Unit
pF
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
DD = 2.5V VDDQ = 2.5V
6.5
3
5
5
7
5
5
7
V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
5.5
pF
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
R = 317Ω
3.3V
OUTPUT
R = 50Ω
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
INCLUDING
V = 1.5V
T
(a)
JIG AND
SCOPE
(b)
(c)
2.5V I/O Test Load
OUTPUT
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R =1538Ω
≤ 1ns
INCLUDING
JIG AND
SCOPE
≤ 1ns
V = 1.25V
T
(a)
(b)
(c)
Thermal Resistance[17]
Parameters
Description
Test Conditions
100 TQFP
165 FBGA
209 FBGA
Unit
QJA
Thermal Resistance
(Junction to Ambient)
Testconditionsfollowstandard
test methods and procedures
for measuring thermal
25.21
20.8
25.31
°C/W
QJC
Thermal Resistance
(Junction to Case)
2.28
3.2
4.48
°C/W
impedence, per EIA / JESD51.
Switching Characteristics Over the Operating Range [22, 23]
250
200
167
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
[18]
tPower
VCC (typical) to the first access read or write
1
1
1
ms
Clock
tCYC
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
4.0
5.0
6.0
ns
MHz
ns
FMAX
tCH
250
200
167
1.5
1.5
2.0
2.0
2.4
2.4
tCL
Clock LOW
ns
Output Times
tCO
Data Output Valid After CLK Rise
OE LOW to Output Valid
2.6
2.6
3.2
3.0
3.4
3.4
ns
ns
ns
ns
tEOV
tDOH
Data Output Hold After CLK Rise
Clock to High-Z[19, 20, 21]
1.0
1.5
1.5
tCHZ
2.6
3.0
3.4
Shaded areas contain advance information.
Notes:
17. Tested initially and after any design or process changes that may affect these parameters.
18. This part has a voltage regulator internally; tpower is the time power needs to be supplied above Vdd minimum initially, before a Read or Write operation can be
initiated.
19. t
, t
, t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ EOLZ
EOHZ
20. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
EOHZ
EOLZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
22. Timing reference is 1.5V when V
3.3V and is 1.25V when V
2.5V.
DDQ=
DDQ=
23. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05353 Rev. *A
Page 20 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)[22, 23]
250
200
167
Parameter
tCLZ
Description
Clock to Low-Z[19, 20, 21]
HIGH to Output High-Z[19, 20, 21]
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ns
1.0
1.3
1.5
tEOHZ
tEOLZ
Set-up Times
tAS
2.6
3.0
3.4
ns
OE
OE LOW to Output Low-Z[19, 20, 21]
0
0
0
ns
Address Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
1.2
1.2
1.2
1.2
1.2
1.2
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tDS
tCENS
tWES
CEN Set-up Before CLK Rise
WE, BWx Set-up Before CLK Rise
tALS
ADV/LD Set-up Before CLK Rise
Chip Select Set-up
tCES
Hold Times
tAH
Address Hold After CLK Rise
Data Input Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tDH
tCENH
tWEH
CEN Hold After CLK Rise
WE, BWx Hold After CLK Rise
tALH
ADV/LD Hold after CLK Rise
tCEH
Chip Select Hold After CLK Rise
Switching Waveforms
Read/Write/Timing[24,25,26]
1
2
3
4
5
6
7
8
9
10
t
CYC
t
CLK
t
t
t
CENS CENH
CL
CH
CEN
t
t
CES
CEH
CE
ADV/LD
WE
BW
x
A1
A2
A4
CO
A3
A5
A6
A7
ADDRESS
t
t
t
t
DS
DH
t
t
t
DOH
OEV
CLZ
CHZ
t
t
AS
AH
Data
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
In-Out (DQ)
t
OEHZ
t
DOH
t
OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes:
24. For this waveform ZZ is tied low.
25. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH,CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
26. Order of the Burst sequence is determined by the status of the MODE (0=Linear, 1=Interleaved).Burst operations are optional.
Document #: 38-05353 Rev. *A
Page 21 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Switching Waveforms (continued)
NOP,STALL and DESELECT Cycles[24,25,27]
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
A1
A2
A3
A4
A5
ADDRESS
t
CHZ
D(A4)
D(A1)
Q(A2)
Q(A3)
Q(A5)
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
ZZ ModeTiming[28,29]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
28. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
29. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05353 Rev. *A
Page 22 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
250
CY7C1460AV33-250AXC
CY7C1462AV33-250AXC
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x
1.4 mm)
Commercial
CY7C1460AV33-250BZC
CY7C1462AV33-250BZC
BB165C 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1464AV33-250BGC
BB209A 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1460AV33-250BZXC
CY7C1462AV33-250BZXC
BB165C Lead-Free 165-ball Fine Pitch Ball Grid Array (15 x
17 x 1.4 mm)
CY7C1464AV33-250BGXC
BB209A Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76
mm)
200
CY7C1460AV33-200AXC
CY7C1462AV33-200AXC
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x
1.4 mm)
CY7C1460AV33-200BZC
CY7C1462AV33-200BZC
BB165C 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1464AV33-200BGC
BB209A 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1460AV33-200BZXC
CY7C1462AV33-200BZXC
BB165C Lead-Free 165-ball Fine Pitch Ball Grid Array (15 x
17 x 1.4 mm)
CY7C1464AV33-200BGXC
BB209A Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76
mm)
167
CY7C1460AV33-167AXC
CY7C1462AV33-167AXC
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x
1.4 mm)
CY7C1460AV33-167BZC
CY7C1462AV33-167BZC
BB165C 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1464AV33-167BGC
BB209A 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1460AV33-167BZXC
CY7C1462AV33-167BZXC
BB165C Lead-Free 165-ball Fine Pitch Ball Grid Array (15 x
17 x 1.4 mm)
CY7C1464AV33-167BGXC
BB209A Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76
mm)
Shaded areas contain advance information.
Document #: 38-05353 Rev. *A
Page 23 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05353 Rev. *A
Page 24 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Package Diagrams (continued)
165-Ball FBGA (15 x 17 x 1.40 mm) BB165C
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
Ø0.45 0.05ꢀ1ꢁ5ꢂX
1
2
3
4
5
ꢁ
7
8
9
10
11
11 10
9
8
7
ꢁ
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
1.00
5.00
10.00
B
15.00 0.10
0.15ꢀ4ꢂX
SEATING PLANE
C
51-85165-*A
Document #: 38-05353 Rev. *A
Page 25 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Package Diagrams (continued)
209-Ball FBGA (14 x 22 x 1.76 mm) BB209A
51-85167-**
ZBT is a registered trademark of Integrated Device Technology. No Bus Latency and NoBL are trademarks of Cypress Semicon-
ductor. All product and company names mentioned in this document are trademarks of their respective holders.
Document #: 38-05353 Rev. *A
Page 26 of 27
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Document History Page
Document Title: CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM
with NoBL™ Architecture
Document Number: 38-05353
Orig. of
REV.
ECN No. Issue Date Change
Description of Change
**
254911
See ECN
SYT
New Datasheet
Part number changed from previous revision. New and old part number differ
by the letter “A”
*A
303533
See ECN
SYT
Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209
FBGA on Page # 5
Changed the test condition from VDD = Min to VDD = Max for VOL in the
Electrical Characteristics table.
Replaced ΘJA and ΘJC from TBD to respective Thermal Values for All
Packages on the Thermal Resistance Table
Changed IDD from 450, 400 & 350 mA to 475, 425 & 375 mA for 250, 200
and 167 Mhz respectively
Changed ISB1 from 190, 180 and 170 mA to 225 mA for 250, 200 and 167
Mhz respectively.
Changed ISB2 from 80 mA to 100 mA for all frequencies
Changed ISB3 from 180, 170 & 160 mA to 200 mA for 250, 200 and 167 Mhz
respectively.
Changed ISB4 from 100 mA to 110 mA for all frequencies
Changed CIN ,CCLK and CI/O to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP
Package.
Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for 200 Mhz
Speed Bin
Added lead-free information for 100-Pin TQFP and 165 FBGA and 209 BGA
packages
Document #: 38-05353 Rev. *A
Page 27 of 27
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