CY7C1472V33-167AXIT [CYPRESS]
ZBT SRAM, 4MX18, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100;
| 型号： | CY7C1472V33-167AXIT |
| 厂家： | 
CYPRESS |
| 描述： | ZBT SRAM, 4MX18, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总40页 (文件大小：738K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1470V33
CY7C1472V33
CY7C1474V33
72-Mbit (2M × 36/4M × 18/1M × 72)
Pipelined SRAM with NoBL™ Architecture
72-Mbit (2M
× 36/4M × 18/1M × 72) Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
■ Pin compatible and functionally equivalent to ZBT
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
3.3 V, 2M × 36/4M × 18/1M × 72 synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL logic, respectively.
They are designed to support unlimited true back-to-back
read/write operations with no wait states. The CY7C1470V33,
CY7C1472V33, and CY7C1474V33 are equipped with the
advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1470V33, CY7C1472V33, and CY7C1474V33 are pin
compatible and functionally equivalent to ZBT devices.
■ Supports 200 MHz Bus operations with zero wait states
❐ Available speed grades are 200 and 167 MHz
■ Internally self timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte write capability
■ Single 3.3 V power supply
■ 3.3 V/2.5 V I/O power supply
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
■ Fast clock-to-output time
❐ 3.0 ns (for 200 MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self timed writes
Write operations are controlled by the byte write selects
(BWa–BWh for CY7C1474V33, BWa–BWd for CY7C1470V33
and BWa–BWb for CY7C1472V33) and a write enable (WE)
input. All writes are conducted with on-chip synchronous self
timed write circuitry.
■ CY7C1470V33 available in JEDEC-standard Pb-free 100-pin
TQFP, and non Pb-free 165-ball FBGA package.
CY7C1472V33 available in JEDEC-standard Pb-free 100-pin
TQFP. CY7C1474V33 available in non Pb-free 209-ball FBGA
package
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. In order to avoid bus
contention, the output drivers are synchronously tristated during
the data portion of a write sequence.
■ IEEE 1149.1 JTAG boundary scan compatible
■ Burst capability – linear or interleaved burst order
■ “ZZ” sleep mode option and stop clock option
For a complete list of related documentation, click here.
Selection Guide
Description
Maximum access time
200 MHz
3.0
167 MHz Unit
3.4
450
120
ns
Maximum operating current
500
mA
mA
Maximum CMOS standby current
120
Errata: For information on silicon errata, see Errata on page 35. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05289 Rev. *X
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 5, 2018
CY7C1470V33
CY7C1472V33
CY7C1474V33
Logic Block Diagram – CY7C1470V33
ADDRESS
REGISTER
A0, A1,
A
0
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
ADV/LD
CLK
CEN
C
C
WRITE ADDRESS
REGISTER
WRITE ADDRESS
REGISTER 2
1
O
U
T
O
U
T
S
E
D
A
T
P
U
T
N
S
P
U
T
ADV/LD
A
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
R
E
G
I
MEMORY
ARRAY
B
U
F
F
E
R
S
S
T
E
E
R
I
DQ s
WRITE
DRIVERS
BW
a
DQ P
DQ P
DQ P
DQ P
a
b
c
A
M
P
BW
BW
BW
b
c
S
T
E
R
S
d
d
S
WE
E
E
N
G
INPUT
REGISTER
INPUT
REGISTER 0
E
E
1
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1472V33
ADDRESS
REGISTER
A0, A1,
A
0
A1
A0
A1'
Q1
D1
D0
A0'
Q0
BURST
LOGIC
MODE
ADV/LD
CLK
CEN
C
C
WRITE ADDRESS
REGISTER
WRITE ADDRESS
REGISTER 2
1
O
O
U
T
U
T
P
U
T
S
E
P
U
T
D
A
T
ADV/LD
N
S
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
R
E
G
I
MEMORY
ARRAY
E
B
U
F
F
E
R
S
DQ s
DQ P
DQ P
WRITE
DRIVERS
BW
BW
a
S
T
E
E
R
I
A
M
P
a
b
S
T
E
R
S
b
S
N
G
WE
E
E
INPUT
REGISTER
INPUT
REGISTER 0
E
E
1
OE
CE1
CE2
CE3
READ LOGIC
Sleep
Control
ZZ
Document Number: 38-05289 Rev. *X
Page 2 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Logic Block Diagram – CY7C1474V33
ADDRESS
REGISTER
A0, A1,
A
0
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
ADV/LD
CLK
CEN
C
C
WRITE ADDRESS
REGISTER
WRITE ADDRESS
REGISTER 2
1
O
U
T
O
U
T
P
U
T
S
E
P
U
T
D
A
T
ADV/LD
N
S
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
BW
BW
BW
BW
BW
a
R
E
G
I
MEMORY
ARRAY
E
B
U
F
F
E
R
S
DQ s
DQ P
DQ P
DQ P
DQ P
DQ P
DQ P
DQ P
DQ P
WRITE
DRIVERS
b
S
T
E
E
R
I
A
M
P
a
c
d
e
S
T
E
R
S
b
c
S
d
e
f
BW
f
N
G
BW
g
E
E
BW
h
g
h
WE
INPUT
REGISTER
INPUT
REGISTER 0
E
E
1
OE
CE1
CE2
CE3
READ LOGIC
Sleep
Control
ZZ
Document Number: 38-05289 Rev. *X
Page 3 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Contents
Pin Configurations ...........................................................5
Pin Definitions ..................................................................8
Functional Overview ......................................................10
Single Read Accesses ..............................................10
Burst Read Accesses ................................................10
Single Write Accesses ...............................................10
Burst Write Accesses ................................................11
Sleep Mode ...............................................................11
Interleaved Burst Address Table ...............................11
Linear Burst Address Table .......................................11
ZZ Mode Electrical Characteristics ............................11
Truth Table ......................................................................12
Partial Write Cycle Description .....................................13
Partial Write Cycle Description .....................................13
Partial Write Cycle Description .....................................14
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................15
Disabling the JTAG Feature ......................................15
Test Access Port (TAP) .............................................15
PERFORMING A TAP RESET ..................................15
TAP REGISTERS ......................................................15
TAP Instruction Set ...................................................15
TAP Controller State Diagram .......................................17
TAP Controller Block Diagram ......................................18
TAP Timing Diagram ......................................................18
TAP AC Switching Characteristics ...............................19
3.3 V TAP AC Test Conditions .......................................20
3.3 V TAP AC Output Load Equivalent .........................20
2.5 V TAP AC Test Conditions .......................................20
2.5 V TAP AC Output Load Equivalent .........................20
TAP DC Electrical Characteristics
Scan Register Sizes .......................................................21
Identification Codes .......................................................21
Boundary Scan Exit Order .............................................22
Boundary Scan Exit Order .............................................23
Maximum Ratings ...........................................................24
Operating Range .............................................................24
Neutron Soft Error Immunity .........................................24
Electrical Characteristics ...............................................24
Capacitance ....................................................................25
Thermal Resistance ........................................................25
AC Test Loads and Waveforms .....................................26
Switching Characteristics ..............................................27
Switching Waveforms ....................................................28
Ordering Information ......................................................30
Ordering Code Definitions .........................................30
Package Diagrams ..........................................................31
Acronyms ........................................................................34
Document Conventions .................................................34
Units of Measure .......................................................34
Errata ...............................................................................35
Part Numbers Affected ..............................................35
Product Status ...........................................................35
Ram9 NoBL ZZ Pin Issues Errata Summary .............35
Document History Page .................................................36
Sales, Solutions, and Legal Information ......................40
Worldwide Sales and Design Support .......................40
Products ....................................................................40
PSoC® Solutions ......................................................40
Cypress Developer Community .................................40
Technical Support .....................................................40
and Operating Conditions .............................................20
Identification Register Definitions ................................21
Document Number: 38-05289 Rev. *X
Page 4 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout [1]
DQPc
DQc
DQc
1
2
3
4
5
6
7
8
NC
NC
NC
DDQ
1
2
3
4
5
6
7
8
A
NC
NC
78
DQPb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
79
V
V
DDQ
V
V
V
NC
DQPa
DQa
DQa
DDQ
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
SS
V
V
V
SS
SS
SS
DQc
DQc
NC
NC
DQb
DQb
DQb
DQb
DQb
DQc
DQc
9
DQb
9
V
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
V
DDQ
DDQ
V
V
DQa
DQa
V
NC
DDQ
DDQ
DQc
DQc
NC
DQb
DQb
DQb
DQb
NC
V
SS
SS
V
V
DD
NC
DD
CY7C1470V33
(2M × 36)
CY7C1472V33
(4M × 18)
NC
NC
V
V
ZZ
DD
DD
V
V
SS
SS
ZZ
DQa
DQa
DQd
DQb
DQa
DQa
DQd
DQb
DDQ
V
V
DDQ
V
V
V
DQa
DQa
NC
NC
V
V
DDQ
DDQ
V
V
SS
V
SS
SS
SS
DQd
DQd
DQd
DQd
DQa
DQa
DQb
DQb
DQa DQPb
DQa
NC
V
SS
V
V
SS
SS
SS
V
V
DDQ
DDQ
V
DDQ
DDQ
DQd
DQd
DQPd
DQa
DQa
DQPa
NC
NC
NC
NC
NC
NC
Note
1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see Errata on page 35.
Document Number: 38-05289 Rev. *X
Page 5 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Pin Configurations (continued)
Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm) pinout [2]
CY7C1470V33 (2M × 36)
1
2
A
3
4
5
6
7
8
9
A
10
A
11
NC
NC/576M
A
B
C
D
CE3
CLK
ADV/LD
OE
CE
BW
BW
BW
b
CEN
WE
1
c
NC/1G
A
CE2
A
A
NC
DQ
NC
BW
V
d
a
DQP
NC
DQ
V
V
V
V
V
V
V
V
V
V
V
DQP
DQ
c
DDQ
DDQ
SS
SS
SS
SS
SS
DDQ
DDQ
b
DQ
V
V
V
V
V
V
V
V
c
c
DD
DD
SS
SS
SS
DD
b
b
DQ
DQ
DQ
DQ
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQ
DQ
DQ
DQ
DQ
DQ
E
F
c
c
c
c
DDQ
DDQ
DDQ
SS
SS
SS
DD
DDQ
DDQ
DDQ
b
b
b
b
DQ
V
V
V
c
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
DD
b
b
DQ
V
V
V
G
H
J
c
SS
SS
DD
NC
NC
DQ
NC
V
V
V
NC
NC
DQ
ZZ
SS
SS
DD
DQ
V
V
V
V
V
DQ
a
d
d
DDQ
DDQ
DDQ
DDQ
SS
SS
DD
DDQ
DDQ
DDQ
DDQ
a
DQ
DQ
DQ
DQ
V
V
V
V
V
V
V
V
V
V
V
DQ
DQ
DQ
DQ
DQ
DQ
K
L
d
d
d
d
DD
DD
DD
SS
SS
SS
SS
SS
DD
a
a
a
a
a
a
DQ
V
V
V
d
SS
SS
DD
DQ
V
V
V
V
V
M
N
P
d
SS
SS
DD
DQP
NC
A
V
NC
NC
A1
NC
V
NC
A
DQP
a
d
DDQ
SS
SS
DDQ
NC/144M
MODE
A
TDI
TDO
A
NC/288M
A
A
A
A
A
A
A
TMS
A0
TCK
A
A
R
Note
2. Errata: The ZZ ball (H11) needs to be externally connected to ground. For more information, see Errata on page 35.
Document Number: 38-05289 Rev. *X
Page 6 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Pin Configurations (continued)
Figure 3. 209-ball FBGA (14 × 22 × 1.76 mm) pinout [3]
CY7C1474V33 (1M × 72)
1
2
3
4
5
6
7
8
9
10
11
DQg
DQg
DQg
DQg
A
CE2
A
ADV/LD
WE
A
A
CE3
A
DQb
DQb
DQb
DQb
DQb
DQb
DQb
A
B
BWSc
BWSg
NC
BWSb
BWSf
DQg
DQg
DQg
DQg
DQPc
DQc
BWSh
VSS
BWSd NC/576M CE1
NC
NC
BWSe
NC
BWSa
VSS
C
D
NC/1G
OE
NC
DQb
DQPb
DQf
E
F
DQPg
DQc
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
NC
VDD
VSS
VDD
DQPf
DQf
VSS
VDDQ
VSS
VSS
VDDQ
VSS
G
H
J
DQc
DQc
DQc
NC
VDDQ
VSS
DQf
DQf
DQf
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
A
DQc
DQc
NC
NC
DQf
DQf
NC
VDDQ
DQc
NC
VDDQ
VDDQ
CLK
VDDQ
NC
NC
DQf
NC
K
L
CEN
NC
NC
NC
DQh
DQh
DQh
VDDQ
VSS
VDDQ
VSS
VDDQ
VDDQ
VSS
VDDQ
VSS
DQa
DQa
DQa
M
N
P
R
T
NC
VSS
VDDQ
VSS
VDDQ
NC
DQh
DQh
DQh
VSS
VDD
VSS
DQa
DQa
DQa
VDDQ
DQh
DQh
DQPd
DQd
DQd
VDDQ
VSS
NC
ZZ
DQa
DQa
DQPa
DQe
DQe
VSS
VDDQ
VDDQ
VDD
NC
A
DQPh
DQd
DQd
DQd
DQd
VDDQ
VDD
DQPe
DQe
DQe
DQe
DQe
VSS
VSS
NC
A
MODE
A
U
V
W
A
NC/288M
NC/144M
A
A
A1
A
DQd
DQd
A
A
A
A
DQe
DQe
TDI
TDO
TCK
A0
A
TMS
Note
3. Errata: The ZZ ball (P6) needs to be externally connected to ground. For more information, see Errata on page 35.
Document Number: 38-05289 Rev. *X
Page 7 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Pin Definitions
Pin Name
I/O Type
Pin Description
A0, A1, A
Input-
synchronous
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK.
BWa, BWb,
Input-
Byte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
BWc, BWd, synchronous the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc
BWe, BWf,
BWg, BWh
and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf controls DQf and DQPf,
BWg controls DQg and DQPg, BWh controls DQh and DQPh.
WE
Input-
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
Input- Advance/load input used to advance the on-chip address counter or load a new address. When
synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address
can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in
order to load a new address.
CLK
CE1
CE2
CE3
OE
Input-
clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
Input-
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select/deselect the device.
Input-
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device.
Input-
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device.
Input-
Output enable, active LOW. Combined with the synchronous logic block inside the device to control
asynchronous the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted
HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the data portion of a write
sequence, during the first clock when emerging from a deselected state and when the device has been
deselected.
CEN
DQS
Input-
Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
I/O-
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0]
during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd
are placed in a tristate condition. The outputs are automatically tristated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
DQPX
I/O-
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQX. During write
synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and
DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, DQPg is controlled
by BWg, DQPh is controlled by BWh.
MODE
TDO
TDI
Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled
LOW selects the linear burst order. MODE should not change states during operation. When left floating
MODE will default HIGH, to an interleaved burst order.
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
output
synchronous
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
input
Synchronous
Document Number: 38-05289 Rev. *X
Page 8 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
TMS
Test mode This pin controls the test access port state machine. Sampled on the rising edge of TCK.
select
synchronous
TCK
VDD
JTAG clock Clock input to the JTAG circuitry.
Power supply Power supply inputs to the core of the device.
VDDQ
I/O power Power supply for the I/O circuitry.
supply
VSS
NC
Ground
Ground for the device. Should be connected to ground of the system.
No connects. This pin is not connected to the die.
–
–
NC (144M,
288M,
These pins are not connected. They will be used for expansion to the 144M, 288M, 576M, and 1G
densities.
576M, 1G)
ZZ[4]
Input-
ZZ “Sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. During normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.
Note
4. Errata: The ZZ pin needs to be externally connected to ground. For more information, see Errata on page 35.
Document Number: 38-05289 Rev. *X
Page 9 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
counter is determined by the MODE input signal. A LOW input
on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and A1
in the burst sequence, and will wrap-around when incremented
sufficiently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (read or write) is maintained throughout the
burst sequence.
Functional Overview
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
synchronous-pipelined burst NoBL SRAMs designed specifically
to eliminate wait states during write/read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
clock enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data outputs
pass through output registers controlled by the rising edge of the
clock. Maximum access delay from the clock rise (tCO) is 3.0 ns
(200 MHz device).
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address inputs is
loaded into the address register. The write signals are latched
into the control logic block.
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW[x] can be used to conduct byte write
operations.
On the subsequent clock rise the data lines are automatically
tristated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
for
CY7C1474V33,
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self timed write circuitry.
DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 and DQa,b/DQPa,b for
CY7C1472V33). In addition, the address for the subsequent
access (read/write/deselect) is latched into the address register
(provided the appropriate control signals are asserted).
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW after the device has been deselected in
order to load a new address for the next operation.
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 and DQa,b/DQPa,b for
CY7C1472V33) (or a subset for byte write operations, see Write
Cycle Description table for details) inputs is latched into the
device and the write is complete.
for
CY7C1474V33,
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus within 3.0 ns (200 MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW in order for the device to
drive out the requested data. During the second clock, a
subsequent operation (read/write/deselect) can be initiated.
Deselecting the device is also pipelined. Therefore, when the
SRAM is deselected at clock rise by one of the chip enable
signals, its output will tristate following the next clock rise.
The data written during the write operation is controlled by BW
(BWa,b,c,d,e,f,g,h for CY7C1474V33, BWa,b,c,d for CY7C1470V33
and BWa,b for CY7C1472V33) signals. The CY7C1470V33,
CY7C1472V33, and CY7C1474V33 provides byte write
capability that is described in the Write Cycle Description table.
Asserting the write enable input (WE) with the selected byte write
select (BW) input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self timed Write mechanism has been
provided to simplify the write operations. Byte write capability
has been included in order to greatly simplify read/modify/write
sequences, which can be reduced to simple byte write
operations.
Because
the
CY7C1470V33,
CY7C1472V33,
and
CY7C1474V33 are common I/O devices, data should not be
driven into the device while the outputs are active. The output
enable (OE) can be deasserted HIGH before presenting data to
the DQ and DQP (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for
CY7C1474V33, DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 and
DQa,b/DQPa,b for CY7C1472V33) inputs. Doing so will tristate
the output drivers. As a safety precaution, DQ and DQP
Burst Read Accesses
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 have
an on-chip burst counter that allows the user the ability to supply
a single address and conduct up to four reads without
reasserting the address inputs. ADV/LD must be driven LOW in
order to load a new address into the SRAM, as described in the
Single Read Accesses section above. The sequence of the burst
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
for
CY7C1474V33,
DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 and DQa,b/DQPa,b for
CY7C1472V33) are automatically tristated during the data
portion of a write cycle, regardless of the state of OE.
Document Number: 38-05289 Rev. *X
Page 10 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Burst Write Accesses
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 has an
on-chip burst counter that allows the user the ability to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW in
order to load the initial address, as described in the Single Write
Accesses section above. When ADV/LD is driven HIGH on the
subsequent clock rise, the chip enables (CE1, CE2, and CE3)
and WE inputs are ignored and the burst counter is incremented.
The correct BW (BWa,b,c,d,e,f,g,h for CY7C1474V33, BWa,b,c,d for
CY7C1470V33 and BWa,b for CY7C1472V33) inputs must be
driven in each cycle of the burst write in order to write the correct
bytes of data.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min
Max
120
2tCYC
–
Unit
mA
ns
ZZ VDD 0.2 V
–
tZZS
ZZ VDD 0.2 V
ZZ 0.2 V
–
2tCYC
–
tZZREC
tZZI
ns
ZZ active to sleep current
This parameter is sampled
2tCYC
–
ns
tRZZI
ZZ Inactive to exit sleep current This parameter is sampled
0
ns
Document Number: 38-05289 Rev. *X
Page 11 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Truth Table
The Truth Table for parts CY7C1470V33/CY7C1472V33/CY7C1474V33 is as follows. [5, 6, 7, 8, 9, 10, 11]
Operation
Address Used CE ZZ ADV/LD WE BWx OE CEN CLK
DQ
Deselect cycle
None
None
H
X
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
X
X
H
X
H
X
L
X
X
X
X
X
X
L
X
X
L
L
L
L
L
L
L
L
L
L
L
H
X
L–H
L–H
Tri-state
Tri-state
Continue deselect cycle
Read cycle (begin burst)
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Write cycle (continue burst)
NOP/write abort (begin burst)
Write abort (continue burst)
Ignore clock edge (stall)
Sleep mode
External
Next
L–H Data out (Q)
L–H Data out (Q)
X
L
H
L
L
External
Next
H
H
X
X
X
X
X
X
L–H
L–H
Tri-state
Tri-state
X
L
H
L
External
Next
L–H Data in (D)
L–H Data in (D)
X
L
H
L
X
L
L
None
H
H
X
X
L–H
L–H
L–H
X
Tri-state
Tri-state
–
Next
X
X
X
H
X
X
X
X
X
Current
None
Tri-state
Notes
5. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = 0 signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
6. Write is defined by WE and BW
. See Write Cycle Description table for details.
[a:d]
7. When a write cycle is detected, all I/Os are tristated, even during byte writes.
8. The DQ and DQP pins are controlled by the current cycle and the OE signal.
9. CEN = H inserts wait states.
10. Device will power-up deselected and the I/Os in a tristate condition, regardless of OE.
11. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQ and DQP
= tristate when OE is
s
[a:d]
inactive or when the device is deselected, and DQ = data when OE is active.
s
Document Number: 38-05289 Rev. *X
Page 12 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Partial Write Cycle Description
The partial write cycle description for part CY7C1470V33 is as follows. [12, 13, 14, 15]
Function (CY7C1470V33)
WE
H
L
BWd
X
H
H
H
H
H
H
H
H
L
BWc
X
H
H
H
H
L
BWb
X
H
H
L
BWa
X
H
L
Read
Write – no bytes written
Write byte a – (DQa and DQPa)
Write byte b – (DQb and DQPb)
Write bytes b, a
L
L
H
L
L
L
Write byte c – (DQc and DQPc)
Write bytes c, a
L
H
H
L
H
L
L
L
Write bytes c, b
L
L
H
L
Write bytes c, b, a
L
L
L
Write byte d – (DQd and DQPd)
Write bytes d, a
L
H
H
H
H
L
H
H
L
H
L
L
L
Write bytes d, b
L
L
H
L
Write bytes d, b, a
L
L
L
Write bytes d, c
L
L
H
H
L
H
L
Write bytes d, c, a
L
L
L
Write bytes d, c, b
L
L
L
H
L
Write all bytes
L
L
L
L
Partial Write Cycle Description
The partial write cycle description for part CY7C1472V33 is as follows. [12, 13, 14, 15]
Function (CY7C1472V33)
WE
H
L
BWb
BWa
x
Read
x
H
H
L
Write – no bytes written
Write byte a – (DQa and DQPa)
Write byte b – (DQb and DQPb)
Write both bytes
H
L
L
L
H
L
L
L
Notes
12. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = 0 signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
13. Write is defined by WE and BW
. See Write Cycle Description table for details.
[a:d]
14. When a write cycle is detected, all I/Os are tristated, even during byte writes.
15. Table only lists a partial listing of the Byte Write combinations. Any combination of BW
is valid. Appropriate write will be done based on which Byte Write is active.
[a:d]
Document Number: 38-05289 Rev. *X
Page 13 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Partial Write Cycle Description
The partial write cycle description for part CY7C1474V33 is as follows. [16, 17, 18, 19]
Function (CY7C1474V33)
WE
H
BWx
Read
x
Write – no bytes written
Write byte X(DQx and DQPx)
Write all bytes
L
H
L
L
L
All BW = L
Notes
16. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = 0 signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
17. Write is defined by WE and BW
. See Write Cycle Description table for details.
[a:d]
18. When a write cycle is detected, all I/Os are tristated, even during byte writes.
19. Table only lists a partial listing of the Byte Write combinations. Any combination of BW
is valid. Appropriate write will be done based on which Byte Write is active.
[a:d]
Document Number: 38-05289 Rev. *X
Page 14 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1470V33, and CY7C1474V33 incorporates a serial
boundary scan test access port (TAP). This port operates in
accordance with IEEE Standard 1149.1-1990 but does not have
the set of functions required for full 1149.1 compliance. These
functions from the IEEE specification are excluded because their
inclusion places an added delay in the critical speed path of the
SRAM. Note that the TAP controller functions in a manner that
does not conflict with the operation of other devices using 1149.1
fully compliant TAPs. The TAP operates using JEDEC-standard
3.3 V or 2.5 V I/O logic levels.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
The CY7C1470V33, and CY7C1474V33 contains a TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.
Three bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 18. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
Test Access Port (TAP)
Test Clock (TCK)
SRAM with minimal delay. The bypass register is set LOW (VSS
)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram on page 17. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
The Boundary Scan Exit Order on page 22 and Boundary Scan
Exit Order on page 23 show the order in which the bits are
connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions
table.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Identification Codes on page 21).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in Identification
Document Number: 38-05289 Rev. *X
Page 15 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Codes on page 21. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so the
device TAP controller is not fully 1149.1 compliant.
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is
captured in the boundary scan register.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
time (tCS plus tCH).
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in this SRAM TAP controller, and
therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
The SRAM clock input might not be captured correctly if there is
no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between the
two instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a high Z state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the same
effect as the Pause-DR command.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
Reserved
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a high Z state.
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 38-05289 Rev. *X
Page 16 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
1
1
1
RUN-TEST/
0
SELECT
DR-SCAN
SELECT
IR-SCAN
IDLE
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
1
0
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 38-05289 Rev. *X
Page 17 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
TAP Controller Block Diagram
0
0
Bypass Register
2
1
Selection
Circuitry
Selection
Circuitry
Instruction Register
31 30 29 .
Identification Register
TDI
TDO
.
.
2
1
0
x
.
.
.
.
. 2 1
0
Boundary Scan Register
TCK
TAP CONTROLLER
TM S
TAP Timing Diagram
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TM SS
TDIS
TM SH
Test M ode Select
(TM S)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Document Number: 38-05289 Rev. *X
Page 18 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
TAP AC Switching Characteristics
Over the Operating Range
Parameter [20, 21]
Clock
Description
Min
Max
Unit
tTCYC
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
50
–
–
20
–
ns
MHz
ns
tTF
tTH
20
20
tTL
–
ns
Output Times
tTDOV
tTDOX
Setup Times
tTMSS
tTDIS
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
–
0
10
–
ns
ns
TMS setup to TCK clock rise
TDI setup to TCK clock rise
Capture setup to TCK rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK clock rise
TDI hold after clock rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture hold after clock rise
Notes
20. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
21. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document Number: 38-05289 Rev. *X
Page 19 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input rise and fall times ...................................................1 ns
Input timing reference levels ......................................... 1.5 V
Output reference levels ................................................ 1.5 V
Test load termination supply voltage ............................ 1.5 V
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall time ....................................................1 ns
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
20pF
ZO= 50Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.135 V to 3.6 V unless otherwise noted)
Parameter [22]
Description
Test Conditions
IOH = –4.0 mA,VDDQ = 3.3 V
IOH = –1.0 mA,VDDQ = 2.5 V
Min
2.4
2.0
2.9
2.1
–
Max
Unit
V
VOH1
Output HIGH voltage
–
–
V
VOH2
VOL1
VOL2
VIH
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input load current
IOH = –100 µA
VDDQ = 3.3 V
–
V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
–
0.4
V
IOL = 8.0 mA
IOL = 1.0 mA
IOL = 100 µA
V
–
0.4
V
–
0.2
V
–
0.2
V
2.0
1.7
–0.3
–0.3
–5
VDD + 0.3
VDD + 0.3
0.8
V
V
VIL
V
0.7
V
IX
GND < VIN < VDDQ
5
µA
Note
22. All voltages referenced to V (GND).
SS
Document Number: 38-05289 Rev. *X
Page 20 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Identification Register Definitions
CY7C1470V33
CY7C1474V33
(1M × 72)
Instruction Field
Description
(2M × 36)
Revision number (31:29)
Device depth (28:24) [23]
000
000
01011
Describes the version number
01011
Reserved for internal use
Architecture/memory type (23:18)
Bus width/density (17:12)
Cypress JEDEC ID code (11:1)
001000
001000
Defines memory type and architecture
Defines width and density
100100
110100
00000110100
00000110100
Allows unique identification of SRAM
vendor
ID register presence indicator (0)
1
1
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size (× 36)
Bit Size (× 72)
Instruction
3
1
3
1
Bypass
ID
32
71
–
32
–
Boundary scan order – 165-ball FBGA
Boundary scan order – 209-ball FBGA
110
Identification Codes
Instruction
EXTEST
Code
Description
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM outputs to high Z state. This instruction is not 1149.1 compliant.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a high Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation. This instruction does not implement 1149.1 preload function and
is therefore not 1149.1 compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
Note
23. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 38-05289 Rev. *X
Page 21 of 40
CY7C1470V33
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Boundary Scan Exit Order
(2M × 36)
Bit #
1
165-ball ID
C1
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
165-ball ID
R3
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
165-ball ID
J11
Bit #
61
62
63
64
65
66
67
68
69
70
71
165-ball ID
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
2
D1
P2
K10
J10
H11
G11
F11
E11
D10
D11
C11
G10
F10
E10
A9
3
E1
R4
4
D2
P6
5
E2
R6
6
F1
R8
7
G1
F2
P3
8
P4
9
G2
J1
P8
10
11
12
13
14
15
16
17
18
19
20
P9
K1
P10
R9
L1
J2
R10
R11
N11
M11
L11
M10
L10
K11
M1
N1
B9
K2
A10
B10
A8
L2
M2
R1
B8
R2
A7
Document Number: 38-05289 Rev. *X
Page 22 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Boundary Scan Exit Order
(1M × 72)
Bit #
1
209-ball ID
A1
Bit #
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
209-ball ID
T1
Bit #
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
209-ball ID
U10
T11
Bit #
85
209-ball ID
B11
B10
A11
A10
A7
2
A2
T2
86
3
B1
U1
T10
R11
R10
P11
P10
N11
N10
M11
M10
L11
87
4
B2
U2
88
5
C1
C2
D1
D2
E1
V1
89
6
V2
90
A5
7
W1
W2
T6
91
A9
8
92
U8
9
93
A6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
E2
V3
94
D6
F1
V4
95
K6
F2
U4
96
B6
G1
G2
H1
H2
J1
W5
V6
L10
97
K3
P6
98
A8
W6
V5
J11
99
B4
J10
100
101
102
103
104
105
106
107
108
109
110
B3
U5
H11
H10
G11
G10
F11
C3
J2
U6
C4
L1
W7
V7
C8
L2
C9
M1
M2
N1
N2
P1
U7
B9
V8
F10
E10
E11
D11
D10
C11
C10
B8
V9
A4
W11
W10
V11
V10
U11
C6
B7
P2
A3
R2
R1
Document Number: 38-05289 Rev. *X
Page 23 of 40
CY7C1470V33
CY7C1472V33
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Maximum Ratings
Operating Range
Ambient
Temperature
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Range
VDD
VDDQ
Commercial 0 °C to +70 °C
Industrial –40 °C to +85 °C
3.3 V– 5% / 2.5 V – 5% to
Storage temperature ................................ –65 °C to +150 °C
+ 10%
VDD
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC to outputs in tri-state ...................–0.5 V to VDDQ + 0.5 V
DC input voltage .................................–0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Neutron Soft Error Immunity
Test
Parameter Description
Conditions
Typ Max* Unit
LSBU
LMBU
SEL
Logical single
bit upsets
25 °C
25 °C
85 °C
361 394
FIT/
Mb
Static discharge voltage
(per MIL-STD-883, method 3015) ..........................> 2001 V
Logical multi
bit upsets
0
0
0.01 FIT/
Mb
Latch-up current ....................................................> 200 mA
Single event
latch-up
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
2
statistical , 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”.
Electrical Characteristics
Over the Operating Range
Parameter[24, 25]
Description
Power supply voltage
I/O supply voltage
Test Conditions
Min
3.135
3.135
2.375
2.4
Max
Unit
V
VDD
3.6
VDDQ
for 3.3 V I/O
for 2.5 V I/O
VDD
V
2.625
V
VOH
VOL
VIH
VIL
IX
Output HIGH voltage
Output LOW voltage
Input HIGH voltage [24]
Input LOW voltage [24]
for 3.3 V I/O, IOH =4.0 mA
for 2.5 V I/O, IOH=1.0 mA
for 3.3 V I/O, IOL=8.0 mA
for 2.5 V I/O, IOL=1.0 mA
for 3.3 V I/O
–
V
2.0
–
0.4
V
–
V
–
0.4
V
2.0
VDD + 0.3
VDD + 0.3
0.8
V
for 2.5 V I/O
1.7
V
for 3.3 V I/O
–0.3
–0.3
–5
V
for 2.5 V I/O
0.7
V
Input leakage current except ZZ GND VI VDDQ
and MODE
5
A
Input current of MODE
Input = VSS
–30
–
–
5
A
A
A
A
A
Input = VDD
Input current of ZZ
Input = VSS
–5
–
–
Input = VDD
30
5
IOZ
Output leakage current
GND VI VDDQ, output disabled
–5
Notes
24. Overshoot: V
< V +1.5 V (Pulse width less than t
/2), undershoot: V
> –2 V (Pulse width less than t
/2).
IH(AC)
DD
CYC
IL(AC)
CYC
25. T
: Assumes a linear ramp from 0 V to V
within 200 ms. During this time V < V and V
< V
.
power up
DD(Min)
IH
DD
DDQ
DD
Document Number: 38-05289 Rev. *X
Page 24 of 40
CY7C1470V33
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CY7C1474V33
Electrical Characteristics (continued)
Over the Operating Range
Parameter[24, 25]
Description
Test Conditions
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
Min
Max
Unit
IDD
VDD operating supply
5.0nscycle,
200 MHz
–
500
mA
6.0nscycle,
167 MHz
–
–
–
–
450
245
245
120
mA
mA
mA
mA
ISB1
Automatic CE power-down
current – TTL inputs
Max VDD, device deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
5.0nscycle,
200 MHz
6.0nscycle,
167 MHz
ISB2
Automatic CE power-down
current – CMOS inputs
Max VDD, device deselected,
VIN 0.3 V or VIN > VDDQ 0.3 V, grades
f = 0
All speed
ISB3
Automatic CE power-down
current – CMOS inputs
Max VDD, device deselected,
VIN 0.3 V or VIN > VDDQ 0.3 V, 200 MHz
f = fMAX = 1/tCYC
5.0nscycle,
–
–
–
245
245
135
mA
mA
mA
6.0nscycle,
167 MHz
ISB4
Automatic CE power-down
current – TTL inputs
Max VDD, device deselected,
VIN VIH or VIN VIL,
f = 0
All speed
grades
Capacitance
100-pin TQFP 165-ballFBGA 209-ballFBGA
Parameter [26]
Description
Test Conditions
Unit
Max
Max
Max
CADDRESS
CDATA
CCTRL
CCLK
Address input capacitance TA = 25 C, f = 1 MHz,
6
5
8
6
5
6
5
8
6
5
6
5
8
6
5
pF
pF
pF
pF
pF
V
DD = 3.3 V, VDDQ = 2.5 V
Data input capacitance
Control input capacitance
Clock input capacitance
Input/output capacitance
CI/O
Thermal Resistance
100-pin TQFP 165-ballFBGA 209-ballFBGA
Parameter [26]
Description
Test Conditions
Unit
Package
Package
Package
JA
Thermal resistance
(junction to ambient)
Test
conditions
follow
24.63
16.3
15.2
C/W
standard test methods and
procedures for measuring
thermal impedance, per
EIA/JESD51.
JC
Thermal resistance
(junction to case)
2.28
2.1
1.7
C/W
Note
26. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05289 Rev. *X
Page 25 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50
0
R = 50
10%
L
GND
5 pF
R = 351
1 ns
1 ns
V = 1.5 V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50
0
10%
L
5 pF
R = 1538
1 ns
1 ns
V = 1.25 V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Document Number: 38-05289 Rev. *X
Page 26 of 40
CY7C1470V33
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CY7C1474V33
Switching Characteristics
Over the Operating Range
-200
-167
Unit
Max
Parameter [27, 28]
Description
Min
Max
Min
[29]
tPower
Clock
tCYC
VCC(typical) to the first access read or write
1
–
1
–
ms
Clock cycle time
Maximum operating frequency
Clock HIGH
5.0
–
–
200
–
6.0
–
–
167
–
ns
MHz
ns
FMAX
tCH
2.0
2.0
2.2
2.2
tCL
Clock LOW
–
–
ns
Output Times
tCO
Data output valid after CLK rise
OE LOW to output valid
–
–
3.0
3.0
–
–
–
3.4
3.4
–
ns
ns
ns
ns
ns
ns
ns
tOEV
tDOH
Data output hold after CLK rise
Clock to high Z [30, 31, 32]
Clock to low Z [30, 31, 32]
OE HIGH to output high Z [30, 31, 32]
OE LOW to output low Z [30, 31, 32]
1.3
–
1.5
–
tCHZ
3.0
–
3.4
–
tCLZ
1.3
–
1.5
–
tEOHZ
tEOLZ
Setup Times
tAS
3.0
–
3.4
–
0
0
Address setup before CLK rise
Data input setup before CLK rise
CEN setup before CLK rise
WE, BWx setup before CLK rise
ADV/LD setup before CLK rise
Chip select setup
1.4
1.4
1.4
1.4
1.4
1.4
–
–
–
–
–
–
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tDS
tCENS
tWES
tALS
tCES
Hold Times
tAH
Address hold after CLK rise
Data input hold after CLK rise
CEN hold after CLK rise
0.4
0.4
0.4
0.4
0.4
0.4
–
–
–
–
–
–
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tDH
tCENH
tWEH
WE, BWx hold after CLK rise
ADV/LD hold after CLK rise
Chip select hold after CLK rise
tALH
tCEH
Notes
27. Timing reference is 1.5 V when V
= 3.3 V and is 1.25 V when V
= 2.5 V.
DDQ
DDQ
28. Test conditions shown in (a) of Figure 4 on page 26 unless otherwise noted.
29. This part has a voltage regulator internally; t is the time power needs to be supplied above V
initially, before a read or write operation can be initiated.
power
DD(minimum)
30. t
, t
, t
, and t
are specified with AC test conditions shown in (b) of Figure 4 on page 26. Transition is measured ±200 mV from steady-state voltage.
CHZ CLZ EOLZ
EOHZ
31. At any voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data bus.
EOHZ
EOLZ
CHZ
CLZ
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z
prior to low Z under the same system conditions.
32. This parameter is sampled and not 100% tested.
Document Number: 38-05289 Rev. *X
Page 27 of 40
CY7C1470V33
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CY7C1474V33
Switching Waveforms
Figure 5. Read/Write/Timing [33, 34, 35]
1
2
3
4
5
6
7
8
9
10
t
CYC
t
CLK
t
t
t
CENS
CENH
CL
CH
CEN
t
t
CES
CEH
CE
ADV/LD
WE
BW
x
A1
A2
A4
CO
A3
A5
A6
A7
ADDRESS
t
t
t
t
DS
DH
t
t
t
DOH
OEV
CLZ
CHZ
t
t
AS
AH
Data
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
In-Out (DQ)
t
OEHZ
t
DOH
t
OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes
33. For this waveform ZZ is tied LOW.
34. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
35. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1= Interleaved). Burst operations are optional.
Document Number: 38-05289 Rev. *X
Page 28 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Switching Waveforms (continued)
Figure 6. NOP, STALL and DESELECT Cycles [36, 37, 38]
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
A1
A2
A3
A4
A5
ADDRESS
t
CHZ
D(A4)
D(A1)
Q(A2)
Q(A3)
Q(A5)
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
Figure 7. ZZ Mode Timing [39, 40]
CLK
ZZ
t
t
ZZ
ZZREC
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
36. For this waveform ZZ is tied LOW.
37. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
38. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
39. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
40. I/Os are in high Z when exiting ZZ sleep mode.
Document Number: 38-05289 Rev. *X
Page 29 of 40
CY7C1470V33
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CY7C1474V33
Ordering Information
The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
167 CY7C1470V33-167AXC
CY7C1470V33-167BZC
CY7C1474V33-167BGC
CY7C1470V33-167AXI
CY7C1470V33-167BZI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
51-85165 165-ball FBGA (15 × 17 × 1.4mm)
51-85167 209-ball FBGA (14 × 22 × 1.76 mm)
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
51-85165 165-ball FBGA (15 × 17 × 1.4mm)
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
lndustrial
200 CY7C1470V33-200AXC
CY7C1472V33-200AXC
CY7C1474V33-200BGC
CY7C1470V33-200BZI
Commercial
51-85167 209-ball FBGA (14 × 22 × 1.76 mm)
51-85165 165-ball FBGA (15 × 17 × 1.4mm)
lndustrial
Ordering Code Definitions
CY
7
C 147X V33
XXX XX X X
-
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: XX = A or BZ or BG
A = 100-pin TQFP
BZ = 165-ball FBGA
BG = 209-ball FBGA
Speed Grade: XXX = 167 MHz or 200 MHz
V33 = 3.3 V
147X = 1470 or 1472 or 1474
1470 = PL, 2Mb × 36 (72Mb)
1472 = PL, 4Mb × 18 (72Mb)
1474 = PL, 1Mb × 72 (72Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05289 Rev. *X
Page 30 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Package Diagrams
Figure 8. 100-pin TQFP (16 × 22 × 1.6 mm) A100RA Package Outline, 51-85050
ș 2
ș
1
ș
DIMENSIONS
MIN. NOM. MAX.
1.60
NOTE:
SYMBOL
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
MOLD PROTRUSION/END FLASH SHALL
A
0.05
0.15
A1
A2
D
1.35 1.40 1.45
15.80 16.00 16.20
13.90 14.00 14.10
21.80 22.00 22.20
19.90 20.00 20.10
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
D1
E
E1
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
0.08
0.08
0°
R
R
ș
0.20
0.20
7°
1
2
ș 1
ș 2
c
0°
11° 12° 13°
0.20
0.22 0.30 0.38
0.45 0.60 0.75
1.00 REF
b
L
L1
L 2
L 3
e
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Document Number: 38-05289 Rev. *X
Page 31 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Package Diagrams (continued)
Figure 9. 165-ball FBGA (15 × 17 × 1.40 mm) (0.45 Ball Diameter) Package Outline, 51-85165
51-85165 *E
Document Number: 38-05289 Rev. *X
Page 32 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Package Diagrams (continued)
Figure 10. 209-ball FBGA (14 × 22 × 1.76 mm) BB209A Package Outline, 51-85167
51-85167 *C
Document Number: 38-05289 Rev. *X
Page 33 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Acronyms
Document Conventions
Units of Measure
Acronym
Description
BGA
CMOS
CE
Ball Grid Array
Symbol
°C
Unit of Measure
Complementary Metal Oxide Semiconductor
Chip Enable
degree Celsius
megahertz
microampere
milliampere
millimeter
millisecond
nanosecond
picofarad
volt
MHz
µA
mA
mm
ms
ns
CEN
FBGA
I/O
Clock Enable
Fine-Pitch Ball Grid Array
Input/Output
JTAG
NoBL
OE
Joint Test Action Group
No Bus Latency
pF
Output Enable
V
SRAM
TCK
TDI
Static Random Access Memory
Test Clock
W
watt
Test Data Input
TMS
TDO
TQFP
WE
Test Mode Select
Test Data Output
Thin Quad Flat Pack
Write Enable
Document Number: 38-05289 Rev. *X
Page 34 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Errata
This section describes the Ram9 NoBL ZZ pin issues. Details include trigger conditions, the devices affected, proposed workaround
and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions.
Part Numbers Affected
Density & Revision
Package Type
100-pin TQFP
165-ball FBGA
209-ball FBGA
Operating Range
72Mb-Ram9 NoBL SRAMs: CY7C147*V33
Commercial/
Industrial
Commercial
Product Status
All of the devices in the Ram9 72Mb NoBL family are qualified and available in production quantities.
Ram9 NoBL ZZ Pin Issues Errata Summary
The following table defines the errata applicable to available Ram9 72Mb NoBL family devices.
Item
Issues
Description
Device
Fix Status
1. ZZ Pin
When asserted HIGH, the ZZ pin places
deviceina“sleep”conditionwith dataintegrity
preserved.The ZZ pin currently does not have
an internal pull-down resistor and hence
cannot be left floating externally by the user
during normal mode of operation.
72M-Ram9 (90 nm)
For the 72M Ram9 (90 nm)
devices, this issue was fixed in
the new revision. Please
contact your local sales rep for
availability.
1. ZZ Pin Issue
■ PROBLEM DEFINITION
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM
device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH
on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the
SRAM.
■ TRIGGER CONDITIONS
Device operated with ZZ pin left floating.
■ SCOPE OF IMPACT
When the ZZ pin is left floating, the device delivers incorrect data.
■ WORKAROUND
Tie the ZZ pin externally to ground.
■ FIX STATUS
Fix was done for the 72M RAM9 NoBL SRAMs devices. Fixed devices have a new revision. The following table lists the devices
affected and the new revision after the fix.
Table 1. List of Affected Devices and the new revision
Revision before the Fix
New Revision after the Fix
CY7C147*V33
CY7C147*BV33
Document Number: 38-05289 Rev. *X
Page 35 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Document History Page
Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33, 72-Mbit (2M × 36/4M × 18/1M × 72) Pipelined SRAM with
NoBL™ Architecture
Document Number: 38-05289
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
**
114676
121520
PKS
CJM
08/06/2002 New data sheet.
*A
01/27/2003 Changed status from Advanced Information to Preliminary.
Updated Features (For package offering, removed 300 MHz frequency related
information).
Updated Selection Guide (Removed 300 MHz frequency related information).
Updated Functional Overview (Removed 300 MHz frequency related
information).
Updated Electrical Characteristics (Removed 300 MHz frequency related
information).
Updated Switching Characteristics (Removed 300 MHz frequency related
information, changed maximum value of tCO, tEOV, tCHZ, tEOHZ parameters from
2.4 ns to 2.6 ns for 250 MHz frequency, changed minimum value of tDOH, tCLZ
parameters from 0.8 ns to 1.0 ns for 250 MHz frequency, changed minimum
value of tDOH, tCLZ parameters from 1.0 ns to 1.3 ns for 200 MHz frequency).
Updated Ordering Information (Updated part numbers).
*B
223721
NJY
05/14/2004 Updated Features (Removed 250 MHz frequency related information and
included 225 MHz frequency related information).
Updated Functional Description (description).
Updated Logic Block Diagram (Splitted Logic Block Diagram into three Logic
Block Diagrams).
Updated Functional Overview (description).
Updated Boundary Scan Exit Order (Replaced TBD with values for all
packages).
Updated Electrical Characteristics (Removed 250 MHz frequency related
information and included 225 MHz frequency related information, replaced
TBD with values for maximum values of IDD, ISB1, ISB2, ISB3, ISB4 parameters).
Updated Capacitance (Replaced TBD with values for all packages).
Updated Thermal Resistance (Replaced TBD with values for all packages).
Updated Switching Characteristics (Removed 250 MHz frequency related
information and included 225 MHz frequency related information).
Updated Switching Waveforms.
Updated Package Diagrams (spec 51-85165 (Changed revision from ** to *A)
for 165-ball FBGA package, removed 119-ball BGA package (spec 51-85115),
removed spec 51-85143 and included spec 51-85167 for 209-ball BGA
package).
*C
*D
235012
243572
RYQ
NJY
06/17/2004 Minor Change (To match on the spec system and external web).
07/20/2004 Updated Pin Configurations (Updated Figure 2 (Changed ball C11, D11, E11,
F11, G11 from DQPb, DQb, DQb, DQb, DQb to DQPa, DQa, DQa, DQa, DQa
(corresponding to CY7C1472V33))).
Updated Capacitance (Splitted CIN parameter into CADDRESS, CDATA, CCLK
parameters and also updated the values).
Document Number: 38-05289 Rev. *X
Page 36 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Document History Page (continued)
Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33, 72-Mbit (2M × 36/4M × 18/1M × 72) Pipelined SRAM with
NoBL™ Architecture
Document Number: 38-05289
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
*E
299511
SYT / VBL 12/14/2004 Updated Features (Removed 225 MHz frequency related information and
included 250 MHz frequency related information).
Updated Selection Guide (Removed 225 MHz frequency related information
and included 250 MHz frequency related information).
Updated Electrical Characteristics (Removed 225 MHz frequency related
information and included 250 MHz frequency related information).
Updated Thermal Resistance (Changed value of JA from 16.8 C/W to
24.63 C/W, and changed value of JC from 3.3 C/W to 2.28 C/W for 100-pin
TQFP Package).
Updated Switching Characteristics (Removed 225 MHz frequency related
information and included 250 MHz frequency related information, changed
minimum value of tCYC from 4.4 ns to 4.0 ns for 250 MHz frequency).
Updated Ordering Information (Updated part numbers (Removed 225 MHz
frequency related information and included 250 MHz frequency related
information, added Pb-free information for 100-pin TQFP Package and
165-ball FBGA Package, added Industrial Temperature Range part numbers),
added comment of ‘Pb-free BG packages availability’ below the Ordering
Information).
*F
323039
PCI
02/23/2005 Changed status from Preliminary to Final.
Updated Selection Guide (Unshaded 250 MHz frequency related information).
Updated Pin Configurations (Address expansion pins/balls in the pinouts for
all packages are modified as per JEDEC standard, updated Figure 3 (Changed
package name from 209-ball PBGA to 209-ball FBGA)).
Updated Pin Definitions (Added Address Expansion pins).
Updated Electrical Characteristics (Updated Test Conditions of VOL, VOH
parameters, unshaded 250 MHz frequency related information).
Updated Switching Characteristics (Unshaded 250 MHz frequency related
information).
Updated Ordering Information (Updated part numbers, unshaded all shaded
areas, removed comment of ‘Pb-free BG packages availability’ below the
Ordering Information).
*G
*H
351937
416221
PCI
04/19/2005 Updated Ordering Information (Updated part numbers).
RXU
12/22/2005 Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Updated Electrical Characteristics (Updated Note 25 (Changed VDDQ < VDD
to VDDQ < VDD), changed description of IX parameter from Input Load Current
except ZZ and MODE to Input Leakage Current except ZZ and MODE,
changed minimum value of IX parameter (corresponding to Input Current of
MODE (Input = VSS)) from –5 µA to –30 µA, changed maximum value of IX
parameter (corresponding to Input Current of MODE (Input = VDD)) from 30 µA
to 5 µA, changed minimum value of IX parameter (corresponding to Input
Current of ZZ (Input = VSS)) from –30 µA to –5 µA, changed maximum value
of IX parameter (corresponding to Input Current of ZZ (Input = VDD)) from 5 µA
to 30 µA).
Updated Ordering Information (Updated part numbers, replaced Package
Name column with Package Diagram in the Ordering Information table).
Replaced Three-state with Tri-state in all instances across the document.
Document Number: 38-05289 Rev. *X
Page 37 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Document History Page (continued)
Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33, 72-Mbit (2M × 36/4M × 18/1M × 72) Pipelined SRAM with
NoBL™ Architecture
Document Number: 38-05289
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
*I
472335
VKN
06/27/2006 Updated Pin Configurations (Updated Figure 3 (Corrected the ball name for
H9 from VSSQ to VSS).
Updated TAP AC Switching Characteristics (Changed minimum value of tTH
,
tTL parameters from 25 ns to 20 ns, changed maximum value of tTDOV
parameter from 5 ns to 10 ns).
Updated Maximum Ratings (Added Maximum Rating for Supply Voltage on
VDDQ Relative to GND).
Updated Ordering Information (Updated part numbers).
*J
2756998
VKN
08/28/2009 Added Neutron Soft Error Immunity.
Updated Ordering Information (Updated part numbers (Including parts that are
available), and modified the disclaimer for the Ordering information).
Updated Package Diagrams (spec 51-85165 (Changed revision from *A to
*B)).
*K
*L
2903057
3033272
NJY
NJY
04/01/2010 Updated Ordering Information (Updated part numbers).
Updated Package Diagrams:
spec 51-85050 – Changed revision from *B to *C.
spec 51-85167 – Changed revision from ** to *A.
09/19/2010 Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits.
Updated to new template.
*M
*N
3052882
3357114
NJY
10/08/2010 Updated Ordering Information (Updated part numbers).
PRIT
08/29/2011 Updated Package Diagrams:
spec 51-85050 – Changed revision from *C to *D.
spec 51-85165 – Changed revision from *B to *C.
spec 51-85167 – Changed revision from *A to *B.
*O
*P
3403584
3638614
PRIT
PRIT
10/12/2011 Updated Ordering Information (Updated part numbers).
Updated Package Diagrams:
spec 51-85165 – Changed revision from *C to *D.
06/06/2012 Updated Features(Removed250MHzfrequencyrelatedinformation, removed
165-ball FBGA package related information (corresponding to
CY7C1472V33)).
Updated Selection Guide (Removed 250 MHz frequency related information).
Updated Pin Configurations (Updated Figure 2 (Removed CY7C1472V33
related information)).
Updated Functional Overview (Removed 250 MHz frequency related
information).
UpdatedIEEE1149.1SerialBoundaryScan (JTAG)(Removed CY7C1472V33
related information).
Updated Identification Register Definitions (Removed CY7C1472V33 related
information).
Updated Scan Register Sizes (Removed “Bit Size (× 18)” column).
Removed Boundary Scan Exit Order (Corresponding to CY7C1472V33).
Updated Electrical Characteristics (Removed 250 MHz frequency related
information).
Updated Switching Characteristics (Removed 250 MHz frequency related
information).
Updated Ordering Information (Updated part numbers).
*Q
3755966
PRIT
09/26/2012 Updated Package Diagrams (spec 51-85167 (Changed revision from *B to
*C)).
Document Number: 38-05289 Rev. *X
Page 38 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Document History Page (continued)
Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33, 72-Mbit (2M × 36/4M × 18/1M × 72) Pipelined SRAM with
NoBL™ Architecture
Document Number: 38-05289
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
*R
3971410
PRIT
04/18/2013 Updated Ordering Information (Updated part numbers).
Added Errata.
*S
4042037
PRIT
06/27/2013 Added Errata Footnotes.
Updated to new template.
*T
4146627
4539205
PRIT
PRIT
10/04/2013 Updated Errata.
*U
10/15/2014 Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
Completing Sunset Review.
*V
*W
*X
4571917
5513955
6015296
PRIT
PRIT
12/29/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams:
spec 51-85165 – Changed revision from *D to *E.
11/08/2016 Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
RMES
01/05/2018 Updated Package Diagrams:
spec 51-85050 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05289 Rev. *X
Page 39 of 40
CY7C1470V33
CY7C1472V33
CY7C1474V33
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2002-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05289 Rev. *X
Revised January 5, 2018
Page 40 of 40
NoBL™ and No Bus Latency™ are trademarks of Cypress Semiconductor Corporation.
相关型号：
CY7C1472V33-167BGC
ZBT SRAM, 4MX18, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CYPRESS
CY7C1472V33-200AXCT
ZBT SRAM, 4MX18, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100
CYPRESS
CY7C1472V33-200BZXI
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture
CYPRESS
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