CY7C1472V33-167BGC_技术文档

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

2M x 36/4M x 18/1M x 72 Pipelined SRAM

with NoBL™ Architecture

Chip Enables (CE₁, CE₂, and CE₃), cycle start input (ADV/LD),

Clock Enable (CEN), Byte Write Selects (BWS_a, BWS_b,

Features

• Zero Bus Latency™, no dead cycles between Write and

Read cycles

• Fast clock speed: 250, 200, and 167 MHz

• Fast access time: 2.4, 3.0 and 3.4 ns

• Internally synchronized registered outputs eliminate

the need to control OE

BWS_c, BWS_d, BWS_e, BWS_f, BWS_g, BWS_h), and Read/Write

control (WE). BWS_cand BWS_dapply to CY7C1470V33 and

CY7C1472V33 only. BWS_e, BWS_f, BWS_g, and BWS_happly to

CY7C1474V33 only.

Address and control signals are applied to the SRAM during

one clock cycle, and two cycles later its associated data

occurs, either Read or Write.

• Single 3.3V –5% and +5% power supply V_DD

• Separate V_DDQfor 3.3V or 2.5V

A

Clock Enable (CEN) pin allows operation of the

CY7C1470V33, CY7C1472V33, and CY7C1474V33 to be

suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is HIGH; the internal device registers will

hold their previous values.

• Single WE (Read/Write) control pin

• Positive clock-edge triggered, address, data, and

control signal registers for fully pipelined applications

• Interleaved or linear four-word burst capability

There are three Chip Enable (CE₁, CE₂, CE₃) pins that allow

the user to deselect the device when desired. If any one of

these three is not active when ADV/LD is LOW, no new

memory operation can be initiated and any burst cycle in

progress is stopped. However, any pending data transfers

(read or write) will be completed. The data bus will be in a

high-impedance state two cycles after chip is deselected or a

Write cycle is initiated.

• Individualbytewrite(BWS_a–BWS_h)control(maybetied

LOW)

• CEN pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• JTAG boundary scan for BGA packaging version

• Available in 119-ball bump BGA and 100-pin TQFP

packages (CY7C1470V33 and CY7C1472V33).

• 165-ball FBGA and 209-ball BGA (CY7C1474V33)

package are offered by opportunity basis. (Please

contact Cypress sales or marketing)

The CY7C1470V33, CY7C1472V33, and CY7C1474V33

have an on-chip two-bit burst counter. In burst mode,

CY7C1470V33, CY7C1472V33, and CY7C1474V33 provide

four cycles of data for a single address presented to the

SRAM. The order of the burst sequence is defined by the

MODE input pin. The MODE pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load

a new external address (ADV/LD = LOW) or increment the

internal burst counter (ADV/LD = HIGH)

Functional Description

The CY7C1470V33, CY7C1472V33, and CY7C1474V33

SRAMs are designed to eliminate dead cycles when making

transitions from Read to Write or vice versa. These SRAMs are

optimized for 100% bus utilization and achieve Zero Bus

Latency. They integrate 2,097,152 × 36/4,194,304 × 18/

1,048,576 × 72 SRAM cells, respectively, with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. The Cypress Synchronous Burst

SRAM family employs high-speed, low-power CMOS designs

using advanced single-layer polysilicon, three-layer metal

technology. Each memory cell consists of six transistors.

Output Enable (OE) and burst sequence select (MODE) are

the asynchronous signals. OE can be used to disable the

outputs at any given time. ZZ may be tied to LOW if it is not

used.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

inputs include all addresses, all data inputs, depth-expansion

D

CLK

Logic Block Diagram

Data-In REG.

CE

Q

ADV/LD

A

x

DQ

A

BWS

X

DP

X

CEN

CE

CONTROL

and Write

LOGIC

2M × 36/

4M × 18/

1M × 72

X = 20:0 X=a,b,c,d X=a,b,c,d X=a,b,c,d

1

2

2M × 36

DQ

DP

x

3

X = 21:0

X = 19:0

X = a, b

X = a, b X = a, b

4M × 18

1M × 72

MEMORY

ARRAY

WE

BWS

x

X = a, b

X = a, b,

c,d,e,f,g,h

X = a, b,

c,d,e,f,g,h

Mode

c,d,e,f,g,h

OE

Cypress Semiconductor Corporation

Document #: 38-05289 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised January 24, 2003

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Selection Guide

CY7C1470V33-250

CY7C1472V33-250

CY7C1474V33-250

CY7C1470V33-200

CY7C1472V33-200

CY7C1474V33-200

CY7C1470V33-167

CY7C1472V33-167

CY7C1474V33-167

Unit

ns

Maximum Access Time

2.6

3.0

3.4

Maximum Operating Current

Maximum CMOS Standby Current

TBD

mA

Pin Configurations

100-pin TQFP Packages

DPc

DQc

1

2

3

4

5

6

7

8

NC

DPb

1

2

3

4

5

6

7

8

A

NC

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQb

V_DDQ

V_SS

V_DDQ

V_SS

NC

V_SS

DQc

V_SS

NC

DQb

V_SS

DQb

DPa

DQa

V_SS

V_DDQ

DQa

V_SS

NC

DQc

V_SS

DQb

V_SS

V_DDQ

DQb

V_SS

NC

V_DD

ZZ

DQa

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V_DDQ

DQc

NC

V_DD

NC

V_SS

DQd

DQb

NC

V_DD

NC

CY7C1470V33

V_DD

ZZ

(2M × 36)

CY7C1472V33

(4M × 18)

V_SS

DQb

DQa

DQd

V_DDQ

V_SS

DQd

V_SS

DQb

V_DDQ

V_SS

V_DDQ

V_SS

V_DDQ

V_SS

DQa

NC

DQa

V_SS

V_DDQ

DQa

DPa

DQb

DPb

NC

V_SS

V_DDQ

NC

V_SS

V_DDQ

NC

V_DDQ

DQd

DPd

NC

Document #: 38-05289 Rev. *A

Page 2 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Pin Configurations (continued)

119-ball Bump BGA

CY7C1470V33 (2M × 36)–7 × 17 BGA

1

2

3

4

5

6

7

V

A

V

DDQ

A

DDQ

NC

DQ

CE

A

ADV/LD

A

CE

A

NC

DQ

B

C

D

E

F

2

c

3

b

V

DD

DP

V

NC

V

DP

c

SS

b

DQ

V

CE

V

DQ

V

DQ

b

c

1

b

V

OE

A

V

DDQ

DQ

BWS

DQ

G

H

J

c

b

a

b

DQ

V

WE

DQ

V

SS

b

SS

V

NC

V

NC

V

DDQ

DD

DQ

DQ_d

V

CLK

NC

V

DQ

K

L

d

SS

a

DQ

BWS

DQ

DP

DQ

d

V

DQ

V

CEN

A1

V

DDQ

M

N

P

DDQ

d

SS

DQ

DP

V

DQ

d

SS

a

DQ

V

A0

V

DQ

d

SS

a

NC

A

MODE

A

V

NC

A

NC

ZZ

R

T

DD

A

V

TMS

TDI

TCK

TDO

NC

V

DDQ

U

DDQ

CY7C1472V33 (4M × 18)–7 × 17 BGA

1

2

3

4

5

6

7

V

A

V

A

B

C

D

E

F

DDQ

NC

CE

A

ADV/LD

A

CE

NC

DQ

2

3

NC

V

A

DD

DQ

NC

DQ

V

NC

V

DP

b

SS

a

NC

V

CE

V

NC

b

1

a

V

NC

DQ

OE

DQ

V

DDQ

a

NC

BWS

A

V

NC

DQ

a

G

H

J

b

SS

DQ

NC

V

WE

DQ

NC

b

SS

a

V

NC

V

NC

V

DDQ

DD

NC

DQ

V

CLK

NC

V

NC

DQ

K

L

b

SS

a

DQ

NC

DQ

V

BWS

DQ

NC

b

SS

a

V

CEN

A1

V

NC

V

DDQ

M

N

P

R

T

DDQ

b

SS

DQ

NC

DP

V

DQ

NC

DQ

b

SS

a

NC

V

A0

V

NC

A

b

SS

a

NC

A

MODE

A

V

NC

A

NC

ZZ

DD

A

V

TMS

TDI

TCK

TDO

NC

V

DDQ

U

DDQ

Document #: 38-05289 Rev. *A

Page 3 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Pin Configurations (continued)

165-ball Bump FBGA (This package is offered by opportunity basis)

CY7C1470V33 (2M × 36)–11 × 15 FBGA

1

2

3

4

5

6

7

8

9

10

11

NC

A

CE

BWS

CE

3

CEN

A

ADV/LD

A

NC

1

2

c

b

a

NC

DPc

DQc

A

CE

BWS

CLK

WE

B

C

D

OE

A

144M

DPb

d

NC

V

NC

DDQ

SS

DDQ

DQc

V

DQb

DD

SS

DD

DQc

NC

DQc

V

E

F

V

DQb

NC

DQb

ZZ

DDQ

DD

SS

DD

DDQ

V

DD

SS

DD

V

G

H

J

V

DD

SS

DD

V

NC

V

NC

DD

SS

DD

DQd

DPd

NC

DQd

NC

V

DQa

NC

DQa

DPa

NC

DDQ

DD

SS

DD

DDQ

V

K

L

V

DD

SS

DD

V

DD

SS

DD

V

M

N

P

V

DDQ

DD

SS

DD

V

NC

A1

A0

NC

V

DDQ

SS

DDQ

A

TDI

TDO

TCK

A

MODE

A

TMS

R

A

CY7C1472V33 (4M × 18)–11 × 15 FBGA

1

2

3

4

5

6

7

8

9

10

11

NC

A

CE

BWS

NC

CE

3

CEN

A

ADV/LD

A

1

2

b

NC

A

CE

NC

BWS

CLK

WE

B

C

D

E

F

OE

A

144M

DPa

a

NC

V

NC

DDQ

SS

DDQ

DQb

V

DQa

DD

SS

DD

NC

DQb

V

NC

DQa

ZZ

DDQ

DD

SS

DD

DDQ

V

DD

SS

DD

NC

V

G

H

J

V

NC

DD

SS

DD

NC

V

NC

V

NC

DD

SS

DD

DQb

DPb

NC

A

V

DQa

NC

DDQ

DD

SS

DD

DDQ

V

K

L

V

NC

DD

SS

DD

V

NC

DD

SS

DD

V

M

N

P

V

NC

DD

SS

DD

DDQ

V

NC

A1

A0

NC

V

NC

DDQ

SS

DDQ

A

TDI

TDO

TCK

A

NC

MODE

A

TMS

R

A

Document #: 38-05289 Rev. *A

Page 4 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Pin Configurations (continued)

209-ball BGA (This package is offered by opportunity basis)

CY7C1474V33 (1M × 72)

1

DQg

2

3

4

5

6

7

8

9

10

DQb

11

A

B

C

D

E

F

DQg

CE

ADV/LD

WE

DQb

3

2

A

BWS

NC

DQb

BWS

f

BWS

b

c

g

DQg

DPc

DQc

NC

BWS

NC

BWS

CE

BWS

a

BWS

e

DQb

DPb

DQf

d

1

h

DQg

V

NC

OE

V

NC

V

SS

DQb

SS

DPg

DQc

V

DD

DDQ

SS

DPf

DQf

DDQ

DD

V

NC

CEN

NC

V

SS

DD

SS

DD

SS

G

H

J

DQc

V

DDQ

V

DDQ

DQf

DDQ

V

SS

V

DQc

NC

SS

SSQ

DDQ

SS

DQf

NC

DQc

NC

V

DDQ

DD

DDQ

DQf

NC

K

L

CLK

NC

V

SS

NC

DQh

V

DDQ

DD

SS

DD

SS

DDQ

DQa

DDQ

M

N

P

R

T

V

DQh

V

SS

DQa

V

DDQ

DQh

DPd

DQd

V

NC

ZZ

DD

SS

DDQ

SS

DDQ

DQa

DPa

DQe

V

SS

V

DPh

DQd

V

DDQ

V

DDQ

DD

DDQ

SS

DD

DPe

DQe

NC

V

NC

A

MODE

A

SS

U

V

W

A

NC

A

A1

A

DQd

A

DQe

TDI

TDO

TCK

A

A0

A

TMS

Pin Definitions

Pin Name

I/O Type

Pin Description

A0

A1

A

Input-

Synchronous

Address Inputs used to select one of the 2097152/4194304/1048576 address locations.

Sampled at the rising edge of the CLK.

BWS_a

BWS_b

BWS_c

BWS_d

BWS_e

BWS_f

BWS_g

BWS_h

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.

Sampled on the rising edge of CLK. BWS_acontrols DQ_aand DP_a, BWS_bcontrols DQ_band DP_b,

BWS_ccontrols DQ_cand DP_c, BWS_dcontrols DQ_dand DP_d. BWS_econtrols DQ_eand DP_e, BWS_f

controls DQ_fand DP_f, BWS_gcontrols DQ_gand DP_g, and BWS_hcontrols DQ_hand DP_h.

WE

Input-

Synchronous

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This

signal must be asserted LOW to initiate a Write sequence.

ADV/LD

Input-

Synchronous

Advance/load input used to advance the on-chip address counter or load a new address.

When HIGH (and CEN is asserted LOW), the internal burst counter is advanced. When LOW, a

new address can be loaded into the device for an access. After being deselected, ADV/LD should

be driven LOW in order to load a new address.

Document #: 38-05289 Rev. *A

Page 5 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Pin Definitions (continued)

Pin Name

I/O Type

Pin Description

CLK

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.

CLK is only recognized if CEN is active LOW.

CE₁

CE₂

CE₃

OE

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE₂and CE₃to select/deselect the device.

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

CE₁and CE₃to select/deselect the device.

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE₁and CE₂to select/deselect the device.

Input-

Output Enable, active LOW. Combined with the synchronous logic block inside the device to

Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.

When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked

during the data portion of a write sequence, during the first clock when emerging from a

deselected state and when the device has been deselected.

CEN

Input-

Synchronous

Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the

SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not

deselect the device, CEN can be used to extend the previous cycle when required.

DQ_a

DQ_b

DQ_c

DQ_d

DQ_e

DQ_f

I/O-

Synchronous

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by A_[x:0]during the previous clock rise of the read cycle. The direction of the pins is

controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave

as outputs. When HIGH, DQ_a–DQ_dare placed in a three-state condition. The outputs are

automatically three-stated during the data portion of a write sequence, during the first clock when

emerging from a deselected state, and when the device is deselected, regardless of the state of

OE. DQ a, b, c, d, e, f, g, and h are eight bits wide

DQ_g

DQ_h

DP_a

DP_b

DP_c

DP_d

DP_e

DP_f

I/O-

Synchronous

Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ_[x:0]. DP a, b,

c, d, e, f, g, and h are one bit wide.

DP_g

DP_h

ZZ

Input-

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition

Asynchronous with data integrity preserved.

MODE

Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.

Pulled LOW selects the linear burst order. MODE should not change states during operation.

When left floating MODE will default HIGH, to an interleaved burst order.

V_DD

Power Supply Power supply inputs to the core of the device.

I/O Power Supply Power supply for the I/O circuitry.

V_DDQ

V_SS

Ground

Ground for the device. Should be connected to ground of the system.

TDO

JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).

Synchronous

TDI

JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK (BGA only).

Synchronous

TMS

Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK

Synchronous

(BGA only).

TCK

144M

NC

JTAG serial clock Serial clock to the JTAG circuit (BGA only).

–

NC. This pin is reserved for expansion to 144 Mb.

No connects.

Document #: 38-05289 Rev. *A

Page 6 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

inputs or WE. WE is latched at the beginning of a burst cycle.

Therefore, the type of access (Read or Write) is maintained

throughout the burst sequence.

Introduction

Functional Overview

The

CY7C1470V33/CY7C1472V33/CY7C1474V33

are

Single Write Accesses

synchronous-pipelined Burst NoBL SRAMs designed specifi-

cally to eliminate wait states during Write/Read transitions. All

synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock signal is qualified with

the Clock Enable input signal (CEN). If CEN is HIGH, the clock

signal is not recognized and all internal states are maintained.

All synchronous operations are qualified with CEN. All data

outputs pass through output registers controlled by the rising

edge of the clock. Maximum access delay from the clock rise

(t_CO) is 2.6 ns (250-MHz device).

Write access are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE₁, CE₂,

and CE₃are ALL asserted active, and (3) the Write signal WE

is asserted LOW. The address presented to A_xis loaded into

the Address Register. The write signals are latched into the

Control Logic block.

On the subsequent clock rise the data lines are automatically

three-stated regardless of the state of the OE input signal. This

allows the external logic to present the data on DQ and DQP

(DQ_{a,b,c,d,e,f,g,h}/DP_{a,b,c,d,e,f,g,h}for CY7C1474V33, DQ_a,b,c,d

/

Accesses can be initiated by asserting Chip Enable (CE₁, CE₂,

CE₃on the TQFP, CE₁on the BGA) active at the rising edge

of the clock. If Clock Enable (CEN) is active LOW and ADV/LD

is asserted LOW, the address presented to the device will be

latched. The access can either be a Read or Write operation,

depending on the status of the Write Enable (WE). BWS_[h:a]

can be used to conduct byte write operations.

DP_a,b,c,dfor CY7C1470V33, and DQ_a,b/DP_a,bfor

CY7C1472V33). In addition, the address for the subsequent

access (Read/Write/Deselect) is latched into the Address

Register (provided the appropriate control signals are

asserted).

On the next clock rise the data presented to DQ and DP

(DQ_{a,b,c,d,e,f,g,h}/DP_{a,b,c,d,e,f,g,h}for CY7C1474V33, DQ_a,b,c,d

/

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self-timed write

circuitry.

Synchronous Chip Enable (CE₁, CE₂, CE₃on TQFP, CE₁on

BGA) and an asynchronous Output Enable (OE) simplify

depth expansion. All operations (Reads, Writes, and

Deselects) are pipelined. ADV/LD should be driven LOW once

the device has been deselected in order to load a new address

for the next operation.

DP_a,b,c,dfor CY7C1470V33, and DQ_a,b/DP_a,bfor

CY7C1472V33) (or a subset for byte write operations; see

Write Cycle Description table for details) inputs is latched into

the device and the write is complete.

The data written during the Write operation is controlled by

BWS (BWS_{a,b,c,d,e,f,g,h}for CY7C1474V33, BWS_a,b,c,dfor

CY7C1470V33, and BWS_a,bfor CY7C1472V33) signals. The

CY7C1470V33/CY7C1472V33/CY7C1474V33 provides byte

write capability that is described in the Write Cycle Description

table. Asserting the Write Enable input (WE) with the selected

Byte Write Select (BWS) input will selectively write only to the

desired bytes. Bytes not selected during a byte write operation

will remain unaltered. A Synchronous self-timed write

mechanism has been provided to simplify the write operations.

Byte write capability has been included in order to greatly

simplify Read/Modify/Write sequences, which can be reduced

to simple byte write operations.

Because the CY7C1470V33/CY7C1472V33/CY7C1474V33

is a common I/O device, data should not be driven into the

device while the outputs are active. The Output Enable (OE)

can be deasserted HIGH before presenting data to the DQand

DP (DQ_{a,b,c,d,e,f,g,h}/DP_{a,b,c,d,e,f,g,h}for CY7C1474V33,

DQ_a,b,c,d/DP_a,b,c,dfor CY7C1470V33, and DQ_a,b/DP_a,bfor

CY7C1472V33) inputs. Doing so will three-state the output

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) chip

enable asserted active, (3) the Write Enable input signal WE

is deasserted HIGH, and (4) ADV/LD is asserted LOW. The

address presented to the address inputs is latched into the

Address Register and presented to the memory core and

control logic. The control logic determines that a read access

is in progress and allows the requested data to propagate to

the input of the output register. At the rising edge of the next

clock the requested data is allowed to propagate through the

output register and onto the data bus within 2.6 ns (250-MHz

device) provided OE is active LOW. After the first clock of the

read access the output buffers are controlled by OE and the

internal control logic. OE must be driven LOW in order for the

device to drive out the requested data. During the second

clock, a subsequent operation (Read/Write/Deselect) can be

initiated. Deselecting the device is also pipelined. Therefore,

when the SRAM is deselected at clock rise by one of the chip

enable signals, its output will three-state following the next

clock rise.

drivers. As a safety precaution, DQ and DP (DQ_{a,b,c,d,e,f,g,h}

/

DP_{a,b,c,d,e,f,g,h}for CY7C1474V33, DQ_a,b,c,d/DP_a,b,c,dfor

CY7C1470V33, and DQ_a,b/DP_a,bfor CY7C1472V33) are

automatically three-stated during the data portion of a Write

cycle, regardless of the state of OE.

Burst Write Accesses

Burst Read Accesses

The CY7C1470V33/CY7C1472V33/CY7C1474V33 has an

on-chip burst counter that allows the user the ability to supply

a single address and conduct up to four Write operations

without reasserting the address inputs. ADV/LD must be

driven LOW in order to load the initial address, as described

in the Single Write Access section above. When ADV/LD is

driven HIGH on the subsequent clock rise, the chip enables

(CE₁, CE₂, and CE₃) and WE inputs are ignored and the burst

counter is incremented. The correct BWS (BWS_{a,b,c,d,e,f,g,h}for

CY7C1474V33, BWS_a,b,c,dfor CY7C1470V33, and BWS_a,b

for CY7C1472V33) inputs must be driven in each cycle of the

burst write in order to write the correct bytes of data.

The CY7C1470V33/CY7C1472V33/CY7C1474V33 have an

on-chip burst counter that allows the user the ability to supply

a single address and conduct up to four Reads without

reasserting the address inputs. ADV/LD must be driven LOW

in order to load a new address into the SRAM, as described in

the Single Read Access section above. The sequence of the

burst counter is determined by the MODE input signal. A LOW

input on MODE selects a linear burst mode, a HIGH selects an

interleaved burst sequence. Both burst counters use A0 and

A1 in the burst sequence, and will wraparound when incre-

mented sufficiently. A HIGH input on ADV/LD will increment

the internal burst counter regardless of the state of chip enable

Document #: 38-05289 Rev. *A

Page 7 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Cycle Description Truth Table^{[1, 2, 3, 4, 5, 6]}

Address

Used

Operation

CE CEN ADV/LD/ WE BWS_xCLK

Comments

Deselected External

Suspend

1

X

0

1

0

X

0

1

X

1

X

L-H I/Os three-state following next recognized clock.

L-H Clock ignored, all operations suspended.

L-H Address latched.

–

Begin Read External

Begin Write External

0

Valid L-H Address latched, data presented two valid clocks later.

Burst Read Internal

Operation

X

L-H Burst Read operation. Previous access was a Read

operation. Addresses incremented internally in

conjunction with the state of Mode.

Burst Write Internal

Operation

X

0

1

X

Valid L-H Burst Write operation. Previous access was a Write

operation. Addresses incremented internally in

conjunction with the state of MODE. Bytes written are

determined by BWS_[h:a]

.

Interleaved Burst Sequence

Linear Burst Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

First

Address

Second

Address

Third

Address

Fourth

Address

A[1:0]

00

A[1:0]

01

A[1:0]

10

A[1:0]

11

A[1:0]

00

A[1:0]

01

A[1:0]

10

A[1:0]

11

01

00

11

10

01

10

11

00

10

11

00

01

10

11

00

01

11

10

01

00

11

00

01

10

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CEs must remain inactive for the duration of

t_ZZRECafter the ZZ input returns LOW.

ZZ Mode Electrical Characteristics

Parameter

I_DDZZ

Description

Test Conditions

ZZ > V_DD– 0.2V

ZZ < 0.2V

Min.

Max.

15

Unit

mA

ns

Snooze mode standby current

Device operation to ZZ

ZZ recovery time

t_ZZS

2t_CYC

t_ZZREC

2t_CYC

ns

[1, 2]

Write Cycle Descriptions

Function (CY7C1470V33)

Read

WE

1

BWS_d

BWS_c

BWS_b

BWS_a

X

1

X

1

X

1

X

1

0

Write – No Bytes Written

0

Write Byte 0 − (DQ_{a and}DP_a)

0

Notes:

1. X =”Don't Care,” 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWS = 0 signifies at least one Byte Write Select is active,

x

BWS = Valid signifies that the desired byte write selects are asserted. See Write Cycle Description table for details.

x

2. Write is defined by WE and BWS . See Write Cycle Description table for details.

x

3. The DQ and DP pins are controlled by the current cycle and the OE signal.

4. CEN = 1 inserts wait states.

5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.

6. OE assumed LOW.

Document #: 38-05289 Rev. *A

Page 8 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Write Cycle Descriptions (continued)^{[1, 2]}

Function (CY7C1470V33)

Write Byte 1 − (DQ_{b and}DP_b)

Write Bytes 1, 0

WE

0

BWS_d

BWS_c

BWS_b

BWS_a

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Write Byte 2 − (DQ_{c and}DP_c)

Write Bytes 2, 0

0

Write Bytes 2, 1

0

Write Bytes 2, 1, 0

0

Write Byte 3 − (DQ_{d and}DP_d)

Write Bytes 3, 0

0

Write Bytes 3, 1

0

Write Bytes 3, 1, 0

0

Write Bytes 3, 2

0

Write Bytes 3, 2, 0

0

Write Bytes 3, 2, 1

0

Write All Bytes

0

Function (CY7C1472V33)

Read

WE

1

BWS_b

BWS_a

x

1

0

x

1

0

1

0

Write – No Bytes Written

Write Byte 0 – (DQ_{a and}DP_a)

Write Byte 1 – (DQ_{b and}DP_b)

Write Both Bytes

0

Function (CY7C1474V33)^[7]

WE

1

BWS_x

Read

x

0

Write Byte X

Write All Bytes

0

All BWS = 0

(V_SS) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to V_DDthrough a pull-up resistor. TDO should

be left unconnected. Upon power-up, the device will come up

in a reset state which will not interfere with the operation of the

device.

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1470V33/CY7C1472V33/CY7C1474V33 incorpo-

rates a serial boundary scan Test Access Port (TAP) in the

BGA package only. The TQFP package does not offer this

functionality. This port operates in accordance with IEEE

Standard 1149.1-1900, but does not have the set of functions

required for full 1149.1 compliance. These functions from the

IEEE specification are excluded because their inclusion

places an added delay in the critical speed path of the SRAM.

Note that the TAP controller functions in a manner that does

not conflict with the operation of other devices using fully

compliant 1149.1 TAPs. The TAP operates using JEDEC

standard 3.3V I/O logic levels.

Test Access Port—Test Clock

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

Test Mode Select

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this pin unconnected if the TAP is not used. The pin is

pulled up internally, resulting in a logic HIGH level.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

Note:

7. BWSx represents any byte write signal BW[0..7]. To enable any byte write BWSx, a low logic signal should be applied at clock rise. Any number of byte writes

can be enabled at the same time for any given write.

Document #: 38-05289 Rev. *A

Page 9 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Test Data-In (TDI)

Capture-DR state and is then placed between the TDI and

TDO pins when the controller is moved to the Shift-DR state.

The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-

tions can be used to capture the contents of the Input and

Output ring.

The TDI pin is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. For

information on loading the instruction register, see the TAP

Controller State Diagram. TDI is internally pulled up and can

be unconnected if the TAP is unused in an application. TDI is

connected to the Most Significant Bit (MSB) on any register.

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI, and the LSB is connected to TDO.

Test Data-Out (TDO)

Identification (ID) Register

The TDO output pin is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine (see TAP Controller State

Diagram). The output changes on the falling edge of TCK.

TDO is connected to the Least Significant Bit (LSB) of any

register.

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

Performing a TAP Reset

TAP Instruction Set

A Reset is performed by forcing TMS HIGH (V_DD) for five rising

edges of TCK. This RESET does not affect the operation of

the SRAM and may be performed while the SRAM is

operating. At power-up, the TAP is reset internally to ensure

that TDO comes up in a High-Z state.

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in the

Instruction Code table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

TAP Registers

The TAP controller used in this SRAM is not fully compliant

with the 1149.1 convention because some of the mandatory

1149.1 instructions are not fully implemented. The TAP

controller cannot be used to load address, data, or control

signals into the SRAM and cannot preload the Input or Output

buffers. The SRAM does not implement the 1149.1 commands

EXTEST or INTEST or the PRELOAD portion of

SAMPLE/PRELOAD; rather it performs a capture of the Inputs

and Output ring when these instructions are executed.

Registers are connected between the TDI and TDO pins and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time through

the instruction registers. Data is serially loaded into the TDI pin

on the rising edge of TCK. Data is output on the TDO pin on

the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

register. This register is loaded when it is placed between the

TDI and TDO pins as shown in the TAP Controller Block

Diagram. Upon power-up, the instruction register is loaded

with the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO pins.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

EXTEST

When the TAP controller is in the CaptureIR state, the two least

significant bits are loaded with a binary “01” pattern to allow for

fault isolation of the board level serial test path.

EXTEST is a mandatory 1149.1 instruction that is to be

executed whenever the instruction register is loaded with all

0s. EXTEST is not implemented in the TAP controller, and

therefore this device is not compliant with the 1149.1 standard.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain states. The bypass

register is a single-bit register that can be placed between TDI

and TDO pins. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

(V_SS) when the BYPASS instruction is executed.

The TAP controller does recognize an all-0 instruction. When

an EXTEST instruction is loaded into the instruction register,

the SRAM responds as if a SAMPLE/PRELOAD instruction

has been loaded. There is one difference between the two

instructions. Unlike the SAMPLE/PRELOAD instruction,

EXTEST places the SRAM outputs in a High-Z state.

Boundary Scan Register

IDCODE

The boundary scan register is connected to all the input and

output pins on the SRAM. Several no connect (NC) pins are

also included in the scan register to reserve pins for higher

density devices. The ×36 configuration has a 70-bit-long

register, and the ×18 configuration has a 51-bit-long register.

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO pins and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state. The IDCODE instruction

is loaded into the instruction register upon power-up or

whenever the TAP controller is given a test logic reset state.

The boundary scan register is loaded with the contents of the

RAM Input and Output ring when the TAP controller is in the

Document #: 38-05289 Rev. *A

Page 10 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

SAMPLE Z

hold times (t_CSand t_CH). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE/PRELOAD instruction. If this

is an issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK# captured in the

boundary scan register.

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO pins when the TAP

controller is in a Shift-DR state. It also places all SRAM outputs

into a High-Z state.

SAMPLE/PRELOAD

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the

boundary scan register between the TDI and TDO pins.

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The

PRELOAD portion of this instruction is not implemented, so

the TAP controller is not fully 1149.1-compliant.

Note that since the PRELOAD part of the command is not

implemented, putting the TAP into the Update to the

Update-DR state while performing a SAMPLE/PRELOAD

instruction will have the same effect as the Pause-DR

command.

When the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 10 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is

possible that during the Capture-DR state, an input or output

will undergo a transition. The TAP may then try to capture a

signal while in transition (metastable state). This will not harm

the device, but there is no guarantee as to the value that will

be captured. Repeatable results may not be possible.

Bypass

When the BYPASS instruction is loaded in the instruction

register and the TAP is placed in a Shift-DR state, the bypass

register is placed between the TDI and TDO pins. The

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

Reserved

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller’s capture set-up plus

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

Document #: 38-05289 Rev. *A

Page 11 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

TAP Controller State Diagram

TEST-LOGIC

1^[8]

RESET

1

TEST-LOGIC/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

0

1

CAPTURE-DR

0

SHIFT-DR

0

SHIFT-IR

0

1

EXIT1-DR

0

1

EXIT1-IR

0

1

0

PAUSE-DR

1

PAUSE-IR

1

0

EXIT2-DR

1

EXIT2-IR

1

UPDATE-DR

UPDATE-IR

1

0

Note:

8. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document #: 38-05289 Rev. *A

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CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

TAP Controller Block Diagram

0

Bypass Register

Selection

Circuitry

Selection

Circuitry

2

1

0

TDO

TDI

Instruction Register

29

Identification Register

31 30

.

2

1

0

.

2

Boundary Scan Register

TCK

TMS

TAP Controller

TAP Electrical Characteristics Over the Operating Range^{[9, 10]}

Parameter

V_OH1

Description

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Input Load Current

Test Conditions

I_OH= −4.0 mA

Min.

2.4

Max.

Unit

V

V_OH2

V_OL1

V_OL2

V_IH

I_OH= −100 µA

I_OL= 8.0 mA

I_OL= 100 µA

3.0

0.4

0.2

V

1.8

–0.5

–5

V_DD+ 0.3

0.8

V

V_IL

V

I_X

GND < V_I< V_DDQ

5

µA

TAP AC Switching Characteristics Over the Operating Range ^{[11, 12]}

Parameter

t_TCYC

Description

Min.

Max.

Unit

TCK Clock Cycle Time

TCK Clock Frequency

TCK Clock HIGH

100

ns

MHz

ns

t_TF

10

t_TH

40

t_TL

TCK Clock LOW

ns

Set-up Times

t_TMSS

TMS Set-up to TCK Clock Rise

TDI Set-up to TCK Clock Rise

Capture Set-up to TCK Rise

10

ns

t_TDIS

t_CS

Notes:

9. All voltage referenced to Ground.

10. Overshoot: V_IH(AC) < V_DD+ 1.5V for t < t_TCYC/2; undershoot: V_IL(AC) < 0.5V for t < t_TCYC/2; power-up: V_IH< 2.6V and V_DD< 2.4V and V_DDQ< 1.4V for t < 200 ms.

11. t_CSand t_CHrefer to the set-up and hold time requirements of latching data from the boundary scan register.

12. Test conditions are specified using the load in TAP AC test conditions. t_R/t_F= 1 ns.

Document #: 38-05289 Rev. *A

Page 13 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

TAP AC Switching Characteristics Over the Operating Range (continued)^{[11, 12]}

Parameter

Hold Times

t_TMSH

Description

Min.

Max.

Unit

TMS Hold after TCK Clock Rise

TDI Hold after Clock Rise

10

ns

t_TDIH

t_CH

Capture Hold after Clock Rise

Output Times

t_TDOVTCK Clock LOW to TDO Valid

t_TDOXTCK Clock LOW to TDO Invalid

20

ns

0

TAP Timing and Test Conditions

1.25V

50Ω

ALL INPUT PULSES

TDO

Vih

Z = 50Ω

0

C = 20 pF

L

0V

GND

t_TL

t_TH

(a)

Test Clock

TCK

t_TCYC

t_TMSS

t_TMSH

Test Mode Select

TMS

t_TDIS

t_TDIH

Test Data-In

TDI

Test Data-Out

TDO

t_TDOV

t_TDOX

Document #: 38-05289 Rev. *A

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CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Identification Register Definitions

Instruction Field

Revision Number (31:29)

Department Number (27:25)

Voltage (28&24)

×18

000

101

00

×36

000

101

00

X72

000

101

00

Description

Reserved for version number

Department number

Architecture (23:21)

001

000

010

100

001

000

100

001

000

110

100

Architecture type

Memory type (20:18)

Device Width (17:15)

Device Density (14:12)

Cypress JEDEC ID (11:1)

ID Register Presence (0)

Defines type of memory

Defines width of the SRAM. ×36 or ×18

Defines the density of the SRAM

00000110100 00000110100

00000110100 Allows unique identification of SRAM vendor

Indicate the presence of an ID register.

1

Scan Register Sizes

Register Name

Bit Size (x18)

Bit Size (x36)

Bit Size (x72)

Instruction

Bypass

3

1

3

1

3

1

ID

32

Boundary Scan

TBD

Identification Codes

Instruction

EXTEST

Code

Description

000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and

TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.

IDCODE

001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This

operation does not affect SRAM operation.

SAMPLE Z

010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED

011 Do Not Use. This instruction is reserved for future use.

SAMPLE/PRELOAD

100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and

TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload

function and is therefore not 1149.1-compliant.

RESERVED

BYPASS

101 Do Not Use. This instruction is reserved for future use.

110 Do Not Use. This instruction is reserved for future use.

111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

operation.

Document #: 38-05289 Rev. *A

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CY7C1470V33

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CY7C1474V33

PRELIMINARY

Boundary Scan Order (2M × 36)

Boundary Scan Order (4M × 18)

TBD

Document #: 38-05289 Rev. *A

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CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Latch-up Current.................................................... > 200 mA

Power Applied.............................................–55°C to +125°C

Operating Range

Supply Voltage on V_DDRelative to GND........ –0.5V to +4.6V

Ambient

Range Temperature^[13]

V_DD

V_DDQ

DC Voltage Applied to Outputs

in High-Z State^[14]............................... –0.5V to V_DDQ+ 0.5V

Com’l

0°C to +70°C

3.3V ±5%

2.375V (min.)

V_DD(max)

DC Input Voltage^[14]............................ –0.5V to V_DDQ+ 0.5V

Electrical Characteristics Over the Operating Range

Parameter

V_DD

Description

Power Supply Voltage

I/O Supply Voltage

Output HIGH Voltage

Test Conditions

Min.

3.135

2.375

2.4

Max.

3.465

V_DD

Unit

V

V_DDQ

V_OH

V_DD= Min., I_OH= –4.0 mA

3.3V

2.5V

3.3V

2.5V

3.3 V

2.5V

3.3V

2.5V

V

V_DD= Min., I_OH= –1.0 mA

V_DD= Min., I_OL= 8.0 mA

V_DD= Min., I_OL= 1.0 mA

2.0

V

V_OL

V_IH

V_IL

I_X

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage^[14]

0.4

V

2.0

1.7

V

–0.3

0.8

0.7

V

Input Load Current

Input Current of MODE

Input Current of ZZ

GND < V_I< V_DDQ

Input = V_SS

5

µA

mA

30

I_OZ

I_DD

Output Leakage Current GND < V_I< V_DDQ,Output Disabled

5

V_DDOperating Supply V_DD= Max., I_OUT= 0 mA,

f = f_MAX= 1/t_CYC

250 MHz

200 MHz

167 MHz

250 MHz

200 MHz

167 MHz

TBD

I_SB1

Automatic CE

Power-down

Current—TTL Inputs

Max. V_DD, Device Deselected,

V_IN> V_IHor V_IN< V_IL

f = f_MAX= 1/t_CYC

I_SB2

Automatic CE

Power-down

Max. V_DD, Device Deselected, V_IN< All speed grades

0.3V or V_IN> V_DDQ− 0.3V,

Current—CMOS Inputs f = 0

I_SB3

Automatic CE

Power-down

Current—CMOS Inputs f = f_MAX= 1/t_CYC

Max. V_DD, Device Deselected, or V_IN250 MHz

TBD

mA

< 0.3V or V_IN> V_DDQ– 0.3V

200 MHz

167 MHz

I_SB4

Automatic CE

Power-down

Max. V_DD, Device Deselected, V_IN> All speed grades

V_IHor V_IN< V_IL, f = 0

Current—TTL Inputs

Shaded areas contain advance information.

Notes:

13.

T_Ais the ambient temperature.

14. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.

Document #: 38-05289 Rev. *A

Page 17 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Capacitance^[16]

Parameter

Description

Input Capacitance

Test Conditions

Max.

Unit

pF

C_IN

T_A= 25°C, f = 1 MHz,

V_DD= V_DDQ= 3.3V

TBD

C_CLK

C_I/O

Clock Input Capacitance

Input/Output Capacitance

pF

AC Test Loads and Waveforms

R = 317Ω

V

DDQ

[15]

OUTPUT

ALL INPUT PULSES

90%

OUTPUT

3.3V

GND

90%

Z = 50Ω

0

R = 50Ω

10%

L

5 pF

R = 351Ω

INCLUDING

JIG AND

V = 1.5V for 3.3V V

L

= 1.25V for 2.5V V

Rise Time:

2 V/ns

DDQ

Fall Time:

2 V/ns

SCOPE

(c)

(a)

(b)

Thermal Resistance^[16]

Parameter

Description

Test Conditions

BGA Typ.

TQFP Typ.

Units

Q_JA

Thermal Resistance

(Junction to Ambient)

Still Air, soldered on a 4.25 × 1.125 inch,

four-layer printed circuit board

TBD

°C/W

Q_JC

Thermal Resistance

(Junction to Case)

TBD

°C/W

Switching Characteristics (Over the Operating Range)

-250

Max.

-200

Max.

-167

Parameter

Clock

t_CYC

Description

Min.

Max.

Unit

Clock Cycle Time

4.0

5

6

ns

MHz

ns

F_MAX

Maximum Operating Frequency

Clock HIGH

250

200

167

t_CH

1.7

2.0

2.2

t_CL

Clock LOW

ns

Output Times

t_CO

Data Output Valid After CLK Rise

OE LOW to Output Valid^{[16, 18, 20]}

Data Output Hold After CLK Rise

Clock to High-Z^{[16, 17, 18, 19, 20]}

Clock to Low-Z^{[16, 17, 18, 19, 20]}

OE HIGH to Output High-Z^{[17, 18, 20]}

OE LOW to Output Low-Z^{[17, 18, 20]}

2.6

3.0

3.4

ns

t_EOV

t_DOH

1.0

0

1.3

0

1.5

0

t_CHZ

2.6

3.0

3.4

t_CLZ

t_EOHZ

t_EOLZ

Set-up Times

t_AS

Address Set-up Before CLK Rise

Data Input Set-up Before CLK Rise

CEN Set-Up Before CLK Rise

1.5

ns

t_DS

1.2

1.4

t_CENS

t_WES

WE, BWS_xSet-up Before CLK Rise

Notes:

15. Input waveform should have a slew rate of 2V/ns.

16. Tested initially and after any design or process change that may affect these parameters.

17. Unless otherwise noted, test conditions assume signal transition time of 1.5ns, timing reference levels of 1.5V, input pulse levels of 0 to 3.3V, and output

loading of the specified I_OL/I_OHand load capacitance. Shown in (a), (b) and (c) of AC Test Loads.

18. t_CHZ, t_CLZ, t_OEV, t_EOLZ, and t_EOHZare specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state

voltage.

19. At any given voltage and temperature, t_EOHZis less than t_EOLZand t_CHZis less than t_CLZto eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

20. This parameter is sampled and not 100% tested.

Document #: 38-05289 Rev. *A

Page 18 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Switching Characteristics (Over the Operating Range) (continued)

-250

-200

Max.

-167

Parameter

t_ALS

Description

ADV/LD Set-up Before CLK Rise

Chip Select Set-up

Min.

1.2

Max.

Min.

1.4

Min.

1.5

Max.

Unit

ns

t_CES

1.2

1.4

1.5

ns

Hold Times

t_AH

Address Hold After CLK Rise

Data Input Hold After CLK Rise

CEN Hold After CLK Rise

0.3

0.4

0.5

ns

t_DH

t_CENH

t_WEH

t_ALH

WE, BW_xHold After CLK Rise

ADV/LD Hold after CLK Rise

Chip Select Hold After CLK Rise

t_CEH

Shaded area contains advanced information.

Switching Waveforms

Read/Write/DESELECT Sequence

CLK

CEN

t_CENH

t_CENS

t_CL

t_CH

t_CYC

t_AH

t_AS

CEN HIGH blocks

all synchronous inputs

WA2

WA5

RA1

RA3

RA4

RA6

ADDRESS

RA7

WE and

BWS_x

t_WS

t_WH

t_CEH

t_CES

CE

t_DH

t_DS

t_CHZ

t_DOH

t_CLZ

t_DOH

Q4

Q1

Out

D2

In

Data

In/Out

D5

In

Q3

Out

Q6

Out

Q7

Out

Device

originally

t_CO

deselected

The combination of WE and BWS_x(x = a, b, c, d, e, f, g, h for x72, x = a, b, c, d for x36 and x = a, b for x18) defines a write

cycle (see Write Cycle Description table). CE is the combination of CE₁, CE₂, and CE₃. All chip enables need to be active

in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for Write

Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. ADV/LD held LOW. OE held LOW.

= UNDEFINED

= DON’T CARE

Document #: 38-05289 Rev. *A

Page 19 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Switching Waveforms (continued)

Burst Sequences

CLK

t_CYC

t_ALH

t_ALS

ADV/LD

t_CL

t_CH

t_AH

t_AS

RA1

WA2

ADDRESS

WE

RA3

t_WS

t_WH

t_WS

t_WH

BWS_x

t_CES

t_CEH

CE

t_CLZ

t_CHZ

t_DH

t_DOH

t_CLZ

Q3

Data

In/Out

Q1

Q1+2

Out

Q1+3

Out

D2

In

D2+2

In

D2+3

Q1+1

Out

D2+1

In

Out

In

Device

originally

deselected

t_CO

t_DS

The combination of WE and BWS_x(x = a, b, c, d, e, f, g, h for x72, x = a, b, c, d for x36 and x = a, b for x18) define a

write cycle (see Write Cycle Description table). CE is the combination of CE₁, CE₂, and CE₃. All chip enables need to

be active in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA

stands for Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held LOW.

During burst writes, byte writes can be conducted by asserting the appropriate BWS_xinput signals. Burst order deter-

mined by the state of the MODE input. CEN held LOW. OE held LOW.

= UNDEFINED

= DON’T CARE

Document #: 38-05289 Rev. *A

Page 20 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Switching Waveforms (continued)

OE Timing

OE

t_EOV

t_EOHZ

Three-state

I/Os

t_EOLZ

Ordering Information

Speed

(MHz)

Package

Name

Operating

Range

Ordering Code

Package Type

250

CY7C1470V33-250AC

CY7C1472V33-250AC

A101

BG119

BB165C

100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack

Commercial

CY7C1470V33-250BGC

CY7C1472V33-250BGC

119-ball BGA (14 × 22 × 2.4 mm)

CY7C1470V33-250BZC

CY7C1472V33-250BZC

165-ball FBGA (15 × 17 mm)

CY7C1474V33-250BGC

BG209

A101

209-ball BGA (14 × 22 × 2.2 mm)

200

167

CY7C1470V33-200AC

CY7C1472V33-200AC

100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack

CY7C1470V33-200BGC

CY7C1472V33-200BGC

BG119

119-ball BGA (14 × 22 × 2.4 mm)

165-ball FBGA (15 × 17 mm)

CY7C1470V33-200BZC

CY7C1472V33-200BZC

BB165C

CY7C1474V33-200BGC

BG209

A101

209-ball BGA (14 × 22 × 2.2 mm)

CY7C1470V33-167AC

CY7C1472V33-167AC

100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack

CY7C1470V33-167BGC

CY7C1472V33-167BGC

BG119

BB165C

BG209

119-ball BGA (14 × 22 × 2.4 mm)

165-ball FBGA (15 × 17 mm)

209-ball BGA (14 × 22 × 2.2 mm)

CY7C1470V33-167BZC

CY7C1472V33-167BZC

CY7C1474V33-167BGC

Shaded area contains advanced information.

Document #: 38-05289 Rev. *A

Page 21 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Package Diagrams

100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

51-85050-A

Document #: 38-05289 Rev. *A

Page 22 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Package Diagrams (continued)

165-ball FBGA (15 × 17 × 1.20 mm) BB165C

51-85165-**

Document #: 38-05289 Rev. *A

Page 23 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Package Diagrams (continued)

119-Lead PBGA (14 x 22 x 2.4 mm) BG119

51-85115-*B

Document #: 38-05289 Rev. *A

Page 24 of 26

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Package Diagrams (continued)

209-Lead PBGA (14 x 22 x 2.20 mm) BG209

51-85143-*B

Zero Bus Latency, No Bus Latency, and NoBL are trademarks of Cypress Semiconductor Corporation. All product and company

names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05289 Rev. *A

Page 25 of 26

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C1470V33

CY7C1472V33

CY7C1474V33

PRELIMINARY

Document History Page

Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33 2M x 36/4M x 18/1M x 72 Pipelined SRAM

with NoBL™ Architecture

Document Number: 38-05289

ISSUE

DATE

ORIG. OF

CHANGE

REV.

**

ECN NO.

114676

121520

DESCRIPTION OF CHANGE

08/06/02

01/27/03

PKS

CJM

New Data Sheet

*A

Updated features for package offering

Removed 300MHz offering

Changed tCO, tEOV, tCHZ, tEOHZ from 2.4 ns to 2.6 ns (250 MHz),

tDOH, tCLZ from 0.8 ns to 1.0 ns (250 MHz), tDOH, tCLZ from 1.0 ns

to 1.3 ns (200 MHz)

Updated ordering information

Changed Advanced Information to Preliminary

Document #: 38-05289 Rev. *A

Page 26 of 26


型号：	CY7C1472V33-167BGC
厂家：	CYPRESS
描述：	ZBT SRAM, 4MX18, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 时钟静态存储器内存集成电路
文件：	总26页 (文件大小：480K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C1472V33-167BGC [CYPRESS]

相关型号：

CY7C1472V33-167BZC

CY7C1472V33-167BZI

CY7C1472V33-167BZXC

CY7C1472V33-167BZXI

CY7C1472V33-200AXC

CY7C1472V33-200AXCT

CY7C1472V33-200AXI

CY7C1472V33-200BZC

CY7C1472V33-200BZI

CY7C1472V33-200BZXC

CY7C1472V33-200BZXI

CY7C1472V33-250AXC