CY7C1484V33-250AC_技术文档

CY7C1484V33

CY7C1485V33

PRELIMINARY

2M x 36/4M x 18 Pipelined DCD SRAM

internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE), burst control

inputs (ADSC, ADSP, and ADV), write enables (BW_a, BW_b,

BW_c, BW_d, and BWE), and Global Write (GW).

Features

• Fast clock speed: 250, 200, and 167 MHz

• Provide high-performance 3-1-1-1 access rate

• Fast access time: 2.6, 3.0, and 3.4 ns

• Optimal for depth expansion

• Single 3.3V –5% and +5% power supply V_DD

• Separate V_DDQfor 3.3V or 2.5V

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Chip enable for address pipeline

• Address, data, and control registers

• Internally self-timed Write Cycle

Asynchronous inputs include the Output Enable (OE) and

burst mode control (MODE). The data (DQx) and the data

parity (DPx) outputs, enabled by OE, are also asynchronous.

DQa,b,c,d and DPa,b,c,d apply to CY7C1484V33 and DQa,b

and DPa,b apply to CY7C1485V33. a, b, c, and d each are

eight bits wide in the case of DQ and one bit wide in the case

of DP.

Addresses and chip enables are registered with either

Address Status Processor (ADSP) or Address Status

Controller (ADSC) input pins. Subsequent burst addresses

can be internally generated as controlled by the Burst Advance

Pin (ADV).

• Burst control pins (interleaved or linear burst

sequence)

• Automatic power-down for portable applications

• High-density, high-speed packages

Address, data inputs, and write controls are registered on-chip

to initiate self-timed Write cycle. Write cycles can be one to

four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BW_a

• JTAG boundary scan for BGA packaging version

• Available in 119-ball bump BGA and 100-pin TQFP

packages (CY7C1484V33 and CY7C1485V33).

• 165-ball FBGA will be offered on an opportunity basis.

(Please contact Cypress sales or marketing)

controls DQa and DPa. BW_bcontrols DQ and DP . BW

b

controls DQc and DPd. BW_dcontrols DQ and DPd. BW_a, BW_b^c,

BW_c, BW_dcan be active only with BWE being LOW. GW being

LOW causes all bytes to be written. Write pass-through

capability allows written data available at the output for the

immediately next Read cycle. This device also incorporates

pipelined enable circuit for easy depth expansion without

penalizing system performance.

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced

single-layer polysilicon, triple-layer metal technology. Each

memory cell consists of six transistors.

The CY7C1484V33 and CY7C1485V33 SRAMs integrate

2,097,152 × 36/4,194,304 × 18 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

The CY7C1484V33/CY7C1485V33 are both double-cycle

deselect parts.All inputs and outputs of the CY7C1484V33,

CY7C1485V33 are JEDEC standard JESD8-5-compatible.

Selection Guide

CY7C1484V33-

250

CY7C1485V33-

250

CY7C1484V33-

200

CY7C1485V33-

200

CY7C1484V33-

167

CY7C1485V33-

167

Unit

ns

Maximum Access Time

2.6

3.0

3.4

Maximum Operating Current

TBD

mA

Maximum CMOS Standby Current

Shaded areas contain advance information.

Cypress Semiconductor Corporation

Document #: 38-05285 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised January 18, 2003

CY7C1484V33

CY7C1485V33

PRELIMINARY

Logic Block Diagram

CY7C1484V33–2M × 36

MODE

2

(A

)

[1;0]

Q

CLK

ADV

ADSC

0

BURST

COUNTER

CE

CLR

1

ADSP

Q

19

21

ADDRESS

REGISTER

CE

D

2M × 36

MEMORY

ARRAY

A

[20:0]

21

19

GW

DQ , DP

BYTEWRITE

REGISTERS

D

Q

d

BWE

BW

d

DQ , DP

BYTEWRITE

REGISTERS

D

Q

c

BW

c

DQ , DP

b

BYTEWRITE

REGISTERS

BW

b

DQ , DP

a

BYTEWRITE

REGISTERS

BW

a

36

CE

1

2

CE

D

Q

ENABLE CE

REGISTER

CE

3

Q

OUTPUT

REGISTERS

INPUT

REGISTERS

CLK

ENABLE DELAY

REGISTER

CLK

OE

ZZ

SLEEP

CONTROL

DQ

DP

a,b,c,d

CY7C1485V33–4M × 18

MODE

2

(A

)

[1;0]

Q

CLK

ADV

ADSC

0

BURST

COUNTER

CE

CLR

1

ADSP

Q

20

22

ADDRESS

REGISTER

CE

D

4M × 18

A

[21:0]

22

20

MEMORY

ARRAY

GW

DQ , DP

BYTEWRITE

REGISTERS

D

Q

b

BWE

BW

b

DQ , DP

BYTEWRITE

REGISTERS

D

Q

a

BW

a

18

CE

2

1

CE

D

CE

Q

ENABLE CE

REGISTER

CE

3

D

Q

OUTPUT

INPUT

REGISTERS

CLK

ENABLE DELAY

REGISTER

REGISTERS

CLK

OE

ZZ

SLEEP

CONTROL

DQ

a,b

DP

Document #: 38-05285 Rev. *A

Page 2 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Pin Configurations

100-Pin TQFP

(Top View)

DQPc

1

NC

V_DDQ

V_SSQ

NC

DQPb

DQb

V_DDQ

V_SSQ

DQb

V_SSQ

V_DDQ

DQb

V_SS

A

NC

V_DDQ

V_SSQ

NC

DPa

DQa

V_SSQ

V_DDQ

DQa

V_SS

NC

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQc

2

DQc

V_DDQ

V_SSQ

DQc

3

4

5

6

DQc

7

NC

DQc

8

DQb

V_SSQ

V_DDQ

DQb

NC

V_DD

NC

V_SS

DQb

V_DDQ

V_SSQ

DQb

DPb

NC

DQc

9

10

11

9

V_SSQ

V_DDQ

DQc

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

12

DQc

13

NC

14

CY7C1485V33

CY7C1484V33

V_DD

15

NC

V_DD

ZZ

(4M × 18)

NC

16

(2M × 36)

V_DD

ZZ

V_SS

17

DQd

18

DQa

V_DDQ

V_SSQ

DQa

V_SSQ

V_DDQ

DQa

V_DDQ

V_SSQ

DQa

NC

DQd

19

20

21

V_DDQ

V_SSQ

DQd

22

DQd

23

DQd

24

DQd

25

26

27

NC

V_SSQ

V_DDQ

DQd

29

V_SSQ

V_DDQ

NC

V_SSQ

V_DDQ

NC

28

NC

DQPa NC

DQPd

30

Document #: 38-05285 Rev. *A

Page 3 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Pin Configurations (continued)

119-ball Bump BGA

CY7C1484V33 (2M × 36)

1

2

3

4

5

6

7

A

V_DDQ

NC

A

V_DDQ

A

ADSP

ADSC

V_DD

B

C

D

E

F

NC

A

V_SS

DQPb

DQb

DQPc

DQc

NC

DQb

DQc

CE₁

OE

V_SS

V_DDQ

DQc

V_DDQ

DQb

V_DDQ

DQa

V_SS

BW_b

V_SS

NC

DQb

ADV

GW

V_DD

G

H

J

DQc

V_DD

DQd

BW_c

V_SS

NC

DQc

DQb

V_DD

V_DDQ

DQd

V_DDQ

DQd

NC

K

L

V_SS

DQa

DQPa

A

V_SS

CLK

NC

BW_d

BW_a

V_SS

DQa

V_DDQ

DQa

M

DQd

BWE

A1

V_SS

N

P

R

T

DQPd

DQa

V_SS

MODE

A

A0

V_SS

NC

A

V_DD

A

NC

ZZ

A

NC

U

V_DDQ

TMS

TDI

TCK

TDO

NC

V_DDQ

CY7C1485V33 (4M × 18)

1

2

3

4

5

6

7

A

B

C

D

E

F

A

V_DDQ

NC

A

V_DDQ

NC

A

ADSP

ADSC

V_DD

A

NC

A

V_SS

DQb

NC

DQPa

NC

DQb

DQa

CE₁

OE

V_SS

DQa

V_DDQ

NC

V_DDQ

DQa

NC

V_SS

NC

ADV

GW

V_DD

G

H

J

NC

DQb

NC

BW_b

V_SS

NC

DQa

V_DD

V_DDQ

DQa

V_DDQ

NC

V_DD

DQb

NC

K

L

V_SS

NC

DQa

NC

DQa

NC

A

V_SS

CLK

NC

DQb

V_DDQ

DQb

NC

BW_a

V_SS

NC

V_DDQ

NC

M

DQb

NC

BWE

A1

V_SS

N

P

R

T

DQPb

DQa

V_SS

MODE

A

A0

V_DD

A

V_SS

NC

A

NC

A

NC

ZZ

A

U

V_DDQ

TMS

TDI

TCK

TDO

NC

V_DDQ

Document #: 38-05285 Rev. *A

Page 4 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Pin Configurations (continued)

165-ball Bump FBGA (This package is offered on an opportunity basis)

CY7C1484V33 (2M × 36)–11 × 15 FBGA

1

2

3

4

5

6

7

8

9

10

11

NC

A

CE

BW

CE

3

BWE

A

ADSC

ADV

A

NC

1

2

c

b

NC

DPc

DQc

A

CE

BW

V

BW

V

CLK

GW

B

C

D

OE

ADSP

A

144M

DPb

d

a

NC

V

NC

DDQ

SS

DDQ

DQc

V

DQb

DD

SS

DD

DDQ

DQc

NC

V

E

F

V

DQb

NC

DQb

ZZ

DDQ

DD

SS

DD

DDQ

V

SS

DD

DDQ

V

G

H

J

V

SS

DD

DDQ

V

NC

V

NC

SS

DD

DQd

DPd

NC

DQd

NC

V

DQa

NC

DQa

DPa

A

DDQ

SS

DD

DDQ

V

K

L

V

SS

DD

DDQ

V

SS

DD

DDQ

V

M

N

P

V

DDQ

DD

SS

DD

DDQ

V

NC

TDI

A

V

DDQ

SS

DDQ

A

A1

A0

TDO

TCK

A

MODE

A

TMS

R

A

CY7C1485V33 (4M × 18)–11 × 15 FBGA

1

2

3

4

5

6

7

8

9

10

11

NC

A

CE

BW

NC

CE

3

BWE

A

ADSC

ADV

A

1

2

b

NC

A

CE

NC

BW

CLK

GW

B

C

D

E

F

OE

ADSP

A

144M

DPa

a

NC

V

NC

DDQ

SS

DDQ

DQb

V

DQa

DD

SS

DD

DDQ

NC

DQb

V

NC

DQa

ZZ

DDQ

DD

SS

DD

DDQ

V

DD

SS

DD

DDQ

NC

V

G

H

J

V

NC

DD

SS

DD

DDQ

NC

V

NC

V

NC

SS

DD

SS

DD

DQb

DPb

NC

A

V

DQa

NC

A

DDQ

DD

SS

DD

DDQ

V

K

L

V

DD

SS

DD

DDQ

V

DD

SS

DD

DDQ

V

M

N

P

V

DDQ

DD

SS

DD

DDQ

V

NC

TDI

A

V

DDQ

SS

DDQ

A

A1

A0

TDO

TCK

A

MODE

A

TMS

R

A

Pin Definitions

Pin Name

I/O

Input-

Synchronous

Pin Description

A0

A1

A

Address Inputs used to select one of the address locations. Sampled at the rising edge

of the CLK if ADSP or ADSC is active LOW, and CE_1,CE₂, and CE₃are sampled active. A_[1:0]

feed the two-bit counter.

BW_a

BW_b

BW_c

BW_d

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the

SRAM. Sampled on the rising edge of CLK.

GW

Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a

global write is conducted (ALL bytes are written, regardless of the values on BW_a,b,c,dand

BWE).

Document #: 38-05285 Rev. *A

Page 5 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Pin Definitions (continued)

Pin Name

I/O

Pin Description

BWE

Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must

be asserted LOW to conduct a byte write.

CLK

CE₁

CE₂

CE₃

OE

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the

burst counter when ADV is asserted LOW, during a burst operation.

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE₂and CE₃to select/deselect the device. ADSP is ignored if CE₁is HIGH.

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction

with CE₁and CE₃to select/deselect the device. (TQFP Only)

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE₁and CE₂to select/deselect the device. (TQFP Only)

Input-

Asynchronous

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.

When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated,

and act as input data pins. OE is masked during the first clock of a read cycle when emerging

from a deselected state.

ADV

Input-

Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically

Synchronous

increments the address in a burst cycle.

ADSP

Input-

Synchronous

Address Strobefrom Processor, sampled ontherising edgeof CLK. When asserted LOW,

A is captured in the address registers. A_[1:0]are also loaded into the burst counter. When ADSP

and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE₁is

deasserted HIGH.

ADSC

MODE

ZZ

Input-

Synchronous

Address Strobe fromController, sampled on the rising edge of CLK. When asserted LOW,

A_[x:0]is captured in the address registers. A_[1:0]are also loaded into the burst counter. When

ADSP and ADSC are both asserted, only ADSP is recognized.

Input-

Static

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V_DDQor

left floating selects interleaved burst sequence. This is a strap pin and should remain static

during device operation.

Input-

Asynchronous

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”

condition with data integrity preserved.

DQa, DPa

DQb, DPb

DQc, DPc

DQd, DPd

DQe, DPe

DQf, DPf

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by A during the previous clock rise of the read cycle. The direction of the pins is

controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx

and DPx are placed in a three-state condition.DQ a,b,c,d and h are eight bits wide. DP a,b,c,d

are one bit wide.

DQg, DPg

DQh, DPh

TDO

JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA Only)

Synchronous

TDI

JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. (BGA Only)

Synchronous

TMS

Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.

Synchronous

(BGA Only)

TCK

V_DD

JTAG serial clock Serial clock to the JTAG circuit. (BGA Only)

Power Supply

Ground

Power supply inputs to the core of the device. Should be connected to

3.3 –5%/+5% power supply.

V_SS

Ground for the core of the device. Should be connected to ground of the system.

V_DDQ

V_SSQ

144M

NC

I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 2.375V(min.) to V_DD(max.)

I/O Ground

Ground for the I/O circuitry. Should be connected to ground of the system.

NC. This pin is reserved for expansion to 144 Mb.

No Connects.

–

Document #: 38-05285 Rev. *A

Page 6 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

write signals (GW, BWE, and BWx) and ADV inputs are

ignored during this first cycle.

Introduction

Functional Overview

ADSP triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQx inputs is written into the corre-

sponding address location in the RAM core. If GW is HIGH,

then the write operation is controlled by BWE and BWx

signals. The CY7C1484V33/CY7C1485V33 provides byte

write capability that is described in the Write Cycle Description

table. Asserting the Byte Write Enable input (BWE) with the

selected Byte Write (BW_a,b,c,dfor CY7C1484V33 and BW_a,b

for CY7C1485V33) input will selectively write to only the

desired bytes. Bytes not selected during a byte write operation

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

Maximum access delay from the clock rise (t_CO) is 2.6 ns

(250-MHz device).

The CY7C1484V33/CY7C1485V33 supports secondary

cache in systems utilizing either a linear or interleaved burst

sequence. The interleaved burst order supports Pentium^®and

i486 processors. The linear burst sequence is suited for

processors that utilize a linear burst sequence. The burst order

is user selectable, and is determined by sampling the MODE

input. Accesses can be initiated with either the Processor

Address Strobe (ADSP) or the Controller Address Strobe

(ADSC). Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

will remain unaltered.

A synchronous self-timed write

mechanism has been provided to simplify the write operations.

Because the CY7C1484V33/CY7C1485V33 is a common I/O

device, the Output Enable (OE) must be deasserted HIGH

before presenting data to the DQ inputs. Doing so will

three-state the output drivers. As a safety precaution, DQ are

automatically three-stated whenever a write cycle is detected,

regardless of the state of OE.

Byte write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BWa,b,c,d for CY7C1484V33

and BWa,b for CY7C1485V33) inputs. A Global Write Enable

(GW) overrides all byte write inputs and writes data to all four

bytes. All writes are simplified with on-chip synchronous

self-timed write circuitry.

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deasserted HIGH, (3) chip select is asserted active, and

(4) the appropriate combination of the write inputs (GW, BWE,

and BWx) are asserted active to conduct a write to the desired

byte(s). ADSC triggered write accesses require a single clock

cycle to complete. The address presented to A_[x:0]is loaded

into the address register and the address advancement logic

while being delivered to the RAM core. The ADV input is

ignored during this cycle. If a global write is conducted, the

data presented to the DQ_[x:0]is written into the corresponding

address location in the RAM core. If a byte write is conducted,

only the selected bytes are written. Bytes not selected during

a byte write operation will remain unaltered. A synchronous

self-timed write mechanism has been provided to simplify the

write operations.

Synchronous Chip Selects (CE₁, CE₂, CE₃for TQFP/CE₁for

BGA) and an asynchronous Output Enable (OE) provide for

easy bank selection and output three-state control. ADSP is

ignored if CE₁is HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,

(2) chip selects are all asserted active, and (3) the write signals

(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE₁

is HIGH. The address presented to the address inputs is

stored into the address advancement logic and the Address

Register while being presented to the memory core. The corre-

sponding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next clock the data

is allowed to propagate through the output register and onto

the data bus within 2.6 ns (250-MHz device) if OE is active

LOW. The only exception occurs when the SRAM is emerging

from a deselected state to a selected state, its outputs are

always three-stated during the first cycle of the access. After

the first cycle of the access, the outputs are controlled by the

OE signal. Consecutive single read cycles are supported.

Because the CY7C1484V33/CY7C1485V33 is a common I/O

device, the Output Enable (OE) must be deasserted HIGH

before presenting data to the DQ_[x:0]inputs. Doing so will

three-state the output drivers. As a safety precaution, DQ_[x:0]

are automatically three-stated whenever a write cycle is

detected, regardless of the state of OE.

Burst Sequences

The CY7C1484V33/CY7C1485V33 provides

a

two-bit

wraparound counter, fed by A_[1:0], that implements either an

interleaved or linear burst sequence. The interleaved burst

sequence is designed specifically to support Intel Pentium

applications. The linear burst sequence is designed to support

processors that follow a linear burst sequence. The burst

sequence is user selectable through the MODE input.

The CY7C1484V33/CY7C1485V33 are double-cycle deselect

parts. Once the SRAM is deselected at clock rise by the chip

select and either ADSP or ADSC signals, its output will

three-state immediately after the next clock rise.

Single Write Accesses Initiated by ADSP

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both read and write burst operations are supported. Asserting

ADV LOW at clock rise will automatically increment the burst

counter to the next address in the burst sequence. Both read

and write burst operations are supported.

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2) chip select is asserted active. The address presented is

loaded into the address register and the address

advancement logic while being delivered to the RAM core. The

Document #: 38-05285 Rev. *A

Page 7 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Sleep Mode

Interleaved Burst Sequence

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CEs, ADSP, and ADSC must remain

inactive for the duration of t_ZZRECafter the ZZ input returns

LOW.

First

Second

Third

Fourth

Address

A_[1:0]]

00

A_[1:0]

01

A_[1:0]

10

A_[1:0]

11

01

00

11

10

11

00

01

11

10

01

00

Linear Burst Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

A_[1:0]

00

A_[1:0]

01

A_[1:0]

10

A_[1:0]

11

01

10

11

00

10

11

00

01

11

00

01

10

Parameter

Description

Test Conditions

ZZ > V_DD– 0.2V

ZZ < 0.2V

Min.

Max.

TBD

Unit

mA

ns

I_DDZZ

Snooze mode standby current

Device operation to ZZ

ZZ recovery time

t_ZZS

2t_CYC

t_ZZREC

2t_CYC

ns

[1, 2, 3, 4]

Cycle Descriptions

Next Cycle

Unselected

Add. Used

ZZ

0

CE₃

X

1

CE₂

X

0

CE₁

ADSP

ADSC

ADV

OE

X

1

DQ

Write

X

None

1

0

X

1

X

1

X

1

0

X

0

1

0

1

X

1

X

1

X

1

0

X

0

X

0

1

0

X

0

1

X

Hi-Z

DQ

Unselected

None

X

Unselected

None

X

1

X

Unselected

None

X

0

X

Unselected

None

X

0

X

Begin Read

External

X

Begin Read

0

1

Read

Write

Continue Read

Suspend Read

Begin Write

X

0

X

1

Hi-Z

DQ

Current

External

1

Hi-Z

DQ

0

1

Hi-Z

DQ

0

X

Hi-Z

Begin Write

Notes:

1. X = “Don’t Care.” 1 = HIGH, 0 = LOW.

2. Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table.

3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

4. CE₁, CE₂, and CE₃are available only in the TQFP package. BGA package has a single chip select CE₁.

Document #: 38-05285 Rev. *A

Page 8 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Cycle Descriptions (continued)^{[1, 2, 3, 4]}

Next Cycle

Continue Write

Suspend Write

ZZ “sleep”

Add. Used

0

CE₃

X

CE₂

X

CE₁

X

ADSP

ADSC

ADV

OE

X

DQ

Hi-Z

Write

X

1

X

1

X

0

1

X

1

X

Current

None

0

X

0

X

1

X

1

X

Write Cycle Descriptions^{[1, 2]}

Function (CY7C1484V33)

GW

BWE

BW_d

BW_c

X

1

BW_b

BW_a

Read

1

0

1

0

X

1

0

X

1

0

1

0

1

0

1

0

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

Write Byte 0 – DQa

Write Byte 1 – DQb

Write Bytes 1, 0

Write Byte 2 – DQc

Write Bytes 2, 0

Write Bytes 2, 1

Write Bytes 2, 1, 0

Write Byte 3 – DQd

Write Bytes 3, 0

Write Bytes 3, 1

Write Bytes 3, 1, 0

Write Bytes 3, 2

Write Bytes 3, 2, 0

Write Bytes 3, 2, 1

Write All Bytes

1

0

1

0

Write All Bytes

X

Function (CY7C1485V33)

GW

1

BWE

BW_b

BW_a

Read

1

0

X

1

0

X

1

0

1

0

X

Read

1

Write Byte 0–DQ_[7:0]and DP₀

Write Byte 1–DQ_[15:8]and DP₁

Write All Bytes

1

Write All Bytes

0

Document #: 38-05285 Rev. *A

Page 9 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

circuitry. Only one register can be selected at a time through

the instruction registers. Data is serially loaded into the TDI pin

on the rising edge of TCK. Data is output on the TDO pin on

the falling edge of TCK.

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1484V33/CY7C1485V33 incorporates a serial

boundary scan Test Access Port (TAP) in the FBGA package

only. The TQFP package does not offer this functionality. This

port operates in accordance with IEEE Standard 1149.1–1900,

but does not have the set of functions required for full 1149.1

compliance. These functions from the IEEE specification are

excluded because their inclusion places an added delay in the

critical speed path of the SRAM. Note that the TAP controller

functions in a manner that does not conflict with the operation

of other devices using 1149.1 fully compliant TAPs. The TAP

operates using JEDEC standard 3.3V I/O logic levels.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

register. This register is loaded when it is placed between the

TDI and TDO pins as shown in the TAP Controller Block

Diagram. Upon power-up, the instruction register is loaded

with the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.

When the TAP controller is in the CaptureIR state, the two least

significant bits are loaded with a binary “01” pattern to allow for

fault isolation of the board level serial test path.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(V_SS) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to V_DDthrough a pull-up resistor. TDO should

be left unconnected. Upon power-up, the device will come up

in a reset state which will not interfere with the operation of the

device.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain states. The bypass

register is a single-bit register that can be placed between TDI

and TDO pins. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

(V_SS) when the BYPASS instruction is executed.

Test Access Port—Test Clock

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

Boundary Scan Register

The boundary scan register is connected to all the input and

output pins on the SRAM. Several no connect (NC) pins are

also included in the scan register to reserve pins for higher

density devices. The ×36 configuration has a 70-bit-long

register, and the ×18 configuration has a 51-bit-long register.

Test Mode Select

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this pin unconnected if the TAP is not used. The pin is

pulled up internally, resulting in a logic HIGH level.

The boundary scan register is loaded with the contents of the

RAM Input and Output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and

TDO pins when the controller is moved to the Shift-DR state.

The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-

tions can be used to capture the contents of the Input and

Output ring.

Test Data-in (TDI)

The TDI pin is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. For

information on loading the instruction register, see the TAP

Controller State Diagram. TDI is internally pulled up and can

be unconnected if the TAP is unused in an application. TDI is

connected to the Most Significant Bit (MSB) on any register.

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI, and the LSB is connected to TDO.

Identification (ID) Register

Test Data-out (TDO)

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

The TDO output pin is used to serially clock data-out from the

registers. The e output is active depending upon the current

state of the TAP state machine (see TAP Controller State

Diagram). The output changes on the falling edge of TCK.

TDO is connected to the Least Significant Bit (LSB) of any

register.

Performing a TAP Reset

TAP Instruction Set

A Reset is performed by forcing TMS HIGH (V_DD) for five rising

edges of TCK. This RESET does not affect the operation of

the SRAM and may be performed while the SRAM is

operating. At power-up, the TAP is reset internally to ensure

that TDO comes up in a high-Z state.

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in the

Instruction Code table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

The TAP controller used in this SRAM is not fully compliant to

the 1149.1 convention because some of the mandatory 1149.1

instructions are not fully implemented. The TAP controller

cannot be used to load address, data or control signals into the

TAP Registers

Registers are connected between the TDI and TDO pins and

allow data to be scanned into and out of the SRAM test

Document #: 38-05285 Rev. *A

Page 10 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

SRAM and cannot preload the Input or Output buffers. The

SRAM does not implement the 1149.1 commands EXTEST or

INTEST or the PRELOAD portion of SAMPLE/PRELOAD;

rather it performs a capture of the Inputs and Output ring when

these instructions are executed.

When the SAMPLE/PRELOAD instructions loaded into the

instruction register and the TAP controller in the Capture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 10 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is

possible that during the Capture-DR state, an input or output

will undergo a transition. The TAP may then try to capture a

signal while in transition (metastable state). This will not harm

the device, but there is no guarantee as to the value that will

be captured. Repeatable results may not be possible.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO pins.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be

executed whenever the instruction register is loaded with all

0s. EXTEST is not implemented in the TAP controller, and

therefore this device is not compliant to the 1149.1 standard.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller’s capture set-up plus

hold times (TCS and TCH). The SRAM clock input might not

be captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE/PRELOAD instruction. If this

is an issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK captured in the

boundary scan register.

The TAP controller does recognize an all-0 instruction. When

an EXTEST instruction is loaded into the instruction register,

the SRAM responds as if a SAMPLE/PRELOAD instruction

has been loaded. There is one difference between the two

instructions. Unlike the SAMPLE/PRELOAD instruction,

EXTEST places the SRAM outputs in a High-Z state.

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the

boundary scan register between the TDI and TDO pins.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO pins and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state. The IDCODE instruction

is loaded into the instruction register upon power-up or

whenever the TAP controller is given a test logic reset state.

Note that since the PRELOAD part of the command is not

implemented, putting the TAP into the Update to the

Update-DR state while performing a SAMPLE/PRELOAD

instruction will have the same effect as the Pause-DR

command.

Bypass

When the BYPASS instruction is loaded in the instruction

register and the TAP is placed in a Shift-DR state, the bypass

register is placed between the TDI and TDO pins. The

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO pins when the TAP

controller is in a Shift-DR state. It also places all SRAM outputs

into a High-Z state.

SAMPLE/PRELOAD

Reserved

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The

PRELOAD portion of this instruction is not implemented, so

the TAP controller is not fully 1149.1-compliant.

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

Document #: 38-05285 Rev. *A

Page 11 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

TAP Controller State Diagram

TEST-LOGIC

RESET

1^[5]

1

TEST-LOGIC/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

0

1

CAPTURE-DR

0

SHIFT-DR

0

SHIFT-IR

0

1

EXIT1-DR

0

1

EXIT1-IR

0

1

0

PAUSE-DR

1

PAUSE-IR

1

0

EXIT2-DR

1

EXIT2-IR

1

UPDATE-DR

UPDATE-IR

1

0

Note:

5. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document #: 38-05285 Rev. *A

Page 12 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

TAP Controller Block Diagram

0

Bypass Register

Selection

Circuitry

Selection

Circuitry

2

1

0

TDO

TDI

Instruction Register

29

31 30

.

2

0

Identification Register

.

2

1

0

Boundary Scan Register

TCK

TMS

TAP Controller

TAP Electrical Characteristics Over the Operating Range^{[6, 7]}

Parameter

V_OH1

Description

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Input Load Current

Test Conditions

I_OH= −4.0 mA

Min.

2.4

Max.

Unit

V

V_OH2

V_OL1

V_OL2

V_IH

I_OH= −100 µA

I_OL= 8.0 mA

I_OL= 100 µA

3.0

0.4

0.2

V

1.8

–0.5

–5

V_DD+ 0.3

0.8

V

V_IL

V

I_X

GND ≤ V_I≤ V_DDQ

5

µA

[8, 9]

TAP AC Switching Characteristics Over the Operating Range

Parameters

Description

Min.

Max.

Unit

ns

t_TCYC

TCK Clock Cycle Time

TCK Clock Frequency

TCK Clock HIGH

100

t_TF

10

MHz

ns

t_TH

40

t_TL

TCK Clock LOW

ns

Set-up Times

t_TMSS

TMS Set-up to TCK Clock Rise

TDI Set-up to TCK Clock Rise

Capture Set-up to TCK Rise

10

ns

t_TDIS

t_CS

Hold Times

t_TMSH

TMS Hold after TCK Clock Rise

10

ns

Notes:

6. All voltage referenced to ground.

7. Overshoot: V_IH(AC) < V_DD+ 1.5V for t < t_TCYC/2; undershoot: V_IL(AC) < 0.5V for t < t_TCYC/2; power-up: V_IH< 2.6V and V_DD< 2.4V and V_DDQ< 1.4V for t <

200 ms.

8. t_CSand t_CHrefer to the set-up and hold time requirements of latching data from the boundary scan register.

9. Test conditions are specified using the load in TAP AC test conditions. t_R/t_F= 1 ns.

Document #: 38-05285 Rev. *A

Page 13 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

TAP AC Switching Characteristics Over the Operating Range (continued)^{[8, 9]}

Parameters

t_TDIH

Description

Min.

10

Max.

Unit

ns

TDI Hold after Clock Rise

t_CH

Capture Hold after Clock Rise

10

ns

Output Times

t_TDOV

TCK Clock LOW to TDO Valid

TCK Clock LOW to TDO Invalid

20

ns

t_TDOX

0

TAP Timing and Test Conditions

1.25V

ALL INPUT PULSES

V

IH

50Ω

0V

TDO

Z = 50Ω

0

C = 20 pF

L

t_TL

t_TH

(a)

GND

Test Clock

TCK

t_TCYC

t_TMSS

t_TMSH

Test Mode Select

TMS

t_TDIS

t_TDIH

Test Data-In

TDI

Test Data-Out

TDO

t_TDOV

t_TDOX

Identification Register Definitions

Instruction Field

Revision Number (31:29)

Department Number (27:25)

Voltage (28&24)

×18

×36

000

101

00

Description

000

Reserved for version number

Department number

101

00

Architecture (23:21)

000

110

100

Architecture type

Memory type (20:18)

Device Width (17:15)

Device Density (14:12)

Cypress JEDEC ID (11:1)

ID Register Presence (0)

110

Defines type of memory

010

Defines width of the SRAM. ×36 or ×18

Defines the density of the SRAM

100

00000110100

1

00000110100

1

Allows unique identification of SRAM vendor

Indicates the presence of an ID register

Document #: 38-05285 Rev. *A

Page 14 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Scan Register Sizes

Register Name

Bit Size (×18)

Bit Size (×36)

Instruction

Bypass

3

1

3

1

ID

32

Boundary Scan

TBD

Identification Codes

Instruction

EXTEST

Code

Description

000

001

010

011

Captures the Input/Output ring contents. Places the boundary scan register between the TDI

and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.

IDCODE

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

SAMPLE Z

Captures the Input/Output contents. Places the boundary scan register between TDI and

TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100

Captures the Input/Output ring contents. Places the boundary scan register between TDI and

TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1

preload function and is therefore not 1149.1-compliant.

RESERVED

BYPASS

101

110

111

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operation.

Document #: 38-05285 Rev. *A

Page 15 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Boundary Scan Order (4M × 18)

Boundary Scan Order (2M × 36)

Signal

Name

Bump

ID

Signal

Name

Bump

ID

Signal

Name

Bump

ID

Signal

Name

Bump

Bit #

TBD

Bit #

TBD

Bit #

TBD

Bit #

TBD

ID

TBD

Document #: 38-05285 Rev. *A

Page 16 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–55°C to +150°C

Latch-up Current.................................................... > 200 mA

Operating Range

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Ambient

Supply Voltage on V_DDRelative to GND........ –0.3V to +4.6V

Range Temp.^[11]

V_DD

V_DDQ

DC Voltage Applied to Outputs

in High-Z State^[10]............................... –0.5V to V_DDQ+ 0.5V

Com’l

0°C−70°C 3.3V +5% /–5%

2.375V(min.)

V_DD(max.)

DC Input Voltage^[10]............................ –0.5V to V_DDQ+ 0.5V

Electrical Characteristics Over the Operating Range

Parameter

V_DD

Description

Test Conditions

Min.

3.135

2.375

2.4

Max.

3.465

V_DD

Unit

Power Supply Voltage

I/O Supply Voltage

Output HIGH Voltage

V

V_DDQ

V_OH

V_DD= Min., I_OH= –4.0 mA

3.3V

V

V_DD= Min., I_OH= –1.0 mA

V_DD= Min., I_OL= 8.0 mA

V_DD= Min., I_OL= 1.0 mA

2.5V

3.3V

2.5V

3.3V

2.5V

3.3V

2.5V

2.0

V

V_OL

V_IH

V_IL

I_X

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage^[10]

0.4

V

2.0

1.7

V

–0.3

0.8

0.7

5

V

Input Load Current

Input Current of MODE

Input Current of ZZ

GND < V_I< V_DDQ

Input = V_SS

µA

30

5

I_OZ

I_DD

Output Leakage

Current

GND < V_I< V_DDQ,Output Disabled

V_DDOperating Supply

V_DD= Max., I_OUT= 0 mA,

f = f_MAX= 1/t_CYC

250 MHz

TBD

mA

200 MHz

167 MHz

250 MHz

200 MHz

167 MHz

I_SB1

Automatic CE

Power-down

Current—TTL Inputs

Max. V_DD, Device

Deselected,

V_IN> V_IHor V_IN< V_IL

f = f_MAX= 1/t_CYC

I_SB2

Automatic CE

Power-down

Max. V_DD, Device

Deselected, V_IN< 0.3V or V_IN

All speed grades

TBD

mA

Current—CMOS Inputs > V_DDQ− 0.3V, f = 0

I_SB3

Automatic CE

Power-down

Current—CMOS Inputs V_IN> V_DDQ– 0.3V

Max. V_DD, Device

Deselected, or V_IN< 0.3V or

250 MHz

200 MHz

167 MHz

TBD

mA

f = f_MAX= 1/t_CYC

I_SB4

Automatic CE

Power-down

Current—TTL Inputs

Max. V_DD, Device

Deselected, V_IN> V_IHor V_IN

V_IL, f = 0

All speed grades

TBD

mA

<

Shaded areas contain advance information.

Notes:

10. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.

11. _Ais the temperature.

T

Document #: 38-05285 Rev. *A

Page 17 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Capacitance^[12]

Parameter

Description

Input Capacitance

Test Conditions

T_A= 25°C, f = 1 MHz,

Max.

Unit

pF

C_IN

TBD

V_DD= 3.3V, V_DDQ= 2.5V

C_CLK

C_I/O

Clock Input Capacitance

Input/Output Capacitance

pF

Thermal Resistance^[12]

Parameter

Description

Test Conditions

BGA Typ.

Q_JA

Thermal Resistance (Junction to Still Air, soldered on a 4.25 ×

TBD

Ambient)

1.125 inch, four-layer printed

circuit board

Q_JC

Thermal Resistance (Junction to

Case)

TBD

AC Test Loads and Waveforms^[13]

R = 317Ω

V

[10]

DDQ

OUTPUT

ALL INPUT PULSES

90%

OUTPUT

Vdd

90%

10%

Z = 50Ω

0

R = 50Ω

10%

2 V/ns

L

5 pF

GND

R = 351Ω

INCLUDING

JIG AND

SCOPE

2 V/ns

= 1.5V for 3.3V V

V_TH

(a)

DDQ

= 1.25V for 2.5V V

DDQ

(c)

(b)

Switching Characteristics Over the Operating Range

-250

-200

-167

Parameter

Clock

Description

Min.

Max.

Min.

Max.

Min.

Max.

Unit

t_CYC

Clock Cycle Time

4.0

5

6

ns

MHz

ns

F_MAX

t_CH

Maximum Operating Frequency

Clock HIGH

250

200

167

1.7

2.0

2.4

t_CL

Clock LOW

ns

Output Times

t_CO

Data Output Valid After CLK Rise

OE LOW to Output Valid^{[ 15, 17]}

Data Output Hold After CLK Rise

Clock to High-Z^{[14, 15, 16, 17]}

Clock to Low-Z^{[14, 15, 16, 17]}

OE HIGH to Output High-Z^{[14, 15, 17]}

OE LOW to Output Low-Z^{[14, 15, 17]}

2.6

3.0

3.4

ns

t_EOV

t_DOH

1.0

0

1.3

0

1.5

0

t_CHZ

2.6

3.0

3.4

t_CLZ

t_EOHZ

t_EOLZ

Set-up Times

t_AS

Address Set-up Before CLK Rise

1.2

1.4

1.5

ns

Shaded areas contain advance information.

Notes:

12. Tested initially and after any design or process changes that may affect these parameters.

13. Input waveform should have a slew rate of 2 V/ns.

14. Unless otherwise noted, test conditions assume signal transition time of 1.5 ns, timing reference levels of 1.5V, input pulse levels of 0 to 3.3V, and output

loading of the specified I_OL/I_OHand load capacitance. Shown in (a), (b) and (c) of AC Test Loads.

15.

t_CHZ, t_CLZ, t_OEV, t_EOLZ, and t_EOHZare specified with AC test conditions shown in (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state

voltage.

16. At any given voltage and temperature, t_EOHZis less than t_EOLZand t_CHZis less than t_CLZto eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

17. This parameter is sampled and not 100% tested.

Document #: 38-05285 Rev. *A

Page 18 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Switching Characteristics Over the Operating Range (continued)

-250

-200

Max.

-167

Parameter

t_DS

Description

Min.

1.2

Max.

Min.

1.4

Min.

1.5

Max.

Unit

ns

Data Input Set-up Before CLK Rise

ADSP, ADSC Set-up Before CLK Rise

BWE, GW, BW_xSet-up Before CLK Rise

ADV Set-up Before CLK Rise

Chip Select Set-up

t_ADS

ns

t_WES

t_ADVS

t_CES

ns

Hold Times

t_AH

Address Hold After CLK Rise

Data Input Hold After CLK Rise

ADSP, ADSC Hold After CLK Rise

BWE, GW, BW_xHold After CLK Rise

ADV Hold after CLK Rise

0.3

0.4

0.5

ns

t_DH

t_ADH

t_WEH

t_ADVH

t_CEH

Chip Select Hold After CLK Rise

Document #: 38-05285 Rev. *A

Page 19 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Switching Waveforms

Write Cycle Timing^{[4, 18, 19]}

Single Write

t_CYC

t_ADH

Burst Write

Pipelined Write

t_CH

Unselected

CLK

t_ADS

t_CL

ADSP ignored with CE₁inactive

ADSP

ADSC

ADV

t_ADH

t_ADS

ADSC initiated write

t_ADVH

t_ADVS

t_AS

ADV Must Be Inactive for ADSP Write

WD3

ADD

GW

WE

WD1

WD2

t_AH

t_WH

t_WS

t_CES

t_CEH

CE₁masks ADSP

CE₁

t_CEH

t_CES

Unselected with CE₂

CE₂

CE₃

OE

t_CES

t_CEH

t_DH

t_DS

High-Z

Data In

3a

2a

1a

2b

2c

2d

= DON’T CARE

= UNDEFINED

Notes:

18. WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Descriptions table).

19. WDx stands for Write Data to Address X.

Document #: 38-05285 Rev. *A

Page 20 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Switching Waveforms (continued)

Read Cycle Timing^{[4, 18, 20]}

Burst Read

Single Read

t_CYC

Unselected

t_CH

Pipelined Read

CLK

t_ADH

t_ADS

t_CL

ADSP ignored with CE₁inactive

ADSP

t_ADS

ADSC initiated read

ADSC

ADV

t_ADVS

t_ADH

Suspend Burst

t_ADVH

t_AS

ADD

GW

RD3

RD1

RD2

t_AH

t_WS

t_WH

WE

t_CES

t_CEH

t_WH

CE₁masks ADSP

CE₁

Unselected with CE₂

CE₂

t_CES

t_CEH

CE₃

OE

t_CES

t_EOV

t_CEH

t_OEHZ

t_DOH

Double-Cycle

Deselect

t_CO

Data Out

2c

1a

3a

2d

2a

2b

t_CLZ

t_CHZ

= DON’T CARE

= UNDEFINED

Note:

20. RDx stands for Read Data from Address X.

Document #: 38-05285 Rev. *A

Page 21 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Switching Waveforms (continued)

Read/Write Cycle Timing^{[4, 18, 19, 20, 21, 22]}

Single Write

Single Read

t_CYC

Single Write

t_CH

Burst Read

Pipelined Read

CLK

t_ADS

t_ADH

t_CL

ADSP

ADSC

ADV

t_ADVS

t_AS

t_ADVH

WD2

ADD

RD1

RD4

WD3

RD5

t_AH

GW

WE

t_WS

t_WH

t_CES

t_WH

t_CEH

Deselect cycle

CE₁

CE₂

CE₃

t_CES

t_CEH

t_EOV

t_CES

t_CEH

OE

t_EOHZ

t_DS

t_DH

t_DOH

t_EOLZ

t_CO

4b

Out

4c

Out

4a

Out

4d

Data In/Out

5a

Out

1a

2a

In

3a

In

Out

t_CHZ

= UNDEFINED

= DON’T CARE

Notes:

21. Device originally deselected.

22. CE is the combination of CE₂and CE₃. All chip selects need to be active in order to select the device.

Document #: 38-05285 Rev. *A

Page 22 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Switching Waveforms (continued)

Pipelined Read/Write Timing^{[4, 18, 19, 20]}

ADSC read

ADSP read

Unselected

ADSC write

ADSP write

CLK

ADSP

ADSC

ADV

ADD

GW

RD1

RD2

RD3

RD4

WD6

WD8

WD5

WD7

WE

CE₁

Deselect cycle

CE₂

CE₃

OE

4a

Out

6a

In

3a

Out

5a

In

7a

In

Data In/Out

1a

2a

Out

= UNDEFINED

= DON’T CARE

Document #: 38-05285 Rev. *A

Page 23 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Switching Waveforms (continued)

OE Switching Waveforms

OE

t_EOV

t_EOHZ

Three-State

I/Os

t_EOLZ

ZZ Mode Timing ^{[4, 23, 24]}

CLK

ADSP

HIGH

ADSC

CE₁

LOW

HIGH

CE₂

CE₃

ZZ

t_ZZS

I_DD(active)

I_DD

I_DDZZ

t_ZZREC

I/Os

Three-state

Notes:

23. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.

24. I/Os are in three-state when exiting ZZ sleep mode.

Document #: 38-05285 Rev. *A

Page 24 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Ordering Information

Speed

(MHz)

Package

Name

Operating

Range

Ordering Code

Package Type

250

CY7C1484V33-250AC

CY7C1485V33-250AC

A101

BG119

BB165C

A101

100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack Commercial

CY7C1484V33-250BGC

CY7C1485V33-250BGC

119-ball BGA (14 × 22 × 2.4 mm)

CY7C1484V33-250BZC

CY7C1485V33-250BZC

165-ball BGA (15 × 17 mm)

200

167

CY7C1484V33-200AC

CY7C1485V33-200AC

100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack

119-ball BGA (14 × 22 × 2.4 mm)

CY7C1484V33-200BGC

CY7C1485V33-200BGC

BG119

BB165C

A101

CY7C1484V33-200BZC

CY7C1485V33-200BZC

165-ball BGA (15 × 17 mm)

CY7C1484V33-167AC

CY7C1485V33-167AC

100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack

119-ball BGA (14 × 22 × 2.4 mm)

CY7C1484V33-167BGC

CY7C1485V33-167BGC

BG119

BB165C

CY7C1484V33-167BZC

CY7C1485V33-167BZC

165-ball BGA (15 × 17 mm)

Shaded areas contain advance information.

Document #: 38-05285 Rev. *A

Page 25 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Package Diagrams

100-lead Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101

51-85050-A

Document #: 38-05285 Rev. *A

Page 26 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Package Diagrams (continued)

165-ball FBGA (15 × 17 × 1.20 mm) BB165C

51-85165-**

Document #: 38-05285 Rev. *A

Page 27 of 29

CY7C1484V33

CY7C1485V33

PRELIMINARY

Package Diagrams (continued)

119-Lead PBGA (14 x 22 x 2.4 mm) BG119

51-85115-*B

Pentium is a registered trademark, and i486 is a trademark, of Intel Corporation. All product and company names mentioned in

this document are the trademarks of their respective holders.

Document #: 38-05285 Rev. *A

Page 28 of 29

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C1484V33

CY7C1485V33

PRELIMINARY

Document History Page

Document Title: CY7C1484V33/CY7C1485V33 2M x 36/4M x 18 Pipelined DCD SRAM

Document Number: 38-05285

Orig. of

REV.

**

ECN NO. Issue Date Change

Description of Change

114672

118285

08/21/02

01/20/03

PKS

HGK

New Data Sheet

*A

Changed tCO from 2.4 to 2.6 ns for 250 MHz

Updated Features on package offering

Updated Ordering Information

Changed Advanced Information to Preliminary

Document #: 38-05285 Rev. *A

Page 29 of 29


型号：	CY7C1484V33-250AC
厂家：	CYPRESS
描述：	2M x 36/4M x 18 Pipelined DCD SRAM 2M ×36 / 4M x 18位流水线DCD SRAM 静态存储器 CD
文件：	总29页 (文件大小：508K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C1484V33-250AC [CYPRESS]

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