CY7C1485V33-250BZXI [CYPRESS]
72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM; 72兆位（ 2M ×36 / 4M ×18 ）流水线DCD同步SRAM
| 型号： | CY7C1485V33-250BZXI |
| 厂家： | 
CYPRESS |
| 描述： | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| 文件： | 总26页 (文件大小：1152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1484V33
CY7C1485V33
72-Mbit (2M x 36/4M x 18) Pipelined
DCD Sync SRAM
Features
Functional Description[1]
• Supports bus operation up to 250 MHz
The CY7C1484V33/CY7C1485V33 SRAM integrates 2M x
36/4M x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE1), depth-expansion Chip
Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP,
and ADV), Write Enables (BWX, and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (double cycle deselect)
• Depth expansion without wait state
• 3.3V core power supply (VDD
• 2.5V/3.3V IO operation
)
• Fast clock-to-output times
— 3.0 ns (for 250 MHz device)
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
• Provide high performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel®
Address Strobe Controller (
burst addresses can be internally generated as controlled by
) are active. Subsequent
ADSC
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed writes
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle. This part supports byte write
operations (see “Pin Definitions” on page 5 and “Truth Table”
on page 8 for further details). Write cycles can be one to four
bytes wide as controlled by the byte write control inputs. GW
active LOW causes all bytes to be written. This device incor-
porates an additional pipelined enable register which delays
turning off the output buffers an additional cycle when a
deselect is executed.This feature enables depth expansion
without penalizing system performance.
• Asynchronous output enable
• CY7C1484V33, CY7C1485V33 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode option
The CY7C1484V33/CY7C1485V33 operates from a +3.3V
core power supply while all outputs operate with a +3.3V or a
+2.5V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
250 MHz
200 MHz
3.0
167 MHz
3.4
Unit
ns
Maximum Access Time
3.0
500
120
Maximum Operating Current
Maximum CMOS Standby Current
500
450
mA
mA
120
120
Note
1. For best practices recommendations, please refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 38-05285 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 01, 2007
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CY7C1484V33
CY7C1485V33
Logic Block Diagram – CY7C1484V33 (2M x 36)
ADDRESS
REGISTER
A0,A1,A
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ D, DQP
BYTE
WRITE REGISTER
D
DQ D, DQP
BYTE
WRITE DRIVER
D
BW
BW
D
DQ ,DQP
c
C
DQ
BYTE
WRITE REGISTER
c,DQP C
MEMORY
ARRAY
BYTE
WRITE DRIVER
C
OUTPUT
BUFFERS
OUTPUT
REGISTERS
SENSE
AMPS
DQs
DQP
DQP
DQP
A
B
C
DQ
BYTE
WRITE DRIVER
B,DQP B
E
DQ
BYTE
WRITE REGISTER
B,DQP B
BW
BW
B
DQP
D
DQ A, DQP
BYTE
A
DQ A, DQP
BYTE
A
A
WRITE DRIVER
WRITE REGISTER
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
ZZ
CONTROL
Logic Block Diagram – CY7C1485V33 (4M x 18)
ADDRESS
REGISTER
A0, A1,
A
2
A[1:0]
MODE
ADV
Q1
BURST
CLK
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
BYTE
WRITE DRIVER
B , DQP B
DQ B, DQP
BYTE
WRITE REGISTER
B
OUTPUT
BUFFERS
BW
B
OUTPUT
REGISTERS
DQ s,
DQP
DQP
SENSE
AMPS
MEMORY
ARRAY
A
B
DQ A, DQP
BYTE
A
E
DQ
A , DQP A
BYTE
WRITE REGISTER
BW
A
WRITE DRIVER
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE
CE
1
PIPELINED
ENABLE
2
3
CE
OE
SLEEP
CONTROL
ZZ
Document #: 38-05285 Rev. *G
Page 2 of 26
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CY7C1484V33
CY7C1485V33
Pin Configurations
100-Pin TQFP Pinout
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQC
VDDQ
VSSQ
DQC
3
4
5
6
DQC
7
NC
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
DQC
9
10
11
9
VSSQ
VDDQ
DQC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
12
DQC
13
NC
14
VDD
15
NC
VDD
ZZ
CY7C1485V33
(4M x 18)
CY7C1484V33
(2M X 36)
NC
16
VDD
ZZ
VSS
17
DQD
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
20
21
VDDQ
VSSQ
DQD
22
DQD
23
DQD
24
DQD
25
26
27
NC
VSSQ
VDDQ
DQD
DQD
29
VSSQ
VDDQ
NC
NC
NC
VSSQ
VDDQ
NC
NC
NC
28
DQPD
30
Document #: 38-05285 Rev. *G
Page 3 of 26
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CY7C1484V33
CY7C1485V33
Pin Configurations (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1484V33 (2M x 36)
1
2
A
3
4
5
6
7
8
9
10
A
11
NC
NC/288M
NC/144M
DQPC
A
B
C
D
CE1
CE2
VDDQ
VDDQ
BWC
BWD
VSS
VDD
BWB
BWA
VSS
VSS
CE3
CLK
VSS
VSS
ADSC
BWE
GW
VSS
VSS
ADV
ADSP
VDDQ
VDDQ
A
A
NC/576M
DQPB
DQB
OE
VSS
VDD
NC
DQC
NC/1G
DQB
DQC
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
TDI
A1
TDO
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
CY7C1485V33 (4M x 18)
1
2
A
3
4
5
NC
6
7
8
9
10
A
11
A
NC/288M
NC/144M
NC
A
B
C
D
BWB
NC
CE3
CLK
VSS
VSS
CE1
CE2
BWE
GW
VSS
VSS
ADSC
OE
ADV
ADSP
VDDQ
VDDQ
A
BWA
VSS
VSS
A
NC/1G
NC
NC/576M
DQPA
DQA
NC
VDDQ
VDDQ
VSS
VDD
VSS
NC
DQB
VDD
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
‘VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
DQA
DQA
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
TDI
A1
A0
TDO
MODE
A
A
A
TMS
TCK
A
A
A
A
R
Document #: 38-05285 Rev. *G
Page 4 of 26
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CY7C1484V33
CY7C1485V33
Pin Definitions
Pin Name
IO
Description
A0, A1, A
Input-
Synchronous
Address Inputs Used to Select One of the Address Locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE1,CE2, andCE3 are sampled active.
A1: A0 are fed to the two-bit counter.
BWA, BWB
BWC, BWD
Input-
Synchronous
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK,
a global write is conducted (ALL bytes are written, regardless of the values on BWX and
BWE).
BWE
CLK
CE1
Input-
Synchronous
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW during a burst operation.
Input-
Synchronous
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE and CE to select or deselect the device. ADSP is ignored
sampled only when a new external address is loaded.
if CE1 is HIGH. CE1 is
2
3
CE2
CE3
OE
Input-
Synchronous
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external
address is loaded.
Input-
Synchronous
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external
address is loaded.
Input-
Asynchronous
Output Enable, Asynchronous Input, active LOW. Controls the direction of the IO pins.
When LOW, the IO pins behave as outputs. When deasserted HIGH, DQ pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
ADV
Input-
Synchronous
Advance Input Signal, Sampled on the Rising Edge of CLK, Active LOW. When
asserted, it automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
Input-
Synchronous
Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
ZZ
Input-
Asynchronous
ZZ “Sleep” Input, Active HIGH. When asserted HIGH, places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull down.
IO-
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory
DQs, DQPs
Synchronous
location specified by the addresses presented during the previous clock rise ofthe read cycle
The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave
as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.
.
VDD
VSS
Power Supply
Ground
Power supply inputs to the core of the device.
Ground for the core of the device.
Ground for the IO circuitry.
[2]
VSSQ
IO Ground
VDDQ
IO Power Supply Power supply for the IO circuitry.
Note
2. Applicable for TQFP package. For BGA package V serves as ground for the core and the IO circuitry.
SS
Document #: 38-05285 Rev. *G
Page 5 of 26
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CY7C1484V33
CY7C1485V33
Pin Definitions (continued)
Pin Name
MODE
IO
Description
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD
or left floating selects interleaved burst sequence. This is a strap pin and must remain static
during device operation. Mode Pin has an internal pull up.
TDO
TDI
JTAG Serial Output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
Synchronous
feature is not used, this pin must be disconnected. This pin is not available on TQFP
packages.
JTAG Serial
Input
Synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not used, this pin can be disconnected or connected to VDD. This pin is not available on
TQFP packages.
TMS
JTAG Serial
Input
Synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not used, this pin can be disconnected or connected to VDD. This pin is not available on
TQFP packages.
TCK
NC
JTAG Clock
-
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be
connected to VSS. This pin is not available on TQFP packages.
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
is allowed to propagate through the output register and onto
the data bus within tCO if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state; its outputs are always tri-stated during the
first cycle of the access. After the first cycle of the access, the
outputs are controlled by the OE signal. Consecutive single
read cycles are supported.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1484V33/CY7C1485V33 supports secondary
cache in systems using either a linear or interleaved burst
sequence. The interleaved burst order supports Pentium and
i486™ processors. The linear burst sequence is suited for
processors that use a linear burst sequence. The burst order
is user selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
The CY7C1484V33/CY7C1485V33 is a double cycle deselect
part. After the SRAM is deselected at clock rise by the chip
select and either ADSP or ADSC signals, its output will tri-state
immediately after the next clock rise.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The write signals (GW, BWE, and
ignored during this first cycle.
) and ADV inputs are
BWX
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the memory core. If GW is HIGH,
Synchronous Chip Selects CE1, CE2, CE3 and an
asynchronous Output Enable (OE) provide easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
then the write operation is controlled by the BWE and
BWX
signals. The CY7C1484V33/CY7C1485V33 provides byte
write capability that is described in the “Truth Table for
Read/Write” on page 9. Asserting the Byte Write Enable input
(BWE) with the selected Byte Write input will selectively write
to only the desired bytes. Bytes not selected during a byte
write operation remain unaltered. A synchronous self timed
write mechanism has been provided to simplify the write
operations.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
Because the CY7C1484V33/CY7C1485V33 is a common IO
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ inputs. Doing so tri-states the
output drivers. As a safety precaution, DQ are automatically
Document #: 38-05285 Rev. *G
Page 6 of 26
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CY7C1484V33
CY7C1485V33
tri-stated whenever a write cycle is detected, regardless of the
state of OE.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected before entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and
) are asserted active to conduct a write to the desired
BWX
byte(s). ADSC triggered write accesses require a single clock
cycle to complete. The address presented is loaded into the
address register and the address advancement logic while
being delivered to the memory core. The ADV input is ignored
during this cycle. If a global write is conducted, the data
presented to the DQX is written into the corresponding address
location in the memory core. If a byte write is conducted, only
the selected bytes are written. Bytes not selected during a byte
write operation remain unaltered. A synchronous self timed
write mechanism has been provided to simplify the write
operations.
LOW
.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Because the CY7C1484V33/CY7C1485V33 is a common IO
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQX inputs. Doing so tri-states
the output drivers. As a safety precaution, DQX are automati-
cally tri-stated whenever a write cycle is detected, regardless
of the state of OE.
Linear Burst Address Table
(MODE = GND)
Burst Sequences
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
The CY7C1484V33/CY7C1485V33 provides
a
two-bit
Address
A1: A0
wraparound counter, fed by A[1:0], that implements either an
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input. Both
read and write burst operations are supported.
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
ZZ > VDD – 0.2V
Min
Max
Unit
mA
ns
120
tZZS
ZZ > VDD – 0.2V
2tCYC
tZZREC
tZZI
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
ZZ Active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
0
ns
Document #: 38-05285 Rev. *G
Page 7 of 26
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CY7C1484V33
CY7C1485V33
Truth Table
The following is the Truth Table for the CY7C1484V33/CY7C1485V33.[3, 4, 5, 6, 7]
Operation
Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Sleep Mode, Power Down
Read Cycle, Begin Burst
None
None
H
L
X
L
X
X
H
X
H
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
None
L
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
L
X
X
X
L
X
Tri-State
Q
External
External
External
External
External
Next
L-H
Read Cycle, Begin Burst
L
L
L
H
X
L
L-H Tri-State
Write Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
Read Cycle, Begin Burst
L
L
L
H
H
H
H
H
H
L
Read Cycle, Begin Burst
L
L
L
H
L
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H Tri-State
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H Tri-State
L-H
L-H Tri-State
Q
H
X
X
L-H
L-H
D
D
L
Notes
3. X = Do Not Care, H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes can occur only on subsequent clocks after
X
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to enable the outputs to tri-state. OE is a do not
care for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as outputs when OE is active (LOW).
Document #: 38-05285 Rev. *G
Page 8 of 26
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CY7C1484V33
CY7C1485V33
Truth Table for Read/Write
The following is the Truth Table for Read/Write for the CY7C1484V33/CY7C1485V33/.[5, 8]
Function (CY7C1484V33)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
H
H
H
H
H
H
H
H
L
X
H
H
H
H
L
X
H
H
L
X
H
L
Read
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
H
L
L
Write Byte C – (DQC and DQPC)
Write Bytes C, A
H
H
L
H
L
L
Write Bytes C, B
L
H
L
Write Bytes C, B, A
Write Byte D – (DQD and DQPD)
Write Bytes D, A
L
L
H
H
H
H
L
H
H
L
H
L
L
Write Bytes D, B
L
H
L
Write Bytes D, B, A
Write Bytes D, C
L
L
L
H
H
L
H
L
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
L
L
L
L
H
L
L
L
L
Write All Bytes
X
X
X
X
Function (CY7C1485V33)
Read
GW
H
BWE
BWB
X
BWA
X
H
L
L
L
L
X
Read
H
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write All Bytes
H
H
L
H
L
H
H
L
L
Write All Bytes
L
X
X
Note
8. Table lists only a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document #: 38-05285 Rev. *G
Page 9 of 26
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CY7C1484V33
CY7C1485V33
Test Mode Select (TMS)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TMS input gives commands to the TAP controller and is
sampled on the rising edge of TCK. You can leave this ball
unconnected if the TAP is not used. The ball is pulled up inter-
nally, resulting in a logic HIGH level.
The CY7C1484V33/CY7C1485V33 incorporates a serial
boundary scan test access port (TAP). This port operates in
accordance with IEEE Standard 1149.1-1990 but does not
have the set of functions required for full 1149.1 compliance.
These functions from the IEEE specification are excluded
because their inclusion places an added delay in the critical
speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V IO logic levels.
Test Data-In (TDI)
The TDI ball serially inputs information into the registers and
can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction
that is loaded into the TAP instruction register. For information
about loading the instruction register, see the TAP Controller
State Diagram. TDI is internally pulled up and can be uncon-
nected if the TAP is unused in an application. TDI is connected
to the most significant bit (MSB) of any register. (See TAP
Controller Block Diagram.)
The CY7C1484V33/CY7C1485V33 contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (VSS) to
prevent device clocking. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be
connected to VDD through a pull up resistor. TDO should be
left unconnected. At power up, the device comes up in a reset
state, which does not interfere with the operation of the device.
The TDO output ball serially clocks data-out from the registers.
Whether the output is active depends upon the current state
of the TAP state machine. The output changes on the falling
edge of TCK. TDO is connected to the least significant bit
(LSB) of any register. (See TAP Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
0
TEST-LOGIC
1
RESET
0
Bypass Register
2
1
0
0
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
Selection
Circuitry
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
0
0
TDI
TDO
1
1
.
.
. 2 1
CAPTURE-DR
CAPTURE-IR
0
0
x
.
.
.
.
. 2 1
SHIFT-DR
0
SHIFT-IR
0
Boundary Scan Register
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
1
0
TCK
TAP CONTROLLER
TM S
1
0
0
EXIT2-DR
1
EXIT2-IR
1
Performing a TAP Reset
UPDATE-DR
UPDATE-IR
Perform a RESET by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating.
1
0
1
0
At power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Registers
Test Access Port (TAP)
Registers are connected between the TDI and TDO balls and
enable data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Document #: 38-05285 Rev. *G
Page 10 of 26
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CY7C1484V33
CY7C1485V33
Instruction Register
SAMPLE/PRELOAD; rather, it performs a capture of the IO
ring when these instructions are executed.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls, as shown in the “TAP Controller Block
Diagram” on page 10. At power up, the instruction register is
loaded with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset state,
as described in the previous section.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction after it is shifted in, the TAP
controller must be moved into the Update-IR state.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary ‘01’ pattern to
enable fault isolation of the board-level serial test data path.
EXTEST
EXTEST is a mandatory 1149.1 instruction, which is to be
executed whenever the instruction register is loaded with all
zeros. EXTEST is not implemented in this SRAM TAP
controller, and therefore this device is not compliant to 1149.1.
The TAP controller does recognize an all-zero instruction.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The x36 configuration has a
73-bit-long register and the x18 configuration has a 54-bit-long
register.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and
enables the IDCODE to be shifted out of the device when the
TAP controller enters the Shift-DR state.
The boundary scan register is loaded with the contents of the
RAM IO ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller moves to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD, and SAMPLE Z instructions can be used
to capture the contents of the IO ring.
The IDCODE instruction is loaded into the instruction register
at power up or whenever the TAP controller is in a test logic
reset state.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in “Identification Register Defini-
tions[12]” on page 13.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
TAP Instruction Set
Overview
Be aware that the TAP controller clock can only operate at a
frequency up to 10 MHz, while the SRAM clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output may undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that may be captured.
Repeatable results may not be possible.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in “Identification
Codes” on page 14. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus
hold time (tCS plus tCH).
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the IO
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
Document #: 38-05285 Rev. *G
Page 11 of 26
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CY7C1484V33
CY7C1485V33
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
After the data is captured, you can shift out the data by putting
the TAP into the Shift-DR state. This places the boundary scan
register between the TDI and TDO balls.
Reserved
Note that because the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TM SS
TDIS
TM SH
Test M ode Select
(TM S)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter
Clock
tTCYC
tTF
Description
Min
Max
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
tTH
20
20
tTL
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
10
ns
ns
tTDOX
0
Setup Times
tTMSS
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
ns
ns
tTDIS
tCS
Hold Times
tTMSH
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tTDIH
tCH
Capture Hold after Clock Rise
Notes
9.
t
and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS CH
10. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document #: 38-05285 Rev. *G
Page 12 of 26
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CY7C1484V33
CY7C1485V33
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ................................................ VSS to 3.3V
Input rise and fall times................................................... 1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels......................................... 1.25V
Output reference levels ................................................ 1.25V
Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.25V
1.5V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
20pF
ZO= 50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)[11]
Parameter
VOH1
Description
Test Conditions
Min
2.4
2.0
2.9
2.1
Max
Unit
V
Output HIGH Voltage IOH = –4.0 mA, VDDQ = 3.3V
IOH = –1.0 mA, VDDQ = 2.5V
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage IOH = –100 µA
VDDQ = 3.3V
VDDQ = 2.5V
V
V
Output LOW Voltage IOL = 8.0 mA, VDDQ = 3.3V
IOL = 1.0 mA, VDDQ = 2.5V
0.4
0.4
0.2
0.2
V
V
Output LOW Voltage IOL = 100 µA
VDDQ = 3.3V
VDDQ = 2.5V
V
V
Input HIGH Voltage
Input LOW Voltage
Input Load Current
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
GND < VIN < VDDQ
2.0
1.7
VDD + 0.3
V
VDD + 0.3
V
VIL
–0.5
–0.3
–5
0.7
0.7
5
V
V
IX
µA
Identification Register Definitions[12]
CY7C1484V33
CY7C1485V33
Instruction Field
Description
(2M x 36)
(4M x 18)
Revision Number (31:29)
000
000
Describes the version number
Reserved for internal use
Device Depth (28:24)
01011
01011
Architecture/Memory Type(23:18)
Bus Width/Density (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
000110
100100
00000110100
1
000110
010100
00000110100
1
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
Notes
11. All voltages referenced to VSS (GND).
12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: 38-05285 Rev. *G
Page 13 of 26
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CY7C1484V33
CY7C1485V33
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Instruction
3
1
3
1
Bypass
ID
32
73
32
54
Boundary Scan Order – 165BGA
Identification Codes
Instruction
EXTEST
Code
Description
000 Captures IO ring contents.
IDCODE
001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operations.
SAMPLE Z
010 Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRE
LOAD
100 Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101 Do Not Use: This instruction is reserved for future use.
110 Do Not Use: This instruction is reserved for future use.
111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
Boundary Scan Exit Order (2M x 36)
Bit #
1
165-Ball ID
C1
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
165-Ball ID
R3
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
165-Ball ID
L10
K11
J11
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
165-Ball ID
B8
A7
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
2
D1
P2
3
E1
R4
4
D2
P6
K10
J10
5
E2
R6
6
F1
N6
H11
G11
F11
7
G1
F2
P11
R8
8
9
G2
J1
P3
E11
D10
D11
C11
G10
F10
E10
A10
B10
A9
10
11
12
13
14
15
16
17
18
19
20
P4
K1
P8
L1
P9
J2
P10
R9
M1
N1
R10
R11
N11
M11
L11
M10
K2
L2
M2
R1
B9
R2
A8
Document #: 38-05285 Rev. *G
Page 14 of 26
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CY7C1484V33
CY7C1485V33
Boundary Scan Exit Order (4M x 18)
Bit #
1
165-Ball ID
D2
Bit #
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
165-Ball ID
R8
Bit #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
165-Ball ID
C11
A11
A10
B10
A9
2
E2
P3
3
F2
P4
4
G2
P8
5
J1
P9
6
K1
P10
R9
B9
7
L1
A8
8
M1
N1
R10
R11
M10
L10
K10
J10
H11
G11
F11
E11
D11
B8
9
A7
10
11
12
13
14
15
16
17
18
R1
B7
R2
B6
R3
A6
P2
B5
R4
A4
P6
B3
R6
A3
N6
A2
P11
B2
Document #: 38-05285 Rev. *G
Page 15 of 26
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CY7C1484V33
CY7C1485V33
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch Up Current .................................................... >200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND ......–0.5V to +VDD
Ambient
Range
VDD
VDDQ
Temperature
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5%
to VDD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Industrial
–40°C to +85°C
Electrical Characteristics Over the Operating Range[13, 14]
Parameter
VDD
Description
Power Supply Voltage
IO Supply Voltage
Test Conditions
Min
3.135
3.135
2.375
2.4
Max
3.6
Unit
V
VDDQ
For 3.3V IO
For 2.5V IO
VDD
2.625
V
V
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
For 3.3V IO, IOH = –4.0 mA
For 2.5V IO, IOH = –1.0 mA
For 3.3V IO, IOL = 8.0 mA
For 2.5V IO, IOL = 1.0 mA
V
2.0
V
0.4
0.4
V
V
Input HIGH Voltage[13] For 3.3V IO
2.0
1.7
VDD + 0.3V
VDD + 0.3V
0.8
V
For 2.5V IO
V
Input LOW Voltage[13]
For 3.3V IO
For 2.5V IO
–0.3
–0.3
–5
V
0.7
V
Input Leakage Current GND ≤ VI ≤ VDDQ
Except ZZ and MODE
5
µA
Input Current of MODE Input = VSS
Input = VDD
–30
–5
µA
µA
5
Input Current of ZZ
Input = VSS
Input = VDD
µA
30
5
µA
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
–5
µA
VDD Operating Supply VDD = Max., IOUT = 0 mA,
4-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 167 MHz
500
500
450
245
245
245
120
mA
mA
mA
mA
mA
mA
mA
Current
f = fMAX = 1/tCYC
ISB1
Automatic CE
Power Down
Current—TTL Inputs
VDD = Max, Device Deselected, 4-ns cycle, 250 MHz
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
5-ns cycle, 200 MHz
6-ns cycle, 167 MHz
ISB2
Automatic CE
Power Down
Current—CMOS Inputs f = 0
VDD = Max, Device Deselected, All speeds
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
ISB3
Automatic CE
Power Down
Current—CMOS Inputs f = fMAX = 1/tCYC
V
DD= Max, Device Deselected, or 4-ns cycle, 250 MHz
245
245
245
135
mA
mA
mA
mA
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
5-ns cycle, 200 MHz
6-ns cycle, 167 MHz
ISB4
Automatic CE
Power Down
Current—TTL Inputs
VDD = Max, Device Deselected, All Speeds
VIN ≥ VIH or VIN ≤ VIL, f = 0
Notes
13. Overshoot: V (AC) < V +1.5V (pulse width less than t
/2). Undershoot: V (AC) > –2V (pulse width less than t
/2).
CYC
IH
DD
CYC
IL
14. Power up: assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
DD
IH
DD
DDQ
DD
Document #: 38-05285 Rev. *G
Page 16 of 26
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CY7C1484V33
CY7C1485V33
Capacitance[15]
100 TQFP
Package
165 FBGA
Unit
Parameter
Description
Test Conditions
Package
CADDRESS
CDATA
CCTRL
CCLK
Address Input Capacitance
Data Input Capacitance
Control Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
TA = 25°C, f = 1 MHz,
6
5
8
6
5
6
5
8
6
5
pF
pF
pF
pF
pF
V
DD = 3.3V.
VDDQ = 2.5V
CI/O
Thermal Resistance[15]
100 TQFP
Package
165 FBGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51.
24.63
16.3
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
2.28
2.1
°C/W
AC Test Loads and Waveforms
3.3V IO Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
GND
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V IO Test Load
R = 1667Ω
2.5V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
5 pF
R = 1538Ω
≤ 1 ns
≤ 1 ns
V = 1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note
15. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05285 Rev. *G
Page 17 of 26
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CY7C1484V33
CY7C1485V33
Switching Characteristics Over the Operating Range[16, 17]
250 MHz
200 MHz
167 MHz
Unit
Description
Parameter
tPOWER
Clock
tCYC
Min
Max
Min
Max
Min
Max
VDD(Typical) to the First Access[18]
1
1
1
ms
Clock Cycle Time
Clock HIGH
4
5
6
ns
ns
ns
tCH
2.0
2.0
2.0
2.0
2.2
2.2
tCL
Clock LOW
Output Times
tCO
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[19, 20, 21]
3.0
3.0
3.4
ns
ns
ns
ns
ns
ns
ns
tDOH
1.3
1.3
1.3
1.3
1.5
1.5
tCLZ
tCHZ
Clock to High-Z[19, 20, 21]
3.0
3.0
3.0
3.0
3.4
3.4
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
Setup Times
tAS
OE LOW to Output Low-Z[19, 20, 21]
OE HIGH to Output High-Z[19, 20, 21]
0
0
0
3.0
3.0
3.4
Address Setup Before CLK Rise
ADSC, ADSP Setup Before CLK Rise
ADV Setup Before CLK Rise
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BWX Setup Before CLK Rise
Data Input Setup Before CLK Rise
Chip Enable Setup Before CLK Rise
tDS
tCES
Hold Times
tAH
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tADH
tADVH
tWEH
GW, BWE, BWX Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tDH
tCEH
Notes
16. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
17. Test conditions shown in (a) of “AC Test Loads and Waveforms” on page 17 unless otherwise noted.
18. This part has a voltage regulator internally; t
is the time that the power must be supplied above V (minimum) initially before a read or write operation can
POWER
DD
be initiated.
19. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms on page 17. Transition is measured ±200
OEHZ
CHZ CLZ OELZ
mV from steady-state voltage.
20. At the supplied voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z before Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
Document #: 38-05285 Rev. *G
Page 18 of 26
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CY7C1484V33
CY7C1485V33
Switching Waveforms
Read Cycle Timing[22]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,BW
X
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
OEV
CO
t
t
CHZ
t
t
t
OELZ
OEHZ
DOH
CLZ
t
Q(A2)
Q(A2
+
1)
Q(A2
+
2)
Q(A2
+
3)
Q(A2)
Q(A2
+
1)
Q(A3)
Q(A1)
Data Out (DQ)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
22. On this diagram, when CE is LOW: CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH: CE is HIGH, CE is LOW, or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05285 Rev. *G
Page 19 of 26
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CY7C1484V33
CY7C1485V33
Switching Waveforms (continued)
Write Cycle Timing[22, 23]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
BWE,
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BW
X
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
D(A2)
D(A2
+
1)
D(A2
+
1)
D(A2
+
2)
D(A2
+
3)
D(A3)
D(A3
+
1)
D(A3
+
2)
D(A1)
High-Z
Data in (D)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Single WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Note
23.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BW LOW.
X
Document #: 38-05285 Rev. *G
Page 20 of 26
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CY7C1484V33
CY7C1485V33
Switching Waveforms (continued)
Read/Write Cycle Timing[22, 24, 25]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Back-to-Back READs
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
High-Z
BURST READ
Back-to-Back
WRITEs
Single WRITE
DON’T CARE
UNDEFINED
Notes
24. The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
25. GW is HIGH.
Document #: 38-05285 Rev. *G
Page 21 of 26
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CY7C1484V33
CY7C1485V33
Switching Waveforms (continued)
ZZ Mode Timing[26, 27]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
26. Device must be deselected when entering ZZ mode. See “Truth Table” on page 8 for all possible signal conditions to deselect the device.
27. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05285 Rev. *G
Page 22 of 26
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CY7C1484V33
CY7C1485V33
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
167 CY7C1484V33-167AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
CY7C1485V33-167AXC
Commercial
CY7C1484V33-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1485V33-167BZC
CY7C1484V33-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1485V33-167BZXC
CY7C1484V33-167AXI
CY7C1485V33-167AXI
CY7C1484V33-167BZI
CY7C1485V33-167BZI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
lndustrial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1484V33-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1485V33-167BZXI
200 CY7C1484V33-200AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
CY7C1485V33-200AXC
Commercial
CY7C1484V33-200BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1485V33-200BZC
CY7C1484V33-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1485V33-200BZXC
CY7C1484V33-200AXI
CY7C1485V33-200AXI
CY7C1484V33-200BZI
CY7C1485V33-200BZI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
lndustrial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1484V33-200BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1485V33-200BZXI
250 CY7C1484V33-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
CY7C1485V33-250AXC
Commercial
CY7C1484V33-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1485V33-250BZC
CY7C1484V33-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1485V33-250BZXC
CY7C1484V33-250AXI
CY7C1485V33-250AXI
CY7C1484V33-250BZI
CY7C1485V33-250BZI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Industrial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1484V33-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1485V33-250BZXI
Document #: 38-05285 Rev. *G
Page 23 of 26
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CY7C1484V33
CY7C1485V33
Package Diagrams
Figure 1. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
1.00 REF.
51-85050-*B
DETAIL
A
Document #: 38-05285 Rev. *G
Page 24 of 26
[+] Feedback
CY7C1484V33
CY7C1485V33
Package Diagrams (continued)
Figure 2. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
1
Ø0.25 M C A B
Ø0.45 0.05(165X)
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
1.00
5.00
10.00
B
15.00 0.10
0.15(4X)
SEATING PLANE
C
51-85165-*A
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05285 Rev. *G
Page 25 of 26
© Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1484V33
CY7C1485V33
Document History Page
Document Title: CY7C1484V33/CY7C1485V33 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
Document Number: 38-05285
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
114672 08/21/02
118285 01/20/03
PKS
HGK
New Data Sheet
*A
Changed tCO from 2.4 to 2.6 ns for 250 MHz
Updated Features on package offering
Updated Ordering information
Changed Advanced Information to Preliminary
*B
233368 See ECN
NJY
Changed timing diagrams
Changed logic block diagrams
Modified Functional Description
Modified “Functional Overview” section
Added boundary scan order for all packages
Included thermal numbers and capacitance values for all packages
Included IDD and ISB values
Removed 250-MHz offering and included 225-MHz speed bin
Changed package outline for 165FBGA package
Removed 119-BGA package offering
*C
*D
299452 See ECN
SYT
PCI
Removed 225-MHz offering and included 250-MHz speed bin
Changed tCYC from 4.4 ns to 4.0 ns for 250-Mhz Speed Bin
Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for 100
TQFP Package on Page # 16
Added lead-free information for 100-Pin TQFP and 165 FBGA Packages
Added comment of ‘Lead-free BG packages availability’ below the Ordering
Information
323080 See ECN
Unshaded 200 and 167 MHz speed bin in the AC/DC Table and Selection
Guide
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Added Address Expansion pins in the Pin Definitions Table
Added Industrial Operating Range
Modified VOL, VOH test conditions
Removed comment of ‘Lead-free BG packages availability’ below the
Ordering Information
Updated Ordering Information Table
*E
416193 See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed the description of IX from Input Load Current to Input Leakage
Current on page# 16
Changed the IX current values of MODE on page # 16 from -5 µA and 30 µA
to -30 µA and 5 µA
Changed the IX current values of ZZ on page # 16 from -30 µA and 5 µA
to -5 µA and 30 µA
Changed VIH < VDD to VIH < VDD on page # 16
Replaced Package Name column with Package Diagram in the Ordering
Information table
*F
470723 See ECN
NXR
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Changed tTH,tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC
Switching Characteristics table.
Updated the Ordering Information table.
*G
1062042 See ECN VKN/KKVTMP Added footnote #2 related to VSSQ
Document #: 38-05285 Rev. *G
Page 26 of 26
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