CY7C1487V33-150BGC_技术文档

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Logic Block Diagrams

CY7C1481V33 – 2M x 36

MODE

2

(A

)

[1;0]

Q

CLK

ADV

ADSC

0

BURST

COUNTER

CE

CLR

1

ADSP

Q

19

21

ADDRESS

REGISTER

CE

D

2M X36

MEMORY

ARRAY

A

[20:0]

21

19

GW

DQ , DP

BYTEWRITE

REGISTERS

D

Q

d

BWE

BW

d

DQ , DP

BYTEWRITE

REGISTERS

D

Q

c

BW

c

DQ , DP

b

BYTEWRITE

REGISTERS

BW

b

DQ , DP

a

BYTEWRITE

REGISTERS

BW

a

36

CE

2

1

CE

D

Q

ENABLE CE

REGISTER

CE

3

Q

INPUT

REGISTERS

CLK

ENABLE DELAY

REGISTER

OE

ZZ

SLEEP

CONTROL

DQ

DP

a,b,c,d

CY7C1483V33 – 4M X 18

MODE

2

(A

)

[1;0]

Q

CLK

ADV

ADSC

0

BURST

COUNTER

CE

CLR

1

ADSP

Q

20

22

ADDRESS

REGISTER

CE

D

4M X 18

A

[21:0]

22

20

MEMORY

ARRAY

GW

DQ , DP

BYTEWRITE

REGISTERS

D

Q

b

BWE

BW

b

DQ , DP

BYTEWRITE

REGISTERS

D

Q

a

BW

a

18

CE

2

1

CE

D

CE

Q

ENABLE CE

REGISTER

CE

3

D

Q

INPUT

REGISTERS

CLK

ENABLE DELAY

REGISTER

OE

ZZ

SLEEP

CONTROL

DQ

a,b

DP

Document #: 38-05284 Rev. *A

Page 2 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Logic Block Diagrams (continued)

CY7C1487V33 – 1M x72

MODE

2

(A

)

[1;0]

Q

CLK

ADV

ADSC

0

BURST

COUNTER

CE

CLR

1

ADSP

Q

18

20

ADDRESS

REGISTER

CE

D

1M X72

MEMORY

ARRAY

A

[19:0]

20

18

GW

DQ , DP

BYTEWRITE

REGISTERS

D

Q

h

BWE

BW

h

DQ , DP

BYTEWRITE

REGISTERS

D

Q

g

BW

g

DQ , DP

f

BYTEWRITE

REGISTERS

BW

f

DQ , DP

e

BYTEWRITE

REGISTERS

BW

e

DQ , DP

BYTEWRITE

REGISTERS

D

Q

d

BW

d

DQ , DP

c

BYTEWRITE

REGISTERS

c

DQ , DP

b

BYTEWRITE

REGISTERS

BW

b

DQ , DP

a

BYTEWRITE

REGISTERS

BW

a

72

CE

2

1

CE

D

Q

ENABLE CE

REGISTER

CE

3

INPUT

REGISTERS

CLK

ENABLE DELAY

REGISTER

OE

ZZ

SLEEP

CONTROL

DQ

DP

a,b,c,d,e,f,g,h

.

Selection Guide

CY7C1481V33-150 CY7C1481V33-133 CY7C1481V33-117 CY7C1481V33-100

CY7C1483V33-150 CY7C1483V33-133 CY7C1483V33-117 CY7C1483V33-100

CY7C1487V33-150 CY7C1487V33-133 CY7C1487V33-117 CY7C1487V33-100 Unit

Maximum Access Time

5.5

6.5

7.5

8.5

ns

Maximum Operating Current

TBD

mA

Maximum CMOS Standby

Current

Document #: 38-05284 Rev. *A

Page 3 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Pin Configurations

100-pin TQFP

(Top View)

DQPc

1

NC

V_DDQ

V_SSQ

NC

DQPb

DQb

V_DDQ

V_SSQ

DQb

V_SSQ

V_DDQ

DQb

V_SS

A

NC

V_DDQ

V_SSQ

NC

DPa

DQa

V_SSQ

V_DDQ

DQa

V_SS

NC

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQc

2

DQc

V_DDQ

V_SSQ

DQc

3

4

5

6

DQc

7

NC

DQc

8

DQb

V_SSQ

V_DDQ

DQb

NC

V_DD

NC

V_SS

DQb

V_DDQ

V_SSQ

DQb

DPb

NC

DQc

9

10

11

9

V_SSQ

V_DDQ

DQc

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

12

DQc

13

NC

14

CY7C1483V33

(4M x 18)

CY7C1481V33

(2M X 36)

V_DD

15

NC

V_DD

ZZ

NC

16

V_DD

ZZ

V_SS

17

DQd

18

DQa

V_DDQ

V_SSQ

DQa

V_SSQ

V_DDQ

DQa

V_DDQ

V_SSQ

DQa

NC

DQd

19

20

21

V_DDQ

V_SSQ

DQd

22

DQd

23

DQd

24

DQd

25

26

27

NC

V_SSQ

V_DDQ

DQd

29

V_SSQ

V_DDQ

NC

V_SSQ

V_DDQ

NC

28

NC

DQPa NC

DQPd

30

Document #: 38-05284 Rev. *A

Page 4 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Pin Configurations (continued)

CY7C1481V33 (2M x 36)

1

2

3

A

4

5

A

6

A

7

A

V_DDQ

NC

V_DDQ

A

ADSP

ADSC

V_DD

B

C

D

E

F

NC

A

NC

A

DQPc

DQc

A

DQPb

DQb

V_SS

NC

DQb

DQc

CE₁

OE

V_SS

V_DDQ

DQc

V_DDQ

DQb

V_DDQ

DQa

V_SS

BW_b

V_SS

DQb

ADV

GW

V_DD

G

H

J

DQc

V_DD

DQd

BW_c

V_SS

NC

DQc

DQb

V_DD

V_DDQ

DQd

V_DDQ

DQd

NC

K

L

V_SS

DQa

DQPa

A

V_SS

CLK

NC

BW_d

BW_a

V_SS

DQa

V_DDQ

DQa

M

DQd

BWE

A1

V_SS

N

P

R

T

DQPd

DQa

V_SS

MODE

A

A0

V_SS

NC

A

V_DD

A

NC

ZZ

A

NC

U

V_DDQ

TMS

TDI

TCK

TDO

NC

V_DDQ

CY7C1483V33 (4M x 18)

1

2

3

A

4

5

A

6

A

7

A

B

C

D

E

F

V_DDQ

NC

V_DDQ

NC

A

ADSP

ADSC

V_DD

A

NC

A

V_SS

DQb

NC

DQPa

NC

DQb

DQa

CE₁

OE

V_SS

DQa

V_DDQ

NC

V_DDQ

DQa

NC

ADV

GW

V_DD

G

H

J

NC

DQb

NC

BW_b

V_SS

DQa

V_DD

V_DDQ

DQa

V_DDQ

NC

VDD

DQb

NC

K

L

V_SS

NC

DQa

NC

DQa

NC

A

V_SS

CLK

NC

DQb

V_DDQ

DQb

NC

BW_a

V_SS

NC

V_DDQ

NC

M

DQb

NC

V_SS

BWE

A1

N

P

R

T

DQPb

DQa

V_SS

MODE

A

A0

V_SS

NC

A

NC

V_DD

A

NC

ZZ

A

U

V_DDQ

TMS

TDI

TCK

TDO

NC

V_DDQ

Document #: 38-05284 Rev. *A

Page 5 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Pin Configurations (continued)

165-Ball Bump FBGA

(This package is offered on opportunity basis)

CY7C1481V33 (2M x 36) – 11 x 15 FBGA

1

2

3

4

5

6

7

8

9

10

11

NC

A

CE

BW

CE

3

BWE

A

ADSC

ADV

A

NC

1

2

c

b

NC

DPc

DQc

A

CE

BW

V

BW

V

CLK

GW

B

C

D

OE

ADSP

A

144M

DPb

d

a

NC

V

NC

DDQ

SS

DD

SS

DDQ

DQc

V

DQb

SS

DD

DDQ

DQc

NC

V

E

F

V

DQb

NC

DQb

ZZ

DDQ

DD

SS

DD

DDQ

V

SS

DD

DDQ

V

G

H

J

V

SS

DD

DDQ

V

NC

V

NC

SS

DD

DQd

DPd

NC

DQd

NC

V

DQa

NC

DQa

DPa

A

DDQ

SS

DD

DDQ

V

K

L

V

SS

DD

DDQ

V

SS

DD

DDQ

V

M

N

P

V

DDQ

DD

SS

DD

DDQ

V

NC

TDI

A

V

DDQ

SS

DDQ

A

A1

A0

TDO

TCK

A

MODE

A

TMS

R

A

CY7C1483V33 (4M x 18) – 11 x 15 FBGA

1

2

3

4

5

6

7

8

9

10

11

NC

A

CE

BW

NC

CE

3

BWE

A

ADSC

ADV

A

1

2

b

NC

A

CE

NC

BW

CLK

GW

B

C

D

E

F

OE

ADSP

A

144M

DPa

a

NC

V

NC

DDQ

SS

DDQ

DQb

V

DQa

DD

SS

DD

DDQ

NC

DQb

V

NC

DQa

ZZ

DDQ

DD

SS

DD

DDQ

V

DD

SS

DD

DDQ

NC

V

G

H

J

V

NC

DD

SS

DD

DDQ

NC

V

NC

V

NC

SS

DD

SS

DD

DQb

DPb

NC

A

V

DQa

NC

A

DDQ

DD

SS

DD

DDQ

V

K

L

V

DD

SS

DD

DDQ

V

DD

SS

DD

DDQ

V

M

N

P

V

DD

SS

DD

DDQ

V

NC

TDI

A

V

DDQ

SS

DDQ

A

A1

A0

TDO

TCK

A

MODE

A

TMS

R

A

Document #: 38-05284 Rev. *A

Page 6 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Pin Configurations (continued)

209-ball BGA (This package is offered on opportunity basis)

CY7C1487V33 (1M x72)

1

DQg

2

3

4

5

6

7

8

9

10

DQb

11

A

B

C

D

E

F

DQg

CE

ADSC

BW

DQb

3

2

A

ADSP

NC

ADV

A

BWS

DQb

BWS

f

BWS

b

c

g

DQg

DPc

DQc

NC

BWS

NC

BWS

CE

BWS

a

BWS

e

DQb

DPb

DQf

d

1

h

DQg

V

OE

GW

V

NC

V

SS

DQb

SS

DPg

DQc

V

DD

DDQ

SS

DDQ

DD

DPf

DQf

V

NC

V

SS

DD

SS

DD

SS

G

H

J

DQc

V

DDQ

V

DDQ

DQf

DDQ

V

SS

V

DQc

NC

SS

SSQ

DDQ

SS

DQf

NC

DQc

NC

V

DDQ

DD

DDQ

DQf

NC

K

L

CLK

V

NC

V

SS

NC

DQh

V

NC

ZZ

V

DDQ

DD

SS

DD

SS

DDQ

DQa

DDQ

M

N

P

R

T

V

DQh

V

SS

DQa

V

DDQ

DQh

DPd

DQd

V

DD

SS

DDQ

SS

DDQ

DQa

DPa

DQe

V

SS

V

DPh

DQd

V

DDQ

V

DDQ

DD

DDQ

SS

DD

DPe

DQe

NC

V

NC

A

MODE

A

SS

U

V

W

A

A1

A

DQd

A

DQe

TDI

TDO

TCK

A

A0

A

TMS

Pin Definitions

Pin Name

I/O

Pin Description

A0

A1

A

Input-

Synchronous

Address Inputs used to select one of the address locations. Sampled at the rising edge of

the CLK if ADSP or ADSC is active LOW, and CE₁, CE₂, and CE₃are sampled active. A_[1:0]

feed the two-bit counter.

BW_a

BW_b

BW_c

BW_d

BW_e

BW_f

Input-

Synchronous

ByteWrite Select Inputs, activeLOW. QualifiedwithBWE to conduct byte writes to the SRAM.

Sampled on the rising edge of CLK.

BW_g

BW_h

GW

Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a

global write is conducted (ALL bytes are written, regardless of the values on BW_{a,b,c,d,e,f,g,h}and

BWE).

BWE

Input-

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must

Synchronous

be asserted LOW to conduct a byte write.

Document #: 38-05284 Rev. *A

Page 7 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Pin Definitions (continued)

Pin Name

I/O

Pin Description

CLK

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the

burst counter when ADV is asserted LOW, during a burst operation.

CE₁

CE₂

CE₃

OE

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE₂and CE₃to select/deselect the device. ADSP is ignored if CE₁is HIGH.

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction

with CE₁and CE₃to select/deselect the device.(TQFP Only)

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE₁and CE₂to select/deselect the device.(TQFP Only)

Input-

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.

Asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated,

and act as input data pins. OE is masked during the first clock of a read cycle when emerging

from a deselected state.

ADV

Input-

Synchronous

Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically

increments the address in a burst cycle.

ADSP

Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW,

A is captured in the address registers. A_[1:0]are also loaded into the burst counter. When ADSP

and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE₁is

deasserted HIGH.

ADSC

MODE

ZZ

Input-

Synchronous

Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW,

A_[x:0]is captured in the address registers. A_[1:0]are also loaded into the burst counter. When

ADSP and ADSC are both asserted, only ADSP is recognized.

Input-

Static

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V_DDQor

left floating selects interleaved burst sequence. This is a strap pin and should remain static

during device operation.

Input-

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”

Asynchronous condition with data integrity preserved.

DQa, DPa

DQb, DPb

DQc, DPc

DQd, DPd

DQe, DPe

DQf, DPf

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by A during the previous clock rise of the read cycle. The direction of the pins is

controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx

and DPx are placed in a three-state condition. DQ a,b,c,d,e,f,g and h are 8 bits wide. DP

a,b,c,d,e,f,g and h are 1 bit wide.

DQg, DPg

DQh, DPh

TDO

JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA Only)

Synchronous

TDI

JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.(BGA Only)

Synchronous

TMS

Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.

Synchronous

(BGA Only)

TCK

V_DD

JTAG serial clock Serial clock to the JTAG circuit. (BGA Only)

Power Supply

Ground

Power supply inputs to the core of the device. Should be connected to 3.3V –5% +5% power

supply.

V_SS

Ground for the core of the device. Should be connected to ground of the system.

V_DDQ

V_SSQ

144M

NC

I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 2.375V(min.) to V_DD(max.)

I/O Ground

Ground for the I/O circuitry. Should be connected to ground of the system.

NC. This pin is reserved for expansion to 144Mb.

No connects.

–

Document #: 38-05284 Rev. *A

Page 8 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

precaution, DQx are automatically three-stated whenever a

write cycle is detected, regardless of the state of OE.

Functional Description

Single Read Accesses

Single Write Accesses Initiated by ADSC

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

chip enable (CE₁, CE₂, CE₃on TQFP, CE₁on BGA) asserted

active, and (3) the write signals (GW, BWE) are all deasserted

HIGH. ADSP is ignored if CE₁is HIGH. The address presented

to the address inputs is stored into the address advancement

logic and the Address Register while being presented to the

memory core. If the OE input is asserted LOW, the requested

data will be available at the data outputs a maximum to t_CDV

after clock rise. ADSP is ignored if CE₁is HIGH.

ADSC write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deasserted HIGH, (3) Chip Enable (CE₁, CE₂, CE₃on TQFP,

CE₁on BGA) asserted active, and (4) the appropriate combi-

nation of the write inputs (GW, BWE, and BW_x) are asserted

active to conduct a write to the desired byte(s). ADSC is

ignored if ADSP is active LOW.

The address presented to A_[17:0]is loaded into the address

register and the address advancement logic while being

delivered to the RAM core. The ADV input is ignored during

this cycle. If a global write is conducted, the data presented to

the DQx is written into the corresponding address location in

the RAM core. If a byte write is conducted, only the selected

bytes are written. Bytes not selected during a byte write

operation will remain unaltered. All I/Os are three-stated

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)

Chip Enable asserted active. The address presented is loaded

into the address register and the address advancement logic

while being delivered to the RAM core. The write signals (GW,

BWE, and BWx) and ADV inputs are ignored during this first

clock cycle. If the write inputs are asserted active (see Write

Cycle Descriptions table for appropriate states that indicate a

write) on the next clock rise, the appropriate data will be

during

a

byte write because the CY7C1481V33/

CY7C1483V33/CY7C1487V33 is a common I/O device, the

Output Enable (OE) must be deasserted HIGH before

presenting data to the DQx inputs. Doing so will three-state the

output drivers. As a safety precaution, DQx are automatically

three-stated whenever a write cycle is detected, regardless of

the state of OE.

latched

and

written

into

the

device.

The

CY7C1481V33/CY7C1483V33/CY7C1487V33 provides byte

write capability that is described in the Write Cycle Description

table. Asserting the Byte Write Enable input (BWE) with the

selected Byte Write (BW_{a,b,c,d,e,f,g,h}for CY7C1487V33,

BW_a,b,c,dfor CY7C1481V33 and BW_a,bfor CY7C1483V33)

input will selectively write to only the desired bytes. Bytes not

selected during a byte write operation will remain unaltered.

All I/Os are three-stated during a byte write.

Burst Sequences

The CY7C1481V33/CY7C1483V33/CY7C1487V33 provides

a two-bit wraparound counter, fed by A_[1:0], that implements

either an interleaved or linear burst sequence. to support

processors that follow a linear burst sequence. The burst

sequence is user selectable through the MODE input.

Because the CY7C1481V33/CY7C1483V33/CY7C1487V33

is a common I/O device, the Output Enable (OE) must be

deasserted HIGH before presenting data to the DQx inputs.

Doing so will three-state the output drivers. As a safety

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both read and write burst operations are supported.

[1, 2, 3, 4]

Cycle Descriptions

Next Cycle

Unselected

Begin Read

Add. Used

None

ZZ

0

CE₃

X

1

CE₂

X

0

CE₁

1

ADSP

ADSC

ADV

X

OE

X

1

DQ

Hi-Z

DQ

Write

X

0

1

0

1

X

1

0

X

0

X

0

1

None

0

X

None

X

1

0

X

None

X

0

X

None

X

0

X

External

1

0

X

0

1

0

X

Read

Continue Read Next

Suspend Read Current

X

1

0

1

Hi-Z

DQ

1

0

X

1

Hi-Z

Notes:

1. X = “Don't Care.” 1 = HIGH, 0 = LOW.

2. Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table.

3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

4. CE₁, CE₂, and CE₃are available only in the TQFP package. BGA package has a single chip select CE₁.

Document #: 38-05284 Rev. *A

Page 9 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Cycle Descriptions (continued)^{[1, 2, 3, 4]}

Next Cycle

Add. Used

ZZ

0

CE₃

X

CE₂

X

CE₁

X

1

ADSP

ADSC

ADV

1

OE

0

DQ

Write

Read

Write

X

Suspend Read Current

1

X

1

0

1

X

0

X

1

Hi-Z

DQ

0

X

1

0

Begin Write

Current

External

0

X

1

X

Hi-Z

0

X

1

0

1

0

X

0

Continue Write Next

Suspend Write Current

0

X

1

0

X

1

0

X

1

0

X

1

ZZ “sleep”

None

1

X

Sleep Mode

Interleaved Burst Sequence

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CEs, ADSP, and ADSC must remain

inactive for the duration of t_ZZRECafter the ZZ input returns

LOW.

First

Second

Third

Fourth

Address

A[1:0]

00

A[1:0]

01

A[1:0]

10

A[1:0]

11

01

00

11

10

11

00

01

11

10

01

00

Linear Burst Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

A[1:0]

00

A[1:0]

01

A[1:0]

10

A[1:0]

11

01

10

11

00

10

11

00

01

11

00

01

10

ZZ Mode Electrical Characteristics

Parameter

I_DDZZ

Description

Test Conditions

Min.

Max.

Unit

Snooze mode

standby current

ZZ > V_DD– 0.2V

TBD

mA

t_ZZS

Device operation to ZZ > V_DD– 0.2V

2t_CYC

ns

ZZ

t_ZZREC

ZZ recovery time

ZZ < 0.2V

2t_CYC

Document #: 38-05284 Rev. *A

Page 10 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Write Cycle Descriptions^{[1, 2]}

Function (CY7C1481V33)

Read

GW

1

BWE

1

BW_d

X

1

BW_c

X

1

BW_b

X

1

BW_a

X

1

Read

1

0

Write Byte 0 – DQa

Write Byte 1 – DQb

Write Bytes 1, 0

Write Byte 2 – DQc

Write Bytes 2, 0

Write Bytes 2, 1

Write Bytes 2, 1, 0

Write Byte 3 – DQd

Write Bytes 3, 0

Write Bytes 3, 1

Write Bytes 3, 1, 0

Write Bytes 3, 2

Write Bytes 3, 2, 0

Write Bytes 3, 2, 1

Write All Bytes

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Write All Bytes

0

X

Function (CY7C1483V33)

Read

GW

1

BWE

BW_b

BW_a

1

0

X

1

0

X

1

0

1

0

X

Read

1

Write Byte 0 – DQ_[7:0]and DP₀

Write Byte 1 – DQ_[15:8]and DP₁

Write All Bytes

1

Write All Bytes

0

Function (CY7C1487V33)^[5]

GW

1

BWE

BW_x

Read

1

0

X

Read

1

All BW = 1

Write Byte X

Write All Bytes

1

0

All BW = 0

X

1

Write All Bytes

0

Note:

5. BWx represents any byte write signal BW[0..7]. To enable any byte write BWx, a low logic signal should be applied at clock rise. Any number of byte writes

can be enabled at the same time for any given write.

Document #: 38-05284 Rev. *A

Page 11 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

TAP Registers

IEEE 1149.1 Serial Boundary Scan (JTAG)

Registers are connected between the TDI and TDO pins and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time through

the instruction registers. Data is serially loaded into the TDI pin

on the rising edge of TCK. Data is output on the TDO pin on

the falling edge of TCK.

The CY7C1483V33/CY7C1481V33/CY7C1487V33 incorpo-

rates a serial boundary scan Test Access Port (TAP) in the

BGA package only. The TQFP package does not offer this

functionality. This port operates in accordance with IEEE

Standard 1149.1-1900, but does not have the set of functions

required for full 1149.1 compliance. These functions from the

IEEE specification are excluded because their inclusion

places an added delay in the critical speed path of the SRAM.

Note that the TAP controller functions in a manner that does

not conflict with the operation of other devices using 1149.1

fully compliant TAPs. The TAP operates using JEDEC

standard 3.3V I/O logic levels.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

register. This register is loaded when it is placed between the

TDI and TDO pins as shown in the TAP Controller Block

Diagram. Upon power-up, the instruction register is loaded

with the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(V_SS) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to V_DDthrough a pull-up resistor. TDO should

be left unconnected. Upon power-up, the device will come up

in a reset state which will not interfere with the operation of the

device.

When the TAP controller is in the CaptureIR state, the two least

significant bits are loaded with a binary “01” pattern to allow for

fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain states. The bypass

register is a single-bit register that can be placed between TDI

and TDO pins. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

(V_SS) when the BYPASS instruction is executed.

Test Access Port (TAP) – Test Clock

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

Boundary Scan Register

Test Mode Select

The boundary scan register is connected to all the input and

output pins on the SRAM. Several no connect (NC) pins are

also included in the scan register to reserve pins for higher

density devices. The x36 configuration has a 70-bit-long

register, and the x18 configuration has a 51-bit-long register.

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this pin unconnected if the TAP is not used. The pin is

pulled up internally, resulting in a logic HIGH level.

The boundary scan register is loaded with the contents of the

RAM Input and Output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and

TDO pins when the controller is moved to the Shift-DR state.

The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-

tions can be used to capture the contents of the Input and

Output ring.

Test Data-In (TDI)

The TDI pin is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. For

information on loading the instruction register, see the TAP

Controller State Diagram. TDI is internally pulled up and can

be unconnected if the TAP is unused in an application. TDI is

connected to the Most Significant Bit (MSB) on any register.

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI, and the LSB is connected to TDO.

Test Data Out (TDO)

The TDO output pin is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine (see TAP Controller State

Diagram). The output changes on the falling edge of TCK.

TDO is connected to the Least Significant Bit (LSB) of any

register.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (V_DD) for five rising

edges of TCK. This RESET does not affect the operation of

the SRAM and may be performed while the SRAM is

operating. At power-up, the TAP is reset internally to ensure

that TDO comes up in a High-Z state.

TAP Instruction Set

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in the

Instruction Code table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

Document #: 38-05284 Rev. *A

Page 12 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

The TAP controller used in this SRAM is not fully compliant to

the 1149.1 convention because some of the mandatory 1149.1

instructions are not fully implemented. The TAP controller

cannot be used to load address, data, or control signals into

the SRAM and cannot preload the Input or Output buffers. The

SRAM does not implement the 1149.1 commands EXTEST or

INTEST or the PRELOAD portion of SAMPLE/PRELOAD;

rather it performs a capture of the Inputs and Output ring when

these instructions are executed.

When the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 10 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is

possible that during the Capture-DR state, an input or output

will undergo a transition. The TAP may then try to capture a

signal while in transition (metastable state). This will not harm

the device, but there is no guarantee as to the value that will

be captured. Repeatable results may not be possible.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO pins.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller’s capture set-up plus

hold times (t_CSand t_CH). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE/PRELOAD instruction. If this

is an issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK captured in the

boundary scan register.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be

executed whenever the instruction register is loaded with all

0s. EXTEST is not implemented in the TAP controller, and

therefore this device is not compliant to the 1149.1 standard.

The TAP controller does recognize an all-0 instruction. When

an EXTEST instruction is loaded into the instruction register,

the SRAM responds as if a SAMPLE/PRELOAD instruction

has been loaded. There is one difference between the two

instructions. Unlike the SAMPLE/PRELOAD instruction,

EXTEST places the SRAM outputs in a High-Z state.

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the

boundary scan register between the TDI and TDO pins.

Note that since the PRELOAD part of the command is not

implemented, putting the TAP into the Update to the

Update-DR state while performing a SAMPLE/PRELOAD

instruction will have the same effect as the Pause-DR

command.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO pins and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state. The IDCODE instruction

is loaded into the instruction register upon power-up or

whenever the TAP controller is given a test logic reset state.

Bypass

When the BYPASS instruction is loaded in the instruction

register and the TAP is placed in a Shift-DR state, the bypass

register is placed between the TDI and TDO pins. The

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO pins when the TAP

controller is in a Shift-DR state. It also places all SRAM outputs

into a High-Z state.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The

PRELOAD portion of this instruction is not implemented, so

the TAP controller is not fully 1149.1 compliant.

Document #: 38-05284 Rev. *A

Page 13 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

TAP Controller State Diagram

TEST-LOGIC

RESET

1^[6]

1

TEST-LOGIC/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

0

1

CAPTURE-DR

0

SHIFT-DR

0

SHIFT-IR

0

1

EXIT1-DR

0

1

EXIT1-IR

0

1

0

PAUSE-DR

1

PAUSE-IR

1

0

EXIT2-DR

1

EXIT2-IR

1

UPDATE-DR

UPDATE-IR

1

0

Note:

6. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document #: 38-05284 Rev. *A

Page 14 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

TAP Controller Block Diagram

0

Bypass Register

Selection

Circuitry

Selection

Circuitry

2

1

0

TDO

TDI

Instruction Register

29

Identification Register

31 30

.

2

1

0

.

2

Boundary Scan Register

TCK

TMS

TAP Controller

TAP Electrical Characteristics Over the Operating Range^{[7, 8]}

Parameter

V_OH1

Description

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Input Load Current

Test Conditions

I_OH= −4.0 mA

Min.

2.4

Max.

Unit

V

V_OH2

V_OL1

V_OL2

V_IH

I_OH= −100 µA

I_OL= 8.0 mA

I_OL= 100 µA

3.0

0.4

0.2

V

1.8

−0.5

−5

V

_DD+ 0.3

V

V_IL

0.8

V

I_X

GND ≤ V_I≤ V_DDQ

5

µA

[9, 10]

TAP AC Switching Characteristics Over the Operating Range

Parameter

t_TCYC

t_TF

Description

Min.

Max

Unit

TCK Clock Cycle Time

TCK Clock Frequency

TCK Clock HIGH

100

ns

MHz

ns

10

t_TH

40

t_TL

TCK Clock LOW

ns

Notes:

7. All Voltage referenced to Ground.

8. Overshoot: V_IH(AC)<V_DD+1.5V for t<t_TCYC/2, Undershoot: V_IL(AC)<0.5V for t<t_TCYC/2, Power-up: V_IH<2.6V and V_DD<2.4V and V_DDQ<1.4V for t<200 ms.

9. t_CSand t_CHrefer to the set-up and hold time requirements of latching data from the boundary scan register.

10. Test conditions are specified using the load in TAP AC test conditions. t_R/t_F= 1 ns.

Document #: 38-05284 Rev. *A

Page 15 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

TAP AC Switching Characteristics Over the Operating Range (continued)^{[9, 10]}

Parameter

Set-up Times

t_TMSS

Description

Min.

Max

Unit

TMS Set-up to TCK Clock Rise

TDI Set-up to TCK Clock Rise

Capture Set-up to TCK Rise

10

ns

t_TDIS

t_CS

Hold Times

t_TMSH

TMS Hold after TCK Clock Rise

TDI Hold after Clock Rise

10

ns

t_TDIH

t_CH

Capture Hold after Clock Rise

Output Times

t_TDOVTCK Clock LOW to TDO Valid

t_TDOXTCK Clock LOW to TDO Invalid

20

ns

0

TAP Timing and Test Conditions

1.25V

50Ω

ALL INPUT PULSES

TDO

Vih

Z = 50Ω

0

C = 20 pF

L

0V

(a)

t_TL

GND

t_TH

Test Clock

TCK

t_{TC YC}

t_TMSS

t_TMSH

Test Mode Select

TMS

t_TDIS

t_TDIH

Test Data-In

TDI

Test Data-Out

TDO

t_TDOV

t_TDOX

Document #: 38-05284 Rev. *A

Page 16 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Identification Register Definitions

Instruction Field

Revision Number (31:29)

Department Number (27:25)

Voltage (28&24)

x 18

000

101

00

x36

000

101

00

x72

Description

Reserved for version number

000

101

00

Department number

Architecture (23:21)

000

001

010

100

000

001

100

000

001

110

100

Architecture type

Memory Type (20:18)

Device Width (17:15)

Device Density (14:12)

Cypress JEDEC ID (11:1)

Defines type of memory

Defines width of the SRAM. x36 or x18

Defines the density of the SRAM

0000011 0000011 0000011 Allows unique identification of SRAM vendor

0100

ID Register Presence (0)

1

Indicate the presence of an ID register

Scan Register Sizes

Register Name

Instruction

Bit Size (x18)

Bit Size (x36)

Bit Size (x72)

3

1

3

1

3

1

Bypass

ID

32

Boundary Scan

TBD

Identification Codes

Instruction

EXTEST

Code

Description

000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and

TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.

IDCODE

001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This

operation does not affect SRAM operation.

SAMPLE Z

RESERVED

010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

011

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO.

Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function

and is therefore not 1149.1 compliant.

RESERVED

BYPASS

101 Do Not Use: This instruction is reserved for future use.

110

111

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.

Boundary Scan Order (2M x 36)

Boundary Scan Order (2M x 36) (continued)

Signal

Name

Bump

ID

Signal

Name

Bump

ID

Signal

Name

Bump

ID

Signal

Name

Bump

ID

Bit #

TBD

Bit #

TBD

Bit #

TBD

Bit #

TBD

Document #: 38-05284 Rev. *A

Page 17 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Boundary Scan Order (2M x 36) (continued)

Boundary Scan Order (4M x 18) (continued)

Signal

Name

Bump

ID

Signal

Name

Bump

ID

Signal

Name

Bump

ID

Signal

Name

Bump

ID

Bit #

TBD

Bit #

TBD

Bit #

TBD

Bit #

TBD

Boundary Scan Order (4M x 18)

Signal

Name

Bump

ID

Signal

Name

Bump

ID

Bit #

TBD

Bit #

TBD

Document #: 38-05284 Rev. *A

Page 18 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Current into Outputs (LOW)......................................... 20 mA

Maximum Ratings

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Latch-up Current..................................................... >200 mA

Storage Temperature .................................–65°C to +150°C

Operating Range

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Ambient

Range Temperature^[11]

V_DD

V_DDQ

Supply Voltage on V_DDRelative to GND........ –0.5V to +4.6V

DC Voltage Applied to Outputs

Com’l

0°C to +70°C

3.3V + 5%/

2.375V (min.)

V_DD(max.)

in High-Z State^[12]............................... –0.5V to V_DDQ+ 0.5V

–5%

DC Input Voltage^[12]............................ –0.5V to V_DDQ+ 0.5V

Electrical Characteristics Over the Operating Range

Parameter

V_DD

Description

Power Supply Voltage

I/O Supply Voltage

Test Conditions

Min.

3.135

2.375

2.4

Max.

3.465

V_DD

Unit

V

V_DDQ

V_OH

Output HIGH Voltage

V_DD= Min., I_OH= –4.0 mA

3.3V

2.5V

3.3V

2.5V

3.3V

2.5V

3.3V

2.5V

V

V_DD= Min., I_OH= –1.0 mA

V_DD= Min., I_OL= 8.0 mA

V_DD= Min., I_OL= 1.0 mA

2.0

V

V_OL

V_IH

V_IL

I_X

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage^[12]

0.4

V

2.0

1.7

V

–0.3

0.8

0.7

V

Input Load Current

GND < V_I< V_DDQ

Input = V_SS

5

µA

mA

Input Current of MODE

Input Current of ZZ

30

I_OZ

I_DD

Output Leakage Current

V_DDOperating Supply

GND < V_I< V_DDQ,Output Disabled

5

V_DD= Max., I_OUT= 0 mA,

f = f_MAX= 1/t_CYC

150 MHz

TBD

133 MHz

117 MHz

100 MHz

I_SB1

Automatic CE

Power-down

Current—TTL Inputs

Max. V_DD, Device Deselected, 150 MHz

V_IN> V_IHor V_IN< V_IL

f = f_MAX= 1/t_CYC

117 MHz

133 MHz

100 MHz

I_SB2

Automatic CE

Max. V_DD, Device Deselected, All speed grades

Power-down

Current—CMOS Inputs

V_IN< 0.3V or V_IN> V_DDQ–

0.3V,

f = 0

I_SB3

Automatic CE

Power-down

Current—CMOS Inputs

Max. V_DD, Device Deselected, 150 MHz

TBD

mA

or V_IN< 0.3V or V_IN> V_DDQ

0.3V

f = f_MAX= 1/t_CYC

–

133 MHz

117 MHz

100 MHz

I_SB4

Automatic CE

Power-down

Max. V_DD, Device Deselected, All speed grades

V_IN> V_IHor V_IN< V_IL, f = 0

Current—TTL Inputs

Shaded area contains advance information.

Notes:

11.

T_Ais the ambient temperature.

12. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.

Document #: 38-05284 Rev. *A

Page 19 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Capacitance^[14]

Parameter

Description

Test Conditions

Max. Unit

C_IN

Input Capacitance

T_A= 25°C, f = 1 MHz,

V_DD= V_DDQ= 3.3V

TBD

pF

C_CLK

C_I/O

Clock Input Capacitance

Input/Output Capacitance

AC Test Loads and Waveforms

R = 317Ω

V

[13]

DDQ

OUTPUT

ALL INPUT PULSES

90%

OUTPUT

Vdd

90%

10%

Z = 50Ω

0

R = 50Ω

10%

L

5 pF

GND

R = 351Ω

V = 1.5 for 3.3V V

Rise Time:

2 V/ns

L

DDQ

Fall Time:

2 V/ns

= 1.25 for 2.5V V

INCLUDING

JIG AND

SCOPE

(c)

(a)

(b)

Thermal Resistance^[14]

Parameter

Description

Test Conditions

BGA Typ.

TQFP Typ.

Unit

Q_JA

Thermal Resistance

(Junction to Ambient)

Still Air, soldered on a 4.25 x 1.125 inch,

4-layer printed circuit board

TBD

°C/W

Q_JC

Thermal Resistance

(Junction to Case)

TBD

°C/W

Switching Characteristics Over the Operating Range

-150

-133

-117

-100

Parameter

Clock

t_CYC

Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Unit

Clock Cycle Time

6.7

7.5

8.5

10

ns

F_MAX

Maximum Operating Frequency

Clock HIGH

150

133

117

100

MHz

ns

t_CH

2.5

2.8

3.0

t_CL

Clock LOW

ns

Output Times

t_CDV

Data Output Valid After CLK Rise

OE LOW to Output Valid^{[14, 16, 18]}

Data Output Hold After CLK Rise

Clock to High-Z^{[14, 15, 16, 17, 18]}

Clock to Low-Z^{[14, 15, 16, 17, 18]}

OE HIGH to Output High-Z^{[15, 16, 18]}

OE LOW to Output Low-Z^{[15, 16, 18]}

5.5

2.5

6.5

3.0

7.5

3.4

8.5

3.8

ns

t_EOV

t_DOH

2.5

0

2.5

3.0

0

2.5

3.0

0

2.5

3.0

0

t_CHZ

3.5

2.5

3.8

3.0

4.0

3.5

4.5

4

t_CLZ

t_EOHZ

t_EOLZ

Set-up Times

t_AS

Address Set-up Before CLK Rise

1.5

ns

Shaded areas contain advance information.

Notes:

13. Input waveform should have a slew rate of > 2 V/ns.

14. Tested initially and after any design or process change that may affect these parameters.

15. Unless otherwise noted, test conditions assume signal transition time of 1.5ns, timing reference levels of 1.75V, input pulse levels of 0 to 3.3V, and output

loading of the specified I_OL/I_OHand load capacitance. Shown in (a), (b) and (c) of AC Test Loads.

16. t_CHZ, t_CLZ, t_OEV, t_EOLZ, and t_EOHZare specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state

voltage.

17. At any given voltage and temperature, t_EOHZis less than t_EOLZand t_CHZis less than t_CLZto eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

18. This parameter is sampled and not 100% tested.

Document #: 38-05284 Rev. *A

Page 20 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Switching Characteristics Over the Operating Range (continued)

-150

-133

Min. Max.

-117

Min. Max.

-100

Parameter

t_DS

t_ADS

t_WES

Description

Min.

Max.

Min.

1.5

Max. Unit

Data Input Set-up Before CLK Rise

1.5

ns

ADSP, ADSC Set-up Before CLK Rise 1.5

1.5

BWE, GW, BW_xSet-up Before CLK

Rise

1.5

t_ADVS

t_CES

ADV Set-up Before CLK Rise

Chip Select Set-up

1.5

ns

Hold Times

t_AH

Address Hold After CLK Rise

Data Input Hold After CLK Rise

ADSP, ADSC Hold After CLK Rise

BWE, GW, BW_xHold After CLK Rise

ADV Hold after CLK Rise

0.5

ns

t_DH

t_ADH

t_WEH

t_ADVH

t_CEH

Chip Select Hold After CLK Rise

Document #: 38-05284 Rev. *A

Page 21 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Switching Waveforms

Write Cycle Timing^[19,20]

Single Write

Burst Write

Pipelined Write

t_CH

Unselected

t_CYC

t_ADH

CLK

t_ADS

t_CL

ADSP ignored with CE₁inactive

ADSP

ADSC

ADV

t_ADH

t_ADS

ADSC initiated write

t_ADVH

t_ADVS

t_AS

ADV Must Be Inactive for ADSP Write

WD3

ADD

GW

WE

CE₁

WD1

WD2

t_AH

t_WH

t_WS

t_CES

t_CEH

CE₁masks ADSP

t_CEH

t_CES

Unselected with CE₂

CE₂

CE₃

OE

t_CES

t_CEH

t_DH

t_DS

High-Z

Data In

3a

2a

1a

2b

2c

2d

= UNDEFINED

= DON’T CARE

Notes:

19. WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Descriptions table).

20. WDx stands for Write Data to Address X.

Document #: 38-05284 Rev. *A

Page 22 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Switching Waveforms (continued)

Read Cycle Timing^{[19, 21]}

Burst Read

Single Read

Unselected

t_CYC

t_CH

Pipelined Read

CLK

t_ADH

t_ADS

t_CL

ADSP ignored with CE₁inactive

ADSP

t_ADS

ADSC initiated read

ADSC

ADV

t_ADVS

t_ADH

Suspend Burst

t_ADVH

t_AS

ADD

GW

RD3

RD1

RD2

t_AH

t_WS

t_WH

WE

t_CES

t_CEH

t_WH

CE₁masks ADSP

CE₁

Unselected with CE₂

CE₂

t_CES

t_CEH

CE₃

OE

t_CEH

t_EOV

t_CES

t_OEHZ

t_DOH

t_CDV

3a

2c

Data Out

2d

2a

2b

2c

1a

t_CLZ

t_CHZ

= DON’T CARE

= UNDEFINED

Note:

21. RDx stands for Read Data from Address X.

Document #: 38-05284 Rev. *A

Page 23 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Switching Waveforms (continued)

Read/Write Timing

t_CYC

t_CL

t_CH

CLK

t_AH

t_AS

A

D

B

C

ADD

t_ADH

t_ADS

ADSP

t_ADH

t_ADS

ADSC

t_ADVH

t_ADVS

ADV

t_CEH

t_CES

CE₁

CE

t_CEH

t_CES

t_WES

t_WEH

WE

OE

ADSP ignored

with CE₁HIGH

t_EOHZ

t_CLZ

Data

Q

(B+3)

D

(C+1)

D

(C+2)

D

(C+3)

Q

(B+2)

Q

(B+1)

Q(B)

D(C)

Q(D)

Q(A)

In/Out

t_CDV

t_DOH

t_CHZ

Device originally

deselected

WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Description table).

CE is the combination of CE₂and CE₃. All chip selects need to be active in order to select

the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,

Qx stands for Data-out X.

= UNDEFINED

= DON’T CARE

Notes:

22. Device originally deselected.

23. CE is the combination of CE₂and CE₃. All chip selects need to be active in order to select the device.

Document #: 38-05284 Rev. *A

Page 24 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Switching Waveforms (continued)

OE Timing

OE

t_EOV

t_EOHZ

Three-state

I/Os

t_EOLZ

Ordering Information

Speed

(MHz)

Package

Name

Operating

Range

Ordering Code

Package Type

150

CY7C1481V33-150AC

CY7C1483V33-150AC

A101

BG119

BB165C

100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack

Commercial

CY7C1481V33-150BGC

CY7C1483V33-150BGC

119-Ball BGA (14 x 22 x 2.4 mm)

CY7C1481V33-150BZC

CY7C1483V33-150BZC

165-Ball FBGA (15 x 17 mm)

CY7C1487V33-150BGC

BG209

A101

209-Ball BGA (14 x 22 x 2.2mm)

133

117

100

CY7C1481V33-133AC

CY7C1483V33-133AC

100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack

CY7C1481V33-133BGC

CY7C1483V33-133BGC

BG119

119-Ball BGA (14 x 22 x 2.4 mm)

165-Ball FBGA (15 x 17 mm)

CY7C1481V33-133BZC

CY7C1483V33-133BZC

BB165C

CY7C1487V33-133BGC

BG209

A101

209-Ball BGA (14 x 22 x 2.2mm)

CY7C1481V33-117AC

CY7C1483V33-117AC

100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack

CY7C1481V33-117BGC

CY7C1483V33-117BGC

BG119

119-Ball BGA (14 x 22 x 2.4 mm)

165-Ball FBGA (15 x 17 mm)

CY7C1481V33-117BZC

CY7C1483V33-117BZC

BB165C

CY7C1487V33-117BGC

BG209

A101

209-Ball BGA (14 x 22 x 2.2mm)

CY7C1481V33-100AC

CY7C1483V33-100AC

100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack

CY7C1481V33-100BGC

CY7C1483V33-100BGC

BG119

BB165C

BG209

119-Ball BGA (14 x 22 x 2.4 mm)

165-Ball FBGA (15 x 17 mm)

209-Ball BGA (14 x 22 x 2.2mm)

CY7C1481V33-100BZC

CY7C1483V33-100BZC

CY7C1487V33-100BGC

Document #: 38-05284 Rev. *A

Page 25 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Package Diagrams

100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

51-85050-A

Document #: 38-05284 Rev. *A

Page 26 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Package Diagrams (continued)

165-Ball FBGA (15 x 17 x 1.20 mm) BB165C

51-85165-**

Document #: 38-05284 Rev. *A

Page 27 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Package Diagrams (continued)

119-Lead PBGA (14 x 22 x 2.4 mm) BG119

51-85115-*B

Document #: 38-05284 Rev. *A

Page 28 of 30

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Package Diagrams (continued)

209-Lead PBGA (14 x 22 x 2.20 mm) BG209

51-85143-*B

All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05284 Rev. *A

Page 29 of 30

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C1481V33

CY7C1483V33

CY7C1487V33

PRELIMINARY

Document History Page

Document Title: CY7C1481V33/CY7C1483V33/CY7C1487V33 2M x 36/4M x 18/1M x 72 Flow-through SRAM

Document Number: 38-05284

Issue

Date

Orig. of

Change

REV.

**

ECN NO.

114671

118283

Description of Change

08/12/02

01/27/03

PKS

HGK

New Data Sheet

*A

Updated Ordering Information

Updated the features for package offering

Changed from Advance Information to Preliminary

Document #: 38-05284 Rev. *A

Page 30 of 30


型号：	CY7C1487V33-150BGC
厂家：	CYPRESS
描述：	2M x 36/4M x 18/1M x 72 Flow-through SRAM 2M ×36 / 4M ×18 / 1M X 72流通式SRAM 静态存储器
文件：	总30页 (文件大小：639K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C1487V33-150BGC [CYPRESS]

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