CY7C1520V18-200BZI [CYPRESS]
72-Mbit DDR-II SRAM 2-Word Burst Architecture; 72兆位的DDR - II SRAM的2字突发架构
| 型号： | CY7C1520V18-200BZI |
| 厂家： | 
CYPRESS |
| 描述： | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| 文件： | 总28页 (文件大小：670K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
72-Mbit DDR-II SRAM 2-Word
Burst Architecture
Features
Functional Description
• 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
• 300-MHz clock for high bandwidth
The CY7C1516V18, CY7C1527V18, CY7C1518V18, and
CY7C1520V18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry
and a 1-bit burst counter. Addresses for Read and Write are
latched on alternate rising edges of the input (K) clock.Write
data is registered on the rising edges of both K and K. Read
data is driven on the rising edges of C and C if provided, or on
the rising edge of K and K if C/C are not provided. Each
address location is associated with two 8-bit words in the case
of CY7C1516V18 and two 9-bit words in the case of
CY7C1527V18 that burst sequentially into or out of the device.
The burst counter always starts with a “0” internally in the case
of CY7C1516V18 and CY7C1527V18. On CY7C1518V18 and
CY7C1520V18, the burst counter takes in the least significant
bit of the external address and bursts two 18-bit words in the
case of CY7C1518V18 and two 36-bit words in the case of
CY7C1520V18 sequentially into or out of the device.
• 2-Word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) @ 300 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–VDD
)
Asynchronous inputs include output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need for
separately capturing data from each individual DDR SRAM in
the system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
• Offered in both lead-free and non lead-free packages
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Configurations
CY7C1516V18 – 8M x 8
CY7C1527V18 – 8M x 9
CY7C1518V18 – 4M x 18
CY7C1520V18 – 2M x 36
Selection Guide
300 MHz
300
278 MHz
250 MHz
250
200 MHz
200
167 MHz
167
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current (x36)
278
860
900
800
700
650
Cypress Semiconductor Corporation
Document #: 38-05563 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 1, 2006
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Logic Block Diagram (CY7C1516V18)
Write
Reg
Write
Reg
A
(21: 0)
Address
Register
22
LD
K
8
Output
Logic
Control
CLK
K
R/W
Gen.
DOFF
C
C
Read Data Reg.
16
CQ
8
V
REF
Reg.
Reg.
Reg.
CQ
8
R/W
Control
Logic
8
NWS
[1 : 0]
DQ
[7:0]
8
Logic Block Diagram (CY7C1527V18)
Write
Reg
Write
Reg
A
(21:0)
Address
Register
22
LD
K
9
Output
Logic
Control
CLK
K
R/W
Gen.
DOFF
C
C
Read Data Reg.
18
CQ
CQ
9
V
REF
Reg.
Reg.
Reg.
9
R/W
Control
Logic
9
BWS
[0]
DQ
[8: 0]
9
Document #: 38-05563 Rev. *D
Page 2 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Logic Block Diagram (CY7C1518V18)
Burst
A0
Logic
21
Write
Reg
Write
Reg
22
A
Address
Register
(21: 0)
A
(21:1)
LD
18
4M x 18 Array
K
K
Output
Logic
Control
CLK
Gen.
R/W
DOFF
C
C
Read Data Reg.
36
CQ
18
V
REF
CQ
Reg.
Reg.
Reg.
R/W
Control
Logic
18
BWS
[1: 0]
18
DQ
[17: 0]
18
Logic Block Diagram (CY7C1520V18)
Burst
Logic
A0
20
Write
Reg
Write
Reg
21
A
Address
Register
(20:0)
A
(20:1)
36
LD
2M x 36 Array
K
K
R/W
Output
Logic
Control
CLK
Gen.
DOFF
C
C
Read Data Reg.
72
CQ
CQ
36
V
REF
36
Reg.
Reg.
Reg.
R/W
Control
Logic
36
BWS
[3:0]
36
DQ
[35: 0]
36
Document #: 38-05563 Rev. *D
Page 3 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Pin Configurations [1]
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1516V18 (8M x 8)
1
2
A
3
A
4
5
6
7
NC
8
9
A
10
A
11
CQ
DQ3
NC
A
B
C
D
CQ
NC
R/W
A
NWS1
NC
K
K
LD
A
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NWS0
A
NC
NC
NC
NC
NC
VSS
VSS
A
A
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
DQ4
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC
DQ2
E
F
VDD
VDD
VDD
VDD
VDD
VSS
NC
NC
NC
DQ5
VDDQ
NC
NC
NC
G
H
J
VREF
NC
VDDQ
NC
VREF
DQ1
NC
ZQ
DOFF
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
K
L
DQ6
NC
NC
NC
DQ0
NC
NC
NC
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
M
N
P
DQ7
A
C
A
A
A
A
A
A
A
TDO
TCK
A
A
TMS
TDI
R
C
CY7C1527V18 (8M x 9)
1
2
A
3
A
4
5
NC
6
7
NC
8
9
A
10
A
11
CQ
DQ3
NC
A
B
C
D
CQ
NC
R/W
A
K
K
LD
A
NC
NC
NC
NC
NC
NC
NC
A
NC
NC
NC
NC
NC
NC
BWS0
A
NC
NC
NC
NC
NC
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
DQ4
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC
DQ2
E
F
VDD
VDD
VDD
VDD
VDD
VSS
NC
NC
ZQ
NC
DQ5
VDDQ
NC
NC
NC
G
H
J
VREF
NC
VDDQ
NC
VREF
DQ1
NC
DOFF
NC
NC
NC
DQ0
NC
NC
NC
NC
NC
K
L
DQ6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
M
N
P
DQ7
A
C
A
DQ8
A
A
A
A
A
A
TDO
TCK
A
A
TMS
TDI
R
C
Note:
1. V /144M and V /288M are not connected to the die and can be tied to any voltage level.
SS
SS
Document #: 38-05563 Rev. *D
Page 4 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Pin Configurations [1] (continued)
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1518V18 (4M x 18)
1
2
A
3
A
4
5
6
7
NC
8
9
A
10
A
11
CQ
DQ8
NC
A
B
C
D
CQ
NC
R/W
A
BWS1
NC
K
K
LD
A
DQ9
NC
NC
NC
NC
NC
NC
NC
DQ7
NC
BWS0
A
NC
NC
NC
NC
NC
VSS
VSS
A
A0
VSS
VSS
VSS
NC
DQ10
VSS
VSS
VSS
NC
NC
DQ12
NC
DQ11
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC
DQ6
E
F
VDD
VDD
VDD
VDD
VDD
VSS
DQ5
NC
DQ13
VDDQ
NC
NC
NC
G
H
J
VREF
NC
VDDQ
NC
VREF
DQ4
NC
ZQ
DOFF
NC
NC
NC
NC
NC
DQ14
NC
NC
DQ3
DQ2
K
L
DQ15
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
DQ1
NC
NC
NC
M
N
P
DQ16
DQ17
A
C
A
NC
DQ0
A
A
A
A
A
A
TDO
TCK
A
A
TMS
TDI
R
C
CY7C1520V18 (2M x 36)
1
2
3
A
4
5
6
7
8
9
A
10
A
11
CQ
VSS/144M
A
B
C
D
CQ
NC
R/W
A
BWS2
K
K
BWS1
LD
A
DQ27
NC
DQ18
DQ28
DQ19
NC
NC
NC
NC
DQ17
NC
DQ8
DQ7
DQ16
BWS3
A
BWS0
A
NC
NC
NC
NC
NC
VSS
VSS
A0
VSS
VSS
VSS
DQ29
VSS
VSS
VSS
NC
DQ30
DQ31
VREF
NC
DQ20
DQ21
DQ22
VDDQ
DQ32
DQ23
DQ24
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
DQ15
NC
DQ6
E
F
VDD
VDD
VDD
VDD
VDD
VSS
DQ5
DQ14
ZQ
NC
NC
G
H
J
VDDQ
NC
VREF
DQ13
DQ12
NC
DOFF
NC
DQ4
DQ3
DQ2
NC
NC
NC
NC
K
L
DQ33
NC
NC
NC
NC
NC
DQ35
NC
DQ34
DQ25
DQ26
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
DQ11
NC
DQ1
DQ10
DQ0
M
N
P
A
C
A
DQ9
A
A
A
A
A
A
TDO
TCK
A
A
TMS
TDI
R
C
Document #: 38-05563 Rev. *D
Page 5 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
Input/Output- Data Input/Output signals. Inputs are sampled on the rising edge of K and K clocks during valid
Synchronous Write operations. These pins drive out the requested data during a Read operation. Valid data is
driven out on the rising edge of both the C and C clocks during Read operations or K and K when
in single clock mode. When read access is deselected, Q[x:0] are automatically tri-stated.
CY7C1516V18 − DQ[7:0]
CY7C1527V18 − DQ[8:0]
CY7C1518V18 − DQ[17:0]
CY7C1520V18 − DQ[35:0]
Input-
Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined.
LD
Synchronous This definition includes address and Read/Write direction. All transactions operate on a burst of
2 data.
Input-
Nibble Write Select 0, 1 − active LOW (CY7C1516V18 only).Sampled on the rising edge of the
NWS0, NWS1
Synchronous K and K clocks during Write operations. Used to select which nibble is written into the device
during the current portion of the Write operations. Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4]
.
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble
Write Select will cause the corresponding nibble of data to be ignored and not written into the
device.
BWS0, BWS1,
Input-
Byte Write Select 0, 1, 2, and 3 − active LOW. Sampled on the rising edge of the K and K clocks
BWS2, BWS3 Synchronous during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1527V18 − BWS0 controls D[8:0]
CY7C1518V18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1520V18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27]
.
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
A, A0
Input-
Address Inputs. These address inputs are multiplexed for both Read and Write operations.
Synchronous Internally, the device is organized as 8M x 8 (2 arrays each of 4M x 8) for CY7C1516V18 and
8M x 9 (2 arrays each of 4M x9) for CY7C1527V18, a single 4M x 18 array for CY7C1518V18,
and a single array of 2M x 36 for CY7C1520V18.
CY7C1516V18 – Since the least significant bit of the address internally is a “0,” only 22 external
address inputs are needed to access the entire memory array.
CY7C1527V18 – Since the least significant bit of the address internally is a “0,” only 22 external
address inputs are needed to access the entire memory array.
CY7C1518V18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 22 address inputs are needed to access the entire memory array.
CY7C1520V18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 21 address inputs are needed to access the entire memory array. All the address inputs
are ignored when the appropriate port is deselected.
Input-
Synchronous Read/Write Input. When LD is LOW, this input designates the access type (Read
R/W
C
Synchronous when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up and
hold times around edge of K.
Input-
Clock
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various devices on
the board back to the controller. See application example for further details.
Input-
Clock
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
C
K
Input-
Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
Input-
Clock
Negative Input Clock Input. K is used to capture synchronous data beingpresented to the device
and to drive out data through Q[x:0] when in single clock mode.
K
Document #: 38-05563 Rev. *D
Page 6 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Pin Definitions (continued)
Pin Name
CQ
I/O
Pin Description
Output-
Clock
CQ is referenced with respect to C. This is a free running clock and is synchronized to the Input
clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to
K. The timings for the echo clocks are shown in the AC Timing table.
Output-
Clock
CQ
ZQ
CQ is referenced with respect to C. This is a free running clock and is synchronized to the Input
clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to
K. The timings for the echo clocks are shown in the AC Timing table.
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to
VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
DOFF
Input
DLL Turn Off - active LOW. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
TDO
Output
Input
Input
Input
N/A
TDO for JTAG.
TCK
TCK pin for JTAG.
TDI
TDI pin for JTAG.
TMS
TMS pin for JTAG.
NC
Not connected to the die. Can be tied to any voltage level.
Address expansion for 144M. Can be tied to any voltage level.
Address expansion for 288M. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs
VSS/144M
VSS/288M
VREF
Input
Input
Input-
Reference as well as AC measurement points.
VDD
VSS
Power Supply Power supply inputs to the core of the device.
Ground
Ground for the device.
VDDQ
Power Supply Power supply inputs for the outputs of the device.
Document #: 38-05563 Rev. *D
Page 7 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
memory array at the specified location. Write accesses can be
initiated on every rising edge of the positive input clock (K).
Doing so will pipeline the data flow such that 18 bits of data
can be transferred into the device on every rising edge of the
input clocks (K and K).
Functional Overview
The CY7C1516V18, CY7C1527V18, CY7C1518V18, and
CY7C1520V18 are synchronous pipelined Burst SRAMs
equipped with a DDR interface.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing
is referenced to the rising edge of the output clocks (C/C or
K/K when in single clock mode).
When write access is deselected, the device will ignore all
inputs after the pending Write operations have been
completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1518V18. A
Write operation is initiated as described in the Write Operation
section above. The bytes that are written are determined by
BWS0 and BWS1 which are sampled with each set of 18-bit
data word. Asserting the appropriate Byte Write Select input
during the data portion of a Write will allow the data being
presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
All synchronous data inputs (D[x:0]) pass through input
registers controlled by the rising edge of the input clocks (K
and K). All synchronous data outputs (Q[x:0]) pass through
output registers controlled by the rising edge of the output
clocks (C/C or K/K when in single-clock mode).
All synchronous control (R/W, LD, BWS[0:X]) inputs pass
through input registers controlled by the rising edge of the
input clock (K).
CY7C1518V18 is described in the following sections. The
same basic descriptions apply to CY7C1516V18,
CY7C1527V18, and CY7C1520V18.
Single Clock Mode
Read Operations
The CY7C1518V18 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power-on. This function is
a strap option and not alterable during device operation.
The CY7C1518V18 is organized internally as a single array of
4M x 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to Address inputs is stored
in the Read address register and the least significant bit of the
address is presented to the burst counter. The burst counter
increments the address in a linear fashion. Following the next
K clock rise the corresponding 18-bit word of data from this
address location is driven onto the Q[17:0] using C as the output
timing reference. On the subsequent rising edge of C the next
18-bit data word from the address location generated by the
burst counter is driven onto the Q[17:0]. The requested data will
be valid 0.45 ns from the rising edge of the output clock (C or
C, or K and K when in single clock mode, 200-MHz, 250-MHz
and 300-MHz device). In order to maintain the internal logic,
each read access must be allowed to complete. Read
accesses can be initiated on every rising edge of the positive
input clock (K).
DDR Operation
The CY7C1518V18 enables high-performance operation
through high clock frequencies (achieved through pipelining)
and double data rate mode of operation. The CY7C1518V18
requires a single No Operation (NOP) cycle when transitioning
from a Read to a Write cycle. At higher frequencies, some
applications may require a second NOP cycle to avoid
contention.
If a Read occurs after a Write cycle, address and data for the
Write are stored in registers. The write information must be
stored because the SRAM cannot perform the last word Write
to the array without conflicting with the Read. The data stays
in this register until the next Write cycle occurs. On the first
Write cycle after the Read(s), the stored data from the earlier
Write will be written into the SRAM array. This is called a
Posted Write.
When read access is deselected, the CY7C1518V18 will first
complete the pending read transactions. Synchronous internal
circuitry will automatically tri-state the outputs following the
next rising edge of the positive output clock (C). This will allow
for a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
If a Read is performed on the same address on which a Write
is performed in the previous cycle, the SRAM reads out the
most current data. The SRAM does this by bypassing the
memory array and reading the data from the registers.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to Address inputs is stored in the Write
address register and the least significant bit of the address is
presented to the burst counter. The burst counter increments
the address in a linear fashion. On the following K clock rise
the data presented to D[17:0] is latched and stored into the
18-bit Write Data register provided BWS[1:0] are both asserted
active. On the subsequent rising edge of the Negative Input
Clock (K) the information presented to D[17:0] is also stored
into the Write Data register provided BWS[1:0] are both
asserted active. The 36 bits of data are then written into the
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Document #: 38-05563 Rev. *D
Page 8 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Programmable Impedance
respect to K and CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC Timing table.
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5x the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
VDDQ = 1.5V. The output impedance is adjusted every 1024
cycles upon power-up to account for drifts in supply voltage
and temperature.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. During power-up, when the DOFF is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K
for a minimum of 30 ns. However, it is not necessary for the
DLL to be specifically reset in order to lock the DLL to the
desired frequency. The DLL will automatically lock 1024 clock
cycles after a stable clock is presented.the DLL may be
disabled by applying ground to the DOFF pin. For information
refer to the application note “DLL Considerations in
QDRII™/DDRII/QDRII+/DDRII+”.
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the DDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are
free-running clocks and are synchronized to the output clock
of the DDR-II. In the single clock mode, CQ is generated with
Application Example[2]
ZQ
ZQ
SRAM#1
SRAM#2
DQ
CQ/CQ#
LD# R/W# C C# K
K#
DQ
CQ/CQ#
LD# R/W# C C# K
K#
R = 250ohms
R = 250ohms
A
A
DQ
Addresses
Cycle Start#
R/W#
BUS
MASTER
(CPU
Return CLK
Source CLK
Return CLK#
Source CLK#
or
ASIC)
Vterm = 0.75V
R = 50ohms
Vterm = 0.75V
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
Truth Table[3, 4, 5, 6, 7, 8]
Operation
K
LD
R/W
DQ
D(A1) at K(t + 1) ↑
DQ
D(A2) at K(t + 1) ↑
Write Cycle:
L-H
L
L
Load address; wait one cycle; input write data on
consecutive K and K rising edges.
Read Cycle:
L-H
L-H
L
H
Q(A1) at C(t + 1) ↑ Q(A2) at C(t + 2) ↑
Load address; wait one and a half cycle; read data on
consecutive C and C rising edges.
NOP: No Operation
H
X
X
X
High-Z
High-Z
Standby: Clock Stopped
Stopped
Previous State
Previous State
Burst Address Table (CY7C1518V18, CY7C1520V18)
First Address (External)
Second Address (Internal)
X..X0
X..X1
X..X1
X..X0
Notes:
2. The above application shows two DDR-II used.
3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge.
4. Device will power-up deselected and the outputs in a tri-state condition.
5. On CY7C1518V18 and CY7C1520V18, “A1” represents address location latched by the devices when transaction was initiated and A2 represents the addresses
sequence in the burst. On CY7C1516V18, “A1” represents A +‘0’ and A2 represents A +‘1.’
6. “t” represents the cycle at which a Read/Write operation is started. t+1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
8. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
Document #: 38-05563 Rev. *D
Page 9 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Write Cycle Descriptions (CY7C1516V18 and CY7C1518V18)[3, 9]
,
, NWS1
BWS0 NWS0 BWS1
K
K
Comments
L
L
L
L
L-H
–
During the Data portion of a Write sequence :
CY7C1516V18 − both nibbles (D[7:0]) are written into the device,
CY7C1518V18 − both bytes (D[17:0]) are written into the device.
L
–
L-H During the Data portion of a Write sequence :
CY7C1516V18 − both nibbles (D[7:0]) are written into the device,
CY7C1518V18 − both bytes (D[17:0]) are written into the device.
H
L-H
–
During the Data portion of a Write sequence :
CY7C1516V18 − only the lower nibble (D[3:0]) is written into the device. D[7:4]
will remain unaltered,
CY7C1518V18 − only the lower byte (D[8:0]) is written into the device. D[17:9]
will remain unaltered.
L
H
H
H
L
L
–
L-H
–
L-H During the Data portion of a Write sequence :
CY7C1516V18 − only the lower nibble (D[3:0]) is written into the device. D[7:4]
will remain unaltered,
CY7C1518V18 − only the lower byte (D[8:0]) is written into the device. D[17:9]
will remain unaltered.
–
During the Data portion of a Write sequence :
CY7C1516V18 − only the upper nibble (D[7:4]) is written into the device. D[3:0]
will remain unaltered,
CY7C1518V18 − only the upper byte (D[17:9]) is written into the device. D[8:0]
will remain unaltered.
L-H During the Data portion of a Write sequence :
CY7C1516V18 − only the upper nibble (D[7:4]) is written into the device. D[3:0]
will remain unaltered,
CY7C1518V18 − only the upper byte (D[17:9]) is written into the device. D[8:0]
will remain unaltered.
H
H
H
H
L-H
–
–
No data is written into the devices during this portion of a Write operation.
L-H No data is written into the devices during this portion of a Write operation.
Document #: 38-05563 Rev. *D
Page 10 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Write Cycle Descriptions[3, 9] (CY7C1520V18)
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L-H
–
During the Data portion of a Write sequence, all four bytes (D[35:0]) are
written into the device.
L
L
L
L
–
L-H
–
L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) are
written into the device.
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
–
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is
written into the device. D[35:9] will remain unaltered.
L
L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is
written into the device. D[35:9] will remain unaltered.
H
H
H
H
H
H
L-H
–
–
During the Data portion of a Write sequence, only the byte (D[17:9]) is
written into the device. D[8:0] and D[35:18] will remain unaltered.
L
L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is
written into the device. D[8:0] and D[35:18] will remain unaltered.
H
H
H
H
L-H
–
–
During the Data portion of a Write sequence, only the byte (D[26:18]) is
written into the device. D[17:0] and D[35:27] will remain unaltered.
L
L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is
written into the device. D[17:0] and D[35:27] will remain unaltered.
H
H
L-H
–
During the Data portion of a Write sequence, only the byte (D[35:27]) is
written into the device. D[26:0] will remain unaltered.
L
L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is
written into the device. D[26:0] will remain unaltered.
H
H
H
H
H
H
H
H
L-H
–
–
No data is written into the device during this portion of a Write operation.
L-H No data is written into the device during this portion of a Write operation.
Write Cycle Descriptions[3, 9](CY7C1527V18)
BWS0
K
K
Comments
L
L-H
–
During the Data portion of a Write sequence, the single byte (D[8:0]) is
written into the device.
L
–
L-H During the Data portion of a Write sequence, the single byte (D[8:0]) is
written into the device.
H
H
L-H
–
–
No data is written into the device during this portion of a Write operation.
L-H No data is written into the device during this portion of a Write operation.
Note:
9. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS , NWS BWS , BWS BWS and BWS can be altered on different
0
1,
0
1,
2
3
portions of a write cycle, as long as the set-up and hold requirements are achieved.
Document #: 38-05563 Rev. *D
Page 11 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP operates using
JEDEC standard 1.8V I/O logic levels.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port—Test Clock
Boundary Scan Register
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
Test Mode Select
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
Document #: 38-05563 Rev. *D
Page 12 of 28
[+] Feedback
CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the in-
struction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
EXTEST Output Bus Tri-State
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possi-
ble that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit
#108. When this scan cell, called the “extest output bus
tri-state”, is latched into the preload register during the
“Update-DR” state in the TAP controller, it will directly control
the state of the output (Q-bus) pins, when the EXTEST is
entered as the current instruction. When HIGH, it will enable
the output buffers to drive the output bus. When LOW, this bit
will place the output bus into a High-Z condition.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells pri-
or to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
Document #: 38-05563 Rev. *D
Page 13 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
TAP Controller State Diagram[10]
TEST-LOGIC
1
RESET
0
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
10. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05563 Rev. *D
Page 14 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
1
0
TDO
TDI
Instruction Register
29
31 30
.
.
2
0
0
Identification Register
.
106 .
.
.
2
1
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[16, 18, 11]
Parameter
VOH1
Description
Output HIGH Voltage
Test Conditions
IOH = −2.0 mA
Min.
1.4
Max.
Unit
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
IOH = −100 µA
IOL = 2.0 mA
IOL = 100 µA
1.6
V
0.4
0.2
V
V
0.65 VDD
–0.3
VDD + 0.3
0.35 VDD
5
V
VIL
Input LOW Voltage
V
IX
Input and OutputLoad Current
GND ≤ VI ≤ VDD
−5
µA
TAP AC Switching Characteristics Over the Operating Range[12, 13]
Parameter
tTCYC
tTF
Description
Min.
Max.
Unit
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
50
20
MHz
ns
tTH
20
20
tTL
TCK Clock LOW
ns
Notes:
11. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
12. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
13. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
Document #: 38-05563 Rev. *D
Page 15 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
TAP AC Switching Characteristics Over the Operating Range[12, 13] (continued)
Parameter
Description
Min.
Max.
Unit
Set-up Times
tTMSS
tTDIS
TMS Set-up to TCK Clock Rise
5
5
5
ns
ns
ns
TDI set-up to TCK Clock Rise
Capture Set-up to TCK Rise
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Capture Hold after Clock Rise
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
10
ns
ns
0
TAP Timing and Test Conditions[13]
0.9V
50Ω
ALL INPUT PULSES
0.9V
TDO
1.8V
Z = 50Ω
0
C = 20 pF
L
0V
tTL
tTH
GND
(a)
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Document #: 38-05563 Rev. *D
Page 16 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Identification Register Definitions
Value
Instruction
Field
CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
000
Description
Revision
Number (31:29)
000
000
000
Version number.
Cypress Device 11010100010000100 11010100010001100 11010100010010100 11010100010100100 Defines the type
ID (28:12)
of SRAM.
Cypress JEDEC
ID (11:1)
00000110100
1
00000110100
1
00000110100
1
00000110100
1
Allows unique
identification of
SRAM vendor.
ID Register
Presence (0)
Indicate the
presence of an
ID register.
Scan Register Sizes
Register Name
Instruction
Bit Size
3
1
Bypass
ID
32
109
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
Description
000
001
Captures the Input/Output ring contents.
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
Document #: 38-05563 Rev. *D
Page 17 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Boundary Scan Order
Bit #
0
Bump ID
6R
Bit #
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Bump ID
10G
9G
Bit #
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Bump ID
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
Bit #
84
Bump ID
1J
1
6P
85
2J
2
6N
11F
11G
9F
86
3K
3
7P
87
3J
4
7N
88
2K
5
7R
10F
11E
10E
10D
9E
89
1K
6
8R
90
2L
7
8P
91
3L
8
9R
92
1M
1L
9
11P
10P
10N
9P
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
10C
11D
9C
94
3N
95
3M
1N
96
10M
11N
9M
9D
97
2M
3P
11B
11C
9B
98
99
2N
9N
100
101
102
103
104
105
106
107
108
2P
11L
11M
9L
10B
11A
10A
9A
1P
3R
4R
10L
11K
10K
9J
4P
8B
5P
7C
3F
5N
6C
1G
1F
5R
9K
8A
Internal
10J
11J
11H
7A
3G
2G
1H
7B
6B
Document #: 38-05563 Rev. *D
Page 18 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Power-Up Sequence in DDR-II SRAM[14, 15]
DLL Constraints
DDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
• DLL uses either K or C clock as its synchronizing input.The
input should have low phase jitter, which is specified as
tKC Var
.
Power-Up Sequence
• The DLL will function at frequencies down to 80 MHz.
• Apply power and drive DOFF LOW (All other inputs can be
HIGH or LOW)
• If the input clock is unstable and the DLL is enabled, then
the DLL may lock to an incorrect frequency, causing
unstable SRAM behavior.
— Apply VDD before VDDQ
— Apply VDDQ before VREF or at the same time as VREF
• After the power and clock (K, K, C, C) are stable take DOFF
HIGH
• The additional 1024 cycles of clocks are required for the
DLL to lock.
Power-up Waveforms
K
K
Unstable Clock
> 1024 Stable clock
Start Normal
Operation
/
V
Clock Start (Clock Starts after V
Stable)
DDQ
DD
Stable (< +/- 0.1V DC per 50ns )
/
/
V
DDQ
VDDQ
V
DD
VDD
Fix High (or tied to V
)
DDQ
DOFF
Notes:
14. It is recommended that the DOFF pin be pulled HIGH via a pull up resistor of 1 Kohm.
15. During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.
Document #: 38-05563 Rev. *D
Page 19 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V
Latch-up Current..................................................... >200 mA
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with Power Applied..–55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V
Supply Voltage on VDDQ Relative to GND ......–0.5V to +VDD
DC Applied to Outputs in High-Z......... –0.5V to VDDQ + 0.3V
DC Input Voltage[16] ...............................–0.5V to VDD + 0.3V
Operating Range
Ambient
[17]
[17]
Range
Com’l
Ind’l
Temperature
0°C to +70°C
–40°C to +85°C
VDD
VDDQ
1.4V to VDD
1.8 ± 0.1V
Electrical Characteristics Over the Operating Range[18]
Over the Operating Range
DC Electrical Characteristics
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
1.7
Typ.
1.8
Max.
Unit
V
1.9
VDDQ
VOH
1.4
1.5
VDD
V
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[16]
Input LOW Voltage[16]
Input Leakage Current
Output Leakage Current
Note 19
Note 19
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOL
VDDQ/2 + 0.12
V
VOH(LOW)
VOL(LOW)
VIH
IOH = –0.1 mA, Nominal Impedance VDDQ – 0.2
VDDQ
0.2
V
IOL = 0.1 mA, Nominal Impedance
VSS
VREF + 0.1
–0.3
V
VDDQ + 0.3
VREF – 0.1
5
V
VIL
V
IX
GND ≤ VI ≤ VDDQ
–5
µA
µA
V
IOZ
GND ≤ VI ≤ VDDQ, Output Disabled
–5
5
VREF
IDD
Input Reference Voltage[21] Typical Value = 0.75V
0.68
0.75
0.95
650
VDD Operating Supply
VDD = Max., IOUT= 0mA, 167 MHz
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
f = fMAX = 1/tCYC
200 MHz
250 MHz
278 MHz
300 MHz
167 MHz
200 MHz
250 MHz
278 MHz
300 MHz
700
800
860
900
ISB1
Automatic Power-down
Current
Max. VDD, Both Ports
Deselected, VIN ≥ VIH or
VIN ≤ VIL
f = fMAX = 1/tCYC
Inputs Static
340
360
380
,
390
400
AC Input Requirements Over the Operating Range
Parameter
Description
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min.
VREF + 0.2
–
Typ.
Max.
–
Unit
V
VIH
VIL
–
–
VREF – 0.2
V
Notes:
16. Overshoot: V (AC) < V + 0.85V (Pulse width less than t
/2); Undershoot V (AC) > -1.5V (Pulse width less than t
2).
IH
DD
TCYC
IL
TCYC/
17. Power-up: Assumes a linear ramp from 0V to V (Min.,) within 200ms. During this time V < V and V
< V
.
DD
IH
DD
DDQ
DD
18. All voltages referenced to ground.
19. Outputs are impedance controlled. IOH = -(V
20. Outputs are impedance controlled. I = (V
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
DDQ
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
OL
DDQ
21. V
(Min.) = 0.68V or 0.46V
, whichever is larger, V
(Max.) = 0.95V or 0.54V
, whichever is smaller.
REF
DDQ
REF
DDQ
Document #: 38-05563 Rev. *D
Page 20 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Capacitance[22]
Parameter
Description
Input Capacitance
Test Conditions
Max.
5.5
8.5
8
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
DD = 1.8V
VDDQ = 1.5V
V
CCLK
CO
Clock Input Capacitance
Output Capacitance
pF
pF
Thermal Resistance[22]
Parameter
Description
Test Conditions
FBGA
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51.
16.2
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
2.3
°C/W
AC Test Loads and Waveforms
V
REF = 0.75V
0.75V
VREF
VREF
0.75V
R = 50Ω
OUTPUT
[23]
ALL INPUT PULSES
1.25V
Z = 50Ω
0
OUTPUT
Device
R = 50Ω
L
0.75V
Under
Device
Under
0.25V
Test
5 pF
VREF = 0.75V
Slew Rate = 2 V/ns
ZQ
Test
ZQ
RQ =
RQ =
250Ω
250Ω
(a)
(b)
Notes:
22. Tested initially and after any design or process change that may affect these parameters.
23. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V
= 0.75V, RQ = 250Ω, V
= 1.5V, input
REF
DDQ
pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC Test Loads.
OL OH
Document #: 38-05563 Rev. *D
Page 21 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Switching Characteristics Over the Operating Range [23, 24]
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Cypress Consortium
Parameter Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tPOWER
VDD(Typical) to the first
Access[25]
1
–
1
–
1
–
1
–
1
–
8.4
–
ms
ns
ns
ns
ns
tCYC
tKH
tKHKH
tKHKL
tKLKH
tKHKH
K Clock and C Clock Cycle 3.30 5.25 3.60 5.25 4.0 6.3 5.0 7.9 6.0
Time
1.32
1.32
1.49
–
–
–
1.4
1.4
1.6
–
–
–
1.6
1.6
1.8
–
–
–
2.0
2.0
2.2
–
–
–
2.4
2.4
2.7
Input Clock (K/K and C/C)
HIGH
tKL
–
Input Clock (K/K and C/C)
LOW
tKHKH
–
K Clock Rise to K Clock Rise
and C to C Rise (rising edge
to rising edge)
tKHCH
tKHCH
0.00 1.45 0.0 1.55 0.0 1.8 0.0 2.2 0.0
2.7
ns
K/KClockRisetoC/CClockRise
(rising edge to rising edge)
Set-up Times
tSA
tAVKH
tIVKH
tIVKH
Address Set-up to K Clock
Rise
0.4
0.4
0.3
–
–
–
0.4
0.4
0.3
–
–
–
0.5
0.5
–
–
–
0.6
0.6
0.4
–
–
–
0.7
0.7
0.5
–
–
–
ns
ns
ns
tSC
Control Set-up to K Clock
Rise (LD, R/W)
tSCDDR
Double Data Rate Control
Set-up to Clock (K/K) Rise
(BWS0, BWS1, BWS2,
BWS3)
0.35
[26]
tSD
tDVKH
D[X:0] Set-up to Clock
(K/K) Rise
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Hold Times
tHA
tKHAX
tKHIX
tKHIX
Address Hold after K Clock 0.4
Rise
–
–
–
0.4
0.4
0.3
–
–
–
0.5
0.5
–
–
–
0.6
0.6
0.4
–
–
–
0.7
0.7
0.5
–
–
–
ns
ns
ns
tHC
Control Hold after K Clock
Rise (LD, R/W)
0.4
tHCDDR
Double Data Rate Control
Hold after Clock (K/K) Rise
(BWS0, BWS1, BWS2,
BWS3)
0.3
0.35
tHD
tKHDX
D[X:0] Hold after Clock
(K/K) Rise
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Output Times
tCO
tCHQV
–
0.45
–
–
0.45
–
–
0.45
–
–
0.45
–
–
0.50
–
ns
ns
ClockRise(or
clock mode) to Data Valid
insingle
K K
/
C/C
tDOH
tCHQX
Data Output Hold after
–0.45
–0.45
–0.45
–0.45
–0.50
Output
Clock Rise
C/C
(Active to Active)
tCCQO
tCHCQV
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
Clock Rise to Echo
Clock Valid
C/C
Notes:
24. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
25. This part has a voltage regulator internally; t
can be initiated.
is the time that the power needs to be supplied above V minimum initially before a read or write operation
DD
POWER
26. For DQ0 data signal on CY7C1527V18 device, t is 0.5ns for 200MHz, 250MHz, 278MHz and 300MHz frequencies.
SD
Document #: 38-05563 Rev. *D
Page 22 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Switching Characteristics Over the Operating Range (continued)[23, 24]
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Cypress Consortium
Parameter Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCQOH
tCQD
tCQDOH
tCHZ
tCHCQX
tCQHQV
tCQHQX
tCHQZ
–0.45
–
–
0.27
–
–0.45
–
–
0.27
–
–0.45
–
–
0.30
–
–0.45
–
–
0.35
–
–0.50
–
–
0.40
–
ns
ns
ns
ns
ns
Echo Clock Hold after
Clock Rise
C/C
Echo Clock High to Data
Valid
Echo Clock High to Data
Invalid
–0.27
–
–0.27
–
–0.30
–
–0.35
–
–0.40
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
–
Clock(Cand )RisetoHigh-Z
C
(Active to High-Z)[27, 28]
tCLZ
tCHQX1
–0.45
–0.45
–0.45
–0.45
–0.50
Clock (C and C) Rise to
Low-Z[27, 28]
DLL Timing
tKC Var
tKC Var
Clock Phase Jitter
–
0.20
–
–
0.20
–
–
0.20
–
–
0.20
–
–
0.20
–
ns
Cycles
ns
tKC lock
tKC Reset
tKC lock
DLL Lock Time (K, C)
K Static to DLL Reset
1024
30
1024
30
1024
30
1024
30
1024
30
tKC Reset
–
–
–
–
–
Notes:
27. t
, t
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
CHZ CLZ
28. At any given voltage and temperature t
is less than t
and t
less than t
.
CO
CHZ
CLZ
CHZ
Document #: 38-05563 Rev. *D
Page 23 of 28
[+] Feedback
CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Switching Waveforms[29, 30, 31]
READ
2
READ
3
NOP
4
NOP
5
WRITE
6
WRITE
7
READ
8
NOP
1
9
10
K
t
t
t
t
KHKH
KH
KL
CYC
K
LD
t
t
SC
HC
R/W
A
A0
A2
A3
A4
A1
t
HD
t
t
t
HD
SA
HA
t
t
SD
SD
DQ
Q00 Q01 Q10 Q11
D21 D30
Q40 Q41
D20
D31
t
CQDOH
t
t
KHCH
CLZ
t
t
CHZ
DOH
t
CO
t
CQD
C
t
t
t
t
t
KHKH
KHCH
KH
KL
CYC
C#
t
CCQO
t
CQOH
CQ
CQ#
t
CCQO
t
CQOH
DON’T CARE
UNDEFINED
Notes:
29. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
30. Output are disabled (High-Z) one clock cycle after a NOP.
31. In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document #: 38-05563 Rev. *D
Page 24 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
167 CY7C1516V18-167BZC
CY7C1527V18-167BZC
CY7C1518V18-167BZC
CY7C1520V18-167BZC
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Commercial
CY7C1516V18-167BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1527V18-167BZXC
CY7C1518V18-167BZXC
CY7C1520V18-167BZXC
CY7C1516V18-167BZI
CY7C1527V18-167BZI
CY7C1518V18-167BZI
CY7C1520V18-167BZI
CY7C1516V18-167BZXI
CY7C1527V18-167BZXI
CY7C1518V18-167BZXI
CY7C1520V18-167BZXI
200 CY7C1516V18-200BZC
CY7C1527V18-200BZC
CY7C1518V18-200BZC
CY7C1520V18-200BZC
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
Commercial
CY7C1516V18-200BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1527V18-200BZXC
CY7C1518V18-200BZXC
CY7C1520V18-200BZXC
CY7C1516V18-200BZI
CY7C1527V18-200BZI
CY7C1518V18-200BZI
CY7C1520V18-200BZI
CY7C1516V18-200BZXI
CY7C1527V18-200BZXI
CY7C1518V18-200BZXI
CY7C1520V18-200BZXI
250 CY7C1516V18-250BZC
CY7C1527V18-250BZC
CY7C1518V18-250BZC
CY7C1520V18-250BZC
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
Commercial
CY7C1516V18-250BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1527V18-250BZXC
CY7C1518V18-250BZXC
CY7C1520V18-250BZXC
Document #: 38-05563 Rev. *D
Page 25 of 28
[+] Feedback
CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
250 CY7C1516V18-250BZI
CY7C1527V18-250BZI
CY7C1518V18-250BZI
CY7C1520V18-250BZI
CY7C1516V18-250BZXI
CY7C1527V18-250BZXI
CY7C1518V18-250BZXI
CY7C1520V18-250BZXI
278 CY7C1516V18-278BZC
CY7C1527V18-278BZC
CY7C1518V18-278BZC
CY7C1520V18-278BZC
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
Commercial
Industrial
CY7C1516V18-278BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1527V18-278BZXC
CY7C1518V18-278BZXC
CY7C1520V18-278BZXC
CY7C1516V18-278BZI
CY7C1527V18-278BZI
CY7C1518V18-278BZI
CY7C1520V18-278BZI
CY7C1516V18-278BZXI
CY7C1527V18-278BZXI
CY7C1518V18-278BZXI
CY7C1520V18-278BZXI
300 CY7C1516V18-300BZC
CY7C1527V18-300BZC
CY7C1518V18-300BZC
CY7C1520V18-300BZC
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Commercial
CY7C1516V18-300BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1527V18-300BZXC
CY7C1518V18-300BZXC
CY7C1520V18-300BZXC
CY7C1516V18-300BZI
CY7C1527V18-300BZI
CY7C1518V18-300BZI
CY7C1520V18-300BZI
CY7C1516V18-300BZXI
CY7C1527V18-300BZXI
CY7C1518V18-300BZXI
CY7C1520V18-300BZXI
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
Document #: 38-05563 Rev. *D
Page 26 of 28
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Package Diagram
165-ball FBGA (15 x 17 x 1.40 mm) (51-85195)
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51-85195-*A
DDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and
Samsung technology. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05563 Rev. *D
Page 27 of 28
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Document History Page
DocumentTitle:CY7C1516V18/CY7C1527V18/CY7C1518V18/CY7C1520V1872-MbitDDR-IISRAM2-Word
Burst Architecture
Document Number: 38-05563
Orig. of
REV.
**
ECN No. Issue Date Change
Description of Change
226981
257089
See ECN
See ECN
DIM
NJY
New Data Sheet
*A
Modified ID code for the x9 option in the JTAG ID Register Definitions table on
page 21
Included thermal values
Modified capacitance values table: included capacitance values for x8, x18 and
x36 options
*B
319496
See ECN
SYT
Removed CY7C1527V18 from the title
Included 300-MHz Speed Bin
Added footnote #1 and accordingly edited the VSS/144M And VSS/288M on the
Pin Definitions table
Added Industrial Temperature Grade
Replaced TBDs for IDD and ISB1 for 300 MHz, 250 MHz, 200 MHz and 167 MHz
speed grades
Changed the CIN from 5 pF to 5.5 pF and CO from 7 pF to 8 pF in the
Capacitance Table
Removed the capacitance value column for the x9 option from Capacitance Table
Changed typo of bit # 47 to bit # 108 under the EXTEST OUTPUT BUS
TRI-STATE on Page 17
Added lead-free product information
Updated the Ordering Information by Shading and unshading as per availability
*C
403231
See ECN
ZSD
Converted from Preliminary to Final
Added CY7C1527V18 part number to the title
Included 278-MHz Speed Bin
Changed C/C Pin Description in the features section and Pin Description
Changed the address of Cypress Semiconductor Corporation on Page#1 from
“3901 North First Street” to “198 Champion Court”
Added power-up sequence details and waveforms
Added foot notes #14, 15, 16 on page# 19
Replaced Three-state with Tri-state
Changed the description of IX from Input Load Current to Input Leakage Current
on page# 20
Modified the IDD and ISB1 values for different speed bins
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated the Ordering Information table
*D
467290
See ECN
NXR
Modified the ZQ Definition from Alternately this pin can be connected directly to
VDD to Alternately, this pin can be connected directly to VDDQ
Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND
Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD
Changed tTCYC from 100 ns to 50 ns, changed tTH and tTL from 40 ns to 20 ns,
changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from10 ns to 5 ns and changed tTDOV
from 20 ns to 10 ns in TAP AC Switching Characteristics table
Modified Power-Up waveform
Changed the Maximum rating of Ambient Temperature with Power Applied from
–10°C to +85°C to –55°C to +125°C
Added additional notes in the AC parameter section
Modified AC Switching Waveform
Corrected the typo In the AC Switching Characteristics Table
Updated the Ordering Information Table
Document #: 38-05563 Rev. *D
Page 28 of 28
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