CY7C1576KV18-450BZC [CYPRESS]
72-Mbit QDR-II+ SRAM 4-Word Burst Architecture; 72 - Mbit的QDR -II SRAM + 4字突发架构型号: | CY7C1576KV18-450BZC |
厂家: | CYPRESS |
描述: | 72-Mbit QDR-II+ SRAM 4-Word Burst Architecture |
文件: | 总28页 (文件大小:813K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
72-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
Features
Configurations
■ Separate Independent Read and Write Data Ports
❐ Supports concurrent transactions
With Read Cycle Latency of 2.5 cycles:
CY7C1561KV18 – 8M x 8
■ 550 MHz Clock for High Bandwidth
CY7C1576KV18 – 8M x 9
CY7C1563KV18 – 4M x 18
CY7C1565KV18 – 2M x 36
■ 4-word Burst for Reducing Address Bus Frequency
■ Double Data Rate (DDR) Interfaces on both Read and Write
Ports (data transferred at 1100 MHz) at 550 MHz
Functional Description
■ Available in 2.5 Clock Cycle Latency
The CY7C1561KV18, CY7C1576KV18, CY7C1563KV18, and
CY7C1565KV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II+ architecture. Similar to QDR-II archi-
tecture, QDR-II+ architecture consists of two separate ports: the
read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR-II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turnaround” the
data bus that exists with common I/O devices. Each port is
accessed through a common address bus. Addresses for read
and write addresses are latched on alternate rising edges of the
input (K) clock. Accesses to the QDR-II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 8-bit
words (CY7C1561KV18), 9-bit words (CY7C1576KV18), 18-bit
words (CY7C1563KV18), or 36-bit words (CY7C1565KV18) that
burst sequentially into or out of the device. Because data is trans-
ferred into and out of the device on every rising edge of both input
clocks (K and K), memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turnarounds”.
■ Two Input Clocks (K and K) for precise DDR Timing
❐ SRAM uses rising edges only
■ Echo Clocks (CQ and CQ) simplify Data Capture inHigh Speed
Systems
■ Data Valid Pin (QVLD) to indicate Valid Data on the Output
■ Single Multiplexed Address Input Bus latches Address Inputs
for Read and Write Ports
■ Separate Port selects for Depth Expansion
■ Synchronous Internally Self-timed Writes
■ QDR™-II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
■ OperatessimilartoQDR-IDevicewithoneCycleReadLatency
when DOFF is asserted LOW
■ Available in x8, x9, x18, and x36 Configurations
■ Full Data Coherency, providing Most Current Data
[1]
■ Core VDD = 1.8V± 0.1V; I/O VDDQ = 1.4V to VDD
❐ Supports both 1.5V and 1.8V I/O supply
■ HSTL Inputs and Variable Drive HSTL Output Buffers
■ Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free Packages
■ JTAG 1149.1 compatible Test Access Port
■ Phase-Locked Loop (PLL) for Accurate Data Placement
Table 1. Selection Guide
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Description
Maximum Operating Frequency
Maximum Operating Current
550 MHz
500 MHz
500
450 MHz
450
400 MHz
400
Unit
MHz
mA
550
900
900
920
1310
x8
x9
830
760
690
830
760
690
x18
x36
850
780
710
1210
1100
1000
Note
1. The Cypress QDR-II+ devices surpass the QDR consortium specification and can support V
= 1.4V to V
.
DD
DDQ
Cypress Semiconductor Corporation
Document Number: 001-15878 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 03, 2009
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Logic Block Diagram (CY7C1561KV18)
8
D
[7:0]
Write Write Write Write
21
Address
Register
A
Reg
Reg
Reg
Reg
(20:0)
21
Address
Register
A
(20:0)
RPS
K
Control
Logic
CLK
Gen.
K
DOFF
Read Data Reg.
CQ
CQ
32
16
V
REF
8
8
8
8
Reg.
Reg.
Reg.
Control
Logic
WPS
NWS
8
16
Q
[7:0]
[1:0]
QVLD
Logic Block Diagram (CY7C1576KV18)
9
D
[8:0]
Write Write Write Write
21
Address
Register
A
Reg
Reg
Reg
Reg
(20:0)
21
Address
Register
A
(20:0)
RPS
K
Control
Logic
CLK
Gen.
K
DOFF
Read Data Reg.
CQ
CQ
36
18
V
REF
9
9
9
9
Reg.
Reg.
Reg.
Control
Logic
WPS
BWS
9
18
Q
[8:0]
[0]
QVLD
Document Number: 001-15878 Rev. *E
Page 2 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Logic Block Diagram (CY7C1563KV18)
18
D
[17:0]
Write Write Write Write
20
Address
Register
A
Reg
Reg
Reg
Reg
(19:0)
20
Address
Register
A
(19:0)
RPS
K
Control
Logic
CLK
Gen.
K
DOFF
Read Data Reg.
CQ
CQ
72
36
V
REF
18
18
18
18
Reg.
Reg.
Reg.
Control
Logic
WPS
BWS
18
36
Q
[17:0]
[1:0]
QVLD
Logic Block Diagram (CY7C1565KV18)
36
D
[35:0]
Write Write Write Write
19
Address
Register
A
Reg
Reg
Reg
Reg
(18:0)
19
Address
Register
A
(18:0)
RPS
K
Control
Logic
CLK
Gen.
K
DOFF
Read Data Reg.
CQ
CQ
144
72
V
REF
36
36
36
36
Reg.
Reg.
Reg.
Control
Logic
WPS
BWS
36
72
Q
[35:0]
[3:0]
QVLD
Document Number: 001-15878 Rev. *E
Page 3 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Pin Configuration
The pin configurations for CY7C1561KV18, CY7C1576KV18, CY7C1563KV18, and CY7C1565KV18 follow.[2]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1561KV18 (8M x 8)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
3
A
4
5
NWS1
NC/288M
A
6
K
7
NC/144M
NWS0
A
8
9
A
10
A
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
A
B
C
D
E
F
WPS
A
RPS
A
NC
NC
D4
NC
NC
NC
Q4
NC
Q5
VDDQ
NC
NC
D6
NC
NC
Q7
A
K
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
NC
NC
D2
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
NC
NC
D5
NC
NC
VREF
Q1
G
H
J
VREF
NC
NC
Q6
NC
D7
K
L
NC
NC
NC
NC
NC
TMS
M
N
P
R
NC
TCK
A
QVLD
NC
A
A
A
A
A
CY7C1576KV18 (8M x 9)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
3
A
4
5
NC
6
K
7
NC/144M
BWS0
A
8
9
A
10
A
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
A
B
C
D
E
F
WPS
A
RPS
A
NC
NC
D5
NC
NC
NC
Q5
NC
Q6
VDDQ
NC
NC
D7
NC
NC
Q8
A
NC/288M
A
K
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
NC
NC
D3
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
NC
NC
D6
NC
NC
VREF
Q2
G
H
J
VREF
NC
NC
Q7
NC
D8
K
L
NC
NC
NC
NC
D0
M
N
P
R
NC
TCK
A
QVLD
NC
A
A
A
A
A
TMS
Note
2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-15878 Rev. *E
Page 4 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Pin Configuration
The pin configurations for CY7C1561KV18, CY7C1576KV18, CY7C1563KV18, and CY7C1565KV18 follow.[2] (continued)
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1563KV18 (4M x 18)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
Q9
3
4
5
BWS1
NC
A
6
K
7
NC/288M
BWS0
A
8
9
A
10
A
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
A
WPS
A
RPS
A
D9
K
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
Q7
NC
D6
NC
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
D11
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
Q12
D13
VREF
NC
NC
NC
VREF
Q4
D3
G
H
J
K
L
NC
Q15
NC
NC
Q1
NC
D0
M
N
P
R
D17
NC
A
QVLD
NC
A
TCK
A
A
A
A
TMS
CY7C1565KV18 (2M x 36)
1
2
NC/288M
Q18
Q28
D20
3
4
5
BWS2
BWS3
A
6
K
7
BWS1
BWS0
A
8
9
10
NC/144M
Q17
Q7
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
CQ
A
WPS
A
RPS
A
A
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
D18
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
D25
Q25
Q26
A
K
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
D15
D6
D29
Q21
D22
Q14
D13
VREF
Q4
G
H
J
VREF
Q31
D32
K
L
D3
Q24
Q34
D26
Q11
Q1
M
N
P
R
D9
D35
A
QVLD
NC
A
D0
TCK
A
A
A
A
A
TMS
Document Number: 001-15878 Rev. *E
Page 5 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Pin Definitions
Pin Name
I/O
Pin Description
Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active.
D[x:0]
Input-
Synchronous CY7C1561KV18 − D[7:0]
CY7C1576KV18 − D[8:0]
CY7C1563KV18 − D[17:0]
CY7C1565KV18 − D[35:0]
WPS
Input-
Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0]
.
NWS0,
NWS1,
Input-
Nibble Write Select 0, 1 − Active LOW (CY7C1561KV18 Only). Sampled on the rising edge of the K
. Used to select which nibble is written into the device
Synchronous and K clocks
when write operations are active
during the current portion of the write operations.
All the Nibble Write Selects are sampled on the same ed0ge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device
NWS controls D[3:0] and NWS1 controls D[7:4]
.
.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks when
Synchronous write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C1576KV18 − BWS0 controls D[8:0]
CY7C1563KV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1565KV18 − BWS0 controls D[8:0], BWS1 controls D[17:9]
BWS2 controls D[26:18] and BWS3 controls D[35:27].
,
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device
.
A
Input-
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as
8M x 8 (4 arrays each of 2M x 8) for CY7C1561KV18, 8M x 9 (4 arrays each of 2M x 9) for CY7C1576KV18,
4M x 18 (4 arrays each of 1M x 18) for CY7C1563KV18 and 2M x 36 (4 arrays each of 512K x 36) for
CY7C1565KV18. Therefore, only 21 address inputs are needed to access the entire memory array of
CY7C1561KV18 and CY7C1576KV18, 20 address inputs for CY7C1563KV18 and 19 address inputs for
CY7C1565KV18. These inputs are ignored when the appropriate port is deselected.
Q[x:0]
Outputs-
Data Output Signals. These pins drive out the requested data when the read operation is active. Valid
Synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the
read port, Q[x:0] are automatically tristated.
CY7C1561KV18 − Q[7:0]
CY7C1576KV18 − Q[8:0]
CY7C1563KV18 − Q[17:0]
CY7C1565KV18 − Q[35:0]
RPS
Input-
Read Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tristated following the next rising edge of the
K clock. Each read access consists of a burst of four sequential transfers.
QVLD
K
Valid output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
K
Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0]
.
CQ
CQ
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR-II+. The timings for the echo clocks are shown in the Switching Characteristics on page 23.
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR-II+.The timings for the echo clocks are shown in the Switching Characteristics on page 23.
Document Number: 001-15878 Rev. *E
Page 6 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Pin Definitions (continued)
Pin Name
I/O
Pin Description
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
PLL Turn Off − Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in QDR-I
mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167
MHz with QDR-I timing.
TDO
Output
Input
Input
Input
N/A
TDO for JTAG
TCK
TCK Pin for JTAG
TDI
TDI Pin for JTAG
TMS
TMS Pin for JTAG
NC
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
NC/144M
NC/288M
VREF
N/A
N/A
Input-
Reference measurement points.
VDD
VSS
Power Supply Power Supply Inputs to the Core of the Device
Ground
Ground for the Device
VDDQ
Power Supply Power Supply Inputs for the Outputs of the Device
Document Number: 001-15878 Rev. *E
Page 7 of 28
[+] Feedback
CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
clock rise. Doing so pipelines the data flow such that data is
transferred out of the device on every rising edge of the input
clocks (K and K).
Functional Overview
The CY7C1561KV18, CY7C1576KV18, CY7C1563KV18,
CY7C1565KV18 are synchronous pipelined Burst SRAMs
equipped with a read port and a write port. The read port is
dedicated to read operations and the write port is dedicated to
write operations. Data flows into the SRAM through the write port
and flows out through the read port. These devices multiplex the
address inputs to minimize the number of address pins required.
By having separate read and write ports, the QDR-II+ completely
eliminates the need to “turnaround” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of four 8-bit data transfers in the case of
CY7C1561KV18, four 9-bit data transfers in the case of
CY7C1576KV18, four 18-bit data transfers in the case of
CY7C1563KV18, and four 36-bit data transfers in the case of
CY7C1565KV18, in two clock cycles.
When the read port is deselected, the CY7C1563KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the outputs following the next
rising edge of the negative input clock (K). This enables for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
clock rise the data presented to D[17:0] is latched and stored into
the lower 18-bit write data register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K) the information presented to D[17:0] is also stored
into the write data register, provided BWS[1:0] are both asserted
active. This process continues for one more cycle until four 18-bit
words (a total of 72 bits) of data are stored in the SRAM. The 72
bits of data are then written into the memory array at the specified
location. Therefore, write accesses to the device can not be
initiated on two consecutive K clock rises. The internal logic of
the device ignores the second write request. Write accesses can
be initiated on every other rising edge of the positive input clock
(K). Doing so pipelines the data flow such that 18 bits of data can
be transferred into the device on every rising edge of the input
clocks (K and K).
These devices operate with a read latency of two and half cycles
when DOFF pin is tied HIGH. When DOFF pin is set LOW or
connected to VSS then device behaves in QDR-I mode with a
read latency of one clock cycle.
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input and output timing are referenced from
the rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) outputs pass through output registers controlled
by the rising edge of the input clocks (K and K) as well.
When deselected, the write port ignores all inputs after the
pending write operations have been completed.
All synchronous control (RPS, WPS, NWS[x:0], BWS[x:0]) inputs
pass through input registers controlled by the rising edge of the
input clocks (K and K).
Byte Write Operations
CY7C1563KV18 is described in the following sections. The
same basic descriptions apply to CY7C1561KV18,
CY7C1576KV18 and CY7C1565KV18.
Byte write operations are supported by the CY7C1563KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read, modify, or write operations to a byte write
operation.
Read Operations
The CY7C1563KV18 is organized internally as four arrays of 1M
x 18. Accesses are completed in a burst of four sequential 18-bit
data words. Read operations are initiated by asserting RPS
active at the rising edge of the positive input clock (K). The
address presented to the address inputs is stored in the read
address register. Following the next two K clock rise, the corre-
sponding lowest order 18-bit word of data is driven onto the
Q[17:0] using K as the output timing reference. On the subse-
quent rising edge of K, the next 18-bit data word is driven onto
the Q[17:0]. This process continues until all four 18-bit data words
have been driven out onto Q[17:0]. The requested data is valid
0.45 ns from the rising edge of the input clock (K or K). To
maintain the internal logic, each read access must be allowed to
complete. Each read access consists of four 18-bit data words
and takes two clock cycles to complete. Therefore, read
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device ignores the second
read request. Read accesses can be initiated on every other K
Concurrent Transactions
The read and write ports on the CY7C1563KV18 operates
completely independently of one another. As each port latches
the address inputs on different clock edges, the user can read or
write to any location, regardless of the transaction on the other
port. If the ports access the same location when a read follows
a write in successive clock cycles, the SRAM delivers the most
recent information associated with the specified address
location. This includes forwarding data from a write cycle that
was initiated on the previous K clock rise.
Document Number: 001-15878 Rev. *E
Page 8 of 28
[+] Feedback
CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Read access and write access must be scheduled such that one
transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on the
previous state of the SRAM. If both ports are deselected, the
read port takes priority. If a read was initiated on the previous
cycle, the write port takes priority (as read operations cannot be
initiated on consecutive cycles). If a write was initiated on the
previous cycle, the read port takes priority (as write operations
can not be initiated on consecutive cycles). Therefore, asserting
both port selects active from a deselected state results in alter-
nating read or write operations being initiated, with the first
access being a read.
Echo Clocks
Echo clocks are provided on the QDR-II+ to simplify data capture
on high-speed systems. Two echo clocks are generated by the
QDR-II+. CQ is referenced with respect to K and CQ is refer-
enced with respect to K. These are free running clocks and are
synchronized to the input clock of the QDR-II+. The timing for the
echo clocks is shown in the Switching Characteristics on page
23.
Valid Data Indicator (QVLD)
QVLD is provided on the QDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the QDR-II+ device
along with data output. This signal is also edge-aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
Depth Expansion
The CY7C1563KV18 has a port select input for each port. This
enables for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
PLL
These chips use a PLL that is designed to function between 120
MHz and the specified maximum clock frequency. During power
up, when the DOFF is tied HIGH, the PLL is locked after 20 μs
of stable clock. The PLL can also be reset by slowing or stopping
the input clocks K and K for a minimum of 30 ns. However, it is
not necessary to reset the PLL to lock to the desired frequency.
The PLL automatically locks 20 μs after a stable clock is
presented. The PLL may be disabled by applying ground to the
DOFF pin. When the PLL is turned off, the device behaves in
QDR-I mode (with one cycle latency and a longer access time).
For information, refer to the application note, PLL Considerations
in QDRII/DDRII/QDRII+/DDRII+.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5X the value of the
intended line impedance driven by the SRAM, the allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Application Example
Figure 1 shows two QDR-II+ used in an application.
Figure 1. Application Example
RQ = 250 ohms
RQ = 250 ohms
ZQ
ZQ
SRAM #2
SRAM #1
Vt
CQ/CQ
Q
K
K
CQ/CQ
Q
D
D
A
R
BWS
A RPS WPS
K
K
BWS
RPS WPS
DATA IN
DATA OUT
Address
R
R
Vt
Vt
RPS
BUS MASTER
WPS
BWS
(CPU or ASIC)
CLKIN1/CLKIN1
CLKIN2/CLKIN2
Source K
Source K
R = 50ohms, Vt = V
/2
R
DDQ
Document Number: 001-15878 Rev. *E
Page 9 of 28
[+] Feedback
CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Truth Table
The truth table for CY7C1561KV18, CY7C1576KV18, CY7C1563KV18, and CY7C1565KV18 follows. [3, 4, 5, 6, 7, 8]
Operation
Write Cycle:
K
RPS WPS
DQ
DQ
DQ
DQ
L-H
H [9] L [10] D(A) at K(t + 1)↑ D(A + 1) at K(t + 1)↑ D(A + 2) at K(t + 2)↑ D(A + 3) at K(t + 2)↑
Load address on the rising
edge of K; input write data
on two consecutive K and
K rising edges.
Read Cycle:
L-H
L-H
L [10]
X
Q(A) at K(t + 2)↑ Q(A + 1) at K(t + 3)↑ Q(A + 2) at K(t + 3)↑ Q(A + 3) at K(t + 4)↑
(2.5 cycle Latency)
Load address on the rising
edge of K; wait two and
half cycles; read data on
two consecutive K and K
rising edges.
NOP: No Operation
H
X
H
X
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
Standby: Clock Stopped Stopped
Previous State
Previous State
Previous State
Previous State
Write Cycle Descriptions
The write cycle description table for CY7C1561KV18 and CY7C1563KV18 follows. [3, 11]
BWS0/ BWS1/
K
Comments
K
NWS0 NWS1
L
L
L–H
–
During the data portion of a write sequence:
CY7C1561KV18 − both nibbles (D[7:0]) are written into the device.
CY7C1563KV18 − both bytes (D[17:0]) are written into the device.
L
L
–
L–H
–
L-H During the data portion of a write sequence:
CY7C1561KV18 − both nibbles (D[7:0]) are written into the device.
CY7C1563KV18 − both bytes (D[17:0]) are written into the device.
L
H
H
L
–
During the data portion of a write sequence:
CY7C1561KV18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1563KV18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
L–H During the data portion of a write sequence:
CY7C1561KV18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1563KV18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H
H
L–H
–
–
During the data portion of a write sequence:
CY7C1561KV18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1563KV18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L
L–H During the data portion of a write sequence:
CY7C1561KV18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1563KV18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
H
H
H
L–H
–
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Notes
3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge.
4. Device powers up deselected with the outputs in a tristate condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
8. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
9. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
10. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
second read or write request.
11. Is based on a write cycle that was initiated in accordance with Table . NWS , NWS , BWS , BWS , BWS , and BWS can be altered on different portions of a write
0
1
0
1
2
3
cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-15878 Rev. *E
Page 10 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Write Cycle Descriptions
The write cycle description table for CY7C1576KV18 follows. [3, 11]
BWS0
K
L–H
–
K
Comments
During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L
L
–
L–H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
H
H
L–H
–
–
Write Cycle Descriptions
The write cycle description table for CY7C1565KV18 follows. [3, 11]
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L–H
–
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H
H
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H
H
H
H
H
H
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Document Number: 001-15878 Rev. *E
Page 11 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Instruction Register
IEEE 1149.1 Serial Boundary Scan (JTAG)
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 15. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternatively
be connected to VDD through a pull up resistor. TDO must be left
unconnected. Upon power up, the device comes up in a reset
state, which does not interfere with the operation of the device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
Test Mode Select (TMS)
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up inter-
nally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see TAP Controller State
Diagram on page 14. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
The section Boundary Scan Order on page 18 shows the order
in which the bits are connected. Each bit corresponds to one of
the bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
Test Data-Out (TDO)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 17.
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 17).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high-Z state.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 17. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
TAP Registers
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document Number: 001-15878 Rev. *E
Page 12 of 28
[+] Feedback
CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
IDCODE
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The advantage
of the BYPASS instruction is that it shortens the boundary scan
path when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High-Z state until the next command is supplied during the
Update IR state.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The TAP controller clock can only operate at a frequency up to
20 MHz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR state, an
input or output undergoes a transition. The TAP may then try to
capture a signal while in transition (metastable state). This does
not harm the device, but there is no guarantee as to the value
that is captured. Repeatable results may not be possible.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tristate,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High-Z condition.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the Shift-DR state. During Update-DR, the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is preset HIGH
to enable the output when the device is powered up, and also
when the TAP controller is in the Test-Logic-Reset state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-15878 Rev. *E
Page 13 of 28
[+] Feedback
CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
TAP Controller State Diagram
The state diagram for the TAP controller follows. [12]
TEST-LOGIC
1
RESET
0
1
1
1
SELECT
TEST-LOGIC/
SELECT
0
IR-SCAN
IDLE
DR-SCAN
0
0
1
1
CAPTURE-DR
0
CAPTURE-IR
0
0
1
0
1
SHIFT-DR
1
SHIFT-IR
1
EXIT1-DR
0
EXIT1-IR
0
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-IR
0
UPDATE-DR
1
1
0
Note
12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-15878 Rev. *E
Page 14 of 28
[+] Feedback
CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
2
1
1
1
0
0
0
Selection
Circuitry
Selection
Circuitry
TDI
TDO
Instruction Register
31 30
29
.
.
2
Identification Register
.
108
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
Over the Operating Range [13, 14, 15]
Parameter
VOH1
Description
Output HIGH Voltage
Test Conditions
IOH = −2.0 mA
IOH = −100 μA
IOL = 2.0 mA
Min
1.4
1.6
Max
Unit
V
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
0.4
0.2
V
IOL = 100 μA
V
0.65VDD VDD + 0.3
V
VIL
Input LOW Voltage
–0.3
–5
0.35VDD
5
V
IX
Input and Output Load Current
GND ≤ VI ≤ VDD
μA
Notes
13. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
14. Overshoot: V (AC) < V + 0.35V (Pulse width less than t /2).
/2), Undershoot: V (AC) > −0.3V (Pulse width less than t
IH
DDQ
CYC
IL
CYC
15. All Voltage referenced to Ground.
Document Number: 001-15878 Rev. *E
Page 15 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
TAP AC Switching Characteristics
Over the Operating Range [16, 17]
Parameter
Description
Min
Max
Unit
ns
tTCYC
TCK Clock Cycle Time
50
tTF
TCK Clock Frequency
TCK Clock HIGH
TCK Clock LOW
20
MHz
ns
tTH
20
20
tTL
ns
Setup Times
tTMSS
tTDIS
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Capture Hold after Clock Rise
Output Times
tTDOV
tTDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
10
ns
ns
0
TAP Timing and Test Conditions
Figure 2 shows the TAP timing and test conditions. [17]
Figure 2. TAP Timing and Test Conditions
0.9V
ALL INPUT PULSES
0.9V
1.8V
50Ω
TDO
0V
Z = 50
Ω
0
C = 20 pF
L
tTL
tTH
GND
(a)
Test Clock
TCK
tTCYC
tTMSH
tTMSS
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Notes
16. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
17. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document Number: 001-15878 Rev. *E
Page 16 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Identification Register Definitions
Value
Instruction Field
Description
CY7C1561KV18
CY7C1576KV18
CY7C1563KV18
000
CY7C1565KV18
Revision Number
(31:29)
000
000
000
Version number.
Cypress Device ID 11010010001000100 11010010001001100 11010010001010100 11010010001100100 Defines the type of
(28:12)
SRAM.
Cypress JEDEC ID
(11:1)
00000110100
1
00000110100
1
00000110100
1
00000110100
1
Allows unique
identification of
SRAM vendor.
ID Register
Presence (0)
Indicates the
presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
Bypass
3
1
ID
32
109
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the input and output ring contents. Places the boundary scan register between
TDI and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-15878 Rev. *E
Page 17 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Boundary Scan Order
Bit #
0
Bump ID
6R
Bit #
Bump ID
10G
9G
Bit #
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Bump ID
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
Bit #
84
Bump ID
1J
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
1
6P
85
2J
2
6N
11F
11G
9F
86
3K
3
7P
87
3J
4
7N
88
2K
5
7R
10F
11E
10E
10D
9E
89
1K
6
8R
90
2L
7
8P
91
3L
8
9R
92
1M
1L
9
11P
10P
10N
9P
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
10C
11D
9C
94
3N
95
3M
1N
96
10M
11N
9M
9D
97
2M
3P
11B
11C
9B
98
99
2N
9N
100
101
102
103
104
105
106
107
108
2P
11L
11M
9L
10B
11A
10A
9A
1P
3R
4R
10L
11K
10K
9J
4P
8B
5P
7C
3F
5N
6C
1G
1F
5R
9K
8A
Internal
10J
11J
11H
7A
3G
2G
1H
7B
6B
Document Number: 001-15878 Rev. *E
Page 18 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
PLL Constraints
Power Up Sequence in QDR-II+ SRAM
■ PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var
QDR-II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
.
■ The PLL functions at frequencies down to 120 MHz.
Power Up Sequence
■ If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20 μs of stable clock to
relock to the desired clock frequency.
■ Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐ Apply VDD before VDDQ
.
❐ Apply VDDQ before VREF or at the same time as VREF
.
❐ Drive DOFF HIGH.
■ Provide stable DOFF (HIGH), power and clock (K, K) for 20 μs
to lock the PLL.
Power Up Waveforms
K
K
Unstable Clock
> 20Ps Stable clock
Stable)
DDQ
Start Normal
Operation
/
V
Clock Start (Clock Starts after V
DD
Stable (< +/- 0.1V DC per 50ns )
/
/
V
VDDQ
V
VDD
DD
DDQ
Fix HIGH (or tie to V
)
DDQ
DOFF
Document Number: 001-15878 Rev. *E
Page 19 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V
Latch up Current.................................................... > 200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied.. –55°C to +125°C
Supply Voltage on VDD Relative to GND ........–0.5V to +2.9V
Supply Voltage on VDDQ Relative to GND...... –0.5V to +VDD
DC Applied to Outputs in High-Z ........–0.5V to VDDQ + 0.3V
DC Input Voltage [14]..............................–0.5V to VDD + 0.3V
Operating Range
Ambient
Temperature (TA)
[18]
[18]
Range
VDD
VDDQ
Commercial
Industrial
0°C to +70°C
1.8 ± 0.1V
1.4V to
VDD
–40°C to +85°C
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range [15]
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min
1.7
Typ
Max
1.9
Unit
1.8
1.5
V
V
VDDQ
VOH
1.4
VDD
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Note 19
Note 20
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
VSS
VDDQ/2 + 0.12
VDDQ/2 + 0.12
VDDQ
0.2
V
VOL
V
VOH(LOW)
VOL(LOW)
VIH
IOH = −0.1 mA, Nominal Impedance
V
IOL = 0.1 mA, Nominal Impedance
V
VREF + 0.1
–0.15
VDDQ + 0.15
VREF – 0.1
2
V
VIL
V
IX
Input Leakage Current
Output Leakage Current
Input Reference Voltage [21] Typical Value = 0.75V
GND ≤ VI ≤ VDDQ
−2
μA
μA
V
IOZ
GND ≤ VI ≤ VDDQ, Output Disabled
−2
2
VREF
0.68
0.75
0.95
[22]
VDD Operating Supply
VDD = Max,
OUT = 0 mA,
f = fMAX = 1/tCYC
550 MHz (x8)
(x9)
900
mA
IDD
I
900
(x18)
920
(x36)
1310
830
500 MHz (x8)
(x9)
mA
mA
mA
830
(x18)
850
(x36)
1210
760
450 MHz (x8)
(x9)
760
(x18)
780
(x36)
1100
690
400 MHz (x8)
(x9)
690
(x18)
710
(x36)
1000
Notes
18. Power up: Assumes a linear ramp from 0V to V (min) within 200 ms. During this time V < V and V
< V
.
DD
DD
IH
DD
DDQ
19. Output are impedance controlled. I = −(V
/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.
/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.
OH
DDQ
20. Output are impedance controlled. I = (V
OL
DDQ
21. V
(min) = 0.68V or 0.46V
, whichever is larger, V
(max) = 0.95V or 0.54V
, whichever is smaller.
DDQ
REF
DDQ
REF
22. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-15878 Rev. *E
Page 20 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Electrical Characteristics (continued)
DC Electrical Characteristics
Over the Operating Range [15]
Parameter
Description
Test Conditions
Min
Typ
Max
380
380
380
380
360
360
360
360
340
340
340
340
320
320
320
320
Unit
ISB1
Automatic Power down
Current
Max VDD
,
550 MHz (x8)
(x9)
mA
Both Ports Deselected,
VIN ≥ VIH or VIN ≤ VIL
(x18)
f = fMAX = 1/tCYC
Inputs Static
,
(x36)
500 MHz (x8)
(x9)
mA
mA
mA
(x18)
(x36)
450 MHz (x8)
(x9)
(x18)
(x36)
400 MHz (x8)
(x9)
(x18)
(x36)
AC Electrical Characteristics
Over the Operating Range [14]
Parameter
Description
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min
VREF + 0.2
–0.24
Typ
–
Max
Unit
V
VIH
VIL
VDDQ + 0.24
VREF – 0.2
–
V
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V
Max
2
Unit
pF
CIN
CO
3
pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
165 FBGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and procedures
for measuring thermal impedance, in accordance with
EIA/JESD51.
13.7
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
3.73
°C/W
Document Number: 001-15878 Rev. *E
Page 21 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Figure 3. AC Test Loads and Waveforms
VREF = 0.75V
0.75V
VREF
VREF
0.75V
R = 50Ω
OUTPUT
[23]
ALL INPUT PULSES
1.25V
Z = 50Ω
0
OUTPUT
Device
Under
Test
R = 50Ω
L
0.75V
Device
Under
0.25V
5 pF
VREF = 0.75V
Slew Rate = 2 V/ns
ZQ
Test
ZQ
RQ =
RQ =
250Ω
250Ω
INCLUDING
JIG AND
SCOPE
(a)
(b)
Note
23. Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, V
= 1.5V, input
DDQ
pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 3.
OL OH
Document Number: 001-15878 Rev. *E
Page 22 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Switching Characteristics
Over the Operating Range [23, 24]
550 MHz
500 MHz
450 MHz
400 MHz
Cypress Consortium
Parameter Parameter
Description
Unit
Min Max Min Max Min Max Min Max
tPOWER
tCYC
tKH
VDD(Typical) to the First Access [25]
K Clock Cycle Time
1
1
1
1
ms
ns
ns
ns
ns
tKHKH
tKHKL
tKLKH
tKHKH
1.81 8.4 2.0 8.4 2.2 8.4 2.5 8.4
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
Input Clock (K/K) HIGH
Input Clock (K/K) LOW
tKL
tKHKH
0.77
0.85
0.94
1.06
K Clock Rise to K Clock Rise
(rising edge to rising edge)
Setup Times
tSA
tAVKH
tIVKH
tIVKH
Address Setup to K Clock Rise
0.23
0.23
–
–
–
0.25
0.25
0.20
–
–
–
0.275
0.275
0.22
–
–
–
0.4
0.4
–
–
–
ns
ns
ns
tSC
Control Setup to K Clock Rise (RPS, WPS)
tSCDDR
Double Data Rate Control Setup to Clock (K/K) 0.18
Rise (BWS0, BWS1, BWS2, BWS3)
0.28
tSD
tDVKH
0.18
–
0.20
–
0.22
–
0.28
–
ns
D[X:0] Setup to Clock (K/K) Rise
Hold Times
tHA
tKHAX
tKHIX
tKHIX
0.23
0.23
–
–
–
0.25
0.25
0.20
–
–
–
0.275
0.275
0.28
–
–
–
0.4
0.4
–
–
–
ns
ns
ns
Address Hold after K Clock Rise
tHC
Control Hold after K Clock Rise (RPS, WPS)
tHCDDR
Double Data Rate Control Hold after Clock (K/K) 0.18
Rise (BWS0, BWS1, BWS2, BWS3)
0.28
tHD
tKHDX
0.18
–
0.20
–
0.28
–
0.28
–
ns
D[X:0] Hold after Clock (K/K) Rise
Output Times
tCO
tCHQV
–
0.29
–
–
0.33
–
–
0.37
–
–
0.45
–
ns
ns
K/K Clock Rise to Data Valid
tDOH
tCHQX
–0.29
–0.33
–0.37
–0.45
Data Output Hold after Output K/K Clock Rise
(Active to Active)
tCCQO
tCQOH
tCQD
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCQHCQL
–
0.29
–
–
0.33
–
–
0.37
–
–
0.45
–
ns
ns
ns
ns
ns
ns
K/K Clock Rise to Echo Clock Valid
Echo Clock Hold after K/K Clock Rise
Echo Clock High to Data Valid
–0.29
–0.33
–0.37
–0.45
0.15
–
0.15
–
0.15
–
0.20
–
tCQDOH
tCQH
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH [26]
–0.15
0.655
0.655
–0.15
0.75
0.75
–0.15
0.85
0.85
–0.20
1.0
–
–
–
–
tCQHCQH tCQHCQH
CQ Clock Rise to CQ Clock Rise
(rising edge to rising edge) [26]
–
–
–
1.0
–
tCHZ
tCHQZ
–
0.29
–
0.33
–
0.37
–
0.45
ns
Clock (K/K) Rise to High-Z
(Active to High-Z) [27, 28]
Clock (K/K) Rise to Low-Z [27, 28]
Echo Clock High to QVLD Valid [29]
tCLZ
tCHQX1
–0.29
–
–0.33
–
–0.37
–
–0.45
–
ns
ns
tQVLD
tCQHQVLD
–0.15 0.15 –0.15 0.15 –0.15 0.15 –0.20 0.20
PLL Timing
tKC Var tKC Var
tKC lock tKC lock
Clock Phase Jitter
–
0.15
–
–
0.15
–
–
0.15
–
–
0.20
–
ns
μs
ns
PLL Lock Time (K)
K Static to PLL Reset [30]
20
30
20
30
20
30
20
30
tKC Reset tKC Reset
Notes
24. When a part with a maximum frequency above 400 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
25. This part has a voltage regulator internally; t
initiated.
is the time that the power must be supplied above V minimum initially before a read or write operation can be
DD
POWER
26. These parameters are extrapolated from the input timing parameters (t
/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
CYC
design and are not tested in production.
27. t
, t
, are specified with a load capacitance of 5 pF as in (b) of Figure 3 on page 22. Transition is measured ± 100 mV from steady-state voltage.
CHZ CLZ
28. At any voltage and temperature t
is less than t
and t
less than t
.
CHZ
CLZ
CHZ
CO
29. t
spec is applicable for both rising and falling edges of QVLD signal.
QVLD
30. Hold to >V or <V .
IH
IL
Document Number: 001-15878 Rev. *E
Page 23 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Switching Waveforms
Read/Write/Deselect Sequence [31, 32, 33]
Figure 4. Waveform for 2.5 Cycle Read Latency
WRITE
3
READ
4
NOP
1
READ
2
WRITE
5
NOP
6
7
8
K
t
t
KL
t
t
KH
CYC
KHKH
K
RPS
t
t
SC HC
t
t
SC
HC
WPS
A
A0
A1
A2
A3
t
t
HD
t
t
HD
SA
HA
t
SD
t
SD
D11
D12
D30
D32
D33
t
D10
QVLD
D13
D31
D
QVLD
t
QVLD
t
DOH
t
t
CQDOH
CO
t
t
CHZ
t
CLZ
t
CQD
Q
Q00 Q01 Q02
CCQO
Q20 Q21 Q22
Q23
Q03
(Read Latency = 2.5 Cycles)
CQOH
CQ
CQ
CCQO
t
t
t
CQHCQH
CQH
CQOH
DON’T CARE
UNDEFINED
Notes
31. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.
32. Outputs are disabled (High-Z) one clock cycle after a NOP.
33. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note
applies to the whole diagram.
Document Number: 001-15878 Rev. *E
Page 24 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Ordering Information
The following table lists all possible speed, package, and temperature range options supported for these devices. Note that some
options listed may not be available for order entry. To verify the availability of a specific option, visit the Cypress web site at
www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales
representative for the status of availability of parts.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://app.cypress.com/portal/server.pt?space=CommunityPage&control=SetCommunity&CommunityID=
201&PageID=230.
Table 2. Ordering Information
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
550 CY7C1561KV18-550BZC
CY7C1576KV18-550BZC
CY7C1563KV18-550BZC
CY7C1565KV18-550BZC
CY7C1561KV18-550BZXC
CY7C1576KV18-550BZXC
CY7C1563KV18-550BZXC
CY7C1565KV18-550BZXC
CY7C1561KV18-550BZI
CY7C1576KV18-550BZI
CY7C1563KV18-550BZI
CY7C1565KV18-550BZI
CY7C1561KV18-550BZXI
CY7C1576KV18-550BZXI
CY7C1563KV18-550BZXI
CY7C1565KV18-550BZXI
500 CY7C1561KV18-500BZC
CY7C1576KV18-500BZC
CY7C1563KV18-500BZC
CY7C1565KV18-500BZC
CY7C1561KV18-500BZXC
CY7C1576KV18-500BZXC
CY7C1563KV18-500BZXC
CY7C1565KV18-500BZXC
CY7C1561KV18-500BZI
CY7C1576KV18-500BZI
CY7C1563KV18-500BZI
CY7C1565KV18-500BZI
CY7C1561KV18-500BZXI
CY7C1576KV18-500BZXI
CY7C1563KV18-500BZXI
CY7C1565KV18-500BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Commercial
Industrial
Commercial
Industrial
Document Number: 001-15878 Rev. *E
Page 25 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Table 2. Ordering Information (continued)
Speed
(MHz)
Package
Diagram
Operating
Ordering Code
Package Type
Range
450 CY7C1561KV18-450BZC
CY7C1576KV18-450BZC
CY7C1563KV18-450BZC
CY7C1565KV18-450BZC
CY7C1561KV18-450BZXC
CY7C1576KV18-450BZXC
CY7C1563KV18-450BZXC
CY7C1565KV18-450BZXC
CY7C1561KV18-450BZI
CY7C1576KV18-450BZI
CY7C1563KV18-450BZI
CY7C1565KV18-450BZI
CY7C1561KV18-450BZXI
CY7C1576KV18-450BZXI
CY7C1563KV18-450BZXI
CY7C1565KV18-450BZXI
400 CY7C1561KV18-400BZC
CY7C1576KV18-400BZC
CY7C1563KV18-400BZC
CY7C1565KV18-400BZC
CY7C1561KV18-400BZXC
CY7C1576KV18-400BZXC
CY7C1563KV18-400BZXC
CY7C1565KV18-400BZXC
CY7C1561KV18-400BZI
CY7C1576KV18-400BZI
CY7C1563KV18-400BZI
CY7C1565KV18-400BZI
CY7C1561KV18-400BZXI
CY7C1576KV18-400BZXI
CY7C1563KV18-400BZXI
CY7C1565KV18-400BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Commercial
Industrial
Commercial
Industrial
Document Number: 001-15878 Rev. *E
Page 26 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Package Diagram
Figure 5. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180
BOTTOM VIEW
PIN 1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
-0.06
Ø0.50 (165X)
+0.14
1
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00
5.00
10.00
13.00 0.10
B
13.00 0.10
B
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
SEATING PLANE
C
51-85180-*A
Document Number: 001-15878 Rev. *E
Page 27 of 28
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CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
PRELIMINARY
Document History Page
Document Title: CY7C1561KV18/CY7C1576KV18/CY7C1563KV18/CY7C1565KV18, 72-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
Document Number: 001-15878
Submission
Date
Orig. of
Change
Rev.
ECN
Description of Change
**
1120252
1246904
See ECN
See ECN
VKN
New datasheet
*A
VKN/AESA Added 550 and 500 MHz speed bins
Removed 375, 333, and 300 MHz speed bins
Added footnote# 2
*B
*C
1739283
2065806
See ECN
See ECN
VKN/AESA Converted from Advance Information to Preliminary
VKN/AESA Changed PLL lock time from 2048 cycles to 20 μs
Added footnote #22 related to IDD
Corrected typo in the footnote #26
*D
*E
2612383 11/25/2008 VKN/AESA Changed JTAG ID [31:29] from 001 to 000,
Updated Power up sequence waveform and it’s description,
Included Thermal Resistance values,
Changed the package size from 15 x 17 x 1.4 mm to 13 x 15 x 1.4 mm.
Updated data sheet template
2683451 04/03/2009 VKN/PYRS Added note on top of the Ordering Information table
Moved to external web
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
PSoC Solutions
General
psoc.cypress.com
clocks.cypress.com
wireless.cypress.com
memory.cypress.com
image.cypress.com
psoc.cypress.com/solutions
psoc.cypress.com/low-power
psoc.cypress.com/precision-analog
psoc.cypress.com/lcd-drive
psoc.cypress.com/can
Clocks & Buffers
Wireless
Low Power/Low Voltage
Precision Analog
LCD Drive
Memories
Image Sensors
CAN 2.0b
USB
psoc.cypress.com/usb
© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-15878 Rev. *E
Revised April 03, 2009
Page 28 of 28
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.
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