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CY7C199L-25VCT [CYPRESS]

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CY7C199L-25VCT
型号： CY7C199L-25VCT
厂家： CYPRESS    CYPRESS
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存储 内存集成电路 静态存储器 光电二极管
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99  
CY7C199  
32K x 8 Static RAM  
provided by an active LOW Chip Enable (CE) and active LOW  
Output Enable (OE) and three-state drivers. This device has  
an automatic power-down feature, reducing the power con-  
sumption by 81% when deselected. The CY7C199 is in the  
standard 300-mil-wide DIP, SOJ, and LCC packages.  
Features  
• High speed  
— 10 ns  
• Fast tDOE  
An active LOW Write Enable signal (WE) controls the writ-  
ing/reading operation of the memory. When CE and WE inputs  
are both LOW, data on the eight data input/output pins (I/O0  
through I/O7) is written into the memory location addressed by  
the address present on the address pins (A0 through A14).  
Reading the device is accomplished by selecting the device  
and enabling the outputs, CE and OE active LOW, while WE  
remains inactive or HIGH. Under these conditions, the con-  
tents of the location addressed by the information on address  
pins are present on the eight data input/output pins.  
• CMOS for optimum speed/power  
• Low active power  
— 467 mW (max, 12 ns “L” version)  
• Low standby power  
— 0.275 mW (max, “L” version)  
• 2V data retention (“L” version only)  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and Write Enable  
(WE) is HIGH. A die coat is used to improve alpha immunity.  
Functional Description  
The CY7C199 is a high-performance CMOS static RAM orga-  
nized as 32,768 words by 8 bits. Easy memory expansion is  
Logic Block Diagram  
Pin Configurations  
DIP / SOJ / SOIC  
Top View  
LCC  
Top View  
A
V
CC  
28  
27  
26  
1
2
3
4
5
6
5
A
A
A
WE  
A
4
6
7
8
3
2 1 2827  
26  
4
A
4
A
A
10  
8
9
A
3
25  
24  
5
6
7
8
25  
24  
23  
22  
21  
20  
19  
18  
A
3
A
9
A
2
A
1
A
A
2
A
10  
A
11  
23  
22  
A
11  
A
1
A
12  
OE  
7
OE  
A
9
13  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
A
A
A
I/O  
I/O  
I/O  
A
21  
20  
19  
18  
17  
16  
15  
A
12  
13  
14  
0
0
1
2
3
4
5
6
8
9
10  
11  
12  
13  
0
A
10  
11  
12  
14  
INPUT BUFFER  
CE  
I/O  
I/O  
CE  
I/O  
I/O  
I/O  
I/O  
I/O  
0
7
6
7
1
A
0
0
1
2
6
5
4
1314151617  
A
1
C199–3  
A
2
I/O  
I/O  
A
3
GND  
14  
3
A
4
C199–2  
1024 x 32 x 8  
ARRAY  
A
5
22  
OE  
A
A
21  
A
0
6
23  
24  
1
A
20  
CE  
I/O  
I/O  
6
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
1
7
A
A
A
A
2
3
4
19  
18  
17  
16  
8
A
7
25  
26  
27  
28  
1
9
5
TSOP I  
Top View  
(not to scale)  
WE  
4
3
CE  
WE  
V
CC  
A
15  
14  
13  
POWER  
DOWN  
COLUMN  
DECODER  
5
A
A
A
2
3
6
7
2
I/O  
7
12  
11  
OE  
4
5
8
9
I/O  
0
C199–1  
A
A
10  
9
14  
A
6
7
10  
A
A
13  
12  
A
11  
8
C199–4  
Selection Guide  
7C199-8 7C199-10 7C199-12 7C199-15 7C199-20 7C199-25 7C199-35 7C199-45  
Maximum Access Time (ns)  
Maximum Operating  
8
10  
110  
90  
12  
160  
90  
15  
155  
90  
20  
150  
90  
25  
150  
80  
35  
140  
70  
45  
120  
140  
Current (mA)  
L
Maximum CMOS  
Standby Current (mA)  
0.5  
0.5  
0.05  
10  
10  
10  
10  
10  
10  
L
0.05  
0.05  
0.05  
0.05  
0.05  
Shaded area contains advance information.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05160 Rev. **  
Revised September 7, 2001  
CY7C199  
DC Voltage Applied to Outputs  
Maximum Ratings  
in High Z State[1] ................................... –0.5V to VCC + 0.5V  
DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V  
Output Current into Outputs (LOW)............................. 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Storage Temperature .................................–65°C to +150°C  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Static Discharge Voltage .......................................... >2001V  
(per MIL-STD-883, Method 3015)  
Supply Voltage to Ground Potential  
(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V  
Latch-Up Current.................................................... >200 mA  
Operating Range  
Range  
Commercial  
Industrial  
Military  
Ambient Temperature[2]  
VCC  
0°C to +70°C  
5V ± 10%  
5V ± 10%  
5V ± 10%  
–40°C to +85°C  
–55°C to +125°C  
Electrical Characteristics Over the Operating Range[3]  
7C199-8  
7C199-10  
7C199-12  
7C199-15  
Parameter  
Description  
Test Conditions  
Min. Max. Min. Max. Min. Max. Min. Max. Unit  
VOH  
Output HIGH  
Voltage  
VCC = Min., IOH=–4.0 mA  
2.4  
2.4  
2.4  
2.4  
V
V
VOL  
VIH  
VIL  
IIX  
Output LOW  
Voltage  
VCC = Min., IOL=8.0 mA  
0.4  
0.4  
0.4  
0.4  
Input HIGH  
Voltage  
2.2  
–0.5  
–5  
VCC  
+0.3V  
2.2  
–0.5  
–5  
VCC  
+0.3V  
2.2  
–0.5  
–5  
VCC  
+0.3V  
2.2  
–0.5  
–5  
VCC  
+0.3V  
V
Input LOW  
Voltage  
0.8  
+5  
0.8  
+5  
+5  
0.8  
+5  
+5  
0.8  
+5  
+5  
V
Input Load  
Current  
GND < VI < VCC  
µA  
µA  
IOZ  
ICC  
Output Leakage GND < VO < VCC  
Current  
,
–5  
+5  
–5  
–5  
–5  
Output Disabled  
VCC Operating  
Supply Current IOUT = 0 mA,  
f = fMAX = 1/tRC  
VCC = Max.,  
Com’l  
L
120  
110  
85  
160  
85  
155  
100  
180  
30  
mA  
mA  
mA  
mA  
mA  
Mil  
ISB1  
Automatic CE  
Power-Down  
Current— TTL  
Inputs  
Max. VCC  
CE > VIH  
VIN > VIH or  
VIN < VIL, f = fMAX  
,
,
Com’l  
L
5
5
5
30  
5
5
ISB2  
Automatic CE  
Power-Down  
Current— CMOS VIN > VCC – 0.3V  
Max. VCC  
CE > VCC – 0.3V  
,
Com’l  
L
0.5  
0.5  
10  
10  
0.05  
15  
mA  
mA  
mA  
0.05  
0.05  
0.05  
Mil  
Inputs or VIN < 0.3V, f = 0  
Shaded area contains advance information.  
Notes:  
1.  
VIL (min.) = –2.0V for pulse durations of less than 20 ns.  
2. TA is the “instant on” case temperature.  
3. See the last page of this specification for Group A subgroup testing information.  
Document #: 38-05160 Rev. **  
Page 2 of 16  
CY7C199  
Electrical Characteristics Over the Operating Range[3] (continued)  
7C199-20  
7C199-25  
7C199-35  
7C199-45  
Parameter  
Description  
Test Conditions  
Min. Max. Min. Max. Min. Max.  
Min.  
Max. Unit  
VOH  
Output HIGH  
Voltage  
VCC = Min., IOH=–4.0 mA 2.4  
2.4  
2.4  
2.4  
V
VOL  
VIH  
VIL  
IIX  
Output LOW  
Voltage  
VCC = Min., IOL=8.0 mA  
0.4  
0.4  
0.4  
0.4  
V
V
Input HIGH  
Voltage  
2.2  
VCC  
+0.3V  
2.2  
-0.5  
–5  
VCC  
+0.3V  
2.2  
-0.5  
–5  
VCC  
+0.3V  
2.2  
-0.5  
–5  
VCC  
+0.3V  
Input LOW  
Voltage  
–0.5  
0.8  
+5  
+5  
0.8  
+5  
+5  
0.8  
+5  
+5  
0.8  
+5  
+5  
V
Input Load  
Current  
GND < VI < VCC  
–5  
–5  
µA  
µA  
IOZ  
ICC  
Output Leakage GND < VI < VCC  
Current  
,
–5  
–5  
–5  
Output Disabled  
VCC Operating  
Supply Current  
VCC = Max.,  
IOUT = 0 mA,  
f = fMAX = 1/tRC  
Com’l  
L
150  
90  
150  
80  
140  
70  
150  
25  
5
140  
70  
mA  
mA  
mA  
mA  
mA  
Mil  
170  
30  
150  
30  
150  
25  
ISB1  
Automatic CE  
Power-Down  
Current—  
Max. VCC,CE> VIH, Com’l  
VIN > VIH  
or VIN < VIL, f = fMAX  
L
5
5
5
TTL Inputs  
ISB2  
Automatic CE  
Power-Down  
Current—  
Max. VCC  
,
Com’l  
L
10  
0.05  
15  
10  
0.05  
15  
10  
0.05  
15  
10  
0.05  
15  
mA  
µA  
CE > VCC – 0.3V  
VIN > VCC – 0.3V or  
VIN < 0.3V, f=0  
CMOS Inputs  
Mil  
mA  
]
Capacitance[4]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
Max.  
Unit  
pF  
CIN  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
8
8
COUT  
Note:  
pF  
4. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05160 Rev. **  
Page 3 of 16  
CY7C199  
AC Test Loads and Waveforms[5]  
R1 481Ω  
R1 481Ω  
5V  
5V  
ALL INPUT PULSES  
90%  
OUTPUT  
OUTPUT  
3.0V  
GND  
90%  
10%  
10%  
R2  
255 Ω  
R2  
255Ω  
30 pF  
5 pF  
≤t  
≤t  
r
r
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
C199–5  
C199–6  
(a)  
(b)  
Equivalent to:  
THÉVENIN EQUIVALENT  
167 Ω  
OUTPUT  
1.73V  
Data Retention Characteristics Over the Operating Range (L version only)  
Parameter Description  
Conditions[6]  
VDR VCC for Data Retention  
ICCDR Data Retention Current  
Min.  
Max.  
Unit  
V
2.0  
Com’l  
VCC = VDR = 2.0V,  
µA  
µA  
ns  
CE > VCC – 0.3V,  
VIN > VCC – 0.3V or  
VIN < 0.3V  
Com’l L  
10  
[4]  
tCDR  
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
[5]  
tR  
200  
µs  
Data Retention Waveform  
DATA RETENTION MODE  
3.0V  
3.0V  
V
DR  
> 2V  
V
CC  
t
t
R
CDR  
CE  
C199–7  
Note:  
5. tR< 3 ns for the -12 and the -15 speeds. tR< 5 ns for the -20 and slower speeds  
6. No input may exceed VCC + 0.5V.  
Document #: 38-05160 Rev. **  
Page 4 of 16  
CY7C199  
Switching Characteristics Over the Operating Range[3, 7]  
7C199-8  
7C199-10  
7C199-12  
Max.  
7C199-15  
Min. Max.  
Parameter  
READ CYCLE  
tRC  
Description  
Min.  
Max.  
Min. Max. Min.  
Unit  
Read Cycle Time  
8
3
10  
3
12  
3
15  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
Data Hold from Address Change  
CE LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z[8]  
OE HIGH to High Z[8, 9]  
CE LOW to Low Z[8]  
CE HIGH to High Z[8,9]  
CE LOW to Power-Up  
CE HIGH to Power-Down  
8
10  
12  
15  
tOHA  
tACE  
8
10  
5
12  
5
15  
7
tDOE  
4.5  
tLZOE  
0
3
0
0
3
0
0
3
0
0
3
0
tHZOE  
tLZCE  
tHZCE  
tPU  
5
4
8
5
5
5
5
7
7
tPD  
10  
12  
15  
WRITE CYCLE[10, 11]  
tWC  
Write Cycle Time  
8
7
7
0
0
7
5
0
10  
7
12  
9
15  
10  
10  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSCE  
tAW  
CE LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
7
9
tHA  
0
0
tSA  
0
0
0
tPWE  
tSD  
7
8
9
Data Set-Up to Write End  
Data Hold from Write End  
WE LOW to High Z[9]  
5
8
9
tHD  
0
0
0
tHZWE  
tLZWE  
5
6
7
7
WE HIGH to Low Z[8]  
3
3
3
3
Shaded area contains advance information.  
Notes:  
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,  
input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.  
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.  
9.  
tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.  
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate  
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD  
.
Document #: 38-05160 Rev. **  
Page 5 of 16  
CY7C199  
Switching Characteristics Over the Operating Range[3,7] (continued)  
7C199-20 7C199-25  
Min. Max.  
7C199-35  
7C199-45  
Parameter  
Description  
Min.  
25  
3
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
READ CYCLE  
tRC  
Read Cycle Time  
20  
3
35  
3
45  
3
ns  
ns  
ns  
tAA  
Address to Data Valid  
20  
25  
35  
45  
tOHA  
Data Hold from Address  
Change  
tACE  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tPU  
CE LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z[8]  
OE HIGH to High Z[8, 9]  
CE LOW to Low Z[8]  
CE HIGH to High Z[8, 9]  
CE LOW to Power-Up  
CE HIGH to Power-Down  
20  
9
25  
10  
35  
16  
45  
16  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
0
3
0
0
3
0
0
3
0
0
3
0
9
9
11  
11  
20  
15  
15  
20  
15  
15  
25  
tPD  
20  
WRITE CYCLE[10,11]  
tWC  
tSCE  
tAW  
Write Cycle Time  
20  
15  
15  
0
25  
18  
20  
0
35  
22  
30  
0
45  
22  
40  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CE LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
tHA  
tSA  
0
0
0
0
tPWE  
tSD  
15  
10  
0
18  
10  
0
22  
15  
0
22  
15  
0
Data Set-Up to Write End  
Data Hold from Write End  
WE LOW to High Z[9]  
tHD  
tHZWE  
tLZWE  
10  
11  
15  
15  
WE HIGH to Low Z[8]  
3
3
3
3
Switching Waveforms  
Read Cycle No. 1[12, 13]  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
C199–8  
Notes:  
12. Device is continuously selected. OE, CE = VIL.  
13. WE is HIGH for read cycle.  
Document #: 38-05160 Rev. **  
Page 6 of 16  
CY7C199  
Switching Waveforms (continued)  
Read Cycle No. 2 [13, 14]  
t
RC  
CE  
t
ACE  
OE  
t
t
HZOE  
t
DOE  
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PD  
t
PU  
V
ICC  
CC  
SUPPLY  
CURRENT  
50%  
50%  
ISB  
C199–9  
Write Cycle No. 1 (WE Controlled)[10, 15, 16]  
t
WC  
ADDRESS  
CE  
t
t
AW  
HA  
t
SA  
t
PWE  
WE  
OE  
t
SD  
t
HD  
DATA VALID  
IN  
DATA I/O  
t
HZOE  
C199–10  
Write Cycle No. 2 (CE Controlled)[10, 15, 16]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
t
HA  
AW  
WE  
t
t
HD  
SD  
DATA I/O  
DATA VALID  
IN  
C199–11  
Notes:  
14. Address valid prior to or coincident with CE transition LOW.  
15. Data I/O is high impedance if OE = VIH  
.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
Document #: 38-05160 Rev. **  
Page 7 of 16  
CY7C199  
Switching Waveforms (continued)  
Write Cycle No. 3 (WE Controlled OE LOW)[11, 16]  
t
WC  
ADDRESS  
CE  
t
t
HA  
AW  
t
SA  
WE  
t
t
HD  
SD  
DATA I/O  
DATA VALID  
IN  
t
t
LZWE  
HZWE  
C199–12  
Typical DC and AC Characteristics  
NORMALIZED SUPPLY CURRENT  
vs. AMBIENT TEMPERATURE  
OUTPUT SOURCE CURRENT  
vs. OUTPUT VOLTAGE  
NORMALIZED SUPPLY CURRENT  
vs. SUPPLY  
VOLTAGE  
120  
100  
80  
1.4  
1.2  
1.4  
1.2  
1.0  
0.8  
0.6  
I
CC  
I
CC  
1.0  
0.8  
0.6  
V
CC  
=5.0V  
60  
T =25°C  
A
V
IN  
=5.0V  
T =25°C  
A
40  
V
V
IN  
=5.0V  
=5.0V  
0.4  
CC  
0.4  
20  
0
0.2  
0.0  
0.2  
0.0  
I
SB  
I
SB  
–55  
25  
125  
0.0  
1.0  
2.0  
3.0  
4.0  
4.0  
4.5  
5.0  
5.5  
6.0  
AMBIENT TEMPERATURE (°C)  
OUTPUT VOLTAGE (V)  
SUPPLY VOLTAGE (V)  
NORMALIZED ACCESS TIME  
vs. AMBIENT TEMPERATURE  
OUTPUT SINK CURRENT  
vs. OUTPUT VOLTAGE  
NORMALIZED ACCESS TIME  
vs. SUPPLY VOLTAGE  
140  
120  
1.6  
1.4  
1.4  
1.3  
1.2  
100  
80  
1.2  
1.0  
1.1  
1.0  
60  
T =25°C  
A
V
CC  
=5.0V  
T =25°C  
A
V
CC  
=5.0V  
40  
0.8  
20  
0
0.9  
0.8  
0.6  
–55  
0.0  
1.0  
2.0  
3.0  
4.0  
25  
125  
4.0  
4.5  
5.0  
5.5  
6.0  
AMBIENT TEMPERATURE (°C)  
OUTPUT VOLTAGE (V)  
SUPPLY VOLTAGE (V)  
Document #: 38-05160 Rev. **  
Page 8 of 16  
CY7C199  
Typical DC and AC Characteristics (continued)  
TYPICALPOWER-ON CURRENT  
vs.SUPPLY VOLTAGE  
TYPICAL ACCESS TIMECHANGE  
vs. OUTPUT LOADING  
NORMALIZED I vs.CYCLETIME  
CC  
3.0  
2.5  
2.0  
1.5  
30.0  
25.0  
20.0  
15.0  
1.25  
1.00  
0.75  
0.50  
V
=5.0V  
CC  
T =25°C  
A
V
IN  
=0.5V  
V
=4.5V  
1.0  
0.5  
10.0  
5.0  
CC  
T =25°C  
A
0.0  
0.0  
0.0  
1.0  
2.0  
3.0  
4.0  
5.0  
0
200 400  
600 800 1000  
10  
20  
30  
40  
SUPPLY VOLTAGE (V)  
CAPACITANCE (pF)  
CYCLE FREQUENCY (MHz)  
Truth Table  
CE  
H
L
WE  
X
OE  
X
Inputs/Outputs  
High Z  
Mode  
Power  
Deselect/Power-Down  
Read  
Standby (ISB  
Active (ICC  
Active (ICC  
Active (ICC  
)
H
L
Data Out  
Data In  
High Z  
)
L
L
X
Write  
)
L
H
H
Deselect, Output Disabled  
)
Ordering Information  
Speed  
Package  
Name  
Operating  
Range  
(ns)  
Ordering Code  
CY7C199-8VC  
Package Type  
28-Lead Molded SOJ  
8
V21  
Z28  
V21  
Z28  
V21  
Z28  
V21  
Z28  
V21  
Z28  
V21  
Z28  
P21  
V21  
Z28  
P21  
V21  
Z28  
V21  
Z28  
V21  
Z28  
Commercial  
Commercial  
Industrial  
CY7C199-8ZC  
CY7C199L-8VC  
CY7C199L-8ZC  
CY7C199-10VC  
CY7C199-10ZC  
CY7C199L-10VC  
CY7C199L-10ZC  
CY7C199-10VI  
CY7C199-10ZI  
CY7C199L-10VI  
CY7C199L-10ZI  
CY7C199-12PC  
CY7C199-12VC  
CY7C199-12ZC  
CY7C199L-12PC  
CY7C199L-12VC  
CY7C199L-12ZC  
CY7C199-12VI  
CY7C199-12ZI  
CY7C199L-12VI  
CY7C199L-12ZI  
28-Lead Thin Small Outline Package  
28-Lead Molded SOJ  
28-Lead Thin Small Outline Package  
28-Lead Molded SOJ  
10  
28-Lead Thin Small Outline Package  
28-Lead Molded SOJ  
28-Lead Thin Small Outline Package  
28-Lead Molded SOJ  
28-Lead Thin Small Outline Package  
28-Lead Molded SOJ  
28-Lead Thin Small Outline Package  
28-Lead (300-Mil) Molded DIP  
28-Lead Molded SOJ  
12  
Commercial  
28-Lead Thin Small Outline Package  
28-Lead (300-Mil) Molded DIP  
28-Lead Molded SOJ  
28-Lead Thin Small Outline Package  
28-Lead Molded SOJ  
Industrial  
28-Lead Thin Small Outline Package  
28-Lead Molded SOJ  
28-Lead Thin Small Outline Package  
Shaded area contains advance information. Contact your Cypress sales representative for availability  
Document #: 38-05160 Rev. **  
Page 9 of 16  
CY7C199  
Ordering Information (continued)  
Speed  
Package  
Name  
Operating  
Range  
(ns)  
Ordering Code  
CY7C199-15PC  
Package Type  
28-Lead (300-Mil) Molded DIP  
28-Lead Molded SOJ  
15  
P21  
V21  
Z28  
P21  
V21  
Z28  
V21  
Z28  
D22  
L54  
D22  
L54  
P21  
V21  
Z28  
P21  
V21  
Z28  
V21  
Z28  
D22  
L54  
D22  
L54  
P21  
S21  
V21  
Z28  
Z28  
D22  
L54  
P21  
S21  
V21  
Z28  
D22  
L54  
D22  
L54  
Commercial  
CY7C199-15VC  
CY7C199-15ZC  
CY7C199L-15PC  
CY7C199L-15VC  
CY7C199L-15ZC  
CY7C199-15VI  
28-Lead Thin Small Outline Package  
28-Lead (300-Mil) Molded DIP  
28-Lead Molded SOJ  
28-Lead Thin Small Outline Package  
28-Lead Molded SOJ  
Industrial  
Military  
CY7C199-15ZI  
28-Lead Thin Small Outline Package  
28-Lead (300-Mil) CerDIP  
CY7C199-15DMB  
CY7C199-15LMB  
CY7C199L-15DMB  
CY7C199L-15LMB  
CY7C199-20PC  
CY7C199-20VC  
CY7C199-20ZC  
CY7C199L-20PC  
CY7C199L-20VC  
CY7C199L-20ZC  
CY7C199-20VI  
28-Pin Rectangular Leadless Chip Carrier  
28-Lead (300-Mil) CerDIP  
28-Pin Rectangular Leadless Chip Carrier  
28-Lead (300-Mil) Molded DIP  
28-Lead Molded SOJ  
20  
Commercial  
28-Lead Thin Small Outline Package  
28-Lead (300-Mil) Molded DIP  
28-Lead Molded SOJ  
28-Lead Thin Small Outline Package  
28-Lead Molded SOJ  
Industrial  
Military  
CY7C199-20ZI  
28-Lead Thin Small Outline Package  
28-Lead (300-Mil) CerDIP  
CY7C199-20DMB  
CY7C199-20LMB  
CY7C199L-20DMB  
CY7C199L-20LMB  
CY7C199-25PC  
CY7C199-25SC  
CY7C199-25VC  
CY7C199-25ZC  
CY7C199L-25ZI  
CY7C199-25DMB  
CY7C199-25LMB  
CY7C199-35PC  
CY7C199-35SC  
CY7C199-35VC  
CY7C199-35ZC  
CY7C199-35DMB  
CY7C199-35LMB  
CY7C199-45DMB  
CY7C199-45LMB  
28-Pin Rectangular Leadless Chip Carrier  
28-Lead (300-Mil) CerDIP  
28-Pin Rectangular Leadless Chip Carrier  
28-Lead (300-Mil) Molded DIP  
28-Lead Molded SOIC  
25  
Commercial  
28-Lead Molded SOJ  
28-Lead Thin Small Outline Package  
28-Lead Thin Small Outline Package  
28-Lead (300-Mil) CerDIP  
Industrial  
Military  
28-Pin Rectangular Leadless Chip Carrier  
28-Lead (300-Mil) Molded DIP  
28-Lead Molded SOIC  
35  
45  
Commercial  
28-Lead Molded SOJ  
28-Lead Thin Small Outline Package  
28-Lead (300-Mil) CerDIP  
Military  
Military  
28-Pin Rectangular Leadless Chip Carrier  
28-Lead (300-Mil) CerDIP  
28-Pin Rectangular Leadless Chip Carrier  
Shaded area contains advance information. Contact your Cypress sales representative for availability  
Document #: 38-05160 Rev. **  
Page 10 of 16  
CY7C199  
MILITARY SPECIFICATIONS  
Group A Subgroup Testing  
DC Characteristics  
Parameter  
Subgroups  
1, 2, 3  
VOH  
VOL  
VIH  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
VIL Max.  
IIX  
IOZ  
ICC  
ISB1  
ISB2  
Switching Characteristics  
Parameter  
Subgroups  
READ CYCLE  
tRC  
7, 8, 9, 10, 11  
7, 8, 9, 10, 11  
7, 8, 9, 10, 11  
7, 8, 9, 10, 11  
7, 8, 9, 10, 11  
tAA  
tOHA  
tACE  
tDOE  
WRITE CYCLE  
tWC  
tAA  
7, 8, 9, 10, 11  
7, 8, 9, 10, 11  
7, 8, 9, 10, 11  
7, 8, 9, 10, 11  
7, 8, 9, 10, 11  
7, 8, 9, 10, 11  
7, 8, 9, 10, 11  
7, 8, 9, 10, 11  
tAW  
tHA  
tSA  
tPWE  
tSD  
tHD  
Document #: 38-05160 Rev. **  
Page 11 of 16  
CY7C199  
Package Diagrams  
28-Lead (300-Mil) CerDIP D22  
MIL-STD-1835 D-15 Config. A  
51-80032  
Document #: 38-05160 Rev. **  
Page 12 of 16  
CY7C199  
Package Diagrams (continued)  
28-Pin Rectangular Leadless Chip Carrier L54  
MIL-STD-1835C-11A  
51-80067  
28-Lead (300-Mil) Molded DIP P21  
51-85014-B  
Document #: 38-05160 Rev. **  
Page 13 of 16  
CY7C199  
Package Diagrams (continued)  
28-Lead (300-Mil) Molded SOIC S21  
51-85026-A  
28-Lead (300-Mil) Molded SOJ V21  
51-85031-B  
Document #: 38-05160 Rev. **  
Page 14 of 16  
CY7C199  
Package Diagrams (continued)  
28-Lead Thin Small Outline Package Z28  
51-85071-F  
Document #: 38-05160 Rev. **  
Page 15 of 16  
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
CY7C199  
Document Title: CY7C199 32K x 8 Static RAM  
Document Number: 38-05160  
Issue  
ECN NO. Date  
Orig. of  
Change  
REV.  
Description of Change  
**  
109971  
10/28/01  
SZV  
Change from Spec number: 38-00239 to 38-05160  
Document #: 38-05160 Rev. **  
Page 16 of 16  

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