CY7C21 [CYPRESS]
256/512/1K/2K/4K x 9 Asynchronous FIFO; 五百一十二分之二百五十六/ 1K / 2K / 4K ×9异步FIFO
| 型号： | CY7C21 |
| 厂家： | 
CYPRESS |
| 描述： | 256/512/1K/2K/4K x 9 Asynchronous FIFO |
| 文件： | 总17页 (文件大小：607K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C419/21/25/29/33256/512/1K/2K/4K
x 9 Asynchronous FIFO
CY7C419/21/25/29/33
256/512/1K/2K/4K x 9 Asynchronous FIFO
Features
Functional Description
■ Asynchronous first-in first-out (FIFO) buffer memories
■ 256 x 9 (CY7C419)
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and
CY7C432/3 are first-in first-out (FIFO) memories offered in
600-mil wide and 300-mil wide packages. There are 256, 512,
1,024, 2,048, and 4,096 words respectively by 9 bits wide. Each
FIFO memory is organized such that the data is read in the same
sequential order that it was written. Full and empty flags are
provided to prevent overrun and underrun. Three additional pins
are also provided to facilitate unlimited expansion in width, depth,
or both. The depth expansion technique steers the control
signals from one device to another in parallel. This eliminates the
serial addition of propagation delays, so that throughput is not
reduced. Data is steered in a similar manner.
■ 512 x 9 (CY7C421)
■ 1K x 9 (CY7C425)
■ 2K x 9 (CY7C429)
■ 4K x 9 (CY7C433)
■ Dual-ported RAM cell
■ High speed 50 MHz read and write independent of depth and
width
The read and write operations may be asynchronous; each can
occur at a rate of 50 MHz. The write operation occurs when the
write (W) signal is LOW. Read occurs when read (R) goes LOW.
The nine data outputs go to the high impedance state when R is
HIGH.
■ Low operating power: ICC = 35 mA
■ Empty and full flags (Half Full flag in standalone)
■ TTL compatible
A Half Full (HF) output flag that is valid in the standalone and
width expansion configurations is provided. In the depth
expansion configuration, this pin provides the expansion out
(XO) information that is used to tell the next FIFO that it is
activated.
■ Retransmit in standalone
■ Expandable in width
■ PLCC, 7x7 TQFP, SOJ, 300-mil, and 600-mil DIP
■ Pb-free packages available
In the standalone and width expansion configurations, a LOW on
the retransmit (RT) input causes the FIFOs to retransmit the
data. Read enable (R) and write enable (W) must both be HIGH
during retransmit, and then R is used to access the data.
■ Pin compatible and functionally equivalent to IDT7200,
IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201,
AM7202, AM7203, and AM7204
The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425,
CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated
using an advanced 0.65-micron P-well CMOS technology. Input
ESD protection is greater than 2000V and latch-up is prevented
by careful layout and guard rings.
Logic Block Diagram
Cypress Semiconductor Corporation
Document #: 38-06001 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 09, 2008
[+] Feedback
CY7C419/21/25/29/33
Pin Configurations
Figure 3. 32-PIn TQFP
Figure 1. 32-Pin PLCC/LCC
Figure 2. 28-Pin DIP
Table 1. Selection Guide
4K x 9
–10
50
–15
40
–20
–25
28.5
25
–30
–40
20
–65
12.5
65
Frequency (MHz)
Maximum Access Time (ns)
ICC1 (mA)
33.3
20
25
30
35
10
15
40
35
35
35
35
35
35
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Output Current, into Outputs (LOW)............................ 20 mA
Maximum Rating
Static Discharge Voltage............................................>2000V
(per MIL–STD–883, Method 3015)
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.[1]
Latch-Up Current.....................................................>200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with Power Applied..–55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +7.0V
Operating Range
Range
Commercial
Industrial
Ambient Temperature[2]
VCC
0°C to + 70°C
–40°C to +85°C
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
Power Dissipation.......................................................... 1.0W
Electrical Characteristics Over the Operating Range[3]
All Speed Grades
Parameter
Description
Test Conditions
Unit
Min
Max
VOH
VOL
VIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VCC = Min., IOH = –2.0 mA
VCC = Min., IOL = 8.0 mA
2.4
V
V
V
0.4
VCC
VCC
0.8
Commercial
Industrial
2.0
2.2
[4]
VIL
IIX
Input LOW Voltage
V
Input Leakage Current
Output Leakage Current
Output Short Circuit Current[5]
GND < VI < VCC
–10
–10
+10
+10
–90
μA
μA
mA
IOZ
IOS
R > VIH, GND < VO < VCC
VCC = Max., VOUT = GND
Notes
1. Single Power Supply: The voltage on any input or I/O pin can not exceed the power pin during power-up.
2. is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. (Min.) = –2.0V for pulse durations of less than 20 ns.
T
A
V
IL
5. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
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Electrical Characteristics Over the Operating Range
–10
–15
–20
–25
Parameter
Description
Test Conditions
Unit
Min Max Min Max Min Max Min Max
ICC
Operating Current
VCC = Max., Commercial
85
65
55
90
50
80
mA
I
OUT = 0 mA
Industrial
100
f = fMAX
ICC1
Operating Current
VCC = Max.,
Commercial
35
35
35
35
mA
I
OUT = 0 mA
F = 20 MHz
ISB1
ISB2
Standby Current
All Inputs =
Commercial
Industrial
10
5
10
15
5
10
15
5
10
15
5
mA
mA
VIH Min.
Power-Down Current All Inputs >
Commercial
Industrial
VCC –0.2V
8
8
8
Electrical Characteristics Over the Operating Range[3]
–30
–40
–65
Parameter
Description
Test Conditions
Unit
Min Max Min Max Min Max
ICC
Operating Current
VCC = Max., Commercial
40
75
35
70
35
65
mA
IOUT = 0 mA
Industrial
f = fMAX
ICC1
Operating Current
Standby Current
VCC = Max.,
Commercial
35
35
35
mA
IOUT = 0 mA
F = 20 MHz
ISB1
ISB2
All Inputs =
Commercial
Industrial
10
15
5
10
15
5
10
15
5
mA
mA
VIH Min.
Power-Down Current All Inputs >
VCC –0.2V
Commercial
Industrial
8
8
8
Capacitance[6]
Parameter
Description
Test Conditions
Max
6
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1
MHz, VCC = 4.5V
pF
pF
COUT
6
Note
6. Tested initially and after any design or process changes that may affect these parameters.
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Switching Characteristics Over the Operating Range[7, 8]
–10
–15
–20
–25
Parameter
Description
Unit
Min Max Min Max Min Max Min Max
tRC
tA
tRR
tPR
tLZR
tDVR
tHZR
tWC
tPW
tHWZ
tWR
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
20
25
30
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
15
20
25
10
10
3
10
15
3
10
20
3
10
25
3
[6,9]
Read LOW to Low Z
[9,10]
Data Valid After Read HIGH
Read HIGH to High Z
Write Cycle Time
Write Pulse Width
Write HIGH to Low Z
Write Recovery Time
Data Set-Up Time
Data Hold Time
MR Cycle Time
5
5
5
5
[6,9,10]
15
15
15
18
20
10
5
10
6
25
15
5
10
8
30
20
5
10
12
0
30
20
10
20
20
30
20
10
35
25
5
10
15
0
35
25
10
25
25
35
25
10
[6,9]
tSD
tHD
0
0
tMRSC
tPMR
tRMR
tRPW
tWPW
tRTC
tPRT
tRTR
tEFL
tHFH
tFFH
tREF
tRFF
tWEF
tWFF
tWHF
tRHF
tRAE
tRPE
tWAF
tWPF
tXOL
tXOH
20
10
10
10
10
20
10
10
25
15
10
15
15
25
15
10
MR Pulse Width
MR Recovery Time
Read HIGH to MR HIGH
Write HIGH to MR HIGH
Retransmit Cycle Time
Retransmit Pulse Width
Retransmit Recovery Time
MR to EF LOW
20
20
20
10
10
10
10
10
10
10
25
25
25
15
15
15
15
15
15
15
30
30
30
20
20
20
20
20
20
20
35
35
35
25
25
25
25
25
25
25
MR to HF HIGH
MR to FF HIGH
Read LOW to EF LOW
Read HIGH to FF HIGH
Write HIGH to EF HIGH
Write LOW to FF LOW
Write LOW to HF LOW
Read HIGH to HF HIGH
Effective Read from Write HIGH
Effective Read Pulse Width After EF HIGH
Effective Write from Read HIGH
Effective Write Pulse Width After FF HIGH
Expansion Out LOW Delay from Clock
Expansion Out HIGH Delay from Clock
10
10
15
15
20
20
25
25
10
15
20
25
10
10
15
15
20
20
25
25
Notes
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V and output loading of the specified I /I and 30 pF load capacitance,
OL OH
as in part (a) of AC Test Load and Waveforms, unless otherwise specified.
8. See the last page of this specification for Group A subgroup testing information.
9.
t
transition is measured at +200 mV from V and –200 mV from V . t
transition is measured at the 1.5V level. t
and t
transition is measured at
HZR
OL
OH DVR
HWZ
LZR
±100 mV from the steady state.
10. t and t use capacitance loading as in part (b) of AC Test Load and Waveforms.
HZR
DVR
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Switching Characteristics Over the Operating Range[7, 8] (continued)
–30
–40
–65
Parameter
Description
Unit
Min
Max
Min
Max
Min
Max
tRC
Read Cycle Time
40
50
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tA
Access Time
30
40
65
tRR
tPR
tLZR
Read Recovery Time
10
30
3
10
40
3
15
65
3
Read Pulse Width
[6,9]
Read LOW to Low Z
[9,10]
tDVR
tHZR
tWC
tPW
Data Valid After Read HIGH
Read HIGH to High Z
Write Cycle Time
5
5
5
[6,9,10]
20
20
20
40
30
5
50
40
5
80
65
5
Write Pulse Width
[6,9]
tHWZ
tWR
Write HIGH to Low Z
Write Recovery Time
10
18
0
10
20
0
15
30
0
tSD
Data Set-Up Time
tHD
Data Hold Time
tMRSC
tPMR
tRMR
tRPW
tWPW
tRTC
tPRT
tRTR
tEFL
MR Cycle Time
40
30
10
30
30
40
30
10
50
40
10
40
40
50
40
10
80
65
15
65
65
80
65
15
MR Pulse Width
MR Recovery Time
Read HIGH to MR HIGH
Write HIGH to MR HIGH
Retransmit Cycle Time
Retransmit Pulse Width
Retransmit Recovery Time
MR to EF LOW
40
40
40
30
30
30
30
30
30
30
50
50
50
35
35
35
35
35
35
35
80
80
80
60
60
60
60
60
60
60
tHFH
tFFH
tREF
tRFF
tWEF
tWFF
tWHF
tRHF
tRAE
tRPE
tWAF
tWPF
tXOL
tXOH
MR to HF HIGH
MR to FF HIGH
Read LOW to EF LOW
Read HIGH to FF HIGH
Write HIGH to EF HIGH
Write LOW to FF LOW
Write LOW to HF LOW
Read HIGH to HF HIGH
Effective Read from Write HIGH
Effective Read Pulse Width After EF HIGH
Effective Write from Read HIGH
Effective Write Pulse Width After FF HIGH
Expansion Out LOW Delay from Clock
Expansion Out HIGH Delay from Clock
30
30
40
40
65
65
30
35
60
30
30
40
40
65
65
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Switching Waveforms
Figure 4. Asynchronous Read and Write
t
t
PR
RC
t
t
RR
t
A
A
R
t
t
t
HZR
LZR
DVR
DATA VALID
DATA VALID
Q –Q
0
8
t
WC
t
t
WR
PW
W
t
t
HD
SD
DATA VALID
DATA VALID
D –D
0
8
Figure 5. Master Reset
[12]
t
MRSC
t
PMR
MR
[11]
R, W
t
RPW
t
WPW
t
RMR
t
EFL
EF
t
HFH
HF
FF
t
FFH
Figure 6. Half-full Flag
HALF FULL
HALF FULL+1
HALF FULL
W
R
t
RHF
t
WHF
HF
Notes
11. W and R ≥ V around the rising edge of MR
IH
12. t
= t
+ t
.
MRSC
PMR
RMR
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Switching Waveforms (continued)
Figure 7. Last Write to First Read Full Flag
ADDITIONAL
READS
LAST WRITE
FIRST READ
FIRST WRITE
R
W
t
t
RFF
WFF
FF
Figure 8. Last Read to First Write Empty Flag
ADDITIONAL
WRITES
LAST READ
FIRST WRITE
FIRST READ
W
R
t
t
WEF
REF
EF
t
A
VALID
VALID
DATA OUT
Figure 9. Retransmit[13]
[14]
RTC
t
t
PRT
FL/RT
R,W
t
RTR
Notes
13. EF, HF and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags will be valid at t
.
RTC
14. t
= t
+ t
.
RTC
PRT
RTR
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Switching Waveforms (continued)
Figure 10. Empty Flag and Read Data Flow-through Mode
DATA IN
W
t
RAE
R
t
RPE
t
REF
EF
t
WEF
t
A
t
HWZ
DATA OUT
DATA VALID
Figure 11. Full Flag and Write Data Flow-through Mode
R
t
t
WPF
WAF
W
t
t
WFF
RFF
FF
t
HD
DATA IN
DATA VALID
t
A
t
SD
DATA OUT
DATA VALID
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Switching Waveforms (continued)
Figure 12. Expansion Timing Diagrams
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1
WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
W
t
WR
t
t
XOH
XOL
[15]
XO (XI )
1
2
t
t
HD
HD
t
t
SD
SD
DATA VALID
DATA VALID
D –D
0
8
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1
READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
R
t
RR
t
t
XOH
XOL
[15]
XO (XI )
1
2
t
HZR
t
DVR
t
t
DVR
LZR
DATA
VALID
DATA
VALID
Q –Q
0
8
t
A
t
A
Note
15. Expansion Out of device 1 (XO ) is connected to Expansion In of device 2 (XI )
1
2
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The retransmit feature is beneficial when transferring packets of
data. It enables the receiver to acknowledge receipt of data and
retransmit, if necessary.
Architecture
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9,
CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048,
4096 words of 9 bits each (implemented by an array of dual-port
RAM cells), a read pointer, a write pointer, control signals (W, R,
XI, XO, FL, RT, MR), and Full, Half Full, and Empty flags.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred since the last MR cycle. A LOW pulse on RT
resets the internal read pointer to the first physical location of the
FIFO. R and W must both be HIGH while and tRTR after
retransmit is LOW. With every read cycle after retransmit, previ-
ously accessed data and not previously accessed data is read
and the read pointer is incremented until it is equal to the write
pointer. Full, Half Full, and Empty flags are governed by the
relative locations of the read and write pointers and are updated
during a retransmit cycle. Data written to the FIFO after activation
of RT are also transmitted. FIFO, up to the full depth, can be
repeatedly retransmitted.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory cell
used in the RAM. The cell itself enables the read and write opera-
tions to be independent of each other, which is necessary to
achieve truly asynchronous operation of the inputs and outputs.
A second benefit is that the time required to increment the read
and write pointers is much less than the time required for data
propagation through the memory, which is the case if memory is
implemented using the conventional register array architecture.
Resetting the FIFO
Standalone/Width Expansion Modes
Upon power up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the Empty flag (EF) being LOW, and both the Half
Full (HF) and Full flags (FF) being HIGH. Read (R) and write (W)
must be HIGH tRPW/tWPW before and tRMR after the rising edge
of MR for a valid reset cycle. If reading from the FIFO after a reset
cycle is attempted, the outputs are in the high impedance state.
Standalone and width expansion modes are set by grounding
Expansion In (XI) and tying First Load (FL) to VCC. FIFOs can be
expanded in width to provide word widths greater than nine in
increments of nine. During width expansion mode, all control line
inputs are common to all devices, and flag outputs from any
device can be monitored.
Depth Expansion Mode
Writing Data to the FIFO
Depth expansion mode (see Figure 13 on page 12) is entered
when, during a MR cycle, Expansion Out (XO) of one device is
connected to Expansion In (XI) of the next device, with XO of the
last device connected to XI of the first device. In the depth
expansion mode the First Load (FL) input, when grounded,
indicates that this part is the first to be loaded. All other devices
must have this pin HIGH. To enable the correct FIFO, XO is
pulsed LOW when the last physical location of the previous FIFO
is written to and pulsed LOW again when the last physical
location is read. Only one FIFO is enabled for read and one for
write at any given time. All other devices are in standby.
The availability of at least one empty location is indicated by a
HIGH FF. The falling edge of W initiates a write cycle. Data
appearing at the inputs (D0–D8) tSD before and tHD after the
rising edge of W will be stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs tWEF after the first
LOW-to-HIGH transition of W for an empty FIFO. HF goes LOW
t
WHF after the falling edge of W following the FIFO actually being
Half Full. Therefore, the HF is active once the FIFO is filled to
half its capacity plus one word. HF will remain LOW while less
than one half of total memory is available for writing. The
LOW-to-HIGH transition of HF occurs tRHF after the rising edge
of R when the FIFO goes from half full +1 to half full. HF is
available in standalone and width expansion modes. FF goes
LOW tWFF after the falling edge of W, during the cycle in which
the last available location is filled. Internal logic prevents
overrunning a full FIFO. Writes to a full FIFO are ignored and the
write pointer is not incremented. FF goes HIGH tRFF after a read
from a full FIFO.
FIFOs can also be expanded simultaneously in depth and width.
Consequently, any depth or width FIFO can be created of word
widths in increments of 9. When expanding in depth, a composite
FF must be created by ORing the FFs together. Likewise, a
composite EF is created by ORing the EFs together. HF and RT
functions are not available in depth expansion mode.
Use of the Empty and Full Flags
To achieve maximum frequency, the flags must be valid at the
beginning of the next cycle. However, because they can be
updated by either edge of the read or write signal, they must be
valid by one-half of a cycle. Cypress FIFOs meet this
requirement; some competitors’ FIFOs do not.
Reading Data from the FIFO
The falling edge of R initiates a read cycle if the EF is not LOW.
Data outputs (Q0 to Q8) are in a high impedance condition
between read operations (R HIGH), when the FIFO is empty, or
when the FIFO is not the active device in the depth expansion
mode.
The reason for why the flags should be valid by the next cycle is
complex. The “effective pulse width violation” phenomenon can
occur at the full and empty boundary conditions, if the flags are
not properly used. The empty flag must be used to prevent
reading from an empty FIFO and the full flag must be used to
prevent writing into a full FIFO.
When one word is in the FIFO, the falling edge of R initiates a
HIGH-to-LOW transition of EF. The rising edge of R causes the
data outputs to go to the high impedance state and remain such
until a write is performed. Reads to an empty FIFO are ignored
and do not increment the read pointer. From the empty condition,
the FIFO can be read tWEF after a valid write.
For example, consider an empty FIFO that is receiving read
pulses. Because the FIFO is empty, the read pulses are ignored
by the FIFO, and nothing happens. Next, a single word is written
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into the FIFO, with a signal that is asynchronous to the read
signal. The (internal) state machine in the FIFO goes from empty
to empty+1. However, it does this asynchronously with respect
to the read signal, so that the effective pulse width of the read
signal cannot be determined, because the state machine does
not look at the read signal until it goes to the empty+1 state.
Similarly, the minimum write pulse width may be violated by
trying to write into a full FIFO, and asynchronously performing a
read. The empty and full flags are used to avoid these effective
pulse width violations, but to do this and operate at the maximum
frequency, the flag must be valid at the beginning of the next
cycle.
Figure 13. Depth Expansion
XO
R
W
D
FF
EF
FL
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
9
9
9
Q
V
CC
XI
XO
FULL
FF
EMPTY
EF
FL
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
9
XI
XO
*
FF
EF
FL
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
9
MR
XI
* FIRSTDEVICE
Document #: 38-06001 Rev. *C
Page 12 of 17
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CY7C419/21/25/29/33
Ordering Information
Speed
(ns)
Package
Type
Operating
Range
Package Type
Ordering Code
10
CY7C421–10AC
CY7C421–10JC
CY7C421–10JXC
CY7C421–10PC
CY7C421–10VC
CY7C421–15AC
CY7C421–15AXC
CY7C421–15JC
CY7C421–15JI
CY7C421–15VI
CY7C421–20JC
CY7C421–20JXC
CY7C421–20PC
CY7C421–20VC
CY7C421–20VXC
CY7C421–20JI
CY7C421–20JXI
CY7C421–25JC
CY7C421–25PC
CY7C421–25VC
CY7C421–25JI
CY7C421–25PI
CY7C421–30JC
CY7C421–30PC
CY7C421–30JI
CY7C421–40JC
CY7C421–40PC
CY7C421–40VC
CY7C421–40JI
CY7C421–65JC
CY7C421–65PC
CY7C421–65VC
CY7C421–65JI
A32
J65
J65
P21
V21
A32
A32
J65
J65
V21
J65
J65
P21
V21
V21
J65
J65
J65
P21
V21
J65
P21
J65
P21
J65
J65
P21
V21
J65
J65
P21
V21
J65
32-Pin Thin Plastic Quad Flatpack
32-Pin Plastic Leaded Chip Carrier
Commercial
32-Pin Pb-Free Plastic Leaded Chip Carriers
28-Pin (300-Mil) Molded DIP
28-Pin (300-Mil) Molded SOJ
15
20
32-Pin Thin Plastic Quad Flatpack
32-Pin Pb-Free Thin Plastic Quad Flatpack
32-Pin Plastic Leaded Chip Carrier
32-Pin Plastic Leaded Chip Carrier
28-Pin (300-Mil) Molded SOJ
Commercial
Industrial
32-Pin Plastic Leaded Chip Carrier
32-Pin Pb-Free Plastic Leaded Chip Carriers
28-Pin (300-Mil) Molded DIP
Commercial
28-Pin (300-Mil) Molded SOJ
28-Pin (300-Mil) Pb-Free Molded SOJ
32-Pin Plastic Leaded Chip Carrier
32-Pin Plastic Leaded Chip Carrier
32-Pin Plastic Leaded Chip Carrier
28-Pin (300-Mil) Molded DIP
Industrial
25
Commercial
28-Pin (300-Mil) Molded SOJ
32-Pin Plastic Leaded Chip Carrier
28-Pin (300-Mil) Molded DIP
Industrial
30
40
32-Pin Plastic Leaded Chip Carrier
28-Pin (300-Mil) Molded DIP
Commercial
32-Pin Plastic Leaded Chip Carrier
32-Pin Plastic Leaded Chip Carrier
28-Pin (300-Mil) Molded DIP
Industrial
Commercial
28-Pin (300-Mil) Molded SOJ
32-Pin Plastic Leaded Chip Carrier
32-Pin Plastic Leaded Chip Carrier
28-Pin (300-Mil) Molded DIP
Industrial
65
Commercial
28-Pin (300-Mil) Molded SOJ
32-Pin Plastic Leaded Chip Carrier
Industrial
Document #: 38-06001 Rev. *C
Page 13 of 17
[+] Feedback
CY7C419/21/25/29/33
Package Diagrams
Figure 14. 32-Pin Thin Plastic Quad Flat Pack A32 (51-85063)
51-85063-*B
Figure 15. 32-Pin Plastic Leaded Chip Carrier J65 (51-85002)
51-85002-*B
Document #: 38-06001 Rev. *C
Page 14 of 17
[+] Feedback
CY7C419/21/25/29/33
Package Diagrams (continued)
Figure 16. 28-Pin (300-Mil) PDIP P21 (51-85014)
SEE LEAD END OPTION
14
1
MIN.
DIMENSIONS IN INCHES [MM]
MAX.
REFERENCE JEDEC MO-095
PACKAGE WEIGHT: 2.15 gms
0.260[6.60]
0.295[7.49]
15
28
0.030[0.76]
0.080[2.03]
SEATING PLANE
1.345[34.16]
1.385[35.18]
0.290[7.36]
0.325[8.25]
0.120[3.05]
0.140[3.55]
0.140[3.55]
0.190[4.82]
0.009[0.23]
0.012[0.30]
0.115[2.92]
0.160[4.06]
3° MIN.
0.015[0.38]
0.060[1.52]
0.055[1.39]
0.065[1.65]
0.310[7.87]
0.385[9.78]
0.090[2.28]
0.110[2.79]
0.015[0.38]
0.020[0.50]
SEE LEAD END OPTION
LEAD END OPTION
(LEAD #1, 14, 15 & 28)
51-85014-*D
Document #: 38-06001 Rev. *C
Page 15 of 17
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CY7C419/21/25/29/33
Package Diagrams (continued)
Figure 17. 28-Pin (300-Mil) Molded SOJ V21(51-85031)
51-85031-*C
Document #: 38-06001 Rev. *C
Page 16 of 17
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CY7C419/21/25/29/33
Document History Page
Document Title: CY7C419, CY7C421, CY7C425, CY7C429, CY7C433, 256/512/1K/2K/4Kx9 Asynchronous FIFO
Document Number: 38-06001
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
106462
122332
383597
SZV
RBI
07/11/01
12/30/02
See ECN
Change from Spec Number: 38-00079 to 38-06001
*A
*B
Added power up requirements to maximum ratings information.
PCX
Added Pb-Free Logo
Added to Part-Ordering Information:
CY7C419–10JXC, CY7C419–15JXC, CY7C419-15VXC,
CY7C421–10JXC, CY7C421–15AXC, CY7C421–20JXC,
CY7C421–20VXC, CY7C425–10AXC, CY7C425–10JXC,
CY7C425–15JXC, CY7C425–20JXC, CY7C425–20VXC,
CY7C429–10AXC, CY7C429–15JXC, CY7C429–20JXC,
CY7C433–10AXC, CY7C433–10JXC, CY7C433–15JXC,
CY7C433–20AXC, CY7C433–20JXC
*C
2623658
VKN/PYRS
12/17/08
Added CY7C421-20JXI
Removed CY7C419/25/29/33 from the ordering information table
Removed 26-Lead CerDIP, 32-Lead RLCC, 28-Lead molded DIP
packages from the data sheet
Removed Military Information
Sales, Solutions and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
PSoC Solutions
General
psoc.cypress.com
clocks.cypress.com
wireless.cypress.com
memory.cypress.com
image.cypress.com
psoc.cypress.com/solutions
psoc.cypress.com/low-power
psoc.cypress.com/precision-analog
psoc.cypress.com/lcd-drive
psoc.cypress.com/can
Clocks & Buffers
Wireless
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psoc.cypress.com/usb
© Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06001 Rev. *C
Revised December 09, 2008
Page 17 of 17
All products and company names mentioned in this document may be the trademarks of their respective holders.
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