CY7C344-15PC/PI_技术文档

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CY7C344B

32-Macrocell MAX^®EPLD

densest EPLD of this size. Eight dedicated inputs and 16

bidirectional I/O pins communicate to one logic array block. In

the CY7C344 LAB there are 32 macrocells and 64 expander

product terms. When an I/O macrocell is used as an input, two

expanders are used to create an input path. Even if all of the

I/O pins are driven by macrocell registers, there are still 16

“buried” registers available. All inputs, macrocells, and I/O pins

are interconnected within the LAB.

Features

• High-performance, high-density replacement for TTL,

74HC, and custom logic

• 32 macrocells, 64 expander product terms in one LAB

• 8 dedicated inputs, 16 I/O pins

• 0.8-micron double-metal CMOS EPROM technology

The speed and density of the CY7C344 makes it a natural for

all types of applications. With just this one device, the designer

can implement complex state machines, registered logic, and

combinatorial “glue” logic, without using multiple chips. This

architectural flexibility allows the CY7C344 to replace

multichip TTL solutions, whether they are synchronous,

asynchronous, combinatorial, or all three.

• 28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC

package

Functional Description

Available in a 28-pin, 300-mil DIP or windowed J-leaded

ceramic chip carrier (HLCC), the CY7C344 represents the

Logic Block Diagram^[1]

Pin Configurations

HLCC

15(22) INPUT

15(23) INPUT

INPUT

1(8)

Top View

INPUT/CLK 2(9)

27(6)

28(7)

INPUT

13(20)

14(21)

4

3

2

1

28 27 26

25

5

6

7

8

9

10

11

I/O

INPUT

INPUT/CLK

I/O

24

23

22

21

20

19

MACROCELL 2

MACROCELL 1

I/O 3(10)

I/O 4(11)

I/O 5(12)

I/O 6(13)

I/O 9(16)

I/O 10(17)

I/O 11(18)

I/O 12(19)

I/O 17(24)

I/O 18(25)

I/O 19(26)

I/O 20(27)

I/O 23(2)

I/O 24(3)

I/O 25(4)

I/O 26(5)

INPUT

I/O

MACROCELL 4

MACROCELL 6

MACROCELL 8

MACROCELL 10

MACROCELL 12

MACROCELL 14

MACROCELL 16

MACROCELL 18

MACROCELL 20

MACROCELL 22

MACROCELL 24

MACROCELL 26

MACROCELL 28

MACROCELL 30

MACROCELL 32

MACROCELL 3

MACROCELL 5

MACROCELL 7

MACROCELL 9

MACROCELL 11

MACROCELL 13

MACROCELL 15

MACROCELL 17

MACROCELL 19

MACROCELL 21

MACROCELL 23

MACROCELL 25

MACROCELL 27

MACROCELL 29

MACROCELL 31

G

L

I

O

B

A

L

I/O

12 13 14 1516 1718

C

O

N

T

CerDIP

B

U

S

Top View

R

O

L

INPUT

I/O

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

INPUT/CLK

I/O

2

3

4

5

6

7

I/O

V

CC

V

CC

GND

I/O

GND

I/O

8

9

I/O

10

11

12

13

14

32

64 EXPANDER PRODUCT TERM ARRAY

I/O

INPUT

I/O

INPUT

Cypress Semiconductor Corporation

Document #: 38-03006 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised April 19, 2004

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CY7C344B

Selection Guide

7C344-15

15

7C344-20

7C344-25

25

Unit

ns

Maximum Access Time

20

Maximum Operating Current

Commercial

Military

200

220

150

170

200

mA

220

Industrial

Commercial

Military

220

150

220

Maximum Standby Current

150

mA

170

Industrial

170

Note:

1. Numbers in () refer to J-leaded packages.

Document #: 38-03006 Rev. *A

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CY7C344B

Static Discharge Voltage

Maximum Ratings

(per MIL-STD-883, Method 3015) .............................>2001V

DC Output Current, per Pin ......................–25 mA to +25 mA

DC Input Voltage^[2].........................................–3.0V to +7.0V

DC Program Voltage...................................................+13.0V

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied...................................................0°C to +70°C

Operating Range

Maximum Junction Temperature (Under Bias).............150°C

Supply Voltage to Ground Potential............... –2.0V to +7.0V

Maximum Power Dissipation...................................1500 mW

DC V_CCor GND Current............................................500 mA

Ambient

Range

Commercial

Industrial

Military

Temperature

V_CC

0°C to +70°C

–40°C to +85°C

–55°C to +125°C (Case)

5V ±5%

5V ±10%

Electrical Characteristics Over the Operating Range^[3]

Parameter

V_OH

V_OL

Description

Output HIGH Voltage

Output LOW Voltage

Input HIGH Level

Test Conditions

Min.

Max.

Unit

V_CC= Min., I_OH= –4.0 mA

2.4

V

V_CC= Min., I_OL= 8 mA

0.45

V_CC+0.3

0.8

V_IH

2.2

–0.3

–10

–40

–30

V

V_IL

Input LOW Level

V

I_IX

Input Current

GND ≤ V_IN≤ V_CC

+10

µA

mA

ns

I_OZ

Output Leakage Current

Output Short Circuit Current

V_O= V_CCor GND

V_CC= Max., V_OUT= 0.5V^{[4, 5]}

+40

I_OS

–90

I_CC1

Power Supply

Current (Standby)

V_I= V_CCor GND (No

Load)

Commercial

Military/Industrial

150

170

I_CC2

Power Supply Current

V_I= V_CCor GND (No

Load) f = 1.0 MHz^[4,6]

Commercial

200

Military/Industrial

220

t_R

t_F

Recommended Input Rise Time

Recommended Input Fall Time

100

ns

Capacitance

Parameter

Description

Input Capacitance

Output Capacitance

Test Conditions

Max.

10

Unit

C_IN

V_IN= 2V, f = 1.0 MHz

pF

C_OUT

V_OUT= 2.0V, f = 1.0 MHz

10

AC Test Loads and Waveforms^[7]

R1 464Ω

5V

ALL INPUT PULSES

OUTPUT

3.0V

90%

10%

90%

10%

R2

250Ω

R2

250Ω

50 pF

5 pF

GND

≤ 6 ns

t

f

≤ 6 ns

INCLUDING

JIG AND

SCOPE

t_R

t_F

(a)

(b)

Equivalent to:

THÉVENIN EQUIVALENT (commercial/military)

163Ω

OUTPUT

1.75V

Notes:

2. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –2.0V for periods less than 20 ns.

3. Typical values are for T = 25°C and V = 5V.

A

CC

4. Guaranteed by design but not 100% tested.

5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V

test problems caused by tester ground degradation.

= 0.5V has been chosen to avoid

OUT

6. Measured with device programmed as a 16-bit counter.

7. Part (a) in AC Test Load and Waveforms is used for all parameters except t and t , which is used for part (b) in AC Test Load and Waveforms. All external timing

ER

XZ

parameters are measured referenced to external pins of the device.

Document #: 38-03006 Rev. *A

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CY7C344B

When expander logic is used in the data path, add the appro-

priate maximum expander delay, t_EXPto t_S1. Determine which of

1/(t_WH+ t_WL), 1/t_CO1, or 1/(t_EXP+ t_S1) is the lowest frequency. The

lowest of these frequencies is the maximum data-path frequency for

the synchronous configuration.

Timing Delays

Timing delays within the CY7C344 may be easily determined

using Warp^®, Warp Professional™, or Warp Enterprise™

software. The CY7C344 has fixed internal delays, allowing the

user to determine the worst case timing delays for any design.

When calculating external asynchronous frequencies, use

t

_AS1if all inputs are on dedicated input pins. If any data is applied to

an I/O pin, t_AS2must be used as the required set-up time. If (t_AS2

_AH) is greater than t_ACO1, 1/(t_AS2+ t_AH) becomes the limiting

Design Recommendations

+

t

Operation of the devices described herein with conditions

above those listed under “Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other

conditions above those indicated in the operational sections of

this data sheet is not implied. Exposure to absolute maximum

ratings conditions for extended periods of time may affect

device reliability. The CY7C344 contains circuitry to protect

device pins from high-static voltages or electric fields; however,

normal precautions should be taken to avoid applying any

voltage higher than maximum rated voltages.

frequency in the data-path mode unless 1/(t_AWH+ t_AWL) is less than

1/(t_AS2+ t_AH).

When expander logic is used in the data path, add the appro-

priate maximum expander delay, t_EXPto t_AS1. Determine which

of 1/(t_AWH+t_AWL), 1/t_ACO1, or 1/(t_EXP+t_AS1) isthelowest frequency.

The lowest of these frequencies is the maximum data-path frequency

for the asynchronous configuration.

The parameter t_OHindicates the system compatibility of this device

when driving other synchronous logic with positive input hold times,

which is controlled by the same synchronous clock. If t_OHis greater

than the minimum required input hold time of the subsequent

synchronous logic, then the devices are guaranteed to function

properly with a common synchronous clock under worst-case

environmental and supply voltage conditions.

For proper operation, input and output pins must be

constrained to the range GND ≤ (V_INor V_OUT) ≤ V_CC. Unused

inputs must always be tied to an appropriate logic level (either V_CCor

GND). Each set of V_CCand GND pins must be connected together

directly at the device. Power supply decoupling capacitors of at least

0.2 µF must be connected between V_CCand GND. For the most

effective decoupling, each V_CCpin should be separately decoupled.

The parameter t_AOHindicates the system compatibility of this

device when driving subsequent registered logic with a positive hold

timeandusingthesameclock as theCY7C344. In general, if t_AOH

is greater than the minimum required input hold time of the subse-

quent logic (synchronous or asynchronous), then the devices are

guaranteed to function properly under worst-case environmental and

supply voltage conditions, provided the clock signal source is the

same. This also applies if expander logic is used in the clock signal

path of the driving device, but not for the driven device. This is due to

the expander logic in the second device’s clock signal path adding an

additional delay (t_EXP), causing the output data from the preceding

device to change prior to the arrival of the clock signal at the following

device’s register.

Timing Considerations

Unless otherwise stated, propagation delays do not include

expanders. When using expanders, add the maximum

expander delay t_EXPto the overall delay.

When calculating synchronous frequencies, use t_S1if all inputs

are on the input pins. t_S2should be used if data is applied at an I/O

pin. If t_S2is greater than t_CO1, 1/t_S2becomes the limiting frequency

in the data-path mode unless 1/(t_WH+ t_WL) is less than 1/t_S2

.

EXPANDER

DELAY

t

EXP

REGISTER

LOGIC ARRAY

OUTPUT

DELAY

t

CONTROLDELAY

CLR

INPUT

t

LAC

t

PRE

OUTPUT

t

OD

XZ

ZX

INPUT

DELAY

IN

t

LOGIC ARRAY

DELAY

t

RSU

RD

t

COMB

LATCH

t

RH

t

LAD

SYSTEM CLOCK DELAYt

ICS

CLOCK

DELAY

I/O

I/O DELAY

I/O

t

IC

t

IO

FEEDBACK

DELAY

t

C344–7

FD

Figure 1. CY7C344 Timing Model

Document #: 38-03006 Rev. *A

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CY7C344B

[7]

External Synchronous Switching CharacteristicsOver Operating Range

7C344-15

7C344-20

7C344-25

Parameter

Description

Min. Max. Min. Max. Min. Max. Unit

t_PD1

Dedicated Input to Combinatorial Output Delay^[8]Com’l/Ind

15

30

20

10

20

30

20

12

22

25

40

25

15

29

ns

Mil

t_PD2

t_PD3

t_PD4

t_EA

I/O Input to Combinatorial Output Delay^[9]

Com’l/Ind

Mil

Dedicated Input to Combinatorial Output Delay Com’l/Ind

with Expander Delay^[10]

Mil

I/O Input to Combinatorial Output Delay with

Expander Delay^{[4, 11]}

Com’l/Ind

Mil

Input to Output Enable Delay^[4]

Com’l/Ind

Mil

t_ER

t_CO1

t_CO2

t_S

Input to Output Disable Delay^[4]

Com’l/Ind

Mil

Synchronous Clock Input to Output Delay

Com’l/Ind

Mil

Synchronous Clock to Local Feedback to

Combinatorial Output^{[4, 12]}

Com’l/Ind

Mil

Dedicated Input or Feedback Set-Up Time to

Synchronous Clock Input

Com’l/Ind

Mil

10

0

12

0

15

0

t_H

Input Hold Time from Synchronous Clock Input^[7]Com’l/Ind

Mil

0

t_WH

t_WL

t_RW

t_RR

t_RO

t_PW

Synchronous Clock Input HIGH Time^[4]

Synchronous Clock Input LOW Time^[4]

Asynchronous Clear Width^[4]

Com’l/Ind

Mil

6

7

8

6

7

8

Com’l/Ind

Mil

6

7

8

6

7

8

Com’l/Ind

Mil

20

25

Asynchronous Clear Recovery Time^[4]

Com’l/Ind

Mil

Asynchronous Clear to Registered Output

Delay^[4]

Com’l/Ind

Mil

15

20

25

Asynchronous Preset Width^[4]

Com’l /Ind

Mil

20

25

t_PR

Asynchronous Preset Recovery Time^[4]

Com’l /Ind

Mil

Notes:

8. This parameter is the delay from an input signal applied to a dedicated input pin to a combinatorial output on any output pin. This delay assumes no expander

terms are used to form the logic function.

9. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to

form the logic function.

10. This parameter is the delay associated with an input signal applied to a dedicated input pin to combinatorial output on any output pin. This delay assumes

expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter

is tested periodically by sampling production material.

11. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output pin. This delay assumes expander terms are used to

form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by

sampling production material.

12. This specification is a measure of the delay from synchronous register clock input to internal feedback of the register output signal to a combinatorial output for

which the registered output signal is used as an input. This parameter assumes no expanders are used in the logic of the combinatorial output and the register

is synchronously clocked. This parameter is tested periodically by sampling production material.

Document #: 38-03006 Rev. *A

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CY7C344B

External Synchronous Switching CharacteristicsOver Operating Range (continued)^[7]

7C344-15

7C344-20

7C344-25

Parameter

Description

Min. Max. Min. Max. Min. Max. Unit

t_PO

Asynchronous Preset to Registered Output

Delay^[4]

Com’l /Ind

Mil

15

4

20

4

25

7

ns

t_CF

Synchronous Clock to Local Feedback Input^{[4, 13]}Com’l /Ind

ns

Mil

4

7

[4]

t_P

External Synchronous Clock Period (1/f_MAX3

)

Com’l/Ind

13

14

16

ns

Mil

f_MAX1

f_MAX2

f_MAX3

f_MAX4

External Maximum Frequency(1/(t_CO1+ t_S))^{[4, 14]}Com’l/Ind

Mil

50.0

71.4

83.3

3

41.6

62.5

71.4

3

33.3

45.4

62.5

3

MHz

ns

Maximum Frequency with Internal Only

Feedback (1/(t_CF+ t_S))^{[4, 15]}

Com’l/Ind

Mil

Data Path Maximum Frequency, least of

Com’l/Ind

Mil

[4, 16]

1/(t_WL+ t_WH), 1/(t_S+ t_H), or (1/t_CO1

)

Maximum Register Toggle Frequency

Com’l/Ind

Mil

[4, 17]

1/(t_WL+ t_WH

)

t_OH

Output Data Stable Time from Synchronous

Clock Input^{[4, 18]}

Com’l/Ind

Mil

3

Notes:

13. This specification is a measure of the delay associated with the internal register feedback path. This delay plus the register set-up time, t , is the minimum internal

S

period for an internal state machine configuration. This parameter is tested periodically by sampling production material.

14. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external only feedback can operate.

15. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states must

also control external points, this frequency can still be observed as long as it is less than 1/t

is tested periodically by sampling production material.

. This specification assumes no expander logic is used. This parameter

CO1

16. This frequency indicates the maximum frequency at which the device may operate in data-path mode (dedicated input pin to output pin). This assumes that no

expander logic is used.

17. This specification indicates the guaranteed maximum frequency in synchronous mode, at which an individual output or buried register can be cycled by a clock

signal applied to either a dedicated input pin or an I/O pin.

18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.

Document #: 38-03006 Rev. *A

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CY7C344B

External Asynchronous Switching Characteristics Over Operating Range^[7]

7C344-15

7C344-20

7C344-25

Parameter

Description

Min. Max. Min. Max. Min. Max. Unit

t_ACO1

Asynchronous Clock Input to Output Delay

Com’l/Ind

Mil

15

30

20

30

25

37

ns

t_ACO2

Asynchronous Clock Input to Local Feedback to

Combinatorial Output^[19]

Com’l/Ind

Mil

ns

t_AS

Dedicated Input or Feedback Set-Up Time to

Asynchronous Clock Input

Com’l/Ind

Mil

7

6

7

9

7

9

12

9

ns

t_AH

Input Hold Time from Asynchronous Clock Input

Asynchronous Clock Input HIGH Time^{[4, 20]}

Asynchronous Clock Input LOW Time^[4]

Com’l/Ind

Mil

ns

t_AWH

Com’l/Ind

Mil

ns

9

t_AWL

Com’l/Ind

Mil

11

ns

t_ACF

Asynchronous Clock to Local Feedback Input^{[4, 21]}Com’l/Ind

18

21

ns

Mil

[4]

t_AP

External Asynchronous Clock Period (1/f_MAX4

)

Com’l/Ind

Mil

13

16

20

ns

f_MAXA1

f_MAXA2

f_MAXA3

f_MAXA4

External Maximum Frequency in Asynchronous

Com’l/Ind 45.4

34.4

37

27

MHz

ns

[4, 22]

Mode 1/(t_ACO1+ t_AS

)

Mil

45.4

40

27

Maximum Internal Asynchronous Frequency

Com’l/Ind

Mil

30.3

40

[4, 23]

1/(t_ACF+ t_AS) or 1/(t_AWH+ t_AWL

)

40

37

Data Path Maximum Frequency in Asynchronous

Mode^{[4, 24]}

Com’l/Ind 66.6

Mil 66.6

Com’l/Ind 76.9

50

40

Maximum Asynchronous Register Toggle

62.5

15

50

[4, 25]

Frequency 1/(t_AWH+ t_AWL

)

Mil

76.9

15

50

t_AOH

Output Data Stable Time from Asynchronous Clock Com’l/Ind

15

Input^{[4, 26]}

Mil

15

Notes:

19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the registered output signal to a combinatorial

output for which the registered output signal is used as an input. Assumes no expanders are used in logic of combinatorial output or the asynchronous clock

input. This parameter is tested periodically by sampling production material.

20. This parameter is measured with a positive-edge-triggered clock at the register. For negative edge triggering, the t

and t

parameters must be swapped. If a

AWH

.

AWL

given input is used to clock multiple registers with both positive and negative polarity, t

should be used for both t

and t

AWH

AWL

21. This specification is a measure of the delay associated with the internal register feedback path for an asynchronously clocked register. This delay plus the

asynchronous register set-up time, t , is the minimum internal period for an asynchronously clocked state machine configuration. This delay assumes no expander logic in

AS

the asynchronous clock path. This parameter is tested periodically by sampling production material.

22. This parameter indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can

operate. It is assumed that no expander logic is employed in the clock signal path or data path.

23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate. If

register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/t

no expander logic is utilized. This parameter is tested periodically by sampling production material.

. Thisspecificationassumes

ACO1

24. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode.

This frequency is least of 1/(t + t ), 1/(t + t ), or 1/t . It also indicates the maximum frequency at which the device may operate in the asynchronously clocked

AWH AWL

AS AH

ACO1

data-path mode. Assumes no expander logic is used.

25. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode

by a clock signal applied to an external dedicated input or an I/O pin.

26. This parameter indicates the minimum time that the previous register output data is maintained on the output pin after an asynchronous register clock input to

an external dedicated input or I/O pin.

Document #: 38-03006 Rev. *A

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CY7C344B

Typical Internal Switching Characteristics Over Operating Range^[7]

7C344-15

7C344-20

7C344-25

Parameter

Description

Min. Max. Min. Max. Min. Max. Unit

t_IN

Dedicated Input Pad and Buffer Delay

Com’l/Ind

Mil

4

8

7

5

4

7

5

7

ns

t_IO

I/O Input Pad and Buffer Delay

Expander Array Delay

Com’l/Ind

Mil

5

7

5

7

t_EXP

t_LAD

t_LAC

t_OD

t_ZX

Com’l/Ind

Mil

10

9

15

10

7

Logic Array Data Delay

Com’l/Ind

Mil

9

Logic Array Control Delay

Output Buffer and Pad Delay

Output Buffer Enable Delay^[27]

Output Buffer Disable Delay

Com’l/Ind

Mil

7

Com’l/Ind

Mil

5

Com’l/Ind

Mil

8

11

8

t_XZ

Com’l/Ind

Mil

8

t_RSU

Register Set-Up Time Relative to Clock Signal Com’l/Ind

at Register

5

7

5

9

8

Mil

t_RH

Register Hold Time Relative to Clock Signal at Com’l/Ind

Register

12

Mil

t_LATCH

Flow-Through Latch Delay

Register Delay

Com’l/Ind

Mil

1

3

1

3

t_RD

Com’l/Ind

Mil

t_COMB

Transparent Mode Delay^[28]

Clock HIGH Time

Com’l/Ind

Mil

t_CH

Com’l/Ind

Mil

6

7

8

t_CL

Clock LOW Time

Com’l/Ind

Mil

t_IC

Asynchronous Clock Logic Delay

Synchronous Clock Delay

Feedback Delay

Com’l/Ind

Mil

7

1

5

8

2

1

6

10

3

t_ICS

Com’l/Ind

Mil

3

t_FD

Com’l/Ind

Mil

1

t_PRE

Asynchronous Register Preset Time

Com’l/Ind

Mil

9

Notes:

27. Sample tested only for an output change of 500 mV.

28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial

operation.

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CY7C344B

Typical Internal Switching Characteristics Over Operating Range^[7](continued)

7C344-15

7C344-20

7C344-25

Parameter

Description

Min. Max. Min. Max. Min. Max. Unit

t_CLR

Asynchronous Register Clear Time

Com’l/Ind

Mil

5

6

9

ns

t_PCW

Asynchronous Preset and Clear Pulse Width

Com’l/Ind

Mil

5

7

t_PCR

Asynchronous Preset and Clear Recovery Time Com’l/Ind

Mil

Switching Waveforms

External Combinatorial

DEDICATED INPUT/

I/O INPUT

t

/t

PD1 PD2

COMBINATORIAL

OUTPUT

t

ER

COMBINATORIAL OR

REGISTERED OUTPUT

HIGH-IMPEDANCE

THREE-STATE

t

EA

HIGH-IMPEDANCE

THREE-STATE

VALID OUTPUT

External Synchronous

DEDICATED INPUTS OR

REGISTERED FEEDBACK

t

S

t

H

t

WL

WH

SYNCHRONOUS

CLOCK

t

/t

t /t

RR PR

CO1

RW PW

ASYNCHRONOUS

CLEAR/PRESET

t

OH

t

/t

RO PO

REGISTERED

OUTPUTS

t

CO2

COMBINATORIAL OUTPUT FROM

[12]

REGISTERED FEEDBACK

Document #: 38-03006 Rev. *A

Page 9 of 16

USE ULTRA37000^TMFOR

ALL NEW DESIGNS

CY7C344B

Switching Waveforms (continued)

External Asynchronous

DEDICATED INPUTS OR

REGISTERED FEEDBACK

t

AWL

t

AS

AH

AWH

ASYNCHRONOUS

CLOCK INPUT

t

ACO1

t

/t

t

/t

RW PW

RR PR

ASYNCHRONOUS

CLEAR/PRESET

t

AOH

t

/t

RO PO

ACO2

ASYNCHRONOUS REGISTERED

OUTPUTS

t

COMBINATORIAL OUTPUT FROM

ASYNCH. REGISTERED

[19]

FEEDBACK

Internal Combinatorial

t

IN

INPUT PIN

t

PIA

t

IO

I/O PIN

t

EXP

EXPANDER

ARRAY DELAY

t

, t

LAC LAD

LOGIC ARRAY

INPUT

LOGIC ARRAY

OUTPUT

Document #: 38-03006 Rev. *A

Page 10 of 16

USE ULTRA37000^TMFOR

ALL NEW DESIGNS

CY7C344B

Switching Waveforms (continued)

Internal Asynchronous

t

AWL

AWH

t t

IOR

t

F

CLOCK PIN

t

IN

CLOCK INTO

LOGIC ARRAY

t

IC

CLOCK FROM

LOGIC ARRAY

t

RH

RSU

DATA FROM

LOGIC ARRAY

t

,t

t

FD

t

,t

t

FD

RD LATCH

CLR PRE

REGISTER OUTPUT

TO LOCAL LAB

LOGIC ARRAY

t

PIA

REGISTER OUTPUT

TO ANOTHER LAB

Internal Synchronous (Input Path)

t

CL

CH

SYSTEM CLOCK PIN

t

IN

t

ICS

SYSTEM CLOCK

AT REGISTER

t

RH

RSU

DATA FROM

LOGIC ARRAY

Internal Synchronous (Output Path)

CLOCK FROM

LOGIC ARRAY

t

OD

RD

DATA FROM

LOGIC ARRAY

t

XZ

t

ZX

HIGH Z

OUTPUT PIN

Document #: 38-03006 Rev. *A

Page 11 of 16

USE ULTRA37000^TMFOR

ALL NEW DESIGNS

CY7C344B

Ordering Information

Speed

Package

Operating

Range

(ns)

Ordering Code

Name

H64

J64

Package Type

15

CY7C344-15HC/HI

CY7C344-15JC/JI

CY7C344-15PC/PI

CY7C344-15WC/WI

CY7C344-20HC/HI

CY7C344-20JC/JI

CY7C344-20PC/PI

CY7C344-20WC/WI

CY7C344-20HMB

CY7C344-20WMB

CY7C344-25HC/HI

CY7C344-25JC/JI

CY7C344-25PC/PI

CY7C344-25WC/WI

CY7C344-25HMB

CY7C344-25WMB

28-Lead Windowed Leaded Chip Carrier

28-Lead Plastic Leaded Chip Carrier

28-Lead (300-Mil) Molded DIP

Commercial/Industrial

P21

W22

H64

J64

28-Lead Windowed CerDIP

20

25

28-Lead Windowed Leaded Chip Carrier

28-Lead Plastic Leaded Chip Carrier

28-Lead (300-Mil) Molded DIP

Commercial/Industrial

P21

W22

H64

W22

H64

J64

28-Lead Windowed CerDIP

28-Lead Windowed Leaded Chip Carrier

28-Lead Windowed CerDIP

Military

28-Lead Windowed Leaded Chip Carrier

28-Lead Plastic Leaded Chip Carrier

28-Lead (300-Mil) Molded DIP

Commercial/Industrial

P21

W22

H64

W22

28-Lead Windowed CerDIP

28-Lead Windowed Leaded Chip Carrier

28-Lead Windowed CerDIP

Military

MILITARY SPECIFICATIONS

Group A Subgroup Testing

Switching Characteristics

Parameter

Subgroups

t_PD1

t_PD2

t_PD3

t_CO1

t_S

7, 8, 9, 10, 11

DC Characteristics

Parameter

Subgroups

V_OH

V_OL

V_IH

V_IL

1, 2, 3

t_H

t_ACO1

t_AS

I_IX

I_OZ

I_CC1

t_AH

Document #: 38-03006 Rev. *A

Page 12 of 16

USE ULTRA37000^TMFOR

ALL NEW DESIGNS

CY7C344B

Package Diagrams

28-Pin Windowed Leaded Chip Carrier H64

51-80077-**

Document #: 38-03006 Rev. *A

Page 13 of 16

USE ULTRA37000^TMFOR

ALL NEW DESIGNS

CY7C344B

Package Diagrams (continued)

28-Lead Plastic Leaded Chip Carrier J64

51-85001-*A

28-Lead (300-Mil) PDIP P21

14

1

MIN.

DIMENSIONS IN INCHES[MM]

REFERENCE JEDEC MO-095

PART #

MAX.

0.260[6.60]

0.280[7.11]

P28.3

STANDARD PKG.

LEAD FREE PKG.

15

28

PZ28.3

0.030[0.76]

0.080[2.03]

SEATING PLANE

1.370[34.79]

1.425[36.19]

0.290[7.36]

0.325[8.25]

0.120[3.05]

0.140[3.55]

0.190[4.82]

0.009[0.23]

0.012[0.30]

0.115[2.92]

0.160[4.06]

3° MIN.

0.015[0.38]

0.060[1.52]

0.310[7.87]

0.385[9.78]

0.055[1.39]

0.065[1.65]

0.090[2.28]

0.110[2.79]

0.015[0.38]

0.020[0.50]

51-85014-*C

Document #: 38-03006 Rev. *A

Page 14 of 16

USE ULTRA37000^TMFOR

ALL NEW DESIGNS

CY7C344B

Package Diagrams (continued)

(300-Mil)

28-Lead

Windowed CerDIP W22

MIL-STD-1835 D-15 Config. A

51-80087-**

MAX and Warp are registered trademarks and Ultra37000, Warp Professional and Warp Enterprise are trademarks of Cypress

SemiconductorCorporation.All productsand company names mentionedinthisdocumentmaybethetrademarksoftheirrespective

holders.

Document #: 38-03006 Rev. *A

Page 15 of 16

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

USE ULTRA37000^TMFOR

ALL NEW DESIGNS

CY7C344B

Document History Page

Document Title: CY7C344 32-Macrocell MAX® EPLD

Document Number: 38-03006

Orig. of

REV.

**

ECN NO.

106271

213375

Issue Date

04/19/01

Change

Description of Change

SZV

Change from Spec number: 38-00127 to 38-03006

*A

See ECN

FSG

Added note to title page: “Use Ultra37000 For All New Designs”

Document #: 38-03006 Rev. *A

Page 16 of 16


型号：	CY7C344-15PC/PI
厂家：	CYPRESS
描述：	32-Macrocell MAX EPLD 32宏单元MAX EPLD
文件：	总16页 (文件大小：242K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C344-15PC/PI [CYPRESS]

相关型号：

CY7C344-15PI

CY7C344-15WC

CY7C344-15WC/WI

CY7C344-15WI

CY7C344-20DC

CY7C344-20DI

CY7C344-20HC/HI

CY7C344-20HI

CY7C344-20HMB

CY7C344-20JC

CY7C344-20JC/JI

CY7C344-20JCR