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CY7C4235-10JIT [CYPRESS]

FIFO, 2KX18, 8ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68;
CY7C4235-10JIT
型号： CY7C4235-10JIT
厂家： CYPRESS    CYPRESS
描述：

FIFO, 2KX18, 8ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68

先进先出芯片
文件： 总25页 (文件大小：412K)
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1CY7C4225  
fax id: 5410  
CY7C4425/4205/4215  
CY7C4225/4235/4245  
64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs  
controlled by a free-running clock (WCLK) and a write enable  
pin (WEN).  
Features  
• High-speed, low-power, first-in first-out (FIFO)  
When WEN is asserted, data is written into the FIFO on the  
rising edge of the WCLK signal. While WEN is held active, data  
is continually written into the FIFO on each cycle. The output  
port is controlled in a similar manner by a free-running read  
clock (RCLK) and a read enable pin (REN). In addition, the  
CY7C42X5 have an output enable pin (OE). The read and  
write clocks may be tied together for single-clock operation or  
the two clocks may be run independently for asynchronous  
read/write applications. Clock frequencies up to 100 MHz are  
achievable.  
memories  
• 64 x 18 (CY7C4425)  
• 256 x 18 (CY7C4205)  
• 512 x 18 (CY7C4215)  
• 1K x 18 (CY7C4225)  
• 2K x 18 (CY7C4235)  
• 4K x 18 (CY7C4245)  
• High-speed 100-MHz operation (10 ns read/write cycle  
time)  
Retransmit and Synchronous Almost Full/Almost Empty flag  
features are available on these devices.  
• Low power (I =45 mA)  
• Fully asynchronous and simultaneous read and write  
operation  
• Empty, Full, Half Full, and Programmable Almost  
Empty/Almost Full status flags  
• TTL-compatible  
• Retransmit function  
• Output Enable (OE) pin  
• Independent read and write enable pins  
• Center power and ground for reduced noise  
• Supports free-running 50% duty cycle clock inputs  
• Width Expansion Capability  
CC  
Depth expansion is possible using the cascade input (WXI,  
RXI), cascade output (WXO, RXO), and First Load (FL) pins.  
The WXO and RXO pins are connected to the WXI and RXI  
pins of the next device, and the WXO and RXO pins of the last  
device should be connected to the WXI and RXI pins of the  
first device. The FL pin of the first device is tied to V and the  
SS  
FL pin of all the remaining devices should be tied to V  
.
CC  
The CY7C42X5 provides five status pins. These pins are de-  
coded to determine one of five states: Empty, Almost Empty,  
Half Full, Almost Full, and Full (see Table 2). The Half Full flag  
shares the WXO pin. This flag is valid in the standalone and  
width-expansion configurations. In the depth expansion, this  
pin provides the expansion out (WXO) information that is used  
to signal the next FIFO when it will be activated.  
• Depth Expansion Capability  
• Space saving 64-pin 10x10 TQFP, and 14x14 TQFP  
• 68-pin PLCC  
The Empty and Full flags are synchronous, i.e., they change  
state relative to either the read clock (RCLK) or the write clock  
(WCLK). When entering or exiting the Empty states, the flag is  
updated exclusively by the RCLK. The flag denoting Full states  
is updated exclusively by WCLK. The synchronous flag archi-  
tecture guarantees that the flags will remain valid from one  
clock cycle to the next. As mentioned previously, the Almost  
Empty/Almost Full flags become synchronous if the  
Functional Description  
The CY7C42X5 are high-speed, low-power, first-in first-out  
(FIFO) memories with clocked read and write interfaces. All  
are 18 bits wide and are pin/functionally compatible to  
IDT722x5. The CY7C42X5 can be cascaded to increase FIFO  
depth. Programmable features include Almost Full/Almost  
Empty flags. These FIFOs provide solutions for a wide variety  
of data buffering needs, including high-speed data acquisition,  
multiprocessor interfaces, and communications buffering.  
V
/SMODE is tied to V . All configurations are fabricated  
CC  
SS  
using an advanced 0.65µ N-Well CMOS technology. Input  
ESD protection is greater than 2001V, and latch-up is prevent-  
ed by the use of guard rings.  
These FIFOs have 18-bit input and output ports that are con-  
trolled by separate clock and enable signals. The input port is  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
April 1995 - Revised August 18, 1997  
CY7C4425/4205/4215  
CY7C4225/4235/4245  
D
0 –17  
Logic Block Diagram  
INPUT  
REGISTER  
WCLK  
WEN  
FLAG  
PROGRAM  
REGISTER  
WRITE  
CONTROL  
DUAL PORT  
RAM ARRAY  
FF  
EF  
FLAG  
LOGIC  
64 x 18  
256 x 18  
512 x 18  
1K x 18  
2K x 18  
4K x 18  
PAE  
PAF  
SMODE  
WRITE  
POINTER  
READ  
POINTER  
RS  
RESET  
LOGIC  
FL/RT  
THREE–STATE  
READ  
CONTROL  
WXI  
WXO/HF  
RXI  
OUTPUT REGISTER  
EXPANSION  
LOGIC  
OE  
RXO  
42X5–1  
Q
0 –17  
RCLK  
REN  
Pin Configurations  
PLCC  
Top View  
TQFP  
Top View  
9
8
7
6
5
4
3
2 1 68 67 66 65 64 63 62 61  
V
/SMODE  
D
D
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
CC  
14  
13  
Q
Q
48  
47  
D
1
2
14  
15  
Q
14  
13  
D
14  
13  
D
12  
Q
GND  
D
13  
46  
45  
3
4
D
D
11  
10  
GND  
Q
12  
D
12  
Q
12  
Q
V
44  
43  
42  
41  
11  
D
D
5
6
7
8
9
10  
11  
12  
13  
11  
10  
CY7C4425  
CY7C4205  
CY7C4215  
CY7C4225  
CY7C4235  
CY7C4245  
CY7C4425  
CY7C4205  
CY7C4215  
CY7C4225  
CY7C4235  
CY7C4245  
D
9
Q
11  
CC  
V
CC  
V
CC  
Q
10  
D
9
D
8
Q
10  
Q
9
D
D
8
GND  
Q
9
GND  
40  
39  
7
D
D
7
6
GND  
Q
8
D
6
5
Q
8
38  
37  
36  
Q
7
D
D
D
3
D
5
21  
22  
23  
24  
25  
26  
Q
7
V
CC  
Q
6
4
D
4
Q
5
D
D
D
3
D
35  
34  
Q
6
47  
46  
45  
44  
14  
15  
GND  
2
Q
4
Q
5
2
D
D
1
33  
V
CC  
16  
0
1
GND  
Q
D
0
4
2728 2930 3132 33 34 35 36 37 38 3940 4142 43  
42X5–3  
42x5–2  
2
CY7C4425/4205/4215  
CY7C4225/4235/4245  
Selection Guide  
7C42X5-10  
7C42X5-15  
7C42X5-25  
7C42X5-35  
Maximum Frequency (MHz)  
Maximum Access Time (ns)  
Minimum Cycle Time (ns)  
100  
8
66.7  
10  
15  
4
40  
15  
25  
6
28.6  
20  
35  
7
10  
3
Minimum Data or Enable Set-Up (ns)  
Minimum Data or Enable Hold (ns)  
Maximum Flag Delay (ns)  
0.5  
8
1
1
2
10  
45  
50  
15  
45  
50  
20  
45  
50  
Operating Current (I  
(mA) @ freq=20MHz  
)
Commercial  
Industrial  
45  
50  
CC2  
CY7C4425  
CY7C4205  
CY7C4215  
CY7C4225  
CY7C4235  
CY7C4245  
Density  
64 x 18  
256 x 18  
512 x 18  
1K x 18  
2K x 18  
4K x 18  
Packages  
68-pin PLCC  
64-pin TQFP  
(10x10/14x14)  
68-pin PLCC  
64-pin TQFP  
(10x10/14x14)  
68-pin PLCC  
64-pin TQFP  
(10x10/14x14)  
68-pin PLCC  
64-pin TQFP  
(10x10/14x14)  
68-pin PLCC  
64-pin TQFP  
(10x10/14x14)  
68-pin PLCC  
64-pin TQFP  
(10x10/14x14)  
Pin Definitions  
Signal Name  
Description  
I/O  
Function  
D
Data Inputs  
Data Outputs  
Write Enable  
Read Enable  
Write Clock  
I
O
I
Data inputs for an 18-bit bus  
Data outputs for an 18-bit bus  
Enables the WCLK input  
Enables the RCLK input  
0–17  
Q
0–17  
WEN  
REN  
I
WCLK  
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not  
Full. When LD is asserted, WCLK writes data into the programmable flag-offset  
register.  
RCLK  
Read Clock  
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not  
Empty. When LD is asserted, RCLK reads data out of the programmable flag-off-  
set register.  
WXO/HF  
Write Expansion  
Out/Half Full Flag  
O
Dual-Mode Pin:  
Single device or width expansion - Half Full status flag.  
Cascaded - Write Expansion Out signal, connected to WXI of next device.  
EF  
Empty Flag  
Full Flag  
O
O
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.  
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.  
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset  
FF  
PAE  
Programmable  
Almost Empty  
value programmed into the FIFO. PAE is asynchronous when V /SMODE is tied  
CC  
to V ; it is synchronized to RCLK when V /SMODE is tied to V .  
CC  
CC  
SS  
PAF  
Programmable  
Almost Full  
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value  
programmed into the FIFO. PAF is asynchronous when V /SMODE is tied to  
CC  
V
; it is synchronized to WCLK when V /SMODE is tied to V  
.
CC  
CC  
SS  
LD  
Load  
I
I
When LD is LOW, D  
ble-flag-offset register.  
(O  
) are written (read) into (from) the programma-  
0 - 17  
0 - 17  
FL/RT  
First Load/  
Retransmit  
Dual-Mode Pin:  
Cascaded - The first device in the daisy chain will have FL tied to V ; all other  
SS  
devices will have FL tied to V . In standard mode of width expansion, FL is tied  
CC  
to V on all devices.  
SS  
Not Cascaded - Tied to V . Retransmit function is also available in standalone  
SS  
mode by strobing RT.  
WXI  
Write Expansion  
Input  
I
Cascaded - Connected to WXO of previous device.  
Not Cascaded - Tied to V  
.
SS  
3
CY7C4425/4205/4215  
CY7C4225/4235/4245  
Pin Definitions (continued)  
Signal Name  
Description  
I/O  
Function  
Cascaded - Connected to RXO of previous device.  
RXI  
Read Expansion  
Input  
I
Not Cascaded - Tied to V  
.
SS  
RXO  
RS  
Read Expansion  
Output  
O
I
Cascaded - Connected to RXI of next device.  
Reset  
Resets device to empty condition. A reset is required before an initial read or write  
operation after power-up.  
OE  
Output Enable  
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are con-  
nected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.  
V
/SMODE Synchronous  
Almost Empty/  
I
Dual-Mode Pin  
Asynchronous Almost Empty/Almost Full flags - tied to V  
CC  
.
CC  
Almost Full Flags  
Synchronous Almost Empty/Almost Full flags - tied to V  
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)  
.
SS  
Output Current into Outputs (LOW)............................. 20 mA  
Static Discharge Voltage ........................................... >2001V  
(per MIL-STD-883, Method 3015)  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Latch-Up Current..................................................... >200 mA  
Storage Temperature ....................................−65°C to +150°C  
Ambient Temperature with  
Power Applied.................................................−55°C to +125°C  
Operating Range  
Ambient  
Supply Voltage to Ground Potential .................−0.5V to +7.0V  
Range  
Temperature  
0°C to +70°C  
−40°C to +85°C  
V
CC  
DC Voltage Applied to Outputs  
in High Z State.....................................................−0.5V to +7.0V  
Commercial  
5V ± 10%  
5V ± 10%  
[1]  
Industrial  
DC Input Voltage .................................................−3.0V to +7.0V  
Electrical Characteristics Over the Operating Range  
[2]  
7C42X5-10 7C42X5-15 7C42X5-25 7C42X5-35  
Parameter  
Description  
Test Conditions  
Min. Max. Min. Max. Min. Max. Min. Max. Unit  
V
Output HIGH Voltage  
V
= Min.,  
= −2.0 mA  
2.4  
2.4  
2.4  
2.4  
V
OH  
CC  
I
OH  
V
Output LOW Voltage  
V
= Min.,  
0.4  
0.4  
0.4  
0.4  
V
OL  
CC  
I
= 8.0 mA  
OL  
[3]  
V
V
Input HIGH Voltage  
Input LOW Voltage  
2.2  
−3.0  
−10  
V
2.2  
−3.0  
−10  
V
2.2  
−3.0  
−10  
V
2.2  
−3.0  
−10  
V
V
V
IH  
[3]  
CC  
CC  
CC  
CC  
0.8  
0.8  
0.8  
0.8  
IL  
I
Input Leakage  
Current  
V
= Max.  
= Max.,  
+10  
+10  
+10  
+10  
µA  
IX  
CC  
[4]  
I
Output Short  
Circuit Current  
V
V
−90  
−10  
−90  
−10  
−90  
−10  
−90  
−10  
mA  
OS  
CC  
= GND  
OUT  
I
I
Output OFF,  
High Z Current  
OE > V ,  
V
+10  
+10  
+10  
+10  
µA  
OZL  
OZH  
IH  
< V < V  
SS  
O
CC  
[5]  
I
Operating Current  
Standby Current  
V
= Max.,  
= 0 mA  
Com’l  
Ind  
45  
50  
10  
15  
45  
50  
10  
15  
45  
50  
10  
15  
45  
50  
10  
15  
mA  
mA  
mA  
mA  
CC2  
CC  
I
OUT  
[6]  
I
V
= Max.,  
= 0 mA  
Com’l  
Ind  
SB  
CC  
I
OUT  
Notes:  
1. TA is the “instant on” case temperature.  
2. See the last page of this specification for Group A subgroup testing information.  
3. The VIH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the  
previous device or VSS  
.
4. Test no more than one output at a time for not more than one second.  
5. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz.  
Outputs are unloaded.  
6. All input signals are connected to VCC. All outputs are unloaded.  
4
CY7C4425/4205/4215  
CY7C4225/4235/4245  
Capacitance[7]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
Max.  
Unit  
pF  
C
T = 25°C, f = 1 MHz,  
5
7
IN  
A
V
= 5.0V  
CC  
C
pF  
OUT  
AC Test Loads and Waveforms[8, 9]  
R11.1K Ω  
5V  
ALL INPUT PULSES  
OUTPUT  
3.0V  
90%  
10%  
90%  
10%  
R2  
680Ω  
C
GND  
< 3 ns  
L
< 3 ns  
INCLUDING  
JIG AND  
SCOPE  
42X5–4  
42X5–5  
Equivalentto:  
THEÉVENIN EQUIVALENT  
410Ω  
OUTPUT  
1.91V  
Notes:  
7. Tested initially and after any design or process changes that may affect these parameters.  
8.  
9.  
C
C
L = 30 pF for all AC parameters except for tOHZ  
.
L = 5 pF for tOHZ  
.
Switching Characteristics Over the Operating Range  
7C42X5-10 7C42X5-15 7C42X5-25 7C42X5-35  
Parameter  
Description  
Clock Cycle Frequency  
Min. Max. Min. Max. Min. Max. Min. Max. Unit  
t
100  
8
66.7  
10  
40  
15  
28.6 MHz  
20  
S
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Data Access Time  
Clock Cycle Time  
Clock HIGH Time  
Clock LOW Time  
Data Set-Up Time  
Data Hold Time  
2
10  
4.5  
4.5  
3
2
15  
6
2
25  
10  
10  
6
2
35  
14  
14  
7
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
A
CLK  
CLKH  
CLKL  
DS  
6
4
0.5  
3
1
1
2
DH  
Enable Set-Up Time  
Enable Hold Time  
4
6
7
ENS  
ENH  
RS  
0.5  
10  
8
1
1
2
[10]  
Reset Pulse Width  
15  
10  
25  
15  
35  
20  
Reset Recovery Time  
RSR  
RSF  
PRT  
RTR  
OLZ  
OE  
Reset to Flag and Output Time  
Retransmit Pulse Width  
10  
15  
25  
35  
12  
12  
0
15  
15  
0
25  
25  
0
35  
35  
0
Retransmit Recovery Time  
Output Enable to Output in Low Z  
Output Enable to Output Valid  
[11]  
3
7
7
3
8
3
12  
12  
15  
15  
20  
3
15  
15  
20  
20  
25  
[12]  
Output Enable to Output in High Z  
Write Clock to Full Flag  
3
3
8
3
3
OHZ  
WFF  
REF  
PAFasynch  
8
10  
10  
16  
Read Clock to Empty Flag  
8
[12]  
Clock to Programmable Almost-Full Flag  
12  
(Asynchronous mode, V /SMODE tied to V  
)
CC  
CC  
5
CY7C4425/4205/4215  
CY7C4225/4235/4245  
Switching Characteristics Over the Operating Range (continued)  
7C42X5-10 7C42X5-15 7C42X5-25 7C42X5-35  
Parameter  
Description  
Min. Max. Min. Max. Min. Max. Min. Max. Unit  
t
Clock to Programmable Almost-Full Flag  
8
12  
8
10  
16  
10  
15  
20  
15  
20  
25  
20  
ns  
ns  
ns  
PAFsynch  
PAEasynch  
PAEsynch  
(Synchronous mode, V /SMODE tied to V  
)
)
CC  
SS  
[12]  
t
t
Clock to Programmable Almost-Empty Flag  
(Asynchronous mode, V /SMODE tied to V  
)
CC  
CC  
Clock to Programmable Almost-Full Flag  
(Synchronous mode, V /SMODE tied to V  
CC  
SS  
t
t
t
t
t
Clock to Half-Full Flag  
12  
7
16  
10  
20  
15  
25  
20  
ns  
ns  
ns  
ns  
ns  
HF  
Clock to Expansion Out  
Expansion in Pulse Width  
Expansion in Set-Up Time  
XO  
3
4.5  
5
6.5  
5
10  
10  
10  
14  
15  
12  
XI  
XIS  
Skew Time between Read Clock and Write  
Clock for Full Flag  
6
SKEW1  
t
t
Skew Time between Read Clock and Write  
Clock for Empty Flag  
5
6
10  
18  
12  
20  
ns  
ns  
SKEW2  
SKEW3  
Skew Time between Read Clock and Write  
Clock for Programmable Almost Empty and Pro-  
grammable Almost Full Flags.  
10  
15  
Switching Waveforms  
Write Cycle Timing  
t
CLK  
t
t
CLKL  
CLKH  
WCLK  
t
t
DH  
DS  
D –D  
0
17  
t
ENH  
t
ENS  
WEN  
FF  
NO OPERATION  
t
t
WFF  
WFF  
[13]  
t
SKEW1  
RCLK  
REN  
42X5–6  
Notes:  
10. Pulse widths less than minimum values are not allowed.  
11. Values guaranteed by design, not currently tested.  
12. PAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E)  
.
13. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the  
rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.  
6
CY7C4425/4205/4215  
CY7C4225/4235/4245  
Switching Waveforms (continued)  
Read Cycle Timing  
t
CLK  
t
t
CLKL  
CLKH  
RCLK  
REN  
t
t
ENH  
ENS  
NO OPERATION  
t
REF  
t
REF  
EF  
t
A
VALID DATA  
Q
–Q  
17  
0
t
OLZ  
t
OHZ  
t
OE  
OE  
[14]  
t
SKEW2  
WCLK  
WEN  
42X5–7  
[15]  
Reset Timing  
t
RS  
RS  
t
RSR  
REN,WEN,  
LD  
t
t
t
RSF  
RSF  
RSF  
EF,PAE  
FF,PAF,  
HF  
[16]  
OE=1  
Q
Q
17  
0 -  
OE=0  
42X5–8  
Notes:  
14. .tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the  
rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge.  
15. The clocks (RCLK, WCLK) can be free-running during reset.  
16. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.  
7
CY7C4425/4205/4215  
CY7C4225/4235/4245  
Switching Waveforms (continued)  
First Data Word Latency after Reset with Simultaneous Read and Write  
WCLK  
t
DS  
D –D  
0
D
0
(FIRSTVALIDWRITE)  
D
1
D
2
D
3
D
4
17  
t
ENS  
[17]  
FRL  
t
WEN  
t
SKEW2  
RCLK  
t
REF  
EF  
REN  
–Q  
[18]  
t
A
t
A
Q
D
D
1
0
17  
0
t
OLZ  
t
OE  
OE  
42X5–9  
Empty Flag Timing  
WCLK  
t
t
DS  
DS  
D0  
D1  
D –D  
0
17  
t
t
ENH  
ENH  
t
t
ENS  
ENS  
WEN  
[17]  
FRL  
t
[17]  
FRL  
t
RCLK  
t
t
t
REF  
t
REF  
t
SKEW2  
REF  
SKEW2  
EF  
REN  
OE  
t
A
D0  
Q
–Q  
17  
0
42X5–10  
Notes:  
17. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2  
.
The Latency Timing applies only at the Empty Boundary (EF = LOW).  
18. The first word is available the cycle after EF goes HIGH, always.  
8
CY7C4425/4205/4215  
CY7C4225/4235/4245  
Switching Waveforms (continued)  
Full Flag Timing  
NO WRITE  
NO WRITE  
WCLK  
[13]  
[13]  
t
t
DS  
DATA WRITE  
t
SKEW1  
SKEW1  
DATA WRITE  
D –D  
0
17  
t
t
t
WFF  
WFF  
WFF  
FF  
WEN  
RCLK  
t
t
ENH  
ENH  
t
t
ENS  
ENS  
REN  
OE  
LOW  
t
A
t
A
DATAREAD  
NEXT DATA READ  
DATA IN OUTPUT REGISTER  
Q
–Q  
17  
0
42X5–11  
Half-Full Flag Timing  
t
t
CLKL  
CLKH  
WCLK  
WEN  
t
t
ENH  
ENS  
t
HF  
HALF FULL+1  
OR MORE  
HALF FULL OR LESS  
HALF FULL OR LESS  
HF  
t
HF  
RCLK  
REN  
t
ENS  
42X5–12  
9
CY7C4425/4205/4215  
CY7C4225/4235/4245  
Switching Waveforms (continued)  
Programmable Almost Empty  
Timing  
Flag  
t
t
CLKL  
CLKH  
WCLK  
t
t
ENS ENH  
WEN  
[19]  
t
PAE  
]
n+1 WORDS  
IN FIFO  
PAE  
n WORDS IN FIFO  
t
PAE  
RCLK  
REN  
t
ENS  
42X5–13  
Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)  
t
t
CLKL  
CLKH  
WCLK  
WEN  
t
t
ENS ENH  
WEN2  
PAE  
t
t
ENS ENH  
Note  
20  
N + 1 WORDS  
INFIFO  
Note  
22  
t
PAEsynch  
[21]  
t
t
SKEW3  
PAEsynch  
RCLK  
REN  
t
ENS  
t
t
ENS ENH  
42X5–14  
Notes:  
19. PAE offset – n. Number of data words into FIFO already = n.  
20. PAE offset – n.  
21.  
tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the  
rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK.  
22. If a read is performed on this rising edge of the read clock, there will be Empty + (n – 1) words in the FIFO when PAE goes LOW.  
10  
CY7C4425/4205/4215  
CY7C4225/4235/4245  
Switching Waveforms (continued)  
Programmable Almost Full Flag Timing  
t
t
CLKL  
CLKH  
23  
Note  
WCLK  
WEN  
t
t
ENS ENH  
t
PAF  
FULL − M WORDS  
[25]  
IN FIFO  
[24]  
FULL − M + 1 WORDS  
PAF  
[26]  
IN FIFO  
t
PAF  
RCLK  
REN  
t
ENS  
42X5–15  
Programmable Almost Full Flag Timing (applies only in SMODE (SMODE in LOW))  
Note  
27  
t
t
CLKL  
CLKH  
WCLK  
WEN  
t
t
ENS ENH  
Note  
28  
WEN2  
PAF  
t
t
t
PAF  
ENS ENH  
FULL − M WORDS  
[29]  
IN FIFO  
FULL- M+1Ω ORDS  
INFIFO  
t
[30]  
PAFsynch  
t
SKEW3  
RCLK  
REN  
t
ENS  
t
t
ENS ENH  
42X5–16  
Notes:  
23. PAF offset = m. Number of data words written into FIFO already = 64 – m + 1 for the CY7C4425, 256 – m + 1 for the CY7C4205, 512 – m + 1 for the  
CY7C4215. 1024 – m + 1 for the CY7C4225, 2048 – m + 1 for the CY7C4235, and 4096 – m + 1 for the CY7C4245.  
24. PAF is offset = m.  
25. 64 – m words in CY7C4425, 256 – m words inCY7C4205, 512 – m word in CY7C4215. 1024 – m words in CY7C4225, 2048 – m words in CY7C4235, and  
4096 – m words in CY7C4245.  
26. 64 – m + 1 words in CY7C4425, 256 – m + 1 words in CY7C4205, 512 – m +1 words in CY7C4215, 1024 – m + 1 CY7C4225, 2048 – m + 1 in CY74235,  
and 4096 – m + 1 words in CY7C4245.  
27. If a write is performed on this rising edge of the write clock, there will be Full – (m – 1) words of the FIFO when PAF goes LOW.  
28. PAF offset = m.  
29. 64 – m words in CY7C4425, 256 – m words in FIFO for CY7C4205, 512 – m word in CY7C4215. 1024 – m words in CY7C4225, 2048 – m words in CY7C4235,  
and 4096 – m words in CY7C4245.  
30.  
tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK and the  
rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge.  
11  
CY7C4425/4205/4215  
CY7C4225/4235/4245  
Switching Waveforms (continued)  
Write Programmable Registers  
t
CLK  
t
t
CLKL  
CLKH  
WCLK  
LD  
t
t
ENS  
ENH  
t
ENS  
WEN  
t
t
DH  
DS  
PAE OFFSET  
D –D  
D –D  
0
17  
PAE OFFSET  
PAF OFFSET  
0
11  
42X5–17  
Read Programmable Registers  
t
CLK  
t
t
CLKL  
CLKH  
RCLK  
LD  
t
t
t
ENS  
ENH  
ENS  
WEN  
t
A
UNKNOWN  
PAE OFFSET  
PAF OFFSET  
PAE OFFSET  
Q
–Q  
17  
0
42X5–18  
Write Expansion Out Timing  
t
CLKH  
WCLK  
Note 31  
t
XO  
WXO  
WEN  
t
XO  
t
ENS  
42X5–19  
Note:  
31. Write to Last Physical Location.  
12  
CY7C4425/4205/4215  
CY7C4225/4235/4245  
Switching Waveforms (continued)  
Read Expansion Out Timing  
t
CLKH  
WCLK  
Note 32  
t
XO  
RXO  
REN  
t
XO  
t
ENS  
42X5–20  
Write Expansion InTiming  
t
XI  
WXI  
t
XIS  
WCLK  
42X5–21  
Read Expansion In Timing  
t
XI  
RXI  
t
XIS  
RCLK  
42X5–22  
[33, 34, 35]  
Retransmit Timing  
FL/RT  
t
PRT  
t
RTR  
REN/WEN  
EF/FF  
and all  
async flags  
HF/PAE/PAF  
42X5–23  
Notes:  
32. Read from Last Physical Location.  
33. Clocks are free running in this case.  
34. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR  
.
35. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags.  
13  
CY7C4425/4205/4215  
CY7C4225/4235/4245  
Architecture  
Table 1. Write Offset Register  
[36]  
The CY7C42X5 consists of an array of 64 to 4K words of 18  
bits each (implemented by a dual-port array of SRAM cells), a  
read pointer, a write pointer, control signals (RCLK, WCLK,  
REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The  
CY7C42X5 also includes the control signals WXI, RXI, WXO,  
RXO for depth expansion.  
LD WEN WCLK  
Selection  
0
0
Writing to offset registers:  
Empty Offset  
Full Offset  
0
1
1
0
1
No Operation  
Write Into FIFO  
No Operation  
Resetting the FIFO  
Upon power-up, the FIFO must be reset with a Reset (RS)  
cycle. This causes the FIFO to enter the Empty condition sig-  
nified by EF being LOW. All data outputs go LOW after the  
falling edge of RS only if OE is asserted. In order for the FIFO  
to reset to its default state, a falling edge must occur on RS  
and the user must not read or write while RS is LOW.  
1
Note:  
36. The same selection sequence applies to reading from the registers. REN  
is enabled and read is performed on the LOW-to-HIGH transition of RCLK.  
FIFO Operation  
Flag Operation  
When the WEN signal is active (LOW), data present on the  
D
pins is written into the FIFO on each rising edge of the  
0–17  
The CY7C42X5 devices provide five flag pins to indicate the  
condition of the FIFO contents. Empty and Full are synchro-  
WCLK signal. Similarly, when the REN signal is active LOW,  
data in the FIFO memory will be presented on the Q out-  
puts. New data will be presented on each rising edge of RCLK  
while REN is active LOW and OE is LOW. REN must set up  
tENS before RCLK for it to be a valid read function. WEN must  
occur tENS before WCLK for it to be a valid write function.  
0–17  
nous. PAE and PAF are synchronous if V /SMODE is tied to  
CC  
V
.
SS  
Full Flag  
The Full Flag (FF) will go LOW when device is Full. Write op-  
erations are inhibited whenever FF is LOW regardless of the  
state of WEN. FF is synchronized to WCLK, i.e., it is exclusive-  
ly updated by each rising edge of WCLK.  
An output enable (OE) pin is provided to three-state the Q  
outputs when OE is deasserted. When OE is enabled (LOW),  
data in the output register will be available to the Q  
after t . If devices are cascaded, the OE function will only  
0–17  
outputs  
0–17  
OE  
Empty Flag  
output data on the FIFO that is read enabled.  
The Empty Flag (EF) will go LOW when the device is empty.  
Read operations are inhibited whenever EF is LOW, regard-  
less of the state of REN. EF is synchronized to RCLK, i.e., it is  
exclusively updated by each rising edge of RCLK.  
The FIFO contains overflow circuitry to disallow additional  
writes when the FIFO is full, and underflow circuitry to disallow  
additional reads when the FIFO is empty. An empty FIFO  
maintains the data of the last valid read on its Q  
even after additional reads occur.  
outputs  
0–17  
Programmable Almost Empty/Almost Full Flag  
Programming  
The CY7C42X5 features programmable Almost Empty and Al-  
most Full Flags. Each flag can be programmed (described in  
the Programming section) a specific distance from the corre-  
sponding boundary flags (Empty or Full). When the FIFO con-  
tains the number of words or fewer for which the flags have  
been programmed, the PAF or PAE will be asserted, signifying  
that the FIFO is either Almost Full or Almost Empty. See Table  
2 for a description of programmable flags.  
The CY7C42X5 devices contain two 12-bit offset registers.  
Data present on D during a program write will determine  
the distance from Empty (Full) that the Almost Empty (Almost  
Full) flags become active. If the user elects not to program the  
FIFO’s flags, the default offset values are used (see Table 2).  
When the Load LD pin is set LOW and WEN is set LOW, data  
0–11  
on the inputs D  
is written into the Empty offset register on  
0–11  
When the SMODE pin is tied LOW, the PAF flag signal transi-  
tion is caused by the rising edge of the write clock and the PAE  
flag transition is caused by the rising edge of the read clock.  
the first LOW-to-HIGH transition of the write clock (WCLK).  
When the LD pin and WEN are held LOW then data is written  
into the Full offset register on the second LOW-to-HIGH tran-  
sition of the write clock (WCLK). The third transition of the write  
clock (WCLK) again writes to the Empty offset register (see  
Table 1). Writing all offset registers does not have to occur at  
one time. One or two offset registers can be written and then,  
by bringing the LD pin HIGH, the FIFO is returned to normal  
read/write operation. When the LD pin is set LOW, and WEN  
is LOW, the next offset register in sequence is written.  
Retransmit  
The retransmit feature is beneficial when transferring packets  
of data. It enables the receipt of data to be acknowledged by  
the receiver and retransmitted if necessary.  
The Retransmit (RT) input is active in the standalone and width  
expansion modes. The retransmit feature is intended for use  
when a number of writes equal to or less than the depth of the  
FIFO have occurred since the last RS cycle. A HIGH pulse on  
RT resets the internal read pointer to the first physical location  
of the FIFO. WCLK and RCLK may be free running but must  
The contents of the offset registers can be read on the output  
lines when the LD pin is set LOW and REN is set LOW; then,  
data can be read on the LOW-to-HIGH transition of the read  
clock (RCLK).  
be disabled during and t  
after the retransmit pulse. With  
RTR  
14  
CY7C4425/4205/4215  
CY7C4225/4235/4245  
every valid read cycle after retransmit, previously accessed  
data is read and the read pointer is incremented until it is equal  
to the write pointer. Flags are governed by the relative loca-  
tions of the read and write pointers and are updated during a  
retransmit cycle. Data written to the FIFO after activation of RT  
are transmitted also.  
The full depth of the FIFO can be repeatedly retransmitted.  
Table 2. Flag Truth Table.  
Number of Words in FIFO  
7C4425 - 64 x 18  
7C4205 - 256 x 18  
7C4215 - 512 x 18  
FF  
H
H
H
H
H
L
PAF  
H
HF  
H
H
H
L
PAE  
L
EF  
L
0
0
0
[37  
[37]  
[37]  
1 to n  
1 to n  
1 to n  
H
L
H
H
H
H
H
(n+1) to 32  
33 to (64 – (m+1))  
(n+1) to 128  
129 to (256 – (m+1))  
(n+1) to 256  
257 to (512 – (m+1))  
H
H
H
H
[38]  
[38]  
[38]  
(64 – m) to 63  
(256 – m) to 255  
(512 – m) to 511  
L
L
H
64  
256  
512  
L
L
H
Number of Words in FIFO  
7C4225 - 1K x 18  
7C4235 - 2K x 18  
7C4245 - 4K x 18  
FF  
H
H
H
H
H
L
PAF  
H
HF  
H
H
H
L
PAE  
L
EF  
L
0
0
0
[37]  
[37]  
[37]  
1 to n  
1 to n  
1 to n  
H
L
H
H
H
H
H
(n+1) to 512  
(n+1) to 1024  
(n+1) to 2048  
H
H
513 to (1024 – (m+1))  
1025 to (2048 – (m+1))  
2049 to (4096 – (m+1))  
H
H
[38]  
[38]  
[38]  
(1024 – m) to 1023  
(2048 – m) to 2047  
(4096 – m) to 4095  
L
L
H
1024  
2048  
4096  
L
L
H
Notes:  
37. n = Empty Offset (Default Values: CY7C4425 n = 7, CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/7C4235/7C4245 n = 127).  
38. m = Full Offset (Default Values: CY7C4425 n = 7, CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/7C4235/7C4245 n = 127).  
are available. Empty (Full) flags should be created by ANDing  
the Empty (Full) flags of every FIFO. This technique will avoid  
ready data from the FIFO that is “staggered” by one clock cycle  
due to the variations in skew between RCLK and WCLK.  
Figure 1 demonstrates a 36-word width by using two CY7C42X5.  
Width Expansion Configuration  
The CY7C42X5 can be expanded in width to provide word  
widths greater than 18 in increments of 18. During width ex-  
pansion mode all control line inputs are common and all flags  
RESET(RS)  
RESET(RS)  
DATAIN (D)  
36  
18  
18  
READCLOCK(RCLK)  
READENABLE(REN)  
WRITECLOCK(WCLK)  
WRITEENABLE(WEN)  
OUTPUTENABLE (OE)  
LOAD (LD)  
PROGRAMMABLE(PAE)  
HALF FULL FLAG (HF)  
7C4425  
PROGRAMMABLE(PAF)  
EMPTYFLAG (EF)  
7C4205  
7C4215  
7C4225  
7C4235  
7C4235  
7C4425  
7C4205  
7C4215  
7C4225  
7C4235  
7C4235  
EF  
FF  
FF  
EF  
DATAOUT (Q)  
18  
36  
FULL FLAG (FF)  
18  
FIRSTLOAD (FL)  
WRITE EXPANSION IN (WXI)  
READ EXPANSION IN (RXI)  
42X5–24  
Figure 1. Block Diagram of 64x36/256 x 36/512 x 36/1024 x 36/2048 x 36/4096 x 36 Synchronous FIFO Memory Used in a  
Width Expansion Configuration.  
15  
CY7C4425/4205/4215  
CY7C4225/4235/4245  
3. The Write Expansion Out (WXO) pin of each device must be  
tied to the Write Expansion In (WXI) pin of the next device.  
Depth Expansion Configuration  
(with Programmable Flags)  
4. The Read Expansion Out (RXO) pin of each device must be  
tied to the Read Expansion In (RXI) pin of the next device.  
The CY7C42X5 can easily be adapted to applications requir-  
ing more than 64/256/512/1024/2048/4096 words of buffering.  
Figure 2 shows Depth Expansion using three CY7C42X5s. Maxi-  
mum depth is limited only by signal loading. Follow these steps:  
5. All Load (LD) pins are tied together.  
6. The Half-Full Flag (HF) is not available in the Depth Expansion  
Configuration.  
1. The first device must be designated by grounding the First  
Load (FL) control input.  
7. EF, FF, PAE, and PAF are created with composite flags by  
ORing together these respective flags for monitoring. The  
composite PAE and PAF flags are not precise.  
2. All other devices must have FL in the HIGH state.  
WXO RXO  
7C4425  
7C4205  
7C4215  
7C4225  
7C4235  
7C4235  
V
CC  
FIRSTLOAD(FL)  
FF  
EF  
PAE  
PAF  
WXI RXI  
WXO RXO  
7C4425  
7C4205  
7C4215  
7C4225  
7C4235  
7C4235  
DATAIN (D)  
DATAOUT(Q)  
V
CC  
FIRSTLOAD(FL)  
FF  
PAF  
EF  
PAE  
WXI RXI  
WRITECLOCK(WCLK)  
WRITE ENABLE(WEN)  
READCLOCK(RCLK)  
READ ENABLE (REN)  
WXO RXO  
7C4425  
7C4205  
7C4215  
7C4225  
7C4235  
7C4235  
RESET(RS)  
OUTPUT ENABLE(OE)  
LOAD(LD)  
FF  
EF  
FF  
EF  
PAE  
PAE  
PAF  
PAF  
WXI RXI  
42X5–23  
FIRSTLOAD(FL)  
Figure 2. Block Diagram of 192 x 18/768 x 18/1536 x 18/3072 x 18/12288 x 18 Synchronous FIFO Memory  
with Programmable Flags used in Depth Expansion Configuration.  
16  
CY7C4425/4205/4215  
CY7C4225/4235/4245  
Typical AC and DC Characteristics  
NORMALIZED SUPPLY CURRENT  
vs. FREQUENCY  
NORMALIZED SUPPLY CURRENT  
vs. SUPPLY VOLTAGE  
NORMALIZED SUPPLY CURRENT  
vs. AMBIENT TEMPERATURE  
1.4  
1.2  
1.2  
1.1  
1.0  
1.1  
1.0  
0.9  
V
=5.0V  
CC  
T =25°C  
A
V
=3.0V  
IN  
1.0  
V
=3.0V  
0.8  
IN  
V
V
=3.0V  
=5.0V  
IN  
T =25°C  
A
0.8  
0.6  
0.9  
0.8  
CC  
f=100 MHz  
0.7  
0.6  
f=100 MHz  
5
4
4.5  
5.5  
6
−55  
25  
125  
0
25  
50  
75  
100  
SUPPLY VOLTAGE(V)  
AMBIENT TEMPERATURE(°C)  
FREQUENCY (MHz)  
NORMALIZED t vs.SUPPLY  
A
VOLTAGE  
NORMALIZED t vs.  
A
AMBIENT TEMPERATURE  
TYPICALt CHANGE vs.  
A
OUTPUT LOADING  
1.2  
1.1  
1.0  
1.50  
40  
25  
T =25°C  
A
1.25  
1.0  
10  
V
=5.0V  
CC  
0.9  
0.8  
.75  
0.5  
V
CC  
=5.0V  
T =25°C  
A
−5.0  
4
4.5  
5
5.5  
6
−55  
25  
125  
(°C)  
.50  
275  
550  
825 1000  
SUPPLY VOLTAGE(V)  
AMBIENT TEMPERATURE  
CAPACITANCE(pF)  
OUTPUT SINK CURRENT vs.  
OUTPUT VOLTAGE  
OUTPUT SOURCECURRENT  
vs. OUTPUT VOLTAGE  
120  
140  
120  
100  
80  
55  
T =25°C  
A
V
CC  
=5.0V  
T =25°C  
45  
35  
25  
A
V
CC  
=5.0V  
60  
40  
20  
0
0
1
2
3
4
0
1
2
3
4
5
OUTPUT VOLTAGE(V)  
OUTPUT VOLTAGE(V)  
17  
CY7C4425/4205/4215  
CY7C4225/4235/4245  
Ordering Information  
64 x 18 Synchronous FIFO  
Speed  
Package  
Name  
Package  
Type  
Operating  
Range  
(ns)  
Ordering Code  
CY7C4425-10AC  
CY7C4425-10ASC  
CY7C4425-10JC  
CY7C4425-10AI  
CY7C4425-10ASI  
CY7C4425-10JI  
CY7C4425-15AC  
CY7C4425-15ASC  
CY7C4425-15JC  
CY7C4425-15AI  
CY7C4425-15ASI  
CY7C4425-15JI  
CY7C4425-25AC  
CY7C4425-25ASC  
CY7C4425-25JC  
CY7C4425-25AI  
CY7C4425-25ASI  
CY7C4425-25JI  
CY7C4425-35AC  
CY7C4425-35ASC  
CY7C4425-35JC  
CY7C4425-35AI  
CY7C4425-35ASI  
CY7C4425-35JI  
10  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
Commercial  
Industrial  
15  
25  
35  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
18  
CY7C4425/4205/4215  
CY7C4225/4235/4245  
256 x 18 Synchronous FIFO  
Speed  
Package  
Name  
Package  
Type  
Operating  
Range  
(ns)  
Ordering Code  
CY7C4205-10AC  
CY7C4205-10ASC  
CY7C4205-10JC  
CY7C4205-10AI  
CY7C4205-10ASI  
CY7C4205-10JI  
CY7C4205-15AC  
CY7C4205-15ASC  
CY7C4205-15JC  
CY7C4205-15AI  
CY7C4205-15ASI  
CY7C4205-15JI  
CY7C4205-25AC  
CY7C4205-25ASC  
CY7C4205-25JC  
CY7C4205-25AI  
CY7C4205-25ASI  
CY7C4205-25JI  
CY7C4205-35AC  
CY7C4205-35ASC  
CY7C4205-35JC  
CY7C4205-35AI  
CY7C4205-35ASI  
CY7C4205-35JI  
10  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
Commercial  
Industrial  
15  
25  
35  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
19  
CY7C4425/4205/4215  
CY7C4225/4235/4245  
512 x 18 Synchronous FIFO  
Speed  
Package  
Name  
Package  
Type  
Operating  
Range  
(ns)  
Ordering Code  
CY7C4215-10AC  
CY7C4215-10ASC  
CY7C4215-10JC  
CY7C4215-10AI  
CY7C4215-10ASI  
CY7C4215-10JI  
CY7C4215-15AC  
CY7C4215-15ASC  
CY7C4215-15JC  
CY7C4215-15AI  
CY7C4215-15ASI  
CY7C4215-15JI  
CY7C4215-25AC  
CY7C4215-25ASC  
CY7C4215-25JC  
CY7C4215-25AI  
CY7C4215-25ASI  
CY7C4215-25JI  
CY7C4215-35AC  
CY7C4215-35ASC  
CY7C4215-35JC  
CY7C4215-35AI  
CY7C4215-35ASI  
CY7C4215-35JI  
10  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
Commercial  
Industrial  
15  
25  
35  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
20  
CY7C4425/4205/4215  
CY7C4225/4235/4245  
1K x 18 Synchronous FIFO  
Speed  
Package  
Name  
Package  
Type  
Operating  
Range  
(ns)  
Ordering Code  
CY7C4225-10AC  
CY7C4225-10ASC  
CY7C4225-10JC  
CY7C4225-10AI  
CY7C4225-10ASI  
CY7C4225-10JI  
CY7C4225-15AC  
CY7C4225-15ASC  
CY7C4225-15JC  
CY7C4225-15AI  
CY7C4225-15ASI  
CY7C4225-15JI  
CY7C4225-25AC  
CY7C4225-25ASC  
CY7C4225-25JC  
CY7C4225-25AI  
CY7C4225-25ASI  
CY7C4225-25JI  
CY7C4225-35AC  
CY7C4225-35ASC  
CY7C4225-35JC  
CY7C4225-35AI  
CY7C4225-35ASI  
CY7C4225-35JI  
10  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
Commercial  
Industrial  
15  
25  
35  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
21  
CY7C4425/4205/4215  
CY7C4225/4235/4245  
2K x 18 Synchronous FIFO  
Speed  
Package  
Name  
Package  
Type  
Operating  
Range  
(ns)  
Ordering Code  
CY7C4235-10AC  
CY7C4235-10ASC  
CY7C4235-10JC  
CY7C4235-10AI  
CY7C4235-10ASI  
CY7C4235-10JI  
CY7C4235-15AC  
CY7C4235-15ASC  
CY7C4235-15JC  
CY7C4235-15AI  
CY7C4235-15ASI  
CY7C4235-15JI  
CY7C4235-25AC  
CY7C4235-25ASC  
CY7C4235-25JC  
CY7C4235-25AI  
CY7C4235-25ASI  
CY7C4235-25JI  
CY7C4235-35AC  
CY7C4235-35ASC  
CY7C4235-35JC  
CY7C4235-35AI  
CY7C4235-35ASI  
CY7C4235-35JI  
10  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
Commercial  
Industrial  
15  
25  
35  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
22  
CY7C4425/4205/4215  
CY7C4225/4235/4245  
4K x 18 Synchronous FIFO  
Speed  
Package  
Name  
Package  
Type  
Operating  
Range  
(ns)  
Ordering Code  
CY7C4245-10AC  
CY7C4245-10ASC  
CY7C4245-10JC  
CY7C4245-10AI  
CY7C4245-10ASI  
CY7C4245-10JI  
CY7C4245-15AC  
CY7C4245-15ASC  
CY7C4245-15JC  
CY7C4245-15AI  
CY7C4245-15ASI  
CY7C4245-15JI  
CY7C4245-25AC  
CY7C4245-25ASC  
CY7C4245-25JC  
CY7C4245-25AI  
CY7C4245-25ASI  
CY7C4245-25JI  
CY7C4245-35AC  
CY7C4245-35ASC  
CY7C4245-35JC  
CY7C4245-35AI  
CY7C4245-35ASI  
CY7C4245-35JI  
10  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
A65  
A64  
J81  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
64-Lead 14x14 Thin Quad Flatpack  
64-Lead 10x10 Thin Quad Flatpack  
68-Lead Plastic Leaded Chip Carrier  
Commercial  
Industrial  
15  
25  
35  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
23  
CY7C4425/4205/4215  
CY7C4225/4235/4245  
Package Diagrams  
64-Lead Thin Plastic Quad Flat Pack A65  
64-Pin Thin Quad Flat Pack A64  
24  
CY7C4425/4205/4215  
CY7C4225/4235/4245  
Package Diagrams (continued)  
68-Lead Plastic Leaded Chip Carrier J81  
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  

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