CY7C4265V-15ASCT [CYPRESS]
FIFO, 16KX18, 10ns, Synchronous, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, STQFP-64;
| 型号： | CY7C4265V-15ASCT |
| 厂家： | 
CYPRESS |
| 描述： | FIFO, 16KX18, 10ns, Synchronous, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, STQFP-64 时钟 先进先出芯片 内存集成电路 |
| 文件： | 总21页 (文件大小：337K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
32K/64Kx18 Low Voltage Deep Sync FIFOs
Features
Functional Description
■ 3.3Voperationforlowpowerconsumptionandeasyintegration
into low voltage systems
The CY7C4255/65/75/85V are high speed, low power, first-in
first-out (FIFO) memories with clocked read and write interfaces.
All are 18 bits wide and are pin and functionally compatible to the
■ High speed, low power, first-in first-out (FIFO) memories
■ 8K x 18 (CY7C4255V)
CY7C42X5V
Synchronous
FIFO
family.
The
CY7C4255/65/75/85V can be cascaded to increase FIFO depth.
Programmable features include Almost Full/Almost Empty flags.
These FIFOs provide solutions for a wide variety of data
buffering needs, including high speed data acquisition,
multiprocessor interfaces, and communications buffering.
■ 16K x 18 (CY7C4265V)
■ 32K x 18 (CY7C4275V)
■ 64K x 18 (CY7C4285V)
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and a write enable
pin (WEN).
■ 0.35 micron CMOS for optimum speed and power
■ High speed 100 MHz operation (10 ns read/write cycle times)
■ Low power
❐ ICC = 30 mA
❐ ISB = 4 mA
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is
continually written into the FIFO on each cycle. The output port
is controlled in a similar manner by a free-running read clock
(RCLK) and a read enable pin (REN). In addition, the
CY7C4255/65/75/85V have an output enable pin (OE). The read
and write clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read or write applications. Clock frequencies up to 67 MHz are
achievable.
■ Fully asynchronous and simultaneous read and write operation
■ Empty, Full, Half Full, and programmable Almost Empty and
Almost Full status flags
■ Retransmit function
■ Output Enable (OE) pin
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
■ Independent read and write enable pins
■ Supports free running 50% duty cycle clock inputs
■ Width Expansion Capability
Depth expansion is possible using the cascade input (WXI, RXI),
cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of
the next device, and the WXO and RXO pins of the last device
must be connected to the WXI and RXI pins of the first device.
The FL pin of the first device is tied to VSS and the FL pin of all
the remaining devices must be tied to VCC .
■ Depth Expansion Capability
■ 64-pin 10x10 STQFP
■ Pin compatible density upgrade to CY7C42X5V-ASC families
■ Pin compatible 3.3V solutions for CY7C4255/65/75/85
Selection Guide
Parameter
7C4255/65/75/85V-10
7C4255/65/75/85V-15
7C4255/65/75/85V-25
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
100
8
66.7
10
15
4
40
15
25
6
10
3.5
0
Minimum Data or Enable Setup (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
0
1
8
10
30
35
15
30
Active Power Supply Commercial
30
Current (ICC1) (mA)
Industrial
Parameter
Density
Package
CY7C4255V
CY7C4265V
CY7C4275V
CY7C4285V
64K x 18
8K x 18
16K x 18
32K x 18
64-pin 10x10 TQFP
64-pin 10x10 TQFP
64-pin 10x10 TQFP
64-pin 10x10 TQFP
Cypress Semiconductor Corporation
Document #: 38-06012 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 22, 2008
[+] Feedback
CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
Logic Block Diagram
D
0 – 17
INPUT
REGISTER
WCLK
WEN
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
High
FF
EF
Density
Dual-Port
RAM Array
FLAG
LOGIC
PAE
PAF
SMODE
8Kx9
16Kx9
32Kx9
64Kx9
WRITE
POINTER
READ
POINTER
RS
RESET
LOGIC
FL/RT
THREE-STATE
OUTPUTREGISTER
READ
CONTROL
WXI
WXO/HF
RXI
EXPANSION
LOGIC
OE
Q
0 – 17
RXO
4275V–1
RCLK
REN
Pinouts
Figure 1. Pin Diagram - 64-Pin STQFP
Top View
Q
48
D
15
D
14
D
13
D
12
1
14
Q
13
47
2
GND
46
45
3
4
Q
12
Q
V
44
43
42
41
11
D
D
5
6
7
8
11
10
CC
CY7C4255V
CY7C4265V
CY7C4275V
CY7C4285V
Q
10
D
9
Q
9
D
D
8
7
6
GND
40
39
9
10
Q
8
D
D
D
D
D
D
38
37
36
11
12
13
Q
7
5
Q
6
4
Q
5
3
35
34
14
15
GND
2
Q
4
1
D
0
33
V
CC
16
4275V–3
Document #: 38-06012 Rev. *B
Page 2 of 21
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CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
Table 1. Pin Definitions - CY7C4255V/65V/75V/85V 64-Pin STQFP
Signal Name
D0–17
Description
Data Inputs
IO
I
Function
Data inputs for an 18-bit bus.
Data outputs for an 18-bit bus.
Enables the WCLK input.
Enables the RCLK input.
Data Outputs
Write Enable
Read Enable
Write Clock
O
I
Q0–17
WEN
I
I
REN
WCLK
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
Read Clock
I
RCLK
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset
register.
Write Expansion
Out/Half Full Flag
O
Dual Mode Pin:
WXO/HF
Single device or width expansion – Half Full status flag
Cascaded – Write Expansion Out signal, connected to WXI of next device
Empty Flag
Full Flag
O
O
O
EF
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
FF
Programmable
Almost Empty
PAE
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied to VCC
It is synchronized to RCLK when VCC/SMODE is tied to VSS
.
.
Programmable
Almost Full
O
PAF
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to VCC
.
It is synchronized to WCLK when VCC/SMODE is tied to VSS
.
Load
I
I
LD
When LD is LOW, D0–17 (Q0–17) are written (read) into (from) the
programmable-flag-offset register.
First Load/
Retransmit
Dual Mode Pin:
FL/RT
Cascaded – The first device in the daisy chain has FL tied to VSS; all other devices have
FL tied to VCC. In standard mode or width expansion, FL is tied to VSS on all devices.
Not Cascaded – Tied to VSS . Retransmit function is also available in standalone mode
by strobing RT.
Write Expansion
Input
I
I
WXI
RXI
Cascaded – Connected to WXO of previous device
Not Cascaded – Tied to VSS
Read Expansion
Input
Cascaded – Connected to RXO of previous device
Not Cascaded – Tied to VSS
Read Expansion
Output
O
RXO
Cascaded – Connected to RXI of next device
Reset
I
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power up.
RS
OE
Output Enable
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Synchronous
Almost Empty/
Almost Full Flags
I
Dual Mode Pin:
VCC/SMODE
Asynchronous Almost Empty/Almost Full flags – tied to VCC
Synchronous Almost Empty/Almost Full flags – tied to VSS
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
Document #: 38-06012 Rev. *B
Page 3 of 21
[+] Feedback
CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
Functional Description
Programming
The CY7C4255/65/75/85V provides five status pins. These pins
are decoded to determine one of five states: Empty, Almost
Empty, Half Full, Almost Full, and Full (see Table 3 on page 5).
The Half Full flag shares the WXO pin. This flag is valid in the
standalone and width expansion configurations. In the depth
expansion, this pin provides the expansion out (WXO)
information that is used to signal the next FIFO when it is to be
activated.
The CY7C4255/65/75/85V devices contain two 16-bit offset
registers. Data present on D0–15 during a program write
determine the distance from Empty (Full) that the Almost Empty
(Almost Full) flags become active. If the user elects not to
program the FIFO’s flags, the default offset values are used (see
Table 3 on page 5). When the Load LD pin is set LOW and WEN
is set LOW, data on the inputs D0–15 is written into the Empty
offset register on the first LOW-to-HIGH transition of the write
clock (WCLK). When the LD pin and WEN are held LOW then
data is written into the Full offset register on the second
LOW-to-HIGH transition of the write clock (WCLK). The third
transition of the write clock (WCLK) again writes to the Empty
offset register (see Table 2). All offset registers do not have to be
written at one time. One or two offset registers can be written and
then, by bringing the LD pin HIGH, the FIFO is returned to normal
read/write operation. When the LD pin is set LOW, and WEN is
LOW, the next offset register in sequence is written.
The Empty and Full flags are synchronous, that is, they change
state relative to either the read clock (RCLK) or the write clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag
architecture guarantees that the flags remain valid from one
clock cycle to the next. The Almost Empty/Almost Full flags
become synchronous if the VCC/SMODE is tied to VSS. All
configurations are fabricated using an advanced 0.35μ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW. Then,
data can be read on the LOW-to-HIGH transition of the read
clock (RCLK).
Architecture
Table 2. Write Offset Register
The CY7C4255/65/75/85V consists of an array of
8K/16K/32K/64K words of 18 bits each (implemented by a dual
port array of SRAM cells), a read pointer, a write pointer, control
signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, HF,
PAF, FF). The CY7C4255/65/75/85V also includes the control
signals WXI, RXI, WXO, RXO for depth expansion.
LD WEN
WCLK[1]
Selection
0
0
Writing to offset registers:
Empty Offset
Full Offset
0
1
1
1
0
1
No Operation
Write Into FIFO
No Operation
Resetting the FIFO
Upon power up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs go LOW after the falling edge of
RS only if OE is asserted. For the FIFO to reset to its default
state, the user must not read or write while RS is LOW.
FIFO Operation
Flag Operation
When the WEN signal is active (LOW), data present on the D0–17
pins is written into the FIFO on each rising edge of the WCLK
signal. Similarly, when the REN signal is active LOW, data in the
FIFO memory is presented on the Q0–17 outputs. New data is
presented on each rising edge of RCLK while REN is active LOW
and OE is LOW. REN must set up tENS before RCLK for it to be
a valid read function. WEN must occur tENS before WCLK for it
to be a valid write function.
The CY7C4255/65/75/85V devices provide five flag pins to
indicate the condition of the FIFO contents. Empty and Full are
synchronous. PAE and PAF are synchronous if VCC/SMODE is
tied to VSS
.
Full Flag
The Full Flag (FF) goes LOW when device is Full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN. FF is synchronized to WCLK, that is, it is
exclusively updated by each rising edge of WCLK.
An output enable (OE) pin is provided to three-state the Q0–17
outputs when OE is deasserted. When OE is enabled (LOW),
data in the output register is available to the Q0–17 outputs after
t
OE. If devices are cascaded, the OE function only outputs data
on the FIFO that is read enabled.
Empty Flag
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and under flow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0–17 outputs even
after additional reads occur.
The Empty Flag (EF) goes LOW when the device is empty. Read
operations are inhibited whenever EF is LOW, regardless of the
state of REN. EF is synchronized to RCLK, that is, it is
exclusively updated by each rising edge of RCLK.
Note
1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Document #: 38-06012 Rev. *B
Page 4 of 21
[+] Feedback
CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
the flags have been programmed, the PAF or PAE is asserted,
signifying that the FIFO is either Almost Full or Almost Empty.
See Table 3 for a description of programmable flags.
Programmable Almost Empty/Almost Full Flag
The CY7C4255/65/75/85V features programmable Almost
Empty and Almost Full Flags. Each flag can be programmed
(described in section Programming on page 4) a specific
distance from the corresponding boundary flags (Empty or Full).
When the FIFO contains the number of words or fewer for which
When the SMODE pin is tied LOW, the PAF flag signal transition
is caused by the rising edge of the write clock and the PAE flag
transition is caused by the rising edge of the read clock.
Table 3. Flag Truth Table
Number of Words in FIFO
FF PAF HF PAE EF
7C4255V – 8K x 18
7C4265V – 16K x 18
7C4275V – 32K x 18
7C4285V – 64K x 18
0
0
0
0
H
H
H
H
H
H
L
L
L
1 to n[2]
1 to n[2]
1 to n[2]
1 to n[2]
H
(n+1) to 4096
(n+1) to 8192
(n+1) to 16384
(n+1) to 32768
H
H
H
H
H
L
H
L
L
H
H
H
H
H
H
4097 to (8192–(m+1)) 8193 to (16384 –(m+1)) 16385 to (32768–(m+1)) 32769 to (65536 –(m+1))
(8192–m)[3] to 8192
8192
(16384–m)[3] to 16384
16384
(32768–m)[3] to 32767
32768
(65536–m)[3] to 65535
65536
L
L
L
H
H
Retransmit
Width Expansion Configuration
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the
receiver and retransmitted if necessary.
The CY7C4255/65/75/85V can be expanded in width to provide
word widths greater than 18 in increments of 18. During width
expansion mode, all control line inputs are common and all flags
are available. Empty (Full) flags must be created by ANDing the
Empty (Full) flags of every FIFO. The PAE and PAF flags can be
detected from any one device. This technique avoids reading
data from, or writing data to the FIFO that is “staggered” by one
clock cycle due to the variations in skew between RCLK and
WCLK. Figure 2 on page 6 demonstrates a 36-word width by
using two CY7C4255/65/75/85Vs.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred and at least one word has been read since
the last RS cycle. A HIGH pulse on RT resets the internal read
pointer to the first physical location of the FIFO. WCLK and
RCLK may be free running but must be disabled during and tRTR
after the retransmit pulse. With every valid read cycle after
retransmit, previously accessed data is read and the read pointer
is incremented until it is equal to the write pointer. Flags are
governed by the relative locations of the read and write pointers
and are updated during a retransmit cycle. Data written to the
FIFO after activation of RT are transmitted also. The full depth of
the FIFO can be repeatedly retransmitted.
Notes
2. n = Empty Offset (Default Values: CY7C4255/65/75/85V n = 127).
3. m = Full Offset (Default Values: CY7C4255/65/75/85V n = 127).
Document #: 38-06012 Rev. *B
Page 5 of 21
[+] Feedback
CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
Figure 2. Block Diagram of 8K/16K/32K/64K x 18 Low Voltage Synchronous FIFO Memory in Width Expansion Configuration
RESET(RS)
RESET(RS)
DATA IN (D)
36
18
18
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAF)
WRITE CLOCK(WCLK)
WRITE ENABLE(WEN)
LOAD (LD)
PROGRAMMABLE(PAE)
HALF FULL FLAG (HF)
7C4255V
7C4265V
7C4275V
7C4285V
7C4255V
7C4265V
7C4275V
7C4285V
EMPTY FLAG (EF)
EF
FF
FF
EF
DATA OUT (Q)
18
36
FULL FLAG (FF)
18
FIRST LOAD (FL)
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
4275V–24
Depth Expansion Configuration (with Programmable Flags)
The CY7C4255/65/75/85V can easily be adapted to applications requiring more than 8K/16K/32K/64K words of buffering. Figure 3
on page 7 shows Depth Expansion using three CY7C4255/65/ 75/85Vs. Maximum depth is limited only by signal loading. Follow these
steps:
1. The first device must be designated by grounding the First Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device.
4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device.
5. All Load (LD) pins are tied together.
6. The Half Full Flag (HF) is not available in the Depth Expansion Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by ORing together these respective flags for monitoring. The composite
PAE and PAF flags are not precise.
Document #: 38-06012 Rev. *B
Page 6 of 21
[+] Feedback
CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
Figure 3. Block Diagram of 8K/16K/32K/64K x 18 Low Voltage Synchronous FIFO Memory with Programmable Flags in Depth
Expansion Configuration
WXO RXO
7C4255V
7C4265V
7C4275V
7C4285V
VCC
FL
FF
PAF
EF
PAE
WXI RXI
WXO RXO
7C4255V
7C4265V
7C4275V
7C4285V
DATAIN (D)
DATA OUT (Q)
VCC
FL
FF
PAF
EF
PAE
WXI RXI
WRITE CLOCK(WCLK)
WRITE ENABLE(WEN)
READCLOCK(RCLK)
READENABLE(REN)
WXO RXO
7C4255V
7C4265V
7C4275V
7C4285V
RESET(RS)
OUTPUTENABLE (OE)
LOAD (LD)
FF
EF
FF
EF
PAE
PAE
PAF
PAF
WXI RXI
FIRST LOAD (FL)
4275V–25
Document #: 38-06012 Rev. *B
Page 7 of 21
[+] Feedback
CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Exceeding maximum ratings[4] may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage............................................>2001V
(per MIL–STD–883, Method 3015)
Latch-Up Current.....................................................>200mA
Storage Temperature ................................ –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied ........................................... –55°C to +125°C
[6]
Range
AmbientTemperature
0°C to +70°C
VCC
Supply Voltage to Ground Potential.........–0.5V to VCC+0.5V
Commercial
3.3V ±300 mV
3.3V ±300 mV
DC Voltage Applied to Outputs
in High Z State.........................................–0.5V to VCC+0.5V
Industrial[5]
–40°C to +85°C
DC Input Voltage ......................................... −0.5V to VCC+0.5V
Electrical Characteristics
[7]
Over the Operating Range
7C4255/65/75/
85V-10
7C4255/65/75/
85V-15
7C4255/65/75/
85V-25
Parameter
Description
Test Conditions
Unit
Min
Max
Min
Max
Min
Max
VOH
VOL
Output HIGH
Voltage
VCC = Min, IOH = –1.0 mA
VCC = 3.0V. IOH = –2.0 mA
2.4
2.4
2.4
V
V
Output LOW
Voltage
VCC = Min.,IOL = 4.0 mA
0.4
0.4
0.4
VCC = 3.0V.,IOL = 8.0 mA
[8]
VIH
Input HIGH Voltage
Input LOW Voltage
2.0
–0.5
–10
VCC
0.8
2.0
–0.5
–10
VCC
0.8
2.0
–0.5
–10
VCC
0.8
V
V
[8]
VIL
IIX
Input Leakage
Current
VCC = Max.
+10
+10
+10
μA
IOZL
IOZH
Output OFF, High Z OE > VIH,
–10
+10
30
–10
+10
–10
+10
30
μA
Current
VSS < VO < VCC
[9]
ICC1
Active Power
Supply Current
Com’l
Ind
30
35
4
mA
mA
mA
mA
[10]
ISB
Average Standby
Current
Com’l
Ind
4
4
4
Capacitance
Parameter[11]
Description
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 3.3V
Max
5
Unit
pF
CIN
Input Capacitance
Output Capacitance
V
COUT
7
pF
Notes
4. The Voltage on any input or IO pin cannot exceed the power pin during power up.
5.
6.
T is the “instant on” case temperature.
A
V
range for commercial -10 ns is 3.3V ±150mV.
CC
7. See the last page of this specification for Group A subgroup testing information.
8. The V and V specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the previous
IH
IL
.
device or V
SS
9. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded.
10. All inputs = V – 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz), and FL/RT which is at V . All outputs are unloaded.
CC
SS
11. Tested initially and after any design changes that may affect these parameters.
Document #: 38-06012 Rev. *B
Page 8 of 21
[+] Feedback
CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
Figure 4. AC Test Loads and Waveforms (-15 -25) [12, 13]
R1=330Ω
3.3V
ALL INPUT PULSES
OUTPUT
3.0V
GND
90%
10%
90%
10%
R2=510Ω
C
L
≤ 3 ns
≤ 3 ns
INCLUDING
JIG AND
SCOPE
4275V–4
4287V–5
Equivalentto:
THÉVENIN EQUIVALENT
200
Ω
OUTPUT
2.0V
Figure 5. AC Test Loads and Waveforms (-10)
ALL INPUT PULSES
V
CC/2
3.0V
GND
90%
10%
90%
10%
50Ω
≤ 3 ns
≤ 3 ns
I/O
Z0=50
Ω
4275V–6
4275V–7
Switching Characteristics
Over the Operating Range
7C4255/65/75/85V-10 7C4255/65/75/85V-15 7C4255/65/75/85V-25
Parameter
tS
Description
Unit
Min
Max
100
8
Min
Max
66.7
10
Min
Max
40
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tA
2
10
4.5
4.5
3.5
0
2
15
6
2
25
10
10
6
15
tCLK
tCLKH
tCLKL
tDS
6
Data Setup Time
4
tDH
Data Hold Time
0
1
tENS
tENH
tRS
Enable Setup Time
Enable Hold Time
Reset Pulse Width[14]
Reset Recovery Time
3.5
0
4
6
0
1
10
8
15
10
25
15
tRSR
tRSF
tPRT
tRTR
tOLZ
Reset to Flag and Output Time
Retransmit Pulse Width
10
7
15
10
25
12
60
90
0
60
90
0
60
90
0
Retransmit Recovery Time
Output Enable to Output in Low Z [15]
Output Enable to Output Valid
tOE
3
3
3
ns
Notes
12. C = 30 pF for all AC parameters except for t
.
OHZ
L
13. C = 5 pF for t
.
L
OHZ
14. Pulse widths less than minimum values are not allowed.
15. Values guaranteed by design, not currently tested.
Document #: 38-06012 Rev. *B
Page 9 of 21
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Switching Characteristics (continued)
Over the Operating Range
7C4255/65/75/85V-10 7C4255/65/75/85V-15 7C4255/65/75/85V-25
Unit
Parameter
Description
Min
Max
Min
Max
Min
Max
Output Enable to Output in High Z[15]
Write Clock to Full Flag
tOHZ
3
7
3
8
3
12
ns
tWFF
8
8
10
10
16
15
15
20
ns
ns
ns
tREF
Read Clock to Empty Flag
tPAFasynch
Clock to Programmable Almost Full
Flag[16] (Asynchronous mode,
15
VCC/SMODE tied to VCC)
tPAFsynch
Clock to Programmable Almost Full
Flag
8
10
15
ns
(Synchronous mode, VCC/SMODE
tied to VSS
)
tPAEasynch
Clock to Programmable Almost Empty
Flag[16] (Asynchronous mode,
15
8
16
10
20
15
ns
ns
VCC/SMODE tied to VCC)
tPAEsynch
Clock to Programmable Almost Full
Flag (Synchronous mode,
VCC/SMODE tied to VSS)
tHF
Clock to Half Full Flag
Clock to Expansion Out
12
6
16
10
20
15
ns
ns
ns
ns
ns
tXO
tXI
Expansion in Pulse Width
Expansion in Setup Time
4.5
4
6.5
5
10
10
10
tXIS
tSKEW1
Skew Time between Read Clock and
Write Clock for Full Flag
5
6
tSKEW2
tSKEW3
Skew Time between Read Clock and
Write Clock for Empty Flag
5
6
10
18
ns
ns
Skew Time between Read Clock and
Write Clock for Programmable Almost
Empty and Programmable Almost Full
Flags (Synchronous Mode only)
10
15
Note
16. t
, t
, after program register write are valid until 5 ns + t
.
PAFasynch PAEasynch
PAF(E)
Document #: 38-06012 Rev. *B
Page 10 of 21
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CY7C4275V, CY7C4285V
Switching Waveforms
Figure 6. Write Cycle Timing
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
DH
DS
D –D
0
17
t
ENH
t
ENS
WEN
FF
NO OPERATION
t
t
WFF
WFF
[17]
t
SKEW1
RCLK
REN
Figure 7. Read Cycle Timing
t
CLK
t
t
CLKL
CLKH
RCLK
REN
t
t
ENH
ENS
NO OPERATION
t
REF
t
REF
EF
t
A
VALID DATA
Q –Q
0
17
t
OLZ
t
OHZ
t
OE
OE
[18]
SKEW2
t
WCLK
WEN
Notes
17. t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between
SKEW1
the rising edge of RCLK and the rising edge of WCLK is less than t
, then FF may not change state until the next WCLK rising edge.
SKEW1
18. t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. If the time between
SKEW2
the rising edge of WCLK and the rising edge of RCLK is less than t
, then EF may not change state until the next RCLK rising edge.
SKEW2
Document #: 38-06012 Rev. *B
Page 11 of 21
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CY7C4275V, CY7C4285V
Switching Waveforms (continued)
Figure 8. Reset Timing [19]
t
RS
RS
t
RSR
REN,WEN,
LD
t
RSF
EF,PAE
t
RSF
FF,PAF,
HF
t
RSF
[20]
OE=1
Q
Q
0 – 17
OE=0
Figure 9. First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
t
DS
D –D
D
0
(FIRSTVALIDWRITE)
D
1
D
2
D
3
D
4
0
17
t
ENS
[21]
FRL
t
WEN
t
SKEW2
RCLK
t
REF
EF
REN
[22]
t
A
t
A
Q –Q
D
0
D
1
0
17
t
OLZ
t
OE
OE
Notes
19. The clocks (RCLK, WCLK) can be free-running during reset.
20. After reset, the outputs are LOW if OE = 0 and three-state if OE = 1.
21. When t > minimum specification, t (maximum) = t + t
. When t
< minimum specification, t
(maximum) = either 2*t
+ t
or t
+
SKEW2
FRL
CLK
SKEW2
SKEW2
FRL
CLK
SKEW2
CLK
t
. The Latency Timing applies only at the Empty Boundary (EF = LOW).
SKEW2
22. The first word is always available the cycle after EF goes HIGH.
Document #: 38-06012 Rev. *B
Page 12 of 21
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CY7C4275V, CY7C4285V
Switching Waveforms (continued)
Figure 10. Empty Flag Timing
WCLK
t
t
DS
DS
D0
D1
D –D
0
17
t
t
ENH
ENH
t
t
ENS
ENS
WEN
[21]
FRL
[21]
FRL
t
t
RCLK
t
t
t
REF
t
REF
t
SKEW2
REF
SKEW2
EF
REN
OE
t
A
D0
Q –Q
0
17
Figure 11. Full Flag Timing
NO WRITE
NO WRITE
WCLK
[17]
[17]
t
t
DATA WRITE
t
SKEW1
DS
SKEW1
DATA WRITE
D –D
0
17
t
t
t
WFF
WFF
WFF
FF
WEN
RCLK
REN
t
t
ENH
ENH
t
t
ENS
ENS
LOW
OE
t
A
t
A
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
Q –Q
0
17
Document #: 38-06012 Rev. *B
Page 13 of 21
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Switching Waveforms (continued)
Figure 12. Half Full Timing
t
t
CLKL
CLKH
WCLK
WEN
t
t
ENH
ENS
t
HF
HALF FULL + 1
OR MORE
HALF
HALF FULL OR LESS
FULL OR LESS
HF
t
HF
RCLK
REN
t
ENS
Figure 13. Programmable Almost Empty Flag Timing
t
t
CLKL
CLKH
WCLK
WEN
t
t
ENH
ENS
t
PAE
[23]
N + 1 WORDS
IN FIFO
PAE
n WORDS IN FIFO
t
PAE
RCLK
REN
t
ENS
Note
23. PAE is offset = n. Number of data words into FIFO already = n.
Document #: 38-06012 Rev. *B
Page 14 of 21
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Switching Waveforms (continued)
Figure 14. Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW))
t
t
CLKL
CLKH
WCLK
WEN
PAE
t
t
ENH
ENS
27
Note
N + 1 WORDS
IN FIFO
Note
26
[25]
t
PAE synch
t
t
SKEW3
PAE synch
RCLK
REN
t
ENS
t
t
ENH
ENS
Figure 15. Programmable Almost Full Flag Timing
t
t
CLKL
CLKH
Note 27
WCLK
WEN
t
t
ENH
ENS
t
PAF
FULL– M WORDS
[28]
[29]
PAF
IN FIFO
FULL– (M+1) WORDS
[30]
IN FIFO
t
PAF
RCLK
REN
t
ENS
Notes
24. PAE offset − n.
25. t is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK
SKEW3
and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK.
26. If a read is performed on this rising edge of the read clock, there are Empty + (n−1) words in the FIFO when PAE goes LOW.
27. PAF offset = m. Number of data words written into FIFO already = 8192 − (m + 1) for the CY7C4255V, 16384 − (m + 1) for the CY7C4265V, 32768 − (m + 1) for the
CY7C4275V, and 65536 − (m + 1) for the CY7C4285V.
28. PAF is offset = m.
29. 8192 − m words in CY7C4255V, 16384 − m words in CY7C4265V, 32768 − m words in CY7C4275V, and 65536 − m words in CY7C4285V.
30. 8192 − (m + 1) words in CY7C4255V, 16384 − (m + 1) words in CY7C4265V, 32768 − (m + 1) words in CY7C4275V, and 65536 − (m + 1) words in CY7C4285V.
Document #: 38-06012 Rev. *B
Page 15 of 21
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Switching Waveforms (continued)
Figure 16. Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))
31
Note
t
t
CLKL
CLKH
WCLK
t
t
ENH
ENS
WEN
PAF
t
PAF
FULL– M WORDS
IN FIFO
[29]
FULL – M + 1 WORDS
IN FIFO
[32]
SKEW3
t
PAF synch
t
RCLK
REN
t
ENS
t
t
ENH
ENS
Figure 17. Write Programmable Registers
t
CLK
t
t
CLKL
CLKH
WCLK
LD
t
t
ENS
ENH
t
ENS
WEN
t
t
DH
DS
PAE OFFSET
D –D
0
17
D
D –
0
PAE OFFSET
PAF OFFSET
11
Notes
31. If a write is performed on this rising edge of the write clock, there are Full − (m−1) words of the FIFO when PAF goes LOW.
32. t is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK
SKEW3
and the rising edge of WCLK is less than t
, then PAF may not change state until the next WCLK rising edge.
SKEW3
Document #: 38-06012 Rev. *B
Page 16 of 21
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Switching Waveforms (continued)
Figure 18. Read Programmable Registers
t
CLK
t
t
CLKL
CLKH
RCLK
LD
t
t
ENS
ENH
t
ENS
WEN
t
A
UNKNOWN
PAE OFFSET
PAF OFFSET
PAE OFFSET
Q –Q
0
17
Figure 19. Write Expansion Out Timing
t
CLKH
WCLK
34
t
XO
33
WXO
WEN
t
XO
t
ENS
Figure 20. Read Expansion Out Timing
t
CLKH
WCLK
34
t
XO
RXO
REN
t
XO
t
ENS
Figure 21. Write Expansion In Timing
t
XI
WXI
t
XIS
WCLK
Notes
33. Write to Last Physical Location.
34. Read from Last Physical Location.
Document #: 38-06012 Rev. *B
Page 17 of 21
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Switching Waveforms (continued)
Figure 22. Read Expansion In Timing
t
XI
RXI
t
XIS
RCLK
Figure 23. Retransmit Timing [35, 36, 37]
FL/RT
t
PRT
t
RTR
REN/WEN
EF/FF
and all
async flags
HF/PAE/PAF
Notes
35. Clocks are free-running in this case.
36. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags are valid at t
.
RTR
37. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t
to update these flags.
RTR
Document #: 38-06012 Rev. *B
Page 18 of 21
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Ordering Information
8Kx18 Low-Voltage Deep Sync FIFO
Speed (ns)
Ordering Code
Package Diagram
Package Type
Operating Range
10
CY7C4255V–10ASC
CY7C4255V–10ASXC
CY7C4255V–15ASC
CY7C4255V–15ASXC
CY7C4255V–15ASXI
CY7C4255V–25ASC
64-Pin Thin Quad Flat Pack (10 x 10 x 1.4 mm)
64-Pin Thin Quad Flat Pack (10 x 10 x 1.4 mm) (Pb-Free)
64-Pin Thin Quad Flat Pack (10 x 10 x 1.4 mm)
64-Pin Thin Quad Flat Pack (10 x 10 x 1.4 mm) (Pb-Free)
64-Pin Thin Quad Flat Pack (10 x 10 x 1.4 mm) (Pb-Free)
64-Pin Thin Quad Flat Pack (10 x 10 x 1.4 mm)
51-85051
Commercial
15
51-85051
Commercial
51-85051
51-85051
Industrial
25
Commercial
16Kx18 Low-Voltage Deep Sync FIFO
Speed (ns)
Ordering Code
CY7C4265V–10ASC
CY7C4265V–15ASC
CY7C4265V–25ASC
Package Diagram
51-85051
Package Type
Operating Range
Commercial
10
15
25
64-Pin Thin Quad Flat Pack (10 x 10 x 1.4 mm)
64-Pin Thin Quad Flat Pack (10 x 10 x 1.4 mm)
64-Pin Thin Quad Flat Pack (10 x 10 x 1.4 mm)
51-85051
Commercial
51-85051
Commercial
32Kx18 Low-Voltage Deep Sync FIFO
Speed (ns)
Ordering Code
CY7C4275V–10ASC
CY7C4275V–15ASC
CY7C4275V–15ASXC
Package Diagram
Package Type
Operating Range
10
15
51-85051
64-Pin Thin Quad Flat Pack (10 x 10 x 1.4 mm)
64-Pin Thin Quad Flat Pack (10 x 10 x 1.4 mm)
64-Pin Thin Quad Flat Pack (10 x 10 x 1.4 mm) (Pb-Free)
Commercial
51-85051
Commercial
64Kx18 Low-Voltage Deep Sync FIFO
Speed (ns)
Ordering Code
CY7C4285V–10ASC
CY7C4285V–10ASXC
CY7C4285V–15ASXC
CY7C4285V–15ASI
CY7C4285V–15ASXI
CY7C4285V–25ASC
Package Diagram
Package Type
Operating Range
10
64-Pin Thin Quad Flat Pack (10 x 10 x 1.4 mm)
64-Pin Thin Quad Flat Pack (10 x 10 x 1.4 mm) (Pb-Free)
64-Pin Thin Quad Flat Pack (10 x 10 x 1.4 mm) (Pb-Free)
64-Pin Thin Quad Flat Pack (10 x 10 x 1.4 mm)
64-Pin Thin Quad Flat Pack (10 x 10 x 1.4 mm) (Pb-Free)
64-Pin Thin Quad Flat Pack (10 x 10 x 1.4 mm)
Commercial
51-85051
15
25
51-85051
Commercial
Industrial
51-85051
51-85051
Commercial
Document #: 38-06012 Rev. *B
Page 19 of 21
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Package Diagrams
Figure 24. 64-Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm)
51-85051 *A
Document #: 38-06012 Rev. *B
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Document History Page
Document Title: CY7C4255V/CY7C4265V/CY7C4275V/CY7C4285V 32K/64Kx18 Low Voltage Deep Sync FIFOs
Document Number: 38-06012
Orig. of
Change
Submission
Date
REV.
ECN
Description of Change
**
106473
122264
SZV
RBI
09/10/01
12/26/02
Change from Spec number: 38-00654 to 38-06012
*A
*B
Power up requirements added to Maximum Ratings Information
2556036 VKN/AESA 08/22/2008 Updated ordering information and data sheet template.
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
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Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06012 Rev. *B
Revised August 22, 2008
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