CY7C4808V25-200BBI [CYPRESS]
FIFO, 64KX80, 3.8ns, Synchronous, CMOS, PBGA288, 19 X 19 MM, 1 MM PITCH, BGA-288;
| 型号： | CY7C4808V25-200BBI |
| 厂家： | 
CYPRESS |
| 描述： | FIFO, 64KX80, 3.8ns, Synchronous, CMOS, PBGA288, 19 X 19 MM, 1 MM PITCH, BGA-288 先进先出芯片 |
| 文件： | 总30页 (文件大小：375K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C4808V25
CY7C4806V25
CY7C4804V25
sure
C025/0251
PRELIMINARY
2.5V 4K/16K/64K x 80 Unidirectional
Synchronous FIFO with Bus Matching
• Bus matching on both ports: ×80, ×40, ×20, ×10
Features
• Free-running CLKA and CLKB. Clocks may be asyn-
chronous or coincident
• Cypress standard or First-Word Fall-Through modes
• Serial and parallel programming of Almost Empty/Full
flags, each with three default values (8, 16, 64)
• High-speed, low-power, unidirectional,
First-in First-out (FIFO) memories with bus-matching
capabilities
• 64K × 80 (CY7C4808V25)
• 16K × 80 (CY7C4806V25)
• 4K × 80 (CY7C4804V25)
• 2.5V ± 100 mV power supply
• All I/Os are 1.5V HSTL
• Master and partial reset capability
• Retransmit capability
• Big or Little Endian format
• 288FBGA19mm×19mm(1.0-mmballpitch)packaging
• Width and depth expansion capability
• Fabricated using Cypress 0.21-micron CMOS technol-
ogy for optimum speed/power
• Individual clock frequency up to 200 MHz (5-ns
Read/Write cycle times)
• High-speed access with tA = 3.8 ns
Preliminary Top-level Block Diagram
CLKA
CSA
CLKB
CSB
ENB
BE/FWFT
SIZE1B
SIZE2B
RT/SPM
Port A
ENA
Control
Port B
Control
Logic
Logic
SIZE1A
SIZE2A
4K/16K/64K×80
OE
Dual-ported
Memory Array
80
A
79–0
80
B
79–0
Read
Pointer
Write
Pointer
MR
PR
FIFO
Reset
Logic
Status
Flag Logic
FF/IR
AF
EF/OR
AE
TDO
Programmable Flag
Offset Registers
FS0/SD
FS1/SEN
JTAG Controller
TDI TCK TMS TRST
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06028 Rev. *B
Revised December 26, 2002
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Pin Configuration for CY7C4804V25 (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A
B
C
D
E
F
VDDQ VDDQ
A16
A19
VDDQ
A30
A34
GND CLKA
A42
GND
A48
A51
VDDQ
A55
A57
VDDQ VDDQ
A
B
C
D
E
F
VDDQ
A10
A8
A14
VDDQ
A11
A17
A13
VDDQ
A18
A29
A28
GND
A25
A24
A23
A4
A33
A32
A27
GND
A31
GND
A36
A39
A38
A41
GND
A44
VDD
AF
A45
A46
A43
GND
A40
A50
A49
GND
GND
A61
A62
A73
A76
B76
B73
B69
B65
NC
VDDQ
A52
A54
A53
A56
VDDQ
A63
A66
A64
A70
A75
A77
VDDQ
B75
B70
B66
B64
B61
VDDQ
B56
B57
16
A58
A59
A67
VDDQ
A60
A9
VDDQ
A7
A6
VDDQ
A20
GND
GND FF/IR
A47
VDDQ
TDI
A69
VDDQ VDDQ
MR
PR
VDD
A21
FS1/
SEN
GND
A37
GND
ENA
VDD
VDD
GND
A74
VDDQ VDDQ
A12
A5
A15
A2
SIZE
1A
GND
A35
CSA
GND
TDO
TCK
GND
B77
A65
A71
GND
A78
B78
GND
B71
B67
A68
A72
GND
A79
B79
GND
B72
B68
G
H
J
SIZE
2B
FS0/
SD
GND
G
H
J
GND
B2
GND
B3
RT/
SPM
VDD
A1
SIZE
1B
VDDQ
GND
GND
A22
GND
B1
A0
GND
GND
B74
K
L
B6
B7
B4
GND
A3
K
L
GND
B10
B14
GND
B9
B5
BE/
FWFT
A26
TMS
M
N
P
R
T
VREF
B12
B15
B16
VDDQ
B22
B23
3
B8
GND
NC
SIZE
2A
GND TRST
M
N
P
R
T
B13
B11
B0
B31
GND
NC
B35
B37
GND
AE
B40
GND
GND
B41
B43
CSB
VDD
B44
B45
GND
ENB
B46
B47
B48
12
NC
VDD
NC
GND
OE
VDDQ VDDQ
NC
EF/
OR
VDDQ VDDQ
B18
B20
B17
B19
B21
VDDQ
B24
B25
B26
4
NC
GND
B28
B29
B30
6
VDD
B36
GND
GND
8
GND
B49
B50
B51
13
VDDQ
B53
B54
B55
15
B62
B59
B58
B63
B60
B27
VDDQ
VDDQ
5
B32
B33
B34
7
VDDQ
B38
B39
9
B52
VDDQ
VDDQ
14
U
V
VDDQ
B42
GND
VDDQ
U
V
VDDQ VDDQ
CLKB GND
VDDQ VDDQ
1
2
10
11
17
18
Document #: 38-06028 Rev. *B
Page 2 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Pin Configuration for CY7C4806V25 (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A
B
C
D
E
F
VDDQ VDDQ
A16
A19
VDDQ
A30
A34
GND CLKA
A42
GND
A48
A51
VDDQ
A55
A57
VDDQ VDDQ
A
B
C
D
E
F
VDDQ
A10
A8
A14
VDDQ
A11
A17
A13
VDDQ
A18
A29
A28
GND
A25
A24
A23
A4
A33
A32
A27
GND
A31
GND
A36
A39
A38
A41
GND
A44
VDD
AF
A45
A46
A43
GND
A40
A50
A49
GND
VDD
A61
A62
A73
A76
B76
B73
B69
B65
NC
VDDQ
A52
A54
A53
A56
VDDQ
A63
A66
A64
A70
A75
A77
VDDQ
B75
B70
B66
B64
B61
VDDQ
B56
B57
16
A58
A59
A67
VDDQ
A60
A9
VDDQ
A7
A6
VDDQ
A20
GND
GND FF/IR
A47
VDDQ
TDI
A69
VDDQ VDDQ
MR
PR
VDD
A21
FS1/
SEN
GND
A37
GND
ENA
VDD
VDD
GND
A74
VDDQ VDDQ
A12
A5
A15
A2
SIZE
1A
GND
A35
CSA
GND
TDO
TCK
GND
B77
A65
A71
GND
A78
B78
GND
B71
B67
A68
A72
GND
A79
B79
GND
B72
B68
G
H
J
SIZE
2B
FS0/
SD
GND
G
H
J
GND
B2
GND
B3
RT/
SPM
VDD
A1
SIZE
1B
VDDQ
GND
GND
A22
GND
B1
A0
GND
GND
B74
K
L
B6
B7
B4
GND
A3
K
L
GND
B10
B14
GND
B9
B5
BE/
FWFT
A26
TMS
M
N
P
R
T
VREF
B12
B15
B16
VDDQ
B22
B23
3
B8
GND
NC
SIZE
2A
GND TRST
M
N
P
R
T
B13
B11
B0
B31
GND
NC
B35
B37
GND
AE
B40
GND
GND
B41
B43
CSB
VDD
B44
B45
GND
ENB
B46
B47
B48
12
NC
VDD
NC
GND
OE
VDDQ VDDQ
NC
EF/
OR
VDDQ VDDQ
B18
B20
B17
B19
B21
VDDQ
B24
B25
B26
4
NC
GND
B28
B29
B30
6
VDD
B36
GND
GND
8
GND
B49
B50
B51
13
VDDQ
B53
B54
B55
15
B62
B59
B58
B63
B60
B27
VDDQ
VDDQ
5
B32
B33
B34
7
VDDQ
B38
B39
9
B52
VDDQ
VDDQ
14
U
V
VDDQ
B42
GND
VDDQ
U
V
VDDQ VDDQ
CLKB GND
VDDQ VDDQ
1
2
10
11
17
18
Document #: 38-06028 Rev. *B
Page 3 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Pin Configuration for CY7C4808V25 (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A
B
C
D
E
F
VDDQ VDDQ
A16
A19
VDDQ
A30
A34
GND CLKA
A42
GND
A48
A51
VDDQ
A55
A57
VDDQ VDDQ
A
B
C
D
E
F
VDDQ
A10
A8
A14
VDDQ
A11
A17
A13
VDDQ
A18
A29
A28
GND
A25
A24
A23
A4
A33
A32
A27
GND
A31
GND
A36
A39
A38
A41
GND
A44
VDD
AF
A45
A46
A43
GND
A40
A50
A49
GND
GND
A61
A62
A73
A76
B76
B73
B69
B65
NC
VDDQ
A52
A54
A53
A56
VDDQ
A63
A66
A64
A70
A75
A77
VDDQ
B75
B70
B66
B64
B61
VDDQ
B56
B57
16
A58
A59
A67
VDDQ
A60
A9
VDDQ
A7
A6
VDDQ
A20
GND
GND FF/IR
A47
VDDQ
TDI
A69
VDDQ VDDQ
MR
PR
VDD
A21
FS1/
SEN
GND
A37
GND
ENA
VDD
VDDQ VDDQ
A12
A5
A15
A2
SIZE
1A
GND
A35
CSA
GND
GND
A74
GND
TDO
TCK
GND
B77
A65
A71
GND
A78
B78
GND
B71
B67
A68
A72
GND
A79
B79
GND
B72
B68
G
H
J
SIZE
2B
FS0/
SD
GND
G
H
J
GND
B2
GND
B3
RT/
SPM
VDD
A1
SIZE
1B
VDDQ
GND
GND
A22
GND
B1
A0
GND
GND
B74
K
L
B6
B7
B4
GND
A3
K
L
GND
B10
B14
GND
B9
B5
BE/
FWFT
A26
TMS
M
N
P
R
T
VREF
B12
B15
B16
VDDQ
B22
B23
3
B8
GND
NC
SIZE
2A
GND TRST
M
N
P
R
T
B13
B11
B0
B31
GND
NC
B35
B37
GND
AE
B40
GND
GND
B41
B43
CSB
VDD
B44
B45
GND
ENB
B46
B47
B48
12
NC
VDD
NC
GND
OE
VDDQ VDDQ
NC
EF/
OR
VDDQ VDDQ
B18
B20
B17
B19
B21
VDDQ
B24
B25
B26
4
NC
GND
B28
B29
B30
6
VDD
B36
GND
GND
8
GND
B49
B50
B51
13
VDDQ
B53
B54
B55
15
B62
B59
B58
B63
B60
B27
VDDQ
VDDQ
5
B32
B33
B34
7
VDDQ
B38
B39
9
B52
VDDQ
VDDQ
14
U
V
VDDQ
B42
GND
VDDQ
U
V
VDDQ VDDQ
CLKB GND
VDDQ VDDQ
1
2
10
11
17
18
Document #: 38-06028 Rev. *B
Page 4 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
memory). In the FWFT mode, the first word written to an empty
FIFO appears automatically on the outputs, and no Read
operation is required. Nevertheless, accessing subsequent
words does necessitate formal Read request. FWFT mode is
primarily used for cascading multiple FIFOs.
Functional Description
The CY7C480XV25 family of FIFOs is comprised of
high-speed, low-power, CMOS Synchronous (clocked) FIFO
memories, meaning both independent ports employ a
synchronous interface. All data transfers through a port are
gated to the LOW-to-HIGH transition of the clock on either port
by the enable signal. The clocks for each port are independent
of one another and can be asynchronous or coincident. The
enable for each port is arranged to provide a simple unidirec-
tional interface between microprocessors and/or buses with
synchronous control.
The FIFO has an EF/OR flag on port B and FF/IR flag on Port
A. The EF and FF functions are selected in the Cypress
Standard mode. EF indicates whether or not the FIFO memory
is empty. FF shows whether or not the memory is full. The IR
and OR functions are selected in the FWFT mode. IR indicates
whether or not the FIFO has memory locations available. OR
shows whether the FIFO has data available for reading or not.
It marks the presence of valid data on the outputs.
Two kinds of reset are available on the CY7C480XV25: Master
Reset and Partial Reset. Master Reset initializes the Read and
Write pointers to the first location of the memory array,
configures the FIFO for Big Endian or Little Endian byte
arrangement, selects the Cypress standard or First-Word
Fall-Through (FWFT) mode, and determines the configuration
of the programmable flags. The flags can be programmed
either in serial mode or in parallel mode. The FIFO also comes
with three possible default flag offset settings: 8, 16, or 64.
The FIFO has a programmable Almost Empty flag (AE) and a
programmable Almost Full flag (AF). AE indicates the number
of words left in the FIFO memory is at the user-defined
amount. AF indicates the number of words written into the
FIFO memory has achieved a predetermined amount.
FF/IR and AF flags are synchronized to Port A clock that writes
data into its array. EF/OR and AE flags are synchronized to
Port B clock that reads data from its array. Programmable
offsets for AE and AF are loaded in parallel via Port A or in
serial via the SD input. The Serial Programming mode (SPM)
pin makes this selection. Three default offsets setting are also
provided. The AE threshold can be set at 8, 16, or 64 locations
from the empty boundary and AF threshold can be set at 8, 16,
or 64 locations from the full boundary. All these choices are
made using the FS0 and FS1 inputs during Master Reset.
Partial Reset also sets the Read and Write pointers to the first
location of the memory. Unlike Master Reset, any settings
existing prior to Partial Reset (i.e., programming method and
partial flag default offsets) are retained. Partial Reset is useful
since it permits flushing of the FIFO memory without changing
any configuration settings.
The CY7C480XV25 have two modes of operation: Cypress
Standard mode or FWFT mode. In the Cypress Standard
mode, the first word written to an empty FIFO is deposited into
the memory array. A Read operation is required to access that
word (along with all other subsequent words residing in
The CY7C480XV25 FIFOs are characterized for operation
from 0°C to 70°C (commercial) and –40°C to 85°C (industrial).
Selection Guide
CY7C480XV25-200
200
CY7C480XV25-166
Unit
MHz
ns
Maximum Frequency
166
4.0
6
Maximum Access Time
Minimum Cycle Time
3.8
5
ns
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
1.0
0.6
3.8
1.5
0.6
4.0
ns
ns
ns
CY7C4808V25
64K × 80
CY7C4806V25
CY7C4804V25
Density
16K × 80
4K × 80
Package
288 FBGA
288 FBGA
288 FBGA
Document #: 38-06028 Rev. *B
Page 5 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Pin Description
Pin
Description
VDDQ
Power supply for I/Os
Power supply for internal logic
Ground
VDD
GND
VREF
Reference voltage
Master reset
MR
PR
Partial reset
A0–A79
Input data bus
B0–B79
Output data bus
Port A enable pin
Port B enable pin
Port A chip select
Port B chip select
Output enable
ENA
ENB
CSA
CSB
OE
CLKA
Port A clock
CLKB
Port B clock
BE/FWFT
Big/Little Endian and Cypress Standard/FWFT mode select pin
Port A bus size configuration pins
Port B bus size configuration pins
Retransmit pin/serial programming select
JTAG pins
SIZE1A, SIZE2A
SIZE1B, SIZE2B
RT/SPM
TDI, TDO, TCK, TMS, TRST
FS1/SEN, FS0/SD
Programmable flags configuration pins
Empty/Output Ready flag (Port B)
Full/Input Ready flag (Port A)
EF/OR
FF/IR
AE
Programmable Almost Empty flag (Port B)
Programmable Almost Full flag (Port A)
AF
Document #: 38-06028 Rev. *B
Page 6 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
A LOW on the BE/FWFT input when the Master Reset (MR)
input goes from LOW to HIGH will select a Little Endian
arrangement. When data is moving from Port A to Port B, the
least significant byte (short word/word) of the long-word
written to Port A will be transferred to Port B first; the most
significant byte (short word/word) of the long-word written to
Port A will be transferred to Port B last.
Signal Description
Master Reset (MR)
The FIFO memory of the CY7C480XV25 undergoes a
complete reset by taking its associated Master Reset (MR)
input LOW for at least four clock edges of the slowest clock.
The Master Reset input can switch asynchronously to the
clocks. A Master Reset initializes the internal Read and Write
pointers and forces the Full/Input Ready flag (FF/IR) LOW, the
Empty/Output Ready flag (EF/OR) LOW, the Almost Empty
flag (AE) LOW, and the Almost Full flag (AF) HIGH. After a
Master Reset, the FIFO’s Full/Input Ready flag is set HIGH
after two clock cycles to begin normal operation. A Master
Reset must be performed on the FIFO after power up, before
data is written to its memory.
After Master Reset, the FWFT select function is active,
permitting a choice between two possible timing modes:
Cypress Standard mode or FWFT mode. Once the Master
Reset (MR) input is HIGH, a HIGH on the BE/FWFT input at
the second LOW-to-HIGH transition of CLKA will select
Cypress Standard mode. This mode uses the Empty Flag
function (EF) to indicate whether or not there are any words
present in the FIFO memory. It uses the Full Flag function (FF)
to indicate whether or not the FIFO memory has any free
space for writing. In Cypress Standard mode, every word read
from the FIFO, including the first, must be requested using a
formal Read operation.
A LOW-to-HIGH transition on a FIFO Master Reset (MR) input
latches the value of the Big Endian (BE) input, determining the
order by which bytes are transferred through Port B.
A LOW-to-HIGH transition on a FIFO reset (MR) input latches
the values of the Flag Select (FS0, FS1) and Serial
Programming mode (SPM) inputs for choosing the Almost Full
and Almost Empty offset programming method (see Almost
Empty and Almost Full flag offset programming below).
Once the Master Reset (MR) input is HIGH, a LOW on the
BE/FWFT input at the second LOW-to-HIGH transition of
CLKA will select FWFT mode. This mode uses the Output
Ready function (OR) to indicate whether or not there is valid
data at the data outputs (B0–79). It also uses the Input Ready
function (IR) to indicate whether or not the FIFO memory has
any free space for writing. In the FWFT mode, the first word
written to an empty FIFO goes directly to data outputs, no
Read request necessary. Subsequent words must be
accessed by performing a formal Read operation.
Partial Reset (PR)
The FIFO memory of the CY7C480XV25 undergoes a limited
reset by taking its associated Partial Reset (PR) input LOW for
at least four clock edges of the slowest clock. The Partial
Reset inputs can switch asynchronously to the clocks. A
Partial Reset initializes the internal Read and Write pointers
and forces the Full/Input Ready flag (FF/IR) LOW, the
Empty/Output Ready flag (EF/OR) LOW, the Almost Empty
flag (AE) LOW, and the Almost Full flag (AF) HIGH. After a
Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH
after two clock cycles to begin normal operation.
Following Master Reset, the level applied to the BE/FWFT
input must remain static throughout the FIFO operation.
Programming the Almost Empty and Almost Full Flags
Two registers in the CY7C480XV25 are used to hold the offset
values for the Almost Empty and Almost Full flags. The Port B
Almost Empty flag (AE) offset register is labeled X. The Port A
Almost Full flag (AF) offset register is labeled Y. The index of
each register name corresponds with preset values during the
reset of a FIFO, programmed in parallel using the FIFO’s Port
A data inputs, or programmed in serial using the Serial Data
(SD) input (see Table 2).
Whatever flag offsets, programming method (parallel or
serial), and timing mode (FWFT or Cypress Standard mode)
are currently selected at the time a Partial Reset is initiated,
those settings will remain unchanged upon completion of the
partial reset operation. A Partial Reset may be useful in the
case where reprogramming a FIFO following a Master Reset
would be inconvenient.
To load a FIFO’s Almost Empty flag and Almost Full flag offset
registers with one of the three preset values listed in Table 2,
the Serial Program mode (SPM) and at least one of the
flag-select inputs must be HIGH during the LOW-to-HIGH
transition of its Master Reset input (MR). For example, to load
the preset value of 64 into X and Y, SPM, FS0, and FS1 must
be HIGH at the rising edge of the FIFO reset (MR).
Big Endian/First-Word Fall-Through (BE/FWFT)
This is a dual-purpose pin. At the time of Master Reset, the BE
select function is active, permitting a choice of Big or Little
Endian byte arrangement for data written to or read from either
one of the ports. This selection determines the order by which
bytes (or short words or words) of data are transferred through
this port. For the following examples, assume that a byte (or
short words or word) bus size has been selected for Port B.
(Note that when Port B is configured for a long-word size, the
Big Endian function has no application and the BE input is a
“don’t care.”)
To program the X and Y registers from Port A, perform a
Master Reset with SPM HIGH and FS0 and FS1 LOW during
the LOW-to-HIGH transition of MR. After this reset is
complete, the first two Writes to the FIFO do not store data in
memory but load the offset registers in the order Y and X. The
Port A data inputs used by the offset registers are (A0–11),
(A0–13), or (A0–15),for the CY7C480XV25, respectively. The
highest numbered input is used as the most significant bit of
the binary number in each case. Valid programming values for
the registers range from 0 to 4095 for the CY7C4804V25; 0 to
A HIGH on the BE/FWFT input when the Master Reset (MR)
input goes from LOW to HIGH will select a Big Endian
arrangement. When data is moving from Port A to Port B, the
most significant byte (short word/word) of the long-word
written to Port A will be transferred to Port B first; the least
significant byte (short word/word) of the long-word written to
Port A will be transferred to Port B last.
16383 for the CY7C4806V25;
0
to 65535 for the
CY7C4808V25. FIFOs begin normal operation after
programming is complete.
Document #: 38-06028 Rev. *B
Page 7 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
To program the X and Y registers serially, initiate a Master
Reset with SPM LOW, FS0/SD LOW, and FS1/SEN HIGH
during the LOW-to-HIGH transition of MR. After this reset is
complete, the X and Y register values are loaded bit-wise
through the FS0/SD input on each LOW-to-HIGH transition of
CLKA with the FS1/SEN input LOW. Twenty-four, twenty-eight
or thirty-two bit Writes are needed to complete the
programming. The two registers are written in the order Y then
finally X. The first-bit Write stores the most significant bit of the
Y register and the last-bit Write stores the least significant bit
of the X register.
Empty/Output Ready Flags (EF/OR)
These are dual-purpose flags. In the FWFT mode, the Output
Ready (OR) function is selected. When the Output Ready flag
is HIGH, new data is present in the FIFO output register. When
the Output Ready flag is LOW, the previous data word is
present in the FIFO output register and attempted FIFO Reads
are ignored.
In the Cypress Standard mode, the Empty Flag (EF) function
is selected. When the Empty Flag is HIGH, data is available in
the FIFO’s memory for reading to the output register. When
Empty Flag is LOW, the previous data word is present in the
FIFO output register and attempted FIFO Reads are ignored.
When the option to program the offset registers serially is
chosen, the Port A Full/Input Ready (FF/IR) flag remains LOW
until all register bits are written. FF/IR is set HIGH by the
second LOW-to-HIGH transition of CLKA after the last bit is
loaded to allow normal FIFO operation.
The Empty/Output Ready flag of a FIFO is synchronized to
CLKB. For both the FWFT and Cypress Standard modes, the
FIFO Read pointer is incremented each time a new word is
clocked to its output register. The state machine that controls
an Output Ready flag monitors a Write pointer and Read
pointer comparator that indicates when the FIFO status is
empty, empty+1, or empty+2.
SPM, FS0/SD, and FS1/SEN function the same way in both
Cypress Standard and FWFT modes.
FIFO Write/Read Operation
In FWFT mode, from the time a word is written to a FIFO, it
can be shifted to the FIFO output register in a minimum of four
cycles of CLKB. Therefore, the CLKB Output Ready flag is
LOW if a word in memory is the next data to be sent to the
FIFO output register and four cycles have not elapsed since
the time the word was written. The Output Ready flag of the
FIFO remains LOW until the fourth LOW-to-HIGH transition of
CLKB occurs, simultaneously forcing the Output Ready flag
HIGH and shifting the word to the FIFO output register.
The state of the Port A data (A0–79) lines is controlled by Port
A Chip Select (CSA). Data is loaded into the FIFO from the
A0–79 inputs on a LOW-to-HIGH transition of CLKA when CSA
is LOW, ENA is HIGH, and FF/IR is HIGH (see Table 3). FIFO
Writes on Port A are independent of any concurrent Port B
operation.
The Port B control signals are identical to those of Port A. The
state of the Port B data (B0–79) lines is controlled by the Port
B Chip Select (CSB) and Output Enable (OE). The B0–79 lines
are in the high-impedance state when CSB or OE is HIGH. The
B0–79 lines are active outputs when CSB and OE are LOW.
In the Cypress Standard mode, from the time a word is written
to a FIFO, the Empty flag will indicate the presence of data
available for reading in a minimum of three cycles of CLKB.
Therefore, an Empty flag is LOW if a word in memory is the
next data to be sent to the FIFO output register and three
cycles have not elapsed since the time the word was written.
The Empty flag of the FIFO remains LOW until the third
LOW-to-HIGH transition of CLKB occurs, forcing the Empty
flag HIGH; only then can data be read.
Data is transferred to the B0–79 outputs by a LOW-to-HIGH
transition of CLKB when CSB is LOW, OE is LOW, ENB is
HIGH, and EF/OR is HIGH (see Table 4). FIFO Reads and
Writes on Port B are independent of any concurrent Port A
operation.
The set-up and hold time constraints to the port clocks for the
port Chip Selects are only for enabling Write and Read opera-
tions and are not related to high-impedance control of the data
outputs. If a port enable is LOW during a clock cycle, the port’s
Chip Select may change states during the set-up and hold time
window of the cycle.
A LOW-to-HIGH transition on the CLKB begins the first
synchronization cycle of a Write if the clock transition occurs
at time tSKEW1 or greater after the Write. Otherwise, the subse-
quent clock cycle can be the first synchronization cycle.
Full/Input Ready Flags (FF/IR)
When operating the FIFO in FWFT mode and the Output
Ready flag is LOW, the next word written is automatically sent
to the FIFO’s output register by the LOW-to-HIGH transition of
CLKB, data residing in the FIFO’s memory array is clocked to
the output register only when a Read is selected using the
port’s Chip Select, and Enable.
This is a dual-purpose flag. In FWFT mode, the Input Ready
(IR) function is selected. In Cypress Standard mode, the Full
Flag (FF) function is selected. For both timing modes, when
the Full/Input Ready flag is HIGH, a memory location is free in
the memory to receive new data. No memory locations are free
when the Full/Input Ready flag is LOW and attempted Writes
to the FIFO are ignored.
When operating the FIFO in Cypress Standard mode, data
residing in the FIFO’s memory array is clocked to the output
register only when a Read is selected using the port’s Chip
Select, and Enable.
The Full/Input Ready flag of a FIFO is synchronized to CLKA.
For both FWFT and Cypress Standard modes, each time a
word is written to a FIFO, its Write pointer is incremented. The
state machine that controls a Full/Input Ready flag monitors a
Write pointer and Read pointer comparator that indicates
when the FIFO memory status is full, full–1, or full–2. From the
time a word is read from a FIFO, its previous memory location
is ready to be written to in a minimum of two cycles CLKA.
Therefore, a Full/Input Ready flag is LOW if less than two
cycles of CLKA have elapsed since the next memory Write
location has been read. The second LOW-to-HIGH transition
on CLKA after the Read sets the Full/Input Ready flag HIGH.
Synchronized FIFO Flags
Each FIFO is synchronized to its port clock through at least two
flip-flop stages. This is done to improve flag-signal reliability by
reducing the probability of the metastable events when CLKA
and CLKB operate asynchronously to one another. EF/OR and
AE are synchronized to CLKB. FF/IR and AF are synchronized
to CLKA. Table 5 shows the relationship of each port flag to
the FIFO.
Document #: 38-06028 Rev. *B
Page 8 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
A LOW-to-HIGH transition on CLKA begins the first synchro-
nization cycle of a Read if the clock transition occurs at time
tSKEW1 or greater after the Read. Otherwise, the subsequent
clock cycle can be the first synchronization cycle.
Bus Sizing
Both Port A and Port B buses can be configured in an 80-bit
long word, 40-bit word, 20-bit short word or 10-bit byte format.
The levels applied to Bus Size Select (SIZE1A, SIZE2A,
SIZE1B, SIZE2B) determine the bus size. Bus size on either
port can be set independent of each other. These levels should
be static throughout FIFO operation. Both bus size selections
are implemented at the completion of Master Reset, by the
time the Full/Input Ready flag is set HIGH.
Almost Empty Flags (AE)
The Almost Empty flag of a FIFO is synchronized to CLKB.
The state machine that controls an Almost Empty flag monitors
a Write pointer and Read pointer comparator that indicates
when the FIFO memory status is almost empty, almost
empty+1, or almost empty+2. The Almost Empty state is
defined by the contents of register X for AE. These registers
are loaded with preset values during a FIFO reset,
programmed from Port A, or programmed serially (see Almost
Empty flag and Almost Full flag offset programming above). An
Almost Empty flag is LOW when its FIFO contains X or less
words and is HIGH when its FIFO contains (X + 2) or more
words.
Only 80-bit long word data is written to or read from the two
FIFO memories. Bus-matching operations are done before the
data is written into the memory (for Port A) and after (for Port
B) data is read from the memory.
Bus-Matching FIFO Reads
Data is read from the FIFO memory in 80-bit long-word incre-
ments. If a long-word bus size is implemented, the entire long-
word immediately shifts to the FIFO output register. If byte or
word size is implemented on Port B, only the first one or two
bytes appear on the selected portion of the FIFO output
register, with the rest of the long-word stored in auxiliary
registers. In this case, subsequent FIFO Reads output the rest
of the long-word to the FIFO output register.
A LOW-to-HIGH transition of CLKB begins the first synchroni-
zation cycle if it occurs at time tSKEW2 or greater after the Write
that fills the FIFO to (X + 2) words. Otherwise, the subsequent
synchronizing clock cycle may be the first synchronization
cycle.
Almost Full Flags (AF)
When reading data from the FIFO in the byte, short word, or
word format, the unused outputs will be LOW.
The Almost Full flag of a FIFO is synchronized to CLKA. The
state machine that controls an Almost Full flag monitors a
Write pointer and Read pointer comparator that indicates
when the FIFO memory status is almost full, Almost Full–1, or
Almost Full–2. The Almost Full state is defined by the contents
of register Y for AF. These registers are loaded with preset
values during a FIFO reset, programmed from Port A, or
programmed serially (see Almost Empty flag and Almost Full
flag offset programming above). An Almost Full flag is LOW
when the number of words in its FIFO is greater than or equal
to (4096 – Y), (16384 – Y), or (65536 – Y), for the
CY7C480XV25, respectively. An Almost Full flag is HIGH
when the number of words in its FIFO is less than or equal to
[4096 – (Y + 2)], [16384 – (Y + 2)], or [65536 – (Y + 2)], for the
CY7C480XV25, respectively.
Retransmit (RT)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The retransmit feature is intended for use when a number of
Writes equal to or less than the depth of the FIFO have
occurred and at least one word has been read since the last
reset cycle. A LOW pulse on RT resets the internal Read
pointer to the first physical location of the FIFO. CLKA and
CLKB may be free running but ENB must be deasserted
during the retransmit pulse and remain deasserted until after
the Empty/Output Ready flag (EF/OR) goes HIGH. With every
valid Read cycle after retransmit, previously accessed data is
read and the Read pointer is incremented until it arrives at the
same location as the Write pointer. Flags are governed by the
relative locations of the Read and Write pointers and are
updated during a retransmit cycle. Data written to the FIFO
after activation of RT are transmitted also. The full depth of the
FIFO can be repeatedly retransmitted.
A LOW-to-HIGH transition of CLKA begins the first synchroni-
zation cycle if it occurs at time tSKEW2 or greater after the Read
that reduces the number of words in memory to
[4096/16384/65536 – (Y + 2)]. Otherwise, the subsequent
synchronizing clock cycle may be the first synchronization
cycle.
Document #: 38-06028 Rev. *B
Page 9 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Table 1. Endian/Bus Matching Configuration[1]
Each character (“A”, “B”,..., “H”) represents 10-bit data
BE/FWFT
Size 1A
Size 2A
Port A
Size 1B
Size 2B
Port B
bit#79 bit#0
1
0
0
x80
0
0
x80
Write to FIFO
ABCDEFGH
Read from FIFO
Read from FIFO
ABCDEFGH
0
1
1
0
x40
x20
ABCD
EFGH
Read from FIFO
Read from FIFO
AB
CD
EF
GH
1
1
x10
A
B
C
D
E
F
G
H
0
1
x40
0
0
x80
Write to FIFO
ABCD
EFGH
Read from FIFO
Read from FIFO
ABCDEFGH
0
1
1
0
x40
x20
ABCD
EFGH
AB
CD
EF
GH
A
Read from FIFO
1
1
x10
Read from FIFO
B
C
D
E
F
G
H
Note:
1. BE is selected at Master Reset; SIZE1A, SIZE2A, SIZE1B, AND SIZE2B must be static throughout device operation.
Document #: 38-06028 Rev. *B
Page 10 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Table 1. Endian/Bus Matching Configuration[1] (continued)
Each character (“A”, “B”,..., “H”) represents 10-bit data
BE/FWFT
Size 1A
Size 2A
Port A
Size 1B
Size 2B
Port B
bit#79 bit#0
1
0
x20
0
0
x80
Write to FIFO
AB
CD
EF
GF
Read from FIFO
Read from FIFO
ABCDEFGH
0
1
1
0
x40
x20
ABCD
EFGH
AB
CD
EF
GH
A
Read from FIFO
1
1
x10
Read from FIFO
B
C
D
E
F
G
H
Document #: 38-06028 Rev. *B
Page 11 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Table 1. Endian/Bus Matching Configuration[1] (continued)
Each character (“A”, “B”,..., “H”) represents 10-bit data
BE/FWFT
Size 1A
Size 2A
Port A
Size 1B
Size 2B
Port B
bit#79 bit#0
1
1
1
x10
0
0
x80
Write to FIFO
A
B
C
D
E
F
G
H
Read from FIFO
Read from FIFO
ABCDEFGH
0
1
1
0
x40
x20
ABCD
EFGH
AB
CD
EF
GH
A
Read from FIFO
1
1
x10
Read from FIFO
B
C
D
E
F
G
H
Document #: 38-06028 Rev. *B
Page 12 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Table 1. Endian/Bus Matching Configuration[1] (continued)
Each character (“A”, “B”,..., “H”) represents 10-bit data
BE/FWFT
Size 1A
Size 2A
Port A
Size 1B
Size 2B
Port B
bit#79 bit#0
0
0
0
x80
0
0
x80
Write to FIFO
ABCDEFGH
Read from FIFO
Read from FIFO
ABCDEFGH
0
1
1
0
x40
x20
EFGH
ABCD
Read from FIFO
GH
EF
CD
AB
1
1
x10
Read from FIFO
H
G
F
E
D
C
B
A
0
1
x40
0
0
x80
Write to FIFO
ABCD
EFGH
Read from FIFO
Read from FIFO
EFGHABCD
0
1
1
0
x40
x20
ABCD
EFGH
CD
AB
GH
EF
D
Read from FIFO
1
1
x10
Read from FIFO
C
B
A
H
G
F
E
Document #: 38-06028 Rev. *B
Page 13 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Table 1. Endian/Bus Matching Configuration[1] (continued)
Each character (“A”, “B”,..., “H”) represents 10-bit data
BE/FWFT
Size 1A
Size 2A
Port A
Size 1B
Size 2B
Port B
bit#79 bit#0
0
1
0
x20
0
0
x80
Write to FIFO
AB
CD
EF
GH
Read from FIFO GH EF CD AB
0
1
1
0
x40
x20
Read from FIFO
CDAB
GHEF
Read from FIFO
AB
CD
EF
GH
1
1
x10
Read from FIFO
B
A
D
C
F
E
H
G
1
1
x10
0
0
x80
Write to FIFO
A
B
C
D
E
F
G
H
HGFEDCBA
DCBA
HGFE
BA
Read from FIFO
Read from FIFO
0
1
1
0
x40
x20
Read from FIFO
DC
FE
HG
Document #: 38-06028 Rev. *B
Page 14 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Table 1. Endian/Bus Matching Configuration[1] (continued)
Each character (“A”, “B”,..., “H”) represents 10-bit data
BE/FWFT
Size 1A
Size 2A
Port A
Size 1B
Size 2B
Port B
bit#79 bit#0
0
1
1
x10
1
1
x10
Read from FIFO
A
B
C
D
E
F
G
H
Table 2. Flag Programming
SPM
H
FS1/SEN
FS0/SD
MR
X and Y Registers[2]
H
H
L
H
L
↑
↑
↑
↑
↑
↑
↑
↑
64
16
8
H
H
H
L
H
L
Parallel programming via Port A
Serial programming via SD
Reserved
L
H
H
L
L
L
H
H
L
L
Reserved
L
L
Reserved
Table 3. Port A Enable Function
CSA
ENA
X
CLKA
A0–79 Inputs
Port Function
None
H
L
L
X
X
↑
In high-impedance state
In high-impedance state
In high-impedance state
L
None
H
FIFO Write
Table 4. Port B Enable Function
CSB
ENB
X
CLKB
B0–79 Outputs
Port Function
None
H
L
L
X
X
↑
In high-impedance state
Active, FIFO output register
Active, FIFO output register
L
None
H
FIFO Read
Note:
2. X register holds the offset for AE; Y register holds the offset for AF.
Document #: 38-06028 Rev. *B
Page 15 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Table 5. FIFO Flag Operation (Cypress Standard and FWFT Modes)
Number of Words in FIFO Memory[4, 5, 6, 7]
Synchronized to CLKB
Synchronized to CLKA
CY7C4804V25
CY7C4806V25
CY7C4808V25
EF/OR
AE
L
AF
H
FF/IR
0
0
0
L
H
H
H
H
H
1 to X
1 to X
1 to X
L
H
(X + 1) to [4096 – (X + 1) to [16834 – (X + 1) to [65536 –
H
H
(Y + 1)]
(Y + 1)]
(Y + 1)]
(4096 – Y1) to
(16384 – Y1) to
(65536 – Y1) to
H
H
H
H
L
L
H
L
4095
16383
65535
4096
16384
65536
2.5V 64K ×80 Unidirectional Synchronous FIFO w/bus matching[3]
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
CY7C4808V25-166BBC
CY7C4808V25-200BBC
CY7C4808V25-200BBI
PackageType
166
200
200
BB288
288-ball Grid Array (1.0-mm pitch, 19 × 19mm) Commercial
BB288
288-ball Grid Array (1.0-mm pitch, 19 × 19mm) Industrial
2.5V 16K ×80 Unidirectional Synchronous FIFO with Bus Matching
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
CY7C4806V25-166BBC
CY7C4806V25-200BBC
Package Type
166
200
BB288
288-ball Grid Array (1.0-mm pitch, 19 × 19mm) Commercial
2.5V 4K ×80 Unidirectional Synchronous FIFO with Bus Matching
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
CY7C4804V25-166BBC
CY7C4804V25-200BBC
Package Type
166
200
BB288
288-ball Grid Array (1.0-mm pitch, 19 × 19mm) Commercial
Notes:
3. Shaded areas contain advance information.
4. X is the Almost Empty offset for FIFO used by AE. Y is the Almost Full offset for FIFO used by AF. Both X and Y are selected during a FIFO reset or Port A
programming.
5. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
6. Data in the output register does not count as a “word in FIFO memory.” Since in FWFT mode the first word written to an empty FIFO goes unrequested to the
output register (no Read operation necessary), it is not included in the FIFO memory count.
7. The OR and IR functions are active during FWFT mode; the EF and FF functions are active in Cypress Standard mode.
Document #: 38-06028 Rev. *B
Page 16 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Maximum Ratings [8]
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current....................................................> 200 mA
Storage Temperature ...................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Ambient
Supply Voltage to Ground Potential............... –0.5V to +3.6V
Range
Temperature
VDD
VDDQ
DC Voltage Applied to Outputs
Commercial 0°C to +70°C 2.5V ± 100 mV 1.4V to 1.9V
Industrial –40°C to +85°C
in High Z State[9] ..................................–0.5V to VDDQ + 0.5V
DC Input Voltage[9]...............................–0.5V to VDDQ + 0.5V
DC Specifications (All I/Os except JTAG ports will be at HSTL level)[10, 11, 14]
CY7C480XV25
Min.
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Max.
2.6
Unit
V
2.4
1.4
VDDQ
1.9
V
VREF
Input Reference Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Typical value = 0.75V
IOH = –8mA
0.7
1.0
V
VOH
VDDQ – 0.4
VSS
VDDQ
V
VOL
IOL=8 mA
0.4
V
VIH(DC)
VIL(DC)
VOH_JTAG
VREF + 0.1[13]
VDDQ + 0.3
VREF – 0.1[13]
V
–0.3
V
JTAG Port Output HIGH Volt-
age
IOH = –100 µA
IOH = –2 mA
2.1
V
1.7
V
VOL_JTAG
JTAG Port Output LOW Voltage
IOL = 100 µA
0.2
0.7
V
IOL = 2 mA
V
VIH_JTAG
VIL_JTAG
IIX
JTAG Port Input HIGH Voltage
JTAG Port Input LOW Voltage
Input LeakageCurrent
VOUT > VVOH(min.)
VOUT < VVOL(max.)
1.7
–0.3
–10
–10
VDD+0.3
0.7
V
V
+10
µA
µA
mA
mA
mA
IOZL,IOZH
ISB
Output OFF, High Z Current
Average Standby Current
Operating current (Typical)
Operating current (Max.)
+10
40[12]
ICC
VDD = max., IOUT = 0 mA
600
680
480
560
Notes:
8. The Voltage on any input or I/O pin cannot exceed the power pin during power-up
9. Minimum voltage equals –2.0V for pulse duration less than 20 ns.
10. All voltage referenced to ground.
11. Overshoot: VIH (AC) < VDD+1.5V for t < tclk/2, power-up: VIH< 2.6V and VDD < 2.4V and VDDQ< 1.4V for t < 200 ns.
12. ISB condition: VREF = VDD. All reset pins are HIGH (VDD). All AINs are LOW (0V). CS is HIGH (VDD). EN is LOW (0V).
13. All input pin voltage levels cannot stay between VIH (DC) and VIL (DC) in the idle mode.
VIH (AC) = VREF + 0.2V
VIH (DC)
VREF
V
IL (DC)
VIL (AC) = VREF - 0.2V
14. Both clocks switching at maximum speeds, data switching at half the clock frequency.
Document #: 38-06028 Rev. *B
Page 17 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
AC Specifications (A 50Ω load terminated into 0.75V is used with VDDQ
)
CY7C480XV25
Parameter
Description
Max. Frequency
Min.
Max.
200
Unit
MHz
ns
FMAX
tCYC
tSD
Clock Cycle Time
Input Data Set-up Time
Input Data Hold Time
Access Time
5
1.0
0.6
3.8
ns
tHD
ns
tA
ns
AC Test Loads and Waveforms[15]
V
TH = (VDDQ)/2
RL = 50Ω
V
TH = (VDDQ)/2
(VDDQ)/2
ZO = 50Ω
(VDDQ)/2
VREF
VREF
Output
RL = 50Ω
Output
5 pF
Device
Device
Under
Test
Under
Test
ALL INPUT PULSES
90%
1.25V
90%
0.75V
0.25V
10%
tF
10%
tR
tR ≤ 0.5 ns, tF ≤ 0.5 ns
Notes:
15. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (b) of AC Test Loads.
Document #: 38-06028 Rev. *B
Page 18 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Timing Parameters
7C480XV25- 7C480XV25-
200 166
Parameter
Description
Min. Max. Min. Max. Unit
fS
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
200
166 MHz
tCLK
tCLKH
tCLKL
tDS
5
6
3
ns
ns
ns
ns
ns
Pulse Duration, CLKA or CLKB HIGH
Pulse Duration, CLKA or CLKB LOW
Data Set-up Time, A79–0 before CLKA↑
2.5
2.5
1.0
1.0
3
1.5
1.5
tENS
Enable Set-up Time, CSA or ENA before CLKA↑; CSB or ENB before
CLKB↑
tFSS
Set-up Time, FS0 and FS1 before MR HIGH
Set-up Time, BE/FWFT before MR HIGH
Set-up Time, SPM before MR HIGH
2
2.5
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBES
tSPMS
tRSTS
tSDS
tSENS
tFWS
tDH
3
2
2.5
3
Set-up Time, MR or PR or RT before CLK↑
Set-up Time, FS0/SD before CLKA↑
2.5
1.0
1.0
1.0
0.6
0.6
2
1.5
1.5
1.5
0.6
0.6
2.5
2.5
2.5
3
Set-up Time, FS1/SEN before CLKA↑
Set-up Time, FWFT before CLKA↑
Data Hold Time, A79–0 after CLKA↑
tENH
tFSH
tBEH
tSPMH
tRSTH
tSDH
tSENH
tSPH
Enable Hold Time, CSA or ENA after CLKA↑; CSB or ENB after CLKB↑
Hold Time, FS0 and FS1 after MR HIGH
Hold Time, BE/FWFT after MR HIGH
2
Hold Time, SPM after MR HIGH
2
Hold Time, MR or PR or RT after CLK↑
Hold Time, FS0/SD after CLKA↑
2.5
0.6
0.6
2
0.6
0.6
2.5
6.5
6.5
Hold Time, FS1/SEN after CLKA↑
Hold Time, FS1/SEN HIGH after MR HIGH
Skew Time between CLKA↑ and CLKB↑ for EF/OR and FF/IR
Skew Time between CLKA↑ and CLKB↑ for AE and AF
Access Time, CLKB↑ to B79–0
tSKEW1
tSKEW2
tA
4.5
4.5
3.8
3.8
3.8
3.8
3.8
7
4.0
4.0
4.0
4.0
4.0
7
ns
ns
ns
ns
ns
ns
tWFF
tREF
Propagation Delay Time, CLKA↑ to FF/IR
Propagation Delay Time, CLKB↑ to EF/OR
Propagation Delay Time, CLKB↑ to AE
Propagation Delay Time, CLKA↑ to AF
tPAE
tPAF
tRSF
Propagation Delay Time, MR or PR LOW to AE LOW, AF HIGH,FF/ IR
LOW and EF/ OR LOW
tEN
tDIS
Enable Time, CSB LOW or OE LOW to B79–0 Active
4.8
4.6
4.8
4.6
ns
ns
Disable Time, CSB HIGH or OE HIGH to B79–0 at High Impedance
Document #: 38-06028 Rev. *B
Page 19 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Switching Waveforms
Master Reset Loading X and Y with a Preset Value of Eight [16, 17, 18, 19]
CLK
1
2
3
4
tRSTH
tRSTS
MR
tFWS
tBEH
tBES
BE/FWFT
tSPMH
tSPMS
RT/SPM
tFSH
tFSS
FS1/SEN,
FS0/SD
tRSF
FF/IR
tRSF
tWFF
EF/OR
tRSF
AE
AF
tRSF
Partial Reset (CY Standard and FWFT Modes)[17, 18, 19, 20]
CLK
tRSTH
4
1
2
3
tRSTS
PR
tRSF
tWFF
FF/IR
tRSF
EF/OR
tRSF
AE
AF
tRSF
Notes:
16. PR must be HIGH during Master Reset.
17. MR and PR must be LOW for at least four clock edges (referenced to the slowest clock).
18. tRSTS and tRSTH are referenced to the slowest clock.
19. tWFF is referenced to CLKA.
20. MR must be HIGH during Partial Reset.
Document #: 38-06028 Rev. *B
Page 20 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Switching Waveforms (continued)
Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(Cypress Standard and FWFT Modes)[21]
CLKA
MR
tSPMS
tSPMH
RT/SPM
tFSH
tFSS
FS1/SEN,
FS0/SD
tWFF
FF/IR
tENS
tENH
tENH
tENS
tENS
tENH
ENA
tDS
tDH
W1
X
Y
A0-79
AE Offset (X)
First Word into FIFO
AF Offset (Y)
Serial Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values (Cypress Standard and FWFT Modes)[22]
CLKA
MR
tSPMH
tSPMS
RT/SPM
tWFF
FF/IR
tSENS
tFSS
tSENS tSENH
tSPH
tSENH
FS1/SEN
tSDS
tSDH
tSDH
tSDS
tFSS tFSH
[23]
FS0/SD
AF Offset (Y) MSB
AE Offset (X) LSB
W1
A0-79
AE
Low
tPAF
AF
Notes:
21. CSA = LOW. It is not necessary to program offset register on consecutive clock cycles.
22. It is not necessary to program offset register bits on consecutive clock cycles. FIFO Write attempts are ignored until FF/IR is set HIGH.
23. Programmable offsets are written serially to the SD input in the order AF offset (Y) then AE offset (X).
Document #: 38-06028 Rev. *B
Page 21 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Switching Waveforms (continued)
Port B Long-Word Read Cycle Timing for FIFO (Cypress Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
CLKB
EF/OR
CSB
HIGH
tENS
tENH
tENS
tENH
tENH
tENS
ENB
tA
tA
tDIS
No Operation
B0–79
tEN
Previous Data
tA
(Standard mode)
OR
B0–79
(FWFT mode)
W1
W2
W2
tDIS
tA
tEN
W1
W3
OE
Port B Word Read Cycle Timing for FIFO (Cypress Standard and FWFT Modes)[24]
CLKB
EF/OR
CSB
HIGH
tENH
tENS
ENB
tA
tDIS
tA
No Operation
Read 2
B0–39
(Standard mode)
tEN
Read 1
Read 2
Previous Data
tA
tDIS
OR
B0–39
(FWFT mode)
tA
tEN
Read 1
Read 3
OE
Note:
24. Unused bits B40–79 are zeroes for word-size reads.
Document #: 38-06028 Rev. *B
Page 22 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Switching Waveforms (continued)
Port B Short Word Read Cycle Timing for FIFO (Cypress Standard and FWFT Modes)[25]
CLKB
EF/OR
HIGH
CSB
t
ENStENH
ENB
tDIS
tA
Read 1
tA
tA
tA
Read 2
No Operation
tEN
B0–19
(Standard mode)
OR
B0–19
Previous Data
tA
Read 4
Read 3
tA
tDIS
tA
tA
tEN
Read 1
Read 5
Read 4
Read 2
(FWFT mode)
Read 3
OE
Port B Byte Read Cycle Timing for FIFO (Cypress Standard and FWFT Modes)[26]
CLKB
EF/OR
HIGH
CSB
t
ENStENH
ENB
tDIS
tA
Read 1
tA
tA
tA
Read 2
No Operation
tEN
B0–9
(Standard mode)
OR
B0–9
Previous Data
tA
Read 4
Read 3
tA
tDIS
tA
tA
tEN
Read 1
Read 5
Read 4
Read 2
(FWFT mode)
Read 3
OE
Notes:
25. Unused bits B20–79 are zeroes for short word-size Reads.
26. Unused bits B10–79 are zeroes for byte-size Reads.
Document #: 38-06028 Rev. *B
Page 23 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Switching Waveforms (continued)
OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode)[27]
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
HIGH
t
ENStENH
ENA
FF/IR
tDS tDH
W1
A0–79
CLKB
[28]
tCLKH
tCLKL
tSKEW1
tREF
tREF
tCLK
EF/OR
CSB
FIFO Empty
LOW
tENS tENH
ENB
tA
B0-79
OE
W1
Old Data in FIFO Output Register
LOW
Notes:
27. If Port B size is word, short word, or byte, EF is set LOW by the last word, short word, or byte Read from the FIFO, respectively.
28. SKEW1 (7 ns minimum) is the time between a rising CLKA edge and a rising CLKB edge for OR flag to transition HIGH. If the time between these two edges
t
is less than tSKEW1, the transition of OR HIGH may occur one CLKB cycle later than shown. CLKA and CLKB above are assumed to run at 200MHz (5 ns
cycle time), which results in OR flag being updated after the fourth CLKB edge. If the clock cycles are more than 7 ns, OR flag may get updated after the
third clock edge, depending on when the clock edges occur. In general, OR flag update cycle = (tSKEW1) + (2 clock cycle) + (tREF).
Document #: 38-06028 Rev. *B
Page 24 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Switching Waveforms (continued)
EF Flag Timing and First Data Read Fall Through when FIFO is Empty (Cypress Standard Mode)[27]
tCLK
tCLKH
tCLKL
CLKA
CSA
ENA
LOW
HIGH
t
ENStENH
FF/IR
A0–79
tDS tDH
W1
[29]
tSKEW1
CLKB
EF/OR
CSB
tREF
tREF
FIFO Empty
LOW
t
ENStENH
ENB
tA
B0–79
OE
W1
LOW
Notes:
29. SKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH. If the time between these two edges is less
t
than tSKEW1, the transition of EF HIGH may occur one CLKB cycle later than shown. CLKA and CLKB above are assumed to run at 200 MHz (5 ns cycle
time), which results in EF flag being updated after the third CLKB edge. If the clock cycles are more than 7 ns, EF flag may get updated after the second
clock edge, depending on when the clock edges occur. In general, EF flag update cycle = (tSKEW1) + (1 clock cycle) + (tREF).
Document #: 38-06028 Rev. *B
Page 25 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Switching Waveforms (continued)
FF/IR Flag Timing and First Available Write when FIFO is Full (Cypress Standard and FWFT Mode)[30]
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
t
ENStENH
ENB
EF/OR
B0–79
HIGH
tA
Previous Word in FIFO
Output Register
Next Word From FIFO
[31]
tCLKH
tSKEW1
tCLKL
CLKA
FF/IR
CSA
tWFF
tWFF
tCLK
FIFO Full
LOW
tENH
tENS
ENA
tDH
tDS
A0−79
Notes:
30. If Port B size is word, short word, or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word, short word, or byte Write of the long-word,
respectively.
31.
tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF/IR to transition HIGH. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW1, the transition of FF/IR HIGH may occur one CLKA cycle later than shown. CLKA and CLKB above are assumed
to run at 200 MHz (5 ns cycle time), which results in FF/IR flag being updated after the third CLKA edge. If the clock cycles are more than 7 ns, FF/IR flag
may get updated after the second clock edge, depending on when the clock edges occur. In general, FF/IR flag update cycle = (tSKEW1) + (1 clock
cycle) + (tWFF).
Document #: 38-06028 Rev. *B
Page 26 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Switching Waveforms (continued)
Timing for AF when FIFO is Almost Full (Cypress Standard and FWFT Modes)[32, 33, 34]
[35]
tSKEW2
CLKA
tENS
tENH
tPAF
ENA
AF
tPAF
(D – Y) Words in FIFO
[D – (Y + 2)] Words in FIFO
[D – (Y + 1)] Words in FIFO
tENS
tENS
CLKB
ENB
tENH
tENH
tENS
Timing for AE when FIFO is Almost Empty (Cypress Standard and FWFT Modes)[36, 37]
CLKA
tENH
tENS
tENHtENS
ENA
[38]
tSKEW2
CLKB
tPAE
tPAE
(X + 1) Words in FIFO
X Word in FIFO
AE
(X + 1) Word in FIFO
X Word in FIFO
(X + 2 ) Word in FIFO
tENH
t
ENHtENS
tENS
ENB
Notes:
32. FIFO Write (CSA = LOW) on Port A, FIFO Read (CSB = LOW) on Port B. Data in the FIFO output register has been read from the FIFO.
33. D = Maximum FIFO Depth = 4K for the CY7C4804V25, 16K for the CY7C4806V25, and 64K for the CY7C4808V25.
34. If Port B size is word, short word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word, short word or byte of the long word, respectively.
35. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between these
two edges is less than tSKEW2, AF may transition HIGH one CLKB cycle later than shown. CLKA and CLKB above are assumed to run at 200 MHz (5 ns
cycle time), which results in AF flag being updated after the third CLKA edge. If the clock cycles are more than 7 ns, AF flag may get updated after the
second clock edge, depending on when the clock edges occur. In general, AF flag update cycle = (tSKEW2) + (1 clock cycle) + (tPAF).
36. FIFO Write (CSA = LOW) on Port A, FIFO Read (CSB = LOW) on Port B. Data in the FIFO output register has been read from the FIFO.
37. If Port B size is word, short word, or byte, AE is set LOW by the last word, short word, or byte Read from FIFO, respectively.
38. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, AE may transition HIGH one CLKB cycle later than shown. CLKA and CLKB above are assumed
to run at 200 MHz (5 ns cycle time), which results in AE flag being updated after the third CLKB edge. If the clock cycles are more than 7 ns, AE flag may
get updated after the second clock edge, depending on when the clock edges occur. In general, AE flag update cycle = (tSKEW2) + (1 clock cycle) + (tPAE).
Document #: 38-06028 Rev. *B
Page 27 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Switching Waveforms (continued)
FIFO Retransmit Timing[39, 40, 41, 42, 43, 44, 45, 46]
tRSTH
tRSTS
RT
CLK
1
2
3
4
5
6
7
8
CLKA
AF
FF
tPAF
tWFF
CLKB
1
2
3
4
5
6
7
8
9
10
EF
(CY)
(STD)dd
tREF
ENB
(CY)
tENS
OR
(FWFT)
tREF
ENB
(FWFT)
tENS
(STD) AE
E
tPAE
Notes:
39. Clocks are free-running in this case.
40. RT must be LOW for at least eight clock edges (referenced to the slowest clock).
41. tRSTS and tRSTH are referenced to the slowest clock.
42. FF goes back HIGH at the second CLKA edge after RT goes HIGH.
43. AF goes back HIGH at the first CLKA edge after RT goes HIGH.
44. AE goes back HIGH at the first CLKB edge after RT goes HIGH.
45. tPAF and tWFF are referenced to CLKA.
46.
tREF, tENS, and tPAE are referenced to CLKB.
Document #: 38-06028 Rev. *B
Page 28 of 30
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Package Diagram
288-ball Grid Array (1.0 pitch, 19 × 19 mm) BB288
51-85129
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06028 Rev. *B
Page 29 of 30
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C4808V25
CY7C4806V25
CY7C4804V25
PRELIMINARY
Document Title: CY7C4808V25, CY7C4806V25, CY7C4804V25 2.5V 4K/16K/64K × 80 Unidirectional Synchronous FIFO
with Bus Matching
Document Number: 38-06028
Issue
Orig. of
Change
REV.
**
ECN NO. Date
Description of Change
109959
111337
10/21/01
SZV
JFU
Change from Spec number: 38-00874 to 38-06028
*A
*B
02/07/01
1. Updated access time values
2. Updated ISB conditions
3. Updated idle mode conditions
4. Updated operating current values
5. Revised master and partial reset timing diagrams
6. Revised FIFO retransmit timing diagram
122280
12/26/02
RBI
Power up requirements added to Maximum Ratings Information
Document #: 38-06028 Rev. *B
Page 30 of 30
相关型号：
CY7C4808V25-200C
FIFO, 64KX80, 3.5ns, Synchronous, CMOS, PBGA288, 19 X 19 MM, 1 MM PITCH, FBGA-288
CYPRESS
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