CY7C4811-10AC [CYPRESS]
256/512/1K/2K/4K/8K x9 x2 Double Sync FIFOs; 五百一十二分之二百五十六/ 1K / 2K / 4K / 8K ×9 ×2双同步FIFO的
| 型号： | CY7C4811-10AC |
| 厂家： | 
CYPRESS |
| 描述： | 256/512/1K/2K/4K/8K x9 x2 Double Sync FIFOs |
| 文件： | 总23页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C4831/4
1
CY7C4801/4811/4821
CY7C4831/4841/4851
256/512/1K/2K/4K/8K x9 x2
Double Sync FIFOs
These FIFOs have two independent sets of 9-bit input and
output ports that are controlled by separate clock and enable
signals. The input port is controlled by a free-running clock
(WCLKA,WCLKB) and two write-enable pins (WENA1,
WENA2/LDA, WENB1, WENB2/LDB).
Features
• Double high speed, low power, first-in first-out (FIFO)
memories
• Double 256 x 9 (CY7C4801)
• Double 512 x 9 (CY7C4811)
• Double 1K x 9 (CY7C4821)
• Double 2K x 9 (CY7C4831)
• Double 4K x 9 (CY7C4841)
• Double 8K x 9 (CY7C4851)
• Functionally equivalent to two CY7C4201/4211/4221/
4231/4241/4251 FIFOs in a single package
• 0.65 micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10 ns read/write cycle
times)
• Offers optimal combination of large capacity, high
speed, design flexibility, and small footprint
• Fully asynchronous and simultaneous read and write
operation
• Four status flags per device: Empty, Full, and program-
mable Almost Empty/Almost Full
When (WENA1,WENB1) is LOW and (WENA2/LDA,
WENB2/LDB) is HIGH, data is written into the FIFO on the
rising edge of the (WCLKA,WCLKB) signal. While (WENA1,
WENA2/LDA, WENB1, WENB2/LDB) is held active, data is
continually written into the FIFO on each WCLKA, WCLKB
cycle. The output port is controlled in a similar manner by a
free-running read clock (RCLKA, RCLKB) and two read-en-
able pins ((RENA1,RENB1), (RENA2,RENB2)). In addition,
the CY7C48X1 has output enable pins (OEA, OEB) for each
FIFO. The read (RCLKA, RCLKB) and write (WCLKA,
WCLKB) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.
• Low power — ICC1= 60mA
• Output Enable (OEA/OEB) pins
• Depth Expansion Capability
• Width Expansion Capability
• Space-saving 64-pin TQFP
The CY7C48X1 provides twosets of four different statuspins: Empty,
Full, Almost Empty, Almost Full. The Almost Empty/Almost Full flags
are programmable to single word granularity. The programmable
flags default to Empty+7 and Full–7.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLKA,RCLKB) or the write clock
(WCLKA,WCLKB). When entering or exiting the Empty and
Almost Empty states, the flags are updated exclusively by the
(RCLKA,RCLKB). The flags denoting Almost Full, and Full
states are updated exclusively by (WCLKA,WCLKB) The syn-
chronous flag architecture guarantees that the flags maintain
their status for at least one cycle
• PincompatibleandfunctionallyequivalenttoIDT72801,
72811, 72821, 72831, 72841,72851
Functional Description
The CY7C48X1 are Double high-speed, low-power, first-in
first-out (FIFO) memories with clocked read and write interfac-
es. All are 9 bits wide and operate as two separate FIFOs. The
CY7C48X1 are pin-compatible to IDT728X1. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor interfac-
es, and communications buffering.
All configurations are fabricated using an advanced 0.65µ
N-Well CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06005 Rev. **
Revised January 15, 1997
CY7C4801/4811/4821
CY7C4831/4841/4851
FLAG
PROGRAM
REGISTER
LDA
LDB
Logic
DB0-8
DA0-8
Block Diagram
WCLKA
WCLKB
WENB1
WENA1
EFA
WENB2/LDB
WENA2/LDA
PAEA
PAFA
FFA
FLAG
LOGIC
INPUT
REGISTER
EFB
PAEB
PAFB
FFB
INPUT
REGISTER
WRITE
CONTROL
WRITE
CONTROL
RAM
ARRAY A
x9
25.6
WRITE
POINTER A
.
8k x 9
READ
POINTER A
READ
POINTER B
RAM
ARRAY B
.
8k.x 9
WRITE
POINTER B
x9
256
READ
CONTROL A
READ
CONTROL B
RSA
RSB
RESET
LOGIC
THREE–STATE
OUTPUT REGISTER
THREE–STATE
OUTPUT REGISTER
OEA
QA0-8
RCLKA
RENA1
RENA2
RCLKB
RENB1
RENB2
OEB
QB0-8
48X1–1
TQFP
Top View
Pin Configuration
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
QB0
QA1
QA2
QA3
QA4
QA5
QA6
QA7
QA8
Vcc
1
2
3
4
5
6
7
8
FFB
EFB
OEB
CY7C4801
CY7C4811
CY7C4821
CY7C4831
CY7C4841
CY7C4851
RENB2
RCLKB
RENB1
GND
Vcc
9
PAEB
PAFB
DB0
WENA2/LDA
WCLKA
WENA1
RSA
10
11
12
13
14
15
16
DB1
DA8
DA7
DA6
DB2
DB3
DB4
48X1–1
Document #: 38-06005 Rev. **
Page 2 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Selection Guide
7C48X1-10
7C48X1-15
7C48X1-25
7C48X1-35
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
100
8
66.7
10
15
4
40
15
25
6
28.6
20
35
7
10
3
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
0.5
8
1
1
2
10
60
70
15
60
70
20
60
70
Active Power Supply
Current (ICC1) (mA)
Commercial
Industrial
60
70
CY7C4801
Double 256 x 9 Double 512 x 9
64-pin TQFP 64-pin TQFP
CY7C4811
CY7C4821
CY7C4831
Double 2K x 9
64-pin TQFP
CY7C4841
CY7C4851
Double 8K x 9
64-pin TQFP
Density
Double 1K x 9
64-pin TQFP
Double 4K x 9
64-pin TQFP
Package
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature .......................................−65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied....................................................−55°C to +125°C
Ambient
Temperature
Range
VCC
Supply Voltage to Ground Potential .................−0.5V to +7.0V
Commercial
0°C to +70°C
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
in High Z State.....................................................−0.5V to +7.0V
Industrial[1]
−40°C to +85°C
Notes:
DC Input Voltage .................................................−0.5V to +7.0V
1. TA is the “instant on” case temperature.
Output Current into Outputs (LOW) .............................20 mA
Document #: 38-06005 Rev. **
Page 3 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Pin Definitions
Signal Name
Description
I/O
I
Description
DA0 − 8
DB0 − 8
QA0 − 8
QB0 − 8
Data Inputs
Data Inputs for 9-bit bus
Data Inputs for 9-bit bus
Data Outputs for 9-bit bus
Data Outputs for 9-bit bus
Data Inputs
I
Data Outputs
Data Outputs
Write Enable 1
O
O
I
WENA1 and WENB1become the only write enables when the device is configured to
have programmable flags. Data is written on a LOW-to-HIGH transition of WCLK when
(WENA1,WENB1) is LOW and (FFA,FFB) is HIGH. If the FIFO isconfigured to have two write
enables, data is written on a LOW-to-HIGH transition of WCLK when (WENA1,WENB1) is
LOW and (WENA2/LDA,WENB2/LDB) and (FFA,FFB) are HIGH.
WENA1
WENB1
Write Enable 2
Load
I
I
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin
operates as a control to write or read the programmable flag offsets. (WENA1,WENB1)
must be LOW and (WENA2/LDA,WENB2/LDB) must be HIGH to write data into the FIFO.
Data will not be written into the FIFO if the (FFA,FFB) is LOW. If the FIFO is configured to have
programmable flags, (WENA2/LDA,WENB2/LDB) is held LOW to write or read the program-
mable flag offsets.
WENA2/LDA
WENB2/LDB
Dual Mode Pin
RENA1
RENA2
RENB1
RENB2
Read Enable
Inputs
I
I
I
Enables the device for Read operation.
WCLKA
WCKLB
Write Clock
Read Clock
The rising edge clocks data into the FIFO when (WENA1,WENB1) is LOW and
(WENA2/LDA,WENB2/LDB) is HIGH and the FIFO is not Full. When
(WENA2/LDA,WENB2/LDB) is asserted, WCLK writes data into the programmable flag-offset
register.
RCLKA
RCLKB
The rising edge clocks data out of the FIFO when (RENA1,RENB1)and(RENA2,RENB2)
are LOW and the FIFO is not Empty. When (WENA2/LDA,WENB2/LDB) is LOW,
(RCLKA,RCLKB) reads data out of the programmable flag-offset register.
EFA,EFB
FFA,FFB
Empty Flag
Full Flag
O
O
O
When (EFA,EFB) isLOW, theFIFOisempty.(EFA,EFB) issynchronizedto(RCLKA,RCLKB).
When (FFA,FFB) is LOW, the FIFO is full. (FFA,FFB) is synchronized to (WCLKA,WCLKB).
PAEA
PAEB
Programmable
Almost Empty
When (PAEA,PAEB) is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO. PAE is synchronized to RCLK.
PAFA
PAFB
Programmable
Almost Full
O
I
When (PAFA,PAFB) is LOW, the FIFO is almost full based on the almost full offset value pro-
grammed into the FIFO. PAF is synchronized to WCLK.
RSA
RSB
Reset
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OEA
OEB
Output Enable
I
When (OEA,OEB) is LOW, the FIFO’s data outputs drive the bus to which they are connected.
If (OEA,OEB) is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Document #: 38-06005 Rev. **
Page 4 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Electrical Characteristics Over the Operating Range[2]
7C48X1-10 7C48X1-15 7C48X1-25 7C48X1-35
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage VCC = Min.,
2.4
2.4
2.4
2.4
V
IOH = −2.0 mA
VOL
Output LOW Voltage VCC = Min.,
IOL = 8.0 mA
0.4
0.4
0.4
0.4
V
VIH
VIL
IIX
Input HIGH Voltage
Input LOW Voltage
2.0
−0.5
−10
VCC
0.8
2.0
−0.5
−10
VCC
0.8
2.0
−0.5
−10
VCC
0.8
2.0
−0.5
−10
VCC
0.8
V
V
Input Leakage
Current
VCC = Max.
+10
+10
+10
+10
µA
[3]
IOS
Output Short
Circuit Current
VCC = Max.,
VOUT = GND
−90
−10
−90
−10
−90
−10
−90
−10
mA
IOZL
IOZH
Output OFF,
High Z Current
OE > VIH,
VSS < VO < VCC
+10
+10
+10
+10
µA
[4]
ICC1
Active Power Supply
Current
Com’l
60
70
60
70
60
70
60
70
mA
mA
Ind
Capacitance[5]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
CIN
Input Capacitance
Output Capacitance
10
10
pF
pF
COUT
AC Test Loads and Waveforms[6, 7]
R1 1.1KΩ
5V
ALL INPUT PULSES
OUTPUT
3.0V
GND
90%
90%
10%
10%
R2
680Ω
C
L
≤ 3 ns
≤ 3 ns
INCLUDING
JIG AND
SCOPE
48X1–4
48X1–5
Equivalentto:
THÉVENIN EQUIVALENT
420Ω
OUTPUT
1.91V
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. Test no more than one output at a time for not more than one second.
4. Outputs open. Tested at Frequency = 20 MHz.
5. Tested initially and after any design or process changes that may affect these parameters.
6. CL = 30 pF for all AC parameters except for tOHZ
7. CL = 5 pF for tOHZ
.
.
Document #: 38-06005 Rev. **
Page 5 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Switching Characteristics Over the Operating Range
7C48X1-10 7C48X1-15 7C48X1-25 7C48X1-35
Parameter
fS
Description
Clock Cycle Frequency
Min. Max. Min. Max. Min. Max. Min. Max. Unit
100
8
66.7
10
40
15
28.6 MHz
20
tA
Data Access Time
2
2
15
6
2
25
10
10
6
2
35
14
14
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
10
4.5
4.5
3.5
0.5
3.5
0.5
10
8
Clock HIGH Time
Clock LOW Time
6
Data Set-Up Time
4
tDH
Data Hold Time
1
1
2
tENS
tENH
tRS
Enable Set-Up Time
4
6
7
Enable Hold Time
Reset Pulse Width[8]
1
1
2
15
10
10
25
15
15
35
20
20
tRSS
tRSR
tRSF
tOLZ
tOE
Reset Set-Up Time
Reset Recovery Time
8
Reset to Flag and Output Time
Output Enable to Output in Low Z[9]
Output Enable to Output Valid
Output Enable to Output in High Z[9]
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Programmable Almost-Full Flag
Clock to Programmable Almost-Full Flag
10
15
25
35
0
3
3
0
3
3
0
3
3
0
3
3
7
7
8
8
8
8
8
12
12
15
15
15
15
15
15
20
20
20
20
tOHZ
tWFF
tREF
tPAF
8
10
10
10
10
tPAE
tSKEW1
Skew Time between Read Clock and Write
Clock for Empty Flag and Full Flag
5
6
10
18
12
20
tSKEW2
Skew Time between Read Clock and Write
Clock for Almost-Empty Flag and Almost-Full
Flag
15
15
ns
Notes:
8. Pulse widths less than minimum values are not allowed.
9. Values guaranteed by design, not currently tested.
Document #: 38-06005 Rev. **
Page 6 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Switching Waveforms
Write Cycle Timing
t
CLK
t
t
CLKL
CLKH
WCLKA (WCLKB)
t
t
DH
DS
DA −DA
0
8
(DB −DB )
0
8
t
ENH
t
ENS
WENA1
(WENB1)
NO OPERATION
NO OPERATION
WENA2(WENB2)
(if applicable)
t
t
WFF
WFF
FFA (FFB)
[10]
t
SKEW1
RCLKA (RCLKB)
RENA1,RENB2
(RENB1, RENB2)
48X1–6
Read Cycle Timing
t
CLK
t
t
CLKL
CLKH
RCLKA (RCLKB)
t
t
ENH
ENS
RENA1,RENA2
(RENB1,RENB2)
NO OPERATION
t
REF
t
REF
EFA(EFB)
t
A
QA −QA
VALID DATA
0
8
(QB −QB )
0
8
t
OLZ
t
OHZ
t
OE
OEA(OEB)
[11]
SKEW1
t
WCLKA,WCLKB
WENA1(WENB1)
WENA2(WENB2
48X1–7
Notes:
10. tSKEW1 is the minimum time between a rising (RCLKA,RCLKB) edge and a rising (WCLKA,WCLKB) edge to guarantee that (FFA,FFB) will go HIGH during the current clock
cycle. If the time between the rising edge of (RCLKA,RCLKB) and the rising edge of (WCLKA,WCLKB) is less than tSKEW1, then (FFA,FFB) may not change state until the
next (WCLKA,WCLKB) rising edge.
11. tSKEW1 is the minimum time between a rising (WCLKA,WCLKB) edge and a rising (RCLKA,RCLKB) edge to guarantee that (EFA,EFB) will go HIGH during the current clock
cycle. It the time between the rising edge of (WCLKA,WCLKB) and the rising edge of RCLK is less than tSKEW1, then (EFA,EFB) may not change state until the next
(RCLKA,RCLKB) rising edge.
Document #: 38-06005 Rev. **
Page 7 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Switching Waveforms (continued)
[12]
Reset Timing
t
RS
RSA(RSB)
t
t
t
t
RSR
RSS
RENA1, RENA2
(RENB1,RENB2)
RSR
RSS
WENA1
(WENB1)
t
t
RSR
RSS
WENA2/LDA
[14]
(WENB2/LDB)
t
t
t
RSF
RSF
RSF
EFA, PAEA
(EFB, PAEB)
FFA, PAFA
(FFB, PAFB)
[13]
OEA(OEB)=1
QA −QA
0
8
(QB −QB )
0
8
48X1–8
OEA(OEB)=0
Notes:
12. The clocks (RCLKA,RCLKB, WCLKA,WCLKB) can be free-running during reset.
13. After reset, the outputs will be LOW if (OEA,OEB) = 0 and three-state if (OEA,OEB)=1.
14. Holding (WENA2/LDA,WENB2/LDB) HIGH during reset will make the pin act as a second enable pin. Holding(WENA2/LDA,WENB2/LDB) LOW during reset will make the
pin act as a load enable for the programmable flag offset registers.
Document #: 38-06005 Rev. **
Page 8 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Switching Waveforms (continued)
First Data Word Latency after Reset with Simultaneous Read and Write
WCLKA,WCLKB
t
DS
DA −DA
D
0
(FIRSTVALIDWRITE)
D
1
D
2
D
3
D
4
0
8
(DB −DB )
0
8
t
ENS
15
[
]
t
FRL
WENA1(WENB1)
WENA2(WENB2)
(if applicable)
t
SKEW1
RCLKA(RCLKB)
EFA(EFB)
t
REF
16
[
]
t
t
A
A
RENA1, RENA2
(RENB1,RENB2)
QA −QA
D
0
D
1
0
8
(QB −QB )
0
8
t
OLZ
t
OE
OEA(OEB)
48X1–9
Notes:
15. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1
.
The Latency Timing applies only at the Empty Boundary (EFA, EFB= LOW).
16. The first word is available the cycle after (EFA, EFB) goes HIGH, always.
Document #: 38-06005 Rev. **
Page 9 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Switching Waveforms (continued)
Empty Flag Timing
WCLKA,WCLKB
t
t
DS
DS
DATA WRITE2
DATA WRITE1
DA −DA
0
8
(DB −DB )
0
8
t
t
ENH
ENH
ENH
t
t
t
ENS
t
t
ENS
WENA1(WENB1)
t
t
ENS
ENH
ENS
WENA2(WENB2)
(if applicable)
[15]
[15]
FRL
t
FRL
RCLKA(RCLKB)
t
t
t
REF
t
t
SKEW1
REF
REF
SKEW1
EFA(EFB)
RENA1, RENA2
(RENB1,RENB2)
LOW
OEA(OEB)
t
A
DATA IN OUTPUT REGISTER
DATA READ
QA −QA
0
8
(QB −QB )
0
8
48X1–10
Document #: 38-06005 Rev. **
Page 10 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Switching Waveforms (continued)
Full Flag Timing
NO WRITE
NO WRITE
NO WRITE
WCLKA,WCLKB
[10]
[10]
SKEW1
t
t
DATA WRITE
t
SKEW1
DS
DATA WRITE
DA −DA
0
8
(DB −DB )
0
8
t
t
t
WFF
WFF
WFF
FFA(FFB)
WENA1(WENB1)
WENA2(WENB2)
(if applicable)
RCLKA(RCLKB)
t
t
ENH
ENH
t
t
ENS
ENS
RENA1, RENA2
(RENB1,RENB2)
LOW
OEA(OEB)
t
A
t
A
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
QA −QA
0
8
(QB −QB )
0
8
48X1–11
Document #: 38-06005 Rev. **
Page 11 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Switching Waveforms (continued)
ProgrammableAlmost Empty Flag Timing
t
t
CLKL
CLKH
WCLKA,WCLKB
t
t
ENS
ENH
WENA1(WENB1)
WENA2(WENB2)
(if applicable)
t
t
ENS
[17]
ENH
Note
18
PAEA(PAEB)
N +1 WORDS
IN FIFO
Note
19
t
PAE
t
t
PAE
SKEW2
RCLKA(RCLKB)
t
t
ENH
ENS
RENA1, RENA2
(RENB1,RENB2)
48X1–12
Programmable Almost Full FlagTiming
Note
20
t
t
CLKL
CLKH
WCLKA,WCLKB
t
t
t
ENS
ENH
WENA1(WENB1)
Note
21
WENA2(WENB2)
(if applicable)
t
t
PAF
ENS
ENH
FULL− M WORDS
[22]
PAFA(PAFB)
IN FIFO
FULL− M+1 WORDS
IN FIFO
[23]
SKEW2
t
t
PAF
RCLKA(RCLKB)
t
ENS
t
t
ENH
ENS
RENA1, RENA2
(RENB1,RENB2)
48X1–13
Notes:
17. tSKEW2 is the minimum time between a rising (WCLKA,WCLKB) and a rising (RCLKA,RCLKB) edge for (PAEA,PAEB) to change state during that clock cycle. If the time
between the edge of (WCLKA,WCLKB) and the rising (RCLKA,RCLKB) is less than tSKEW2, then (PAEA,PAEB) may not change state until the next RCLK.
18. (PAEA,PAEB) offset = n.
19. If a read is preformed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when (PAEA,PAEB) goes LOW.
20. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words of the FIFO when (PAFA,PAFB) goes LOW.
21. (PAFA,PAFB) offset = m.
22. 256-m words in FIFO for CY7C4801, 512-m words for CY7C4811, 1024-m words for CY7C4821, 2048-m words for CY7C4831, 4096-m words for CY7C4841,
8192-m words for CY7C4851.
23. tSKEW2 is the minimum time between a rising (RCLKA,RCLKB) edge and a rising (WCLKA,WCLKB) edge for (PAFA,PAFB) to change during that clock cycle. If the time
between the rising edge of (RCLKA,RCLKB) and the rising edge of (WCLKA,WCLKB) is less than tSKEW2, then (PAFA,PAFB) may not change state until the next
(WCLKA,WCLKB).
Document #: 38-06005 Rev. **
Page 12 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Switching Waveforms (continued)
Write Programmable Registers
t
CLK
t
t
CLKL
CLKH
WCLKA,WCLKB
t
t
ENS
ENH
WENA2/LD
(WENB2/LDB)
t
ENS
WENA1(WENB1)
t
t
DH
DS
DA −DA
0
8
(DB −DB )
0
8
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
48X1–14
Read Programmable Registers
t
CLK
t
t
CLKL
CLKH
RCLKA(RCLKB)
t
t
ENS
ENH
WENA2/LDA
(WENB2/LDB)
t
ENS
PAF OFFSET
MSB
RENA1, RENA2
(RENB1,RENB2)
t
A
PAF OFFSET
LSB
UNKNOWN
PAE OFFSET LSB
PAE OFFSET MSB
QA −QA
0
8
(QB −QB )
0
8
48X1–15
Document #: 38-06005 Rev. **
Page 13 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
transition of every write clock (WCLKA,WCLKB). Data is
stored is the RAM array sequentially and independently of any
on-going read operation.
Architecture
The CY7C48X1 functions as two independent FIFOs in a single
package, each with its own separate set of controls. The device con-
sists of two arrays of 256 to 8K words of 9 bits each (imple-
mented by a dual-port array of SRAM cells), two read pointers,
two write pointers, control signals (RCLKA, RCLKB, WCLKA,
WCLKB, RENA1, RENB1, RENA2, RENB2, WENA1, WENB1,
WENA2, WENB2, RSA, RSB), and flags (EFA,EFB, PAEA,PAEB,
PAFA,PAFB, FFA,FFB).
Write Enable 2/Load (WENA2/LDA, WENB2/LDB) - This is a
dual-purpose pin. The FIFO is configured at Reset to have
programmable flags or to have two write enables, which allows
for depth expansion. If Write Enable 2/Load (WENA2/LDA,
WENB2/LDB) is set active HIGH at Reset (RSA,RSB=LOW),
this pin operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable 1 (WENA1,WENB1) is LOW and Write Enable 2/Load
(WENA2/LDA, WENB2/LDB) is HIGH, data can be loaded into the
input register and RAM array on the LOW-to-HIGH transition of every
write clock (WCLKA,WCLKB). Data is stored in the RAM array se-
quentially and independently of any on-going read operation.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RSA,
RSB) cycle. This causes the FIFO to enter the Empty condition signi-
fied by (EFA,EFB) being LOW. All data outputs (QA0−8,QB0−8) go
LOW tRSF after the rising edge of RSA, RSB. In order for the FIFO to
reset to its default state, a falling edge must occur on (RSA,RSB) and
the user must not read or write while (RSA,RSB) is LOW. All flags are
guaranteed to be valid tRSF after (RSA,RSB) is taken LOW.
Programming
When (WENA2/LDA, WENB2/LDB) is held LOW during Reset, this
pin is the load (LDA,LDB) enable for flag offset programming. In this
configuration, (WENA2/LDA, WENB2/LDB) can be used to access
the four 8-bit offset registers contained in the CY7C48X1 for writing
or reading data to these registers.
FIFO Operation
When the (WENA1,WENB1) signal is active LOW and
(WENA2,WENB2) is active HIGH, data present on the
(DA0−8,DB0−8) pins is written into the FIFO on each rising edge
(WCLKA,WCLKB) of the (WCLKA,WCLKB) signal. Similarly, when
the (RENA1,RENB1) and (RENA2,RENB2) signals are active LOW,
When the device is configured for programmable flags and
both (WENA2/LDA, WENB2/LDB) and (WENA1,WENB1) are
LOW, the first LOW-to-HIGH transition of (WCLKA,WCLKB) writes
data from the data inputs to the empty offset least significant bit (LSB)
register. The second, third, and fourth LOW-to-HIGH transitions of
(WCLKA,WCLKB) store data in the empty offset most significant bit
(MSB) register, full offset LSB register, and full offset MSB register,
data in the FIFO memory will be presented on the (QA0−8,QB0−8
)
outputs. New data will be presented on each rising edge of
(RCLKA,RCLKB) while (RENA1,RENB1) and (RENA2,RENB2) are
active. (RENA1,RENB1) and (RENA2,RENB2) must set up tENS be-
fore (RCLKA,RCLKB) for it to be a valid read function.
(WENA1,WENB1) and (WENA2,WENB2) must occur tENS before
(WCLKA,WCLKB) for it to be a valid write function.
respectively,
when
(WENA2/LDA,
WENB2/LDB)
and
(WENA1,WENB1) are LOW. The fifth LOW-to-HIGH transition of
(WCLKA,WCLKB) while (WENA2/LDA, WENB2/LDB) and
(WENA1,WENB1) are LOW writes data to the empty LSB register
again. Figure 1 shows the register sizes and default values for the
various device types.
An output enable (OEA,OEB) pin is provided to three-state the
(QA0−8,QB0−8) outputs when (OEA,OEB) is asserted. When
(OEA,OEB) isenabled (LOW), data in the output register willbeavail-
able to the (QA0−8,QB0−8) outputs after tOE.
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the (WENA2/LDA, WENB2/LDB) input HIGH, the FIFO is returned
to normal read and write operation. The next time (WENA2/LDA,
WENB2/LDB) is brought LOW, a write operation stores data in the
next offset register in sequence.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its (QA0−8,QB0−8
)
outputs even after additional reads occur.
The contents of the offset registers can be read to the data
outputs when (WENA2/LDA, WENB2/LDB) is LOW and both
(RENA1,RENB1) and (RENA2,RENB2) are LOW. LOW-to-HIGH
transitions of (RCLKA,RCLKB) read register contents to the data out-
puts. Writes and reads should not be preformed simultaneously on
the offset registers.
Write Enable 1 (WENA1,WENB1) - If the FIFO is configured
for programmable flags, Write Enable 1 (WENA1,WENB1) is
the only write enable control pin. In this configuration, when
Write Enable 1 (WENA1,WENB1) is LOW, data can be loaded
into the input register and RAM array on the LOW-to-HIGH
Document #: 38-06005 Rev. **
Page 14 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
256 x 9 x 2
7
512 x 9 x 2
7
1K x 9 x 2
0
0
0
0
8
8
8
8
0
0
0
0
0
0
0
0
8
8
8
8
8
8
8
8
7
Empty Offset (LSB) Reg.
Default Value= 007h
Empty Offset (LSB) Reg.
Default Value = 007h
Empty Offset (LSB) Reg.
Default Value = 007h
1
1
(MSB)
0
(MSB)
00
7
7
7
Full Offset (LSB) Reg
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
1
1
(MSB)
0
(MSB)
00
2K x 9 x 2
7
4K x 9 x 2
7
8K x 9 x 2
7
0
0
0
0
0
0
0
0
0
8
8
8
8
8
8
8
8
8
Empty Offset (LSB) Reg.
Default Value = 007h
Empty Offset (LSB) Reg.
Default Value= 007h
Empty Offset (LSB) Reg.
Default Value = 007h
0
0
0
2
8
8
8
3
4
(MSB)
0000
(MSB)
00000
(MSB)
000
7
7
7
Full Offset (LSB) Reg
Default Value = 007h
Full Offset (LSB) Reg
Default Value= 007h
Full Offset (LSB) Reg
Default Value = 007h
2
3
4
(MSB)
000
(MSB)
0000
(MSB)
00000
Figure 1. Offset Register Location and Default Values.
Programmable Flag (PAEA,PAEB, PAFA,PAFB) Operation
The number formed by the empty offset least significant bit
register and empty offset most significant register is referred
to as n and determines the operation of (PAEA,PAEB).
(PAEA,PAEB) is synchronized to the LOW-to-HIGH transition of
RCLK by one flip-flop and is LOW when the FIFO contains n or fewer
unread words. (PAEA,PAEB) is set HIGH by the LOW-to-HIGH tran-
sition of RCLK when the FIFO contains (n+1) or greater unread
words.
Whether the flag offset registers are programmed as de-
scribed in Table 1or the default values are used, the programmable
almost-empty flag (PAEA,PAEB) and programmable almost-full flag
(PAFA,PAFB) states are determined by their corresponding offset
registers and the difference between the read and write pointers.
Table 1. Writing the Offset Registers.
LD WEN WCLK[24]
Selection
The number formed by the full offset least significant bit regis-
ter and full offset most significant bit register is referred to as
m and determines the operation of (PAFA,PAFB). (PAEA,PAEB) is
synchronized to the LOW-to-HIGH transitionof (WCLKA,WCLKB) by
one flip-flop and is set LOW when the number of unread words in the
FIFO is greater than or equal to CY7C4801 (256–m), CY7C4811
(512–m), CY7C4821 (1K–m), CY7C4831 (2K–m), CY7C4841
(4K–m), and CY7C4851 (8K–m). (PAFA,PAFB) is set HIGH by the
LOW-to-HIGH transition of (WCLKA,WCLKB) when the number of
available memory locations is greater than m.
0
0
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
1
0
1
No Operation
Write Into FIFO
No Operation
1
Notes:
24. The same selection sequence applies to reading form the registers. REN1 and REN2 are enabled and a read is performed on the LOW- to-HIGH transition of
RCLK.
Document #: 38-06005 Rev. **
Page 15 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Flag Operation
(FFA,FFB) is synchronized to (WCLKA,WCLKB), i.e., it is exclusively
updated by each rising edge of (WCLKA,WCLKB).
The CY7C48X1 devices provide four flag pins to indicate the
condition of the FIFO contents. Empty, Full, (PAEA,PAEB), and
(PAFA,PAFB) are synchronous.
Empty Flag
The Empty Flag (EFA,EFB) will go LOW when the device is empty.
Read operations are inhibited whenever (EFA,EFB) is LOW, regard-
less of the state of (RENA1,RENB1) and (RENA2,RENB2.
(EFA,EFB) is synchronized to (RCLKA,RCLKB), i.e., it is exclusively
Full Flag.
Full Flag
The Full Flag (FFA,FFB) will go LOW when the device is full. Write
operations are inhibited whenever (FFA,FFB) is LOW regardless of
the state of (WENA1,WENB1) and (WENA2/LDA,WENB2/LDB).
Table 2. Status Flags.
Number of Words in FIFO
CY7C4801
CY7C4811
CY7C4821
FF
H
H
H
H
L
PAF
H
PAE
L
EF
L
0
0
0
1 to n[25]
1 to n[25]
1 to n[25]
H
L
H
H
H
H
(n+1) to (256-(m+1))
(256−m)[26] to 255
256
(n+1) to (512-(m+1))
(512−m)[26] to 511
512
(n+1) to (1024 −(m+1))
(1024−m)[26] to 1023
1024
H
H
L
H
L
H
Number of Words in FIFO
CY7C4841
CY7C4831
CY7C4851
FF PAF PAE EF
0
0
0
H
H
H
H
L
H
H
H
L
L
L
L
1 to n[25]
1 to n[25]
1 to n[25]
H
H
H
H
(n+1) to (2048 −(m+1)) (n+1) to (4096 −(m+1)) (n+1) to (8192 −(m+1))
H
H
H
(2048−m)[26] to 2047
(4096−m)[26] to 4095
(8192−m)[26] to 8191
2048
4096
8192
L
Notes:
25. n =Empty Offset (n=7 default value).
26. m = Full Offset (m=7 default value).
Document #: 38-06005 Rev. **
Page 16 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
(WENA2/LDA,WENB2/LDB) pin is set LOW at Reset so that
the pin operates as a control to load and read the programma-
ble flag offsets.
Single Device Configuration
When FIFO A(B) is in a Single Device Configuration, the Read
Enable 2 RENA2(RENB2) control input can be grounded (see
Figure 2). in this configuration, the Write Enable2/Load
RESET(RSA,RSB)
DATAIN DA0−DA8(DB0−DB8)
DATAOUT QA0−QA8(QB0−QB8)
READ CLOCK(RCLKA,RCLKB)
WRITE CLOCK (WCLKA,WCLKB)
WRITE ENABLE1 (WENA1,WENB1)
CY7C4801
READ ENABLE1 (RENA1,RENB1)
CY7C4811
CY7C4821
CY7C4831
CY7C4841
CY7C4851
WRITEENABLE2/LOAD(WENA2/LDA,WENB/LDB)
OUTPUT ENABLE(OEA,OEB)
PROGRAMMABLE(PAEA,PAEA)
(PAFA,PAFB)
PROGRAMMABLE
EMPTY FLAG(EFA,EFB)
FULL FLAG (FFA,FFB)
Read Enable 2 (RENA2,RENB2)
48X1–16
Figure 2. Block Diagram of 256 x 9,512 x 9,1024 x 9,2048 x 9,4096 x 9,8192 x 9 Double Sync FIFO
Used in a Single Device Configuration.
Document #: 38-06005 Rev. **
Page 17 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
When the CY7C4801/4811/4821/4831/4841/4851 is in a
Width Expansion Configuration, the Read Enable 2 (RENA2
and RENB2) control unputs can be grounded (see Figure 3).
In this configuration, the Write Enable 2/Load
(WENA2/LDA,WENB2/LDB) pins are set LOW at Reset so that
the pin operates as a control to load and read the programma-
ble flag offsets.
Width Expansion Configuration
Word width may be increased simply by connecting the corre-
sponding input control signals of FIFOs A and B. A composite
flag should be created for each of the end-point status flags
EFA and EFB, also FFA and FFB. The partial status flags
PAEA, PAFB, PAFA, PAFB can be detected from any one de-
vice. Figure 3 demonstrates an 18-bit word width using the two
FIFOs contained in one CY7C4801/4811/4821/4831/4841
/4851. Any word width can be attained by adding additional
CY7C4801/4811/4821/4831/4841/4851s.
9
RESET
RESET(RSA)
(RSB)
RESET
D −D
0
17
9
18
9
READCLOCK
READENABLE
RAM ARRAY B
RCLKB
RENB1
OEB
RCLKA
RAM ARRAY A
WRITECLOCK
WCLKA
WENA
WCLKB
RENA1
WENB1
OEA
256 x 9
512 x 9
1024 x 9
2048 x 9
4096 x 9
8192 x 9
256 x 9
512 x 9
1024 x 9
2048 x 9
4096 x 9
8192 x 9
WRITE ENABLE
OUTPUT ENABLE
WRITE ENABLE2/LOAD
WEN2/LD
WENB2/LDB
EFA
EFB
EMPTY FLAG
FFA
FFB
EF
FULLFLAG
FF
Q −Q
9
0
17
18
9
Read Enable 2 (RENA2)
Read Enable 2 (RENB2)
48X1–17
Figure 3. Block Diagram of two FIFOs contained in one CY7C4801/4811/4821/4831/4841/4851 configured for an 18-bit
width-expansion.
Document #: 38-06005 Rev. **
Page 18 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
FIFO A, and, in turn, processor B can write processor A via
FIFO B.
Bidirectional Configuration
The two FIFOs of the CY7C4801/4811/4821/4831/4841/4851
can be used to buffer data flow in two directions. In the exam-
ple that follows, processor A can write data to processor B via
RAM ARRAY A
VCC
RENA2
WENA2
WCLKA
WENA1
DA0−DA8
RCLKA
OEA
9
RENA1
QA0−QA8
PROCESSOR A
PROCESSOR A
CLOCK
9
CLOCK
CY7C4801
ADDRESS
CONTROL
CY7C4811
CY7C4821
CY7C4831
CY7C4841
CY7C4851
ADDRESS
CONTROL
DATA
RAM
9
9
DATA
RAM
9
9
RAM ARRAY B
WENB1
RCLKB
RENB1
OEB
WCLKB
DB0−DB8
QB0−QB8
9
9
WENB2
RENB2
VCC
48X1–18
Figure 4. Block Diagram of Bidirectional Configuration.
data. a typical application would have the expansion logic al-
ternate data access from one device to the next in a sequential
manner. The CY7C4801/4811/4821/4831/4841/ 4851 oper-
ates in the Depth Expansion configuration when the following
conditions are met:
Depth Expansion
CY7C4801/4811/4821/4831/4841/4851can be adapted to ap-
plications that require greater than 256/512/1024/2048/4096/
8192 words. The existence of dual enable pins on the read and
write ports allow depth expansion. The Write Enable 2/Load
(WENA2, WENB2) pins are used as a second write enables in
a depth expansion configuration, thus the Programmable flags
are set to the default values. Depth expansion is possible by
using one enable input for system control while the other en-
able input is controlled by expansion logic to direct the flow of
1. WENA2/LDA and WENB2/LDB pins are held HIGH during
Reset so that these pins operate as second Write Enables.
2. External logic is used to control the flow of data.
Document #: 38-06005 Rev. **
Page 19 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Ordering Information
Double 256x9 FIFO
Speed
Package
Name
Package
Type
Operating
(ns)
Ordering Code
CY7C4801-10AC
CY7C4801-10AI
CY7C4801-15AC
CY7C4801-15AI
CY7C4801-25AC
CY7C4801-25AI
CY7C4801-35AC
CY7C4801-35AI
Range
10
A65
A65
A65
A65
A65
A65
A65
A65
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
Commercial
Industrial
15
25
35
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Double 512x9 FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
10
CY7C4811-10AC
CY7C4811-10AI
CY7C4811-15AC
CY7C4811-15AI
CY7C4811-25AC
CY7C4811-25AI
CY7C4811-35AC
CY7C4811-35AI
A65
A65
A65
A65
A65
A65
A65
A65
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
Commercial
Industrial
15
25
35
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Double 1Kx9 FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
10
CY7C4821-10AC
CY7C4821-10AI
CY7C4821-15AC
CY7C4821-15AI
CY7C4821-25AC
CY7C4821-25AI
CY7C4821-35AC
CY7C4821-35AI
A65
A65
A65
A65
A65
A65
A65
A65
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
Commercial
Industrial
15
25
35
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Document #: 38-06005 Rev. **
Page 20 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Ordering Information (continued)
Double 2Kx9 FIFO
Speed
(ns)
Package
Package
Type
Operating
Ordering Code
CY7C4831-10AC
CY7C4831-10AI
CY7C4831-15AC
CY7C4831-15AI
CY7C4831-25AC
CY7C4831-25AI
CY7C4831-35AC
CY7C4831-35AI
Name
A65
A65
A65
A65
A65
A65
A65
A65
Range
10
15
25
35
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Double 4Kx9 FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
10
CY7C4841-10AC
CY7C4841-10AI
CY7C4841-15AC
CY7C4841-15AI
CY7C4841-25AC
CY7C4841-25AI
CY7C4841-35AC
CY7C4841-35AI
A65
A65
A65
A65
A65
A65
A65
A65
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
Commercial
Industrial
15
25
35
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Double 8Kx9 FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
10
CY7C4851-10AC
CY7C4851-10AI
CY7C4851-15AC
CY7C4851-15AI
CY7C4851-25AC
CY7C4851-25AI
CY7C4851-35AC
CY7C4851-35AI
A65
A65
A65
A65
A65
A65
A65
A65
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
Commercial
Industrial
15
25
35
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Document #: 38-06005 Rev. **
Page 21 of 23
CY7C4801/4811/4821
CY7C4831/4841/4851
Package Diagram
64-Lead Thin Plastic Quad Flat Pack A65
Document #: 38-06005 Rev. **
Page 22 of 23
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C4801/4811/4821
CY7C4831/4841/4851
Document Title: CY7C4801/4811/4821/CY7C4831.4841/4851 256/512/1K/2K/4K/8K x9 x2 Double Sync (TM) Fifos
Document Number: 38-06005
Issue
ECN NO. Date
Orig. of
Change
REV.
Description of Change
**
106466
07/11/01
SZV
Change from Spec Number: 38-00538 to 38-06005
Document #: 38-06005 Rev. **
Page 23 of 23
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