CY7C63310-SXC_12 [CYPRESS]
enCoRe⢠II Low Speed USB Peripheral Controller; enCoReâ ?? ¢ II低速USB外设控制器
| 型号： | CY7C63310-SXC_12 |
| 厂家： | 
CYPRESS |
| 描述： | enCoRe⢠II Low Speed USB Peripheral Controller |
| 文件： | 总91页 (文件大小：1018K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C63310, CY7C638xx
enCoRe™ II
Low Speed USB Peripheral Controller
enCoRe™ II Low Speed USB Peripheral Controller
■ GPIO ports
Features
❐ Up to 20 GPIO pins
■ USB 2.0-USB-IF certified (TID # 40000085)
❐ 2 mA source current on all GPIO pins. Configurable 8 or
50 mA/pin current sink on designated pins.
■ enCoRe™ II USB - ‘enhanced Component Reduction’
❐ Crystalless oscillator with support for an external clock. The
internal oscillator eliminates the need for an external crystal
or resonator.
❐ Each GPIO port supports high impedance inputs,
configurable pull-up, open drain output, CMOS/TTL inputs,
and CMOS output
❐ Two internal 3.3 V regulators and an internal USB Pull-up
❐ Maskable interrupts on all I/O pins
resistor
■ A dedicated 3.3 V regulator for the USB PHY. Aids in signalling
and D– line pull-up
❐ Configurable I/O for real world interface without external
components
■ 125 mA 3.3 V voltage regulator powers external 3.3 V devices
■ 3.3 V I/O pins
■ USB Specification compliance
❐ Conforms to USB Specification, Version 2.0
❐ Conforms to USB HID Specification, Version 1.1
❐ Supports one low speed USB device address
❐ Supports one control endpoint and two data endpoints
❐ 4 I/O pins with 3.3 V logic levels
❐ Each 3.3 V pin supports high impedance input, internal
pull-up, open drain output or traditional CMOS output
■ SPI serial communication
❐ Integrated USB transceiver with dedicated 3.3 V regulator for
USB signalling and D– pull-up.
❐ Master or slave operation
❐ Configurable up to 4 Mbps transfers in the master mode
❐ Supports half duplex single data line mode for optical sensors
■ Enhanced 8-bit microcontroller
❐ Harvard architecture
■ 2-channel 8-bit or 1-channel 16-bit capture timer registers.
Capture timer registers store both rising and falling edge times.
❐ M8C CPU speed is up to 24 MHz or sourced by an external
clock signal
❐ Two registers each for two input pins
■ Internal memory
❐ Separate registers for rising and falling edge capture
❐ Simplifies the interface to RF inputs for wireless applications
■ Internal low power wakeup timer during suspend mode:
❐ Periodic wakeup with no external components
■ 12-bit Programmable Interval Timer with interrupts
■ Advanced development tools based on Cypress PSoC® tools
■ Watchdog timer (WDT)
❐ Up to 256 bytes of RAM
❐ Up to eight Kbytes of flash including EEROM emulation
■ Interface can auto configure to operate as PS/2 or USB
❐ No external components for switching between PS/2 and
USB modes
❐ No General Purpose I/O (GPIO) pins required to manage
dual mode capability
■ Low power consumption
❐ Typically 10 mA at 6 MHz
❐ 10 A sleep
■ Low-voltage detection with user configurable threshold
voltages
■ Operating voltage from 4.0 V to 5.5 V DC
■ Operating temperature from 0 °C–70 °C
■ In system reprogrammability
❐ Allows easy firmware update
■ Available in 18-pin PDIP; 16, 18, and 24-pin SOIC; 24-pin
QSOP, and 24-pin and 32-pin QFN Sawn packages
■ Industry standard programmer support
Cypress Semiconductor Corporation
Document Number: 38-08035 Rev. *Q
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 19, 2012
CY7C63310, CY7C638xx
❐ Game pad
Applications
■ General purpose
❐ Barcode scanners
❐ POS terminal
The CY7C63310/CY7C638xx is targeted for the following
applications:
■ PC HID devices
❐ Consumer electronics
❐ Toys
❐ Mice (optomechanical, optical, trackball)
■ Gaming
❐ Remote controls
❐ Security dongles
❐ Joysticks
Logic Block Diagram
Low-Speed
USB/PS2
Transceiver
and Pull up
Up to 6
GPIO
pins
Up to 14
4 3.3 V I/O /
Extended
Wakeup
Timer
Low-Speed
USB SIE
Interrupt
Control
3.3V
Regulator
SPI Pins
IO Pins
Internal
24 MHz
Oscillator
16-bit Free
running
timer
RAM
Up to 256
Byte
Flash
Up to 8K
Byte
M8C CPU
Clock
Control
12-bit Timer
External Clock
Watchdog
Timer
POR /
Low-Voltage
Detect
Document Number: 38-08035 Rev. *Q
Page 2 of 91
CY7C63310, CY7C638xx
Contents
Introduction .......................................................................4
Conventions ......................................................................4
Pinouts ..............................................................................5
QFN Pinouts ................................................................6
Pin Descriptions ...............................................................7
CPU Architecture ..............................................................8
CPU Registers ...................................................................9
Flags Register .............................................................9
Addressing Modes .....................................................10
Instruction Set Summary ...............................................13
Memory Organization .....................................................14
Flash Program Memory Organization .......................14
Data Memory Organization .......................................15
Flash ..........................................................................15
SROM ........................................................................15
SROM Function Descriptions ....................................16
Clocking ..........................................................................20
Clock Architecture Description ..................................22
CPU Clock During Sleep Mode ......................................28
Reset ................................................................................29
Power on Reset .........................................................30
Watchdog Timer Reset ..............................................30
Sleep Mode ......................................................................30
Sleep Sequence ........................................................31
Wake up Sequence ...................................................31
Low Power in Sleep Mode .........................................32
Low Voltage Detect Control ..........................................33
General Purpose I/O (GPIO) Ports ................................35
Port Data Registers ...................................................35
GPIO Port Configuration ...........................................37
Serial Peripheral Interface (SPI) ....................................42
SPI Data Register ......................................................42
SPI Configure Register .............................................43
SPI Interface Pins ......................................................44
Timer Registers ..............................................................45
Registers ...................................................................45
Interrupt Controller .........................................................53
Architectural Description ...........................................53
Interrupt Processing ..................................................54
Interrupt Trigger Conditions .......................................54
Interrupt Latency .......................................................54
Interrupt Registers .....................................................55
Regulator Output ............................................................60
VREG Control ............................................................60
USB/PS2 Transceiver .....................................................61
USB Transceiver Configuration .................................61
USB Serial Interface Engine (SIE) .................................61
USB Device .....................................................................62
USB Device Address .................................................62
Endpoint 0, 1, and 2 Count ........................................62
Endpoint 0 Mode .......................................................63
Endpoint 1 and 2 Mode .............................................64
USB Mode Tables ...........................................................66
Mode Column ............................................................66
Encoding Column ......................................................66
SETUP, IN, and OUT Columns .................................66
Details of Mode for Differing Traffic Conditions ..........67
Register Summary ..........................................................69
Voltage versus CPU Frequency Characteristics .........72
Absolute Maximum Ratings ..........................................73
DC Characteristics .........................................................73
AC Characteristics .........................................................75
Ordering Information ......................................................81
Ordering Code Definitions .........................................81
Package Handling ...........................................................81
Package Diagrams ..........................................................82
Acronyms ........................................................................86
Document Conventions .................................................86
Units of Measure .......................................................86
Document History Page .................................................87
Sales, Solutions, and Legal Information ......................91
Worldwide Sales and Design Support .......................91
Products ....................................................................91
PSoC Solutions .........................................................91
Document Number: 38-08035 Rev. *Q
Page 3 of 91
CY7C63310, CY7C638xx
POR and LVD share the same interrupt. There is no separate
interrupt for each. The Watchdog timer may be used to ensure
the firmware never gets stalled in an infinite loop.
Introduction
Cypress has reinvented its leadership position in the low speed
USB market with a new family of innovative microcontrollers.
Introducing enCoRe II USB - ‘enhanced Component Reduction.’
Cypress has leveraged its design expertise in USB solutions to
advance its family of low speed USB microcontrollers, which
enable peripheral developers to design new products with a
minimum number of components. The enCoRe II USB
technology builds on the enCoRe family. The enCoRe family has
an integrated oscillator that eliminates the external crystal or
resonator, reducing overall cost. Also integrated into this chip are
other external components commonly found in low speed USB
applications, such as pull-up resistors, wakeup circuitry, and a
3.3 V regulator. Integrating these components reduces the
overall system cost.
The microcontroller supports 22 maskable interrupts in the
vectored interrupt controller. Interrupt sources include a USB bus
reset, LVR/POR, a programmable interval timer, a 1.024 ms
output from the free-running timer, three USB endpoints, two
capture timers, four GPIO Ports, three Port 0 pins, two SPI, a
16-bit free running timer wrap, an internal sleep timer, and a bus
active interrupt. The sleep timer causes periodic interrupts when
enabled. The USB endpoints interrupt after a USB transaction
complete is on the bus. The capture timers interrupt when a new
timer value is saved because of a selected GPIO edge event. A
total of seven GPIO interrupts support both TTL or CMOS
thresholds. For additional flexibility on the edge sensitive GPIO
pins, the interrupt polarity is programmed as rising or falling.
The enCoRe II is an 8-bit flash programmable microcontroller
with an integrated low speed USB interface. The instruction set
is optimized specifically for USB and PS/2 operations, although
the microcontrollers may be used for a variety of other embedded
applications.
The free-running 16-bit timer provides two interrupt sources: the
1.024 ms outputs and the free running counter wrap interrupt.
The programmable interval timer provides up to 1 sec
resolution and provides an interrupt every time it expires. These
timers are used to measure the duration of an event under
firmware control by reading the desired timer at the start and at
the end of an event, then calculating the difference between the
two values. The two 8-bit capture timer registers save a
programmable 8-bit range of the free-running timer when a GPIO
edge occurs on the two capture pins (P0.5, P0.6). The two 8-bit
captures may be ganged into a single 16-bit capture.
The enCoRe II features up to 20 GPIO pins to support USB,
PS/2, and other applications. The IO pins are grouped into four
ports (Port 0 to 3). The pins on Port 0 and Port 1 may each be
configured individually while the pins on Ports 2 and 3 are
configured only as a group. Each GPIO port supports high
impedance inputs, configurable pull-up, open drain output,
CMOS/TTL inputs, and CMOS output with up to five pins that
support a programmable drive strength of up to 50 mA sink
current. GPIO Port 1 features four pins that interface at a voltage
level of 3.3V. Additionally, each IO pin may be used to generate
a GPIO interrupt to the microcontroller. Each GPIO port has its
own GPIO interrupt vector; in addition, GPIO Port 0 has three
dedicated pins that have independent interrupt vectors
(P0.2–P0.4).
The enCoRe II includes an integrated USB serial interface
engine (SIE) that allows the chip to easily interface to a USB
host. The hardware supports one USB device address with three
endpoints.
The USB D+ and D– pins are optionally used as PS/2 SCLK and
SDATA signals so that products are designed to respond to
either USB or PS/2 modes of operation. The PS/2 operation is
supported with internal 5 K pull-up resistors on P1.0 (D+) and
P1.1 (D–), and an interrupt to signal the start of PS/2 activity. In
USB mode, the integrated 1.5 Kpull-up resistor on D– may be
controlled under firmware. No external components are
necessary for dual USB and PS/2 systems, and no GPIO pins
need to be dedicated to switching between modes.
The enCoRe II features an internal oscillator. With the presence
of USB traffic, the internal oscillator may be set to precisely tune
to USB timing requirements (24 MHz ±1.5%). Optionally, an
external 12 MHz or 24 MHz clock is used to provide a higher
precision reference for USB operation. The clock generator
provides the 12 MHz and 24 MHz clocks that remain internal to
The enCoRe II supports in system programming by using the D+
and D– pins as the serial programming mode interface. The
programming protocol is not USB.
the microcontroller. The enCoRe II also has
a 12-bit
programmable interval timer and a 16-bit Free Running Timer
with Capture Timer registers. In addition, the enCoRe II includes
a Watchdog timer and a vectored interrupt controller.
Conventions
The enCoRe II has up to eight Kbytes of flash for user code and
up to 256 bytes of RAM for stack space and user variables.
In this data sheet, bit positions in the registers are shaded to
indicate which members of the enCoRe II family implement the
bits.
The power on reset circuit detects logic when power is applied
to the device, resets the logic to a known state, and begins
executing instructions at flash address 0x0000. When power
falls below a programmable trip voltage, it generates a reset or
may be configured to generate an interrupt. There is a low
voltage detect circuit that detects when VCC drops below a
programmable trip voltage. It is configurable to generate an LVD
interrupt to inform the processor about the low voltage event.
Available in all enCoRe II family members
CY7C638(1/2/3)3 only
Document Number: 38-08035 Rev. *Q
Page 4 of 91
CY7C63310, CY7C638xx
Pinouts
Figure 1. Pin Diagrams
Top View
CY7C63801, CY7C63310
16-Pin SOIC
CY7C63803
16-Pin SOIC
P1.6/SMISO
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
P1.6/SMISO
15 P1.5/SMOSI
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
16
1
2
3
4
5
6
7
8
P1.5/SMOSI
P1.4/SCLK
P1.3/SSEL
P1.2
P1.4/SCLK
P1.3/SSEL
P1.2/VREG
14
13
12
11
10
9
V
P0.1
P0.0
V
CC
P0.1
P0.0
CC
P1.1/D–
P1.0/D+
P1.1/D–
P1.0/D+
V
V
SS
SS
CY7C63813
18-Pin PDIP
CY7C63813
18-Pin SOIC
P1.2/VREG
SSEL/P1.3
SCLK/P1.4
SMOSI/P1.5
SMISO/P1.6
P1.7
18
17
16
15
14
13
12
11
10
P1.7
17 P1.6/SMISO
1
2
3
4
5
6
7
8
9
P0.7
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
18
1
2
3
4
5
6
7
8
9
V
CC
P1.1/D–
P1.0/D+
P1.5/SMOSI
P1.4/SCLK
P1.3/SSEL
16
15
14
13
12
11
10
V
SS
P0.7
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
P0.0
P0.1
P0.2/INT0
P0.3/INT1
INT0/P0.2
P0.1
P1.2/VREG
V
CC
P0.0
P1.1/D–
P1.0/D+
V
SS
CY7C63823
24-Pin SOIC
CY7C63823
24-Pin QSOP
NC
NC
P0.7
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
P1.7
NC
P0.7
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
P1.7
P1.6/SMISO
P1.6/SMISO
P1.5/SMOSI
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
P0.1
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
P0.1
P1.5/SMOSI
P1.4/SCLK
P3.1
P3.0
P1.3/SSEL
P1.2/VREG
P1.4/SCLK
P3.1
P3.0
P1.3/SSEL
P1.2/VREG
P0.0
P2.1
P2.0
9
V
P0.0
P2.1
P2.0
NC
9
CC
V
P1.1/D–
10
11
12
CC
10
11
12
P1.1/D–
P1.0/D+
14
13
P1.0/D+
14
13
V
V
SS
SS
Document Number: 38-08035 Rev. *Q
Page 5 of 91
CY7C63310, CY7C638xx
QFN Pinouts
Figure 2. CY7C63803 24-Pin QFN
1
2
3
4
5
6
P1.5/MOSI
P1.4/SCLK
P1.3/SSEL
P1.2/VREG
VCC
P0.7
TIO0/P0.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
P0.1
18
17
16
15
14
13
QFN
P1.1 D-
Figure 3. CY7C63833 32-Pin Sawn QFN
30 29
32 31
28 27 26 25
24
23
22
21
20
19
18
17
P0.6/TIO1
P0.5/TIO0
P0.4/INT2
P0.3/INT1
P1.5/SMOSI
P1.4/SCLK
P3.1
1
2
3
4
5
6
7
8
P3.0
P1.3/SSEL
P0.2/INT0
P0.1
NC
P0.0
P1.2/VREG
NC
P2.1
9
10 11 12 13 14 15 16
Document Number: 38-08035 Rev. *Q
Page 6 of 91
CY7C63310, CY7C638xx
Pin Descriptions
32
QFN
24
QSOP
24
QFN
24
SOIC
18
SIOC
18
16
Name
Description
PDIP SOIC
21
22
–
–
19
20
18
19
–
–
–
–
–
–
P3.0
P3.1
GPIO Port 3. Configured as a group (byte).
9
8
–
–
11
10
11
10
–
–
–
–
–
–
P2.0
P2.1
GPIO Port 2. Configured as a group (byte).
14
15
18
12
13
15
14
15
17
13
14
16
10
11
13
15
16
18
9
P1.0/D+ GPIO Port 1 bit 0/USB D+ [1]/ISSP-SCLK If this pin is used
as a General Purpose output, it draws current. This pin must
be configured as an input to reduce current draw.
P1.1/D– GPIO Port 1 bit 1/USB D– [1]/ISSP-SDATA If this pin is used
as a General Purpose output, it draws current. This pin must
be configured as an input to reduce current draw.
10
12
P1.2/VREG GPIO Port 1 bit 2. Configured individually.
3.3V if regulator is enabled. (The 3.3 V regulator is not available
in the CY7C63310 and CY7C63801.) A 1-F min, 2-F max
capacitor is required on Vreg output.
20
23
24
25
16
17
18
–
18
21
22
23
17
20
21
22
14
15
16
17
1
2
3
4
13
14
P1.3/SSEL GPIO Port 1 bit 3. Configured individually.
Alternate function is SSEL signal of the SPI bus TTL voltage
thresholds. Although Vreg is not available with the
CY7C63310, 3.3 V I/O is still available.
P1.4/SCLK GPIO Port 1 bit 4. Configured individually.
Alternate function is SCLK signal of the SPI bus TTL voltage
thresholds. Although Vreg is not available with the
CY7C63310, 3.3 V I/O is still available.
15 P1.5/SMOSI GPIO Port 1 bit 5. Configured individually.
Alternate function is SMOSI signal of the SPI bus TTL voltage
thresholds. Although Vreg is not available with the
CY7C63310, 3.3 V I/O is still available.
16 P1.6/SMISO GPIO Port 1 bit 6. Configured individually.
Alternate function is SMISO signal of the SPI bus TTL voltage
thresholds. Although Vreg is not available with the
CY7C63310, 3.3 V I/O is still available.
26
7
19
7
24
9
23
9
18
8
5
–
7
6
5
4
3
P1.7
P0.0
P0.1
GPIO Port 1 bit 7. Configured individually.
TTL voltage threshold.
13
12
11
10
9
GPIO Port 0 bit 0. Configured individually.
External clock input when configured as Clock In.
6
6
8
8
7
GPIO Port 0 bit 1. Configured individually.
Clock output when configured as Clock Out.
5
5
7
7
6
P0.2/INT0 GPIO Port 0 bit 2. Configured individually.
Optional rising edge interrupt INT0.
4
4
6
6
5
P0.3/INT1 GPIO Port 0 bit 3. Configured individually.
Optional rising edge interrupt INT1.
3
3
5
5
4
P0.4/INT2 GPIO Port 0 bit 4. Configured individually.
Optional rising edge interrupt INT2.
Note
1. P1.0(D+) and P1.1(D–) pins must be in I/O mode when used as GPIO and in I mode.
sb
Document Number: 38-08035 Rev. *Q
Page 7 of 91
CY7C63310, CY7C638xx
Pin Descriptions (continued)
32
QFN
24
QSOP
24
QFN
24
SOIC
18
SIOC
18
16
Name
Description
PDIP SOIC
2
2
–
1
4
3
2
4
3
2
3
2
1
8
7
6
2
1
–
P0.5/TIO0 GPIO Port 0 bit 5. Configured individually
Alternate function Timer capture inputs or Timer output TIO0
1
P0.6/TIO1 GPIO Port 0 bit 6. Configured individually
Alternate function Timer capture inputs or Timer output TIO1
32
P0.7
GPIO Port 0 bit 7. Configured individually
Not present in the 16 pin SOIC package
10
11
12
17
19
27
28
29
30
31
16
13
8
1
12
–
1
24
–
–
–
–
–
–
–
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Vcc
VSS
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
Supply
9
10
20
21
22
23
24
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
14
11
16
13
15
12
12
9
17
14
11
8
Ground
The Stack Pointer Register (CPU_SP) holds the address of the
current top of the stack in the data memory space. It is affected
by the PUSH, POP, LCALL, CALL, RETI, and RET instructions,
which manage the software stack. It is also affected by the SWAP
and ADD instructions.
CPU Architecture
This family of microcontrollers is based on a high performance,
8-bit, Harvard architecture microprocessor. Five registers control
the primary operation of the CPU core. These registers are
affected by various instructions, but are not directly accessible
through the register space by the user.
The Flag Register (CPU_F) has three status bits: Zero Flag bit
[1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global
Interrupt Enable bit [0] globally enables or disables interrupts.
The user cannot manipulate the Supervisory State status bit [3].
The flags are affected by arithmetic, logic, and shift operations.
The manner in which each flag is changed is dependent upon
the instruction being executed, such as AND, OR, XOR, and
others. See Table 18 on page 13.
Table 1. CPU Registers and Register Names
CPU Register
Register Name
CPU_F
Flags
Program Counter
Accumulator
Stack Pointer
Index
CPU_PC
CPU_A
CPU_SP
CPU_X
The 16-bit Program Counter Register (CPU_PC) allows direct
addressing of the full 8 Kbytes of program memory space.
The Accumulator Register (CPU_A) is the general purpose
register, which holds the results of instructions that specify any
of the source addressing modes.
The Index Register (CPU_X) holds an offset value that is used
in the indexed addressing modes. Typically, this is used to
address a block of data within the data memory space.
Document Number: 38-08035 Rev. *Q
Page 8 of 91
CY7C63310, CY7C638xx
CPU Registers
The CPU registers in enCoRe II devices are in two banks with 256 registers in each bank. Bit[4]/XI/O bit in the CPU Flags register
must be set/cleared to select between the two register banks Table 2 on page 9
Flags Register
The Flags Register is set or reset only with logical instruction.
Table 2. CPU Flags Register (CPU_F) [R/W]
Bit #
Field
7
6
5
4
XIO
R/W
0
3
Super
R
2
Carry
RW
0
1
Zero
RW
1
0
Global IE
RW
Reserved
Read/Write
Default
–
0
–
0
–
0
0
0
Bit [7:5]: Reserved
Bit 4: XIO
Set by the user to select between the register banks
0 = Bank 0
1 = Bank 1
Bit 3: Super
Indicates whether the CPU is executing user code or Supervisor Code. (This code cannot be accessed directly by the user.)
0 = User Code
1 = Supervisor Code
Bit 2: Carry
Set by the CPU to indicate whether there has been a carry in the previous logical/arithmetic operation.
0 = No Carry
1 = Carry
Bit 1: Zero
Set by the CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation.
0 = Not Equal to Zero
1 = Equal to Zero
Bit 0: Global IE
Determines whether all interrupts are enabled or disabled
0 = Disabled
1 = Enabled
Note CPU_F register is only readable with the explicit register address 0xF7. The OR F, expr and AND F, expr instructions must
be used to set and clear the CPU_F bits.
Table 3. CPU Accumulator Register (CPU_A)
Bit #
Field
7
6
5
4
3
2
1
0
CPU Accumulator [7:0]
Read/Write
Default
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
Bit [7:0]: CPU Accumulator [7:0]
8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode
Document Number: 38-08035 Rev. *Q
Page 9 of 91
CY7C63310, CY7C638xx
Table 4. CPU X Register (CPU_X)
Bit #
Field
7
6
5
4
3
2
1
0
X [7:0]
Read/Write
Default
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
Bit [7:0]: X [7:0]
8-bit data value holds an index for any instruction that uses an indexed addressing mode.
Table 5. CPU Stack Pointer Register (CPU_SP)
Bit #
Field
7
6
5
4
3
2
1
0
Stack Pointer [7:0]
Read/Write
Default
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
Bit [7:0]: Stack Pointer [7:0]
8-bit data value holds a pointer to the current top of the stack.
Table 6. CPU Program Counter High Register (CPU_PCH)
Bit #
Field
7
6
5
4
3
2
1
0
Program Counter [15:8]
Read/Write
Default
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
Bit [7:0]: Program Counter [15:8]
8-bit data value holds the higher byte of the program counter.
Table 7. CPU Program Counter Low Register (CPU_PCL)
Bit #
Field
7
6
5
4
3
2
1
0
Program Counter [7:0]
Read/Write
Default
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
Bit [7:0]: Program Counter [7:0]
8-bit data value holds the lower byte of the program counter.
Table 8. Source Immediate
Opcode
Addressing Modes
Operand 1
Source Immediate
Instruction
Immediate Value
The result of an instruction using this addressing mode is placed
in the A register, the F register, the SP register, or the X register,
which is specified as part of the instruction opcode. Operand 1
is an immediate value that serves as a source for the instruction.
Arithmetic instructions require two sources; the second source is
the A or the X register specified in the opcode. Instructions using
this addressing mode are two bytes in length.
Examples
ADD
A
7
The immediate value of 7 is added with the
Accumulator and the result is placed in the
Accumulator.
MOV
AND
X
F
8
9
The immediate value of 8 is moved to the X
register.
The immediate value of 9 is logically ANDed with
the F register and the result is placed in the F
register.
Document Number: 38-08035 Rev. *Q
Page 10 of 91
CY7C63310, CY7C638xx
Source Direct
Destination Direct
The result of an instruction using this addressing mode is placed
in either the A register or the X register, which is specified as part
of the instruction opcode. Operand 1 is an address that points to
a location in the RAM memory space or the register space that
is the source of the instruction. Arithmetic instructions require
two sources; the second source is the A register or X register
specified in the opcode. Instructions using this addressing mode
are two bytes in length.
The result of an instruction using this addressing mode is placed
within the RAM memory space or the register space. Operand 1
is an address that points to the location of the result. The source
for the instruction is either the A register or the X register, which
is specified as part of the instruction opcode. Arithmetic
instructions require two sources; the second source is the
location specified by Operand 1. Instructions using this
addressing mode are two bytes in length.
Table 11. Destination Direct
Table 9. Source Direct
Opcode
Instruction
Operand 1
Destination address
Opcode
Instruction
Operand 1
Source address
Examples
Examples
ADD
MOV
[7]
A
A
The value in the memory location at
address 7 is added with the Accumu-
lator, and the result is placed in the
memory location at address 7. The
Accumulator is unchanged.
ADD
A
[7]
The value in the RAM memory location at
address 7 is added with the Accumulator,
and the result is placed in the Accumu-
lator.
MOV
X
REG[8]
Thevaluein the registerspace ataddress
8 is moved to the X register.
REG[8]
The Accumulator is moved to the
register space location at address 8.
The Accumulator is unchanged.
Source Indexed
The result of an instruction using this addressing mode is placed
in either the A register or the X register, which is specified as part
of the instruction opcode. Operand 1 is added to the X register
forming an address that points to a location in the RAM memory
space or the register space that is the source of the instruction.
Arithmetic instructions require two sources; the second source is
the A register or X register specified in the opcode. Instructions
using this addressing mode are two bytes in length.
Destination Indexed
The result of an instruction using this addressing mode is placed
within the RAM memory space or the register space. Operand 1
is added to the X register forming the address that points to the
location of the result. The source for the instruction is the A
register. Arithmetic instructions require two sources; the second
source is the location specified by Operand 1 added with the X
register. Instructions using this addressing mode are two bytes
in length.
Table 10. Source Indexed
Table 12. Destination Indexed
Opcode
Instruction
Operand 1
Source index
Opcode
Instruction
Operand 1
Destination index
Examples
Example
ADD
A
[X+7]
The value in the memory location at
address X + 7 is added with the
Accumulator, and the result is placed
in the Accumulator.
ADD [X+7]
A
The value in the; memory location at
address X+7 is added with the Accumu-
lator, and the result is placed in the
memory location at address x+7. The
Accumulator is unchanged.
MOV
X
REG[X+8]
The value in the register space at
address X + 8 is moved to the X
register.
Document Number: 38-08035 Rev. *Q
Page 11 of 91
CY7C63310, CY7C638xx
.
Destination Direct Source Immediate
Table 15. Destination Direct Source Direct
The result of an instruction using this addressing mode is placed
within the RAM memory space or the register space. Operand 1
is the address of the result. The source of the instruction is
Operand 2, which is an immediate value. Arithmetic instructions
require two sources; the second source is the location specified
by Operand 1. Instructions using this addressing mode are three
bytes in length.
Opcode
Operand 1
Operand 2
Instruction
Destination address
Source address
Example
MOV [7]
[8]
The value in the memory location at address 8
is moved to the memory location at address 7.
Table 13. Destination Direct Source Immediate
Opcode
Operand 1
Operand 2
Source Indirect Post Increment
Instruction
Destination address
Immediate Value
The result of an instruction using this addressing mode is placed
in the Accumulator. Operand 1 is an address pointing to a
location within the memory space, which contains an address
(the indirect address) for the source of the instruction. The
indirect address is incremented as part of the instruction
execution. This addressing mode is only valid on the MVI
instruction. The instruction using this addressing mode is two
bytes in length. Refer to the PSoC Designer: Assembly
Language User Guide for further details on MVI instruction.
Examples
ADD [7]
5
6
The value in the memory location at address
7 is added to the immediate value of 5, and
the result is placed in the memory location at
address 7.
MOV REG[8]
The immediate value of 6 is moved into the
register space location at address 8.
Table 16. Source Indirect Post Increment
Destination Indexed Source Immediate
Opcode
Instruction
Operand 1
The result of an instruction using this addressing mode is placed
within the RAM memory space or the register space. Operand 1
is added to the X register to form the address of the result. The
source of the instruction is Operand 2, which is an immediate
value. Arithmetic instructions require two sources; the second
source is the location specified by Operand 1 added with the X
register. Instructions using this addressing mode are three bytes
in length.
Source address address
Example
MVI
A
[8]
The value in the memory location at address
8 is an indirect address. The memory location
pointed to by the indirect address is moved
into the Accumulator. The indirect address is
then incremented.
Table 14. Destination Indexed Source Immediate
Opcode
Operand 1
Operand 2
Destination Indirect Post Increment
Instruction
Destination index
Immediate value
The result of an instruction using this addressing mode is placed
within the memory space. Operand 1 is an address pointing to a
location within the memory space, which contains an address
(the indirect address) for the destination of the instruction. The
indirect address is incremented as part of the instruction
execution. The source for the instruction is the Accumulator. This
addressing mode is only valid on the MVI instruction. The
instruction using this addressing mode is two bytes in length.
Examples
ADD
MOV
[X+7]
5
6
The value in the memory location at
address X+7 is added with the
immediate value of 5, and the result
is placed in the memory location at
address X+7.
Table 17. Destination Indirect Post Increment
REG[X+8]
The immediate value of 6 is moved
into the location in the register space
at address X+8.
Opcode
Instruction
Operand 1
Destination address address
Destination Direct Source Direct
Example
The result of an instruction using this addressing mode is placed
within the RAM memory. Operand 1 is the address of the result.
Operand 2 is an address that points to a location in the RAM
memory that is the source for the instruction. This addressing
mode is only valid on the MOV instruction. The instruction using
this addressing mode is three bytes in length.
MVI
[8]
A
The value in the memory location at
address 8 is an indirect address. The
Accumulator is moved into the memory
location pointed to by the indirect
address. The indirect address is then
incremented.
Document Number: 38-08035 Rev. *Q
Page 12 of 91
CY7C63310, CY7C638xx
Instruction Set Summary
The instruction set is summarized in Table 18 numerically and serves as a quick reference. If more information is needed, the
Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (available on the
Cypress web site at http://www.cypress.com/?docID=15538).
Table 18. Instruction Set Summary Sorted Numerically by Opcode Order [2, 3]
Instruction Format
1 SSC
Flags
Instruction Format
2 OR [X+expr], A
3 OR [expr], expr
3 OR [X+expr], expr
1 HALT
Flags
Instruction Format
2 MOV [expr], X
1 MOV A, X
1 MOV X, A
2 MOV A, reg[expr]
2 MOV A, reg[X+expr]
3 MOV [expr], [expr]
2 MOV reg[expr], A
2 MOV reg[X+expr], A
3 MOV reg[expr], expr
3 MOV reg[X+expr], expr
1 ASL A
Flags
00 15
–
2D
2E
8
9
Z
5A
5B
5C
5D
5E
5
4
4
6
7
–
Z
–
Z
Z
–
–
–
–
–
01
02
03
04
05
06
4
6
7
7
8
9
2 ADD A, expr
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
–
Z
Z
–
Z
Z
Z
Z
Z
Z
Z
–
2 ADD A, [expr]
2 ADD A, [X+expr]
2 ADD [expr], A
2 ADD [X+expr], A
3 ADD [expr], expr
3 ADD [X+expr], expr
1 PUSH A
2F 10
30
31
32
33
34
35
36
9
4
6
7
7
8
9
2 XOR A, expr
2 XOR A, [expr]
5F 10
2 XOR A, [X+expr]
2 XOR [expr], A
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
5
6
8
9
4
7
8
4
7
8
4
7
8
4
7
8
4
4
4
4
4
4
7
8
4
4
7
8
07 10
08
09
4
4
6
7
7
8
9
2 XOR [X+expr], A
3 XOR [expr], expr
3 XOR [X+expr], expr
2 ADD SP, expr
2 ADC A, expr
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
–
0A
0B
0C
0D
0E
2 ADC A, [expr]
2 ADC A, [X+expr]
2 ADC [expr], A
2 ADC [X+expr], A
3 ADC [expr], expr
3 ADC [X+expr], expr
1 PUSH X
37 10
C, Z
38
39
5
5
7
8
8
9
2 ASL [expr]
2 ASL [X+expr]
1 ASR A
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
2 CMP A, expr
3A
3B
3C
3D
2 CMP A, [expr]
if (A=B) Z=1
if (A<B) C=1
2 CMP A, [X+expr]
3 CMP [expr], expr
3 CMP [X+expr], expr
2 MVI A, [ [expr]++]
2 MVI [ [expr]++], A
1 NOP
2 ASR [expr]
2 ASR [X+expr]
1 RLC A
0F 10
10
11
12
13
14
15
16
4
4
6
7
7
8
9
2 SUB A, expr
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
3E 10
3F 10
Z
–
–
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
Z
–
Z
Z
Z
–
–
–
–
–
–
–
2 RLC [expr]
2 RLC [X+expr]
1 RRC A
2 SUB A, [expr]
2 SUB A, [X+expr]
2 SUB [expr], A
2 SUB [X+expr], A
3 SUB [expr], expr
3 SUB [X+expr], expr
1 POP A
40
41
4
9
3 AND reg[expr], expr
3 AND reg[X+expr], expr
3 OR reg[expr], expr
3 OR reg[X+expr], expr
3 XOR reg[expr], expr
3 XOR reg[X+expr], expr
3 TST [expr], expr
3 TST [X+expr], expr
3 TST reg[expr], expr
3 TST reg[X+expr], expr
1 SWAP A, X
2 RRC [expr]
2 RRC [X+expr]
2 AND F, expr
2 OR F, expr
2 XOR F, expr
1 CPL A
42 10
43
44 10
45
46 10
9
17 10
18
19
5
4
6
7
7
8
9
9
2 SBB A, expr
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
–
1A
1B
1C
1D
1E
2 SBB A, [expr]
2 SBB A, [X+expr]
2 SBB [expr], A
2 SBB [X+expr], A
3 SBB [expr], expr
3 SBB [X+expr], expr
1 POP X
47
48
49
8
9
9
1 INC A
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
–
1 INC X
2 INC [expr]
2 INC [X+expr]
1 DEC A
4A 10
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5
7
7
5
4
4
5
6
5
6
8
9
4
6
7
1F 10
2 SWAP A, [expr]
2 SWAP X, [expr]
1 SWAP A, SP
1 DEC X
20
21
22
23
24
25
26
5
4
6
7
7
8
9
2 DEC [expr]
2 DEC [X+expr]
3 LCALL
2 AND A, expr
Z
2 AND A, [expr]
2 AND A, [X+expr]
2 AND [expr], A
2 AND [X+expr], A
3 AND [expr], expr
3 AND [X+expr], expr
1 ROMX
Z
1 MOV X, SP
7C 13
7D
7E 10
Z
2 MOV A, expr
7
3 LJMP
–
Z
2 MOV A, [expr]
1 RETI
C, Z
–
Z
2 MOV A, [X+expr]
2 MOV [expr], A
7F
8x
8
5
1 RET
Z
2 JMP
–
27 10
28 11
Z
2 MOV [X+expr], A
3 MOV [expr], expr
3 MOV [X+expr], expr
2 MOV X, expr
9x 11
2 CALL
–
Z
Ax
Bx
Cx
Dx
Ex
5
5
5
5
7
2 JZ
–
29
2A
2B
2C
4
6
7
7
2 OR A, expr
Z
2 JNZ
–
2 OR A, [expr]
Z
2 JC
–
2 OR A, [X+expr]
2 OR [expr], A
Z
2 MOV X, [expr]
2 JNC
–
Z
2 MOV X, [X+expr]
2 JACC
–
Fx 13
2 INDEX
Z
Notes
2. Interrupt routines take 13 cycles before execution resumes at interrupt vector table.
3. The number of cycles required by an instruction is increased by one for instructions that span 256 byte boundaries in the flash memory space.
Document Number: 38-08035 Rev. *Q
Page 13 of 91
CY7C63310, CY7C638xx
Memory Organization
Flash Program Memory Organization
Figure 4. Program Memory Space with Interrupt Vector Table
after reset
16-bit PC
Address
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0040
0x0044
0x0048
0x004C
0x0050
0x0054
0x0058
0x005C
0x0060
0x0064
0x0068
Program execution begins here after a reset
POR/LVD
INT0
SPI transmitter empty
SPI receiver full
GPIO port 0
GPIO port 1
INT1
EP0
EP1
EP2
USB reset
USB active
1 ms interval timer
Programmable interval timer
Timer capture 0
Timer capture 1
16-bit free running timer wrap
INT2
PS2 data low
GPIO port 2
GPIO port 3
Reserved
Reserved
Reserved
Sleep timer
Program Memory begins here (if below interrupts not used,
program memory can start lower)
0x0BFF
0x0FFF
3 KB ends here (CY7C63310)
4 KB ends here (CY7C63801)
0x1FFF
8 KB ends here (CY7C638x3)
Document Number: 38-08035 Rev. *Q
Page 14 of 91
CY7C63310, CY7C638xx
Data Memory Organization
The CY7C63310/638xx microcontrollers provide up to 256 bytes of data RAM.
Figure 5. Data Memory Organization
after reset
8-bit PSP
Address
0x00
Stack begins here and grows upward.
Top of RAM Memory
0xFF
to enable the enCoRe II part to enter the serial programming
mode, and then use the test queue to issue flash access
functions in the SROM. The programming protocol is not USB.
Flash
This section describes the flash block of the enCoRe II. Much of
the user visible flash functionality including programming and
security are implemented in the M8C Supervisory Read Only
Memory (SROM). The enCoRe II flash has an endurance of 1000
cycles and a 10 year data retention capability.
SROM
The SROM holds code that boots the part, calibrates circuitry,
and performs flash operations (Table 19 on page 15 lists the
SROM functions). The functions of the SROM are accessed in
the normal user code or operating from flash. The SROM exists
in a separate memory space from the user code. The SROM
functions are accessed by executing the Supervisory System
Call instruction (SSC), which has an opcode of 00h. Before
executing the SSC the M8C’s accumulator must be loaded with
the desired SROM function code from Table 19 on page 15.
Undefined functions cause a HALT if called from the user code.
The SROM functions are executing code with calls; as a result,
the functions require stack space. With the exception of Reset,
all of the SROM functions have a parameter block in SRAM that
must be configured before executing the SSC. Table 20 on page
16 lists all possible parameter block variables. The meaning of
each parameter, with regards to a specific SROM function, is
described later in this section.
Flash Programming and Security
All flash programming is performed by code in the SROM. The
registers that control the flash programming are only visible to
the M8C CPU when it executes out of SROM. This makes it
impossible to read, write or erase the flash by bypassing the
security mechanisms implemented in the SROM.
Customer firmware can program the flash only through SROM
calls. The data or code images are sourced through any interface
with the appropriate support firmware. This type of programming
requires a ‘boot-loader’, which is a piece of firmware resident on
the flash. For safety reasons this boot-loader must not be
overwritten during firmware rewrites.
The flash provides four extra auxiliary rows that are used to hold
flash block protection flags, boot time calibration values,
configuration tables, and any device values. The routines for
accessing these auxiliary rows are documented in the section
SROM on page 15 section. The auxiliary rows are not affected
by the device erase function.
Table 19. SROM Function Codes
Function Code
Function Name
SWBootReset
Stack Space
00h
01h
02h
03h
05h
06h
07h
0
7
In System Programming
ReadBlock
WriteBlock
EraseBlock
EraseAll
Most designs that include an enCoRe II part have a USB
connector attached to the USB D+ and D– pins on the device.
These designs require the ability to program or reprogram a part
through the USB D+ and D– pins alone.
10
9
11
3
The enCoRe II devices enable this type of in system
programming by using the D+ and D– pins as the serial
programming mode interface. This allows an external controller
TableRead
CheckSum
3
Document Number: 38-08035 Rev. *Q
Page 15 of 91
CY7C63310, CY7C638xx
Two important variables that are used for all functions are KEY1
and KEY2. These variables are used to help discriminate
between valid SSCs and inadvertent SSCs. KEY1 must always
have a value of 3Ah, while KEY2 must have the same value as
the stack pointer when the SROM function begins execution.
This would be the Stack Pointer value when the SSC opcode is
executed, plus three. If either of the keys do not match the
expected values, the M8C halts (with the exception of the
SWBootReset function). The following code puts the correct
value in KEY1 and KEY2. The code starts with a halt, to force the
program to jump directly into the setup code and not run into it.
halt
SROM Function Descriptions
SWBootReset Function
The SROM function, SWBootReset, is the function that is
responsible for transitioning the device from a reset state to
running user code. The SWBootReset function is executed
whenever the SROM is entered with an M8C accumulator value
of 00h: the SRAM parameter block is not used as an input to the
function. This happens by design after a hardware reset,
because the M8C's accumulator is reset to 00h or when the user
code executes the SSC instruction with an accumulator value of
00h. The SWBootReset function is not executed when the SSC
instruction is executed with a bad key value and a non-zero
function code. An enCoRe II device executes the HALT
instruction if a bad value is given for either KEY1 or KEY2.
SSCOP: mov [KEY1], 3ah
mov X, SP
mov A, X
add A, 3
The SWBootReset function verifies the integrity of the calibration
data by way of a 16-bit checksum, before releasing the M8C to
run user code.
mov [KEY2], A
Table 20. SROM Function Parameters
Variable Name
SRAM Address
0,F8h
ReadBlock Function
Key1/Counter/Return Code
The ReadBlock function is used to read 64 contiguous bytes
from flash: a block.
Key2/TMP
BlockID
Pointer
Clock
0,F9h
0,FAh
This function first checks the protection bits and determines if the
desired BLOCKID is readable. If the read protection is turned on,
the ReadBlock function exits setting the accumulator and KEY2
back to 00h. KEY1 has a value of 01h, indicating a read failure.
If read protection is not enabled, the function reads 64 bytes from
the flash using a ROMX instruction and stores the results in the
SRAM using an MVI instruction. The first of the 64 bytes are
stored in the SRAM at the address indicated by the value of the
POINTER parameter. When the ReadBlock completes
successfully, the accumulator, KEY1, and KEY2 all have a value
of 00h.
0,FBh
0,FCh
Mode
0,FDh
Delay
0,FEh
PCL
0,FFh
Return Codes
The SROM also features Return Codes and Lockouts.
Return codes aid in the determination of the success or failure of
a particular function. The return code is stored in KEY1’s position
in the parameter block. The CheckSum and TableRead functions
do not have return codes because KEY1’s position in the
parameter block is used to return other data.
Table 22. ReadBlock Parameters
Name
KEY1
Address
0,F8h
Description
3Ah
KEY2
0,F9h
Stack Pointer value, when SSC is
executed.
Table 21. SROM Return Codes
Return Code
Description
BLOCKID
POINTER
0,FAh
flash block number
00h
01h
Success
0,FBh First of 64 addresses in SRAM
where returned data must be stored.
Function not allowed due to level of protection
on block.
02h
03h
Software reset without hardware reset.
Fatal error, SROM halted.
Read, write, and erase operations may fail if the target block is
read or write protected. Block protection levels are set during
device programming.
The EraseAll function overwrites data in addition to leaving the
entire user flash in the erase state. The EraseAll function loops
through the number of flash macros in the product, executing the
following sequence: erase, bulk program all zeros, erase. After
all the user space in all the flash macros are erased, a second
loop erases and then programs each protection block with zeros.
Document Number: 38-08035 Rev. *Q
Page 16 of 91
CY7C63310, CY7C638xx
WriteBlock Function
Table 24. EraseBlock Parameters
The WriteBlock function is used to store data in the flash. Data
is moved 64 bytes at a time from SRAM to flash using this
function. The WriteBlock function first checks the protection bits
and determines if the desired BLOCKID is writable. If write
protection is turned on, the WriteBlock function exits setting the
accumulator and KEY2 back to 00h. KEY1 has a value of 01h,
indicating a write failure. The configuration of the WriteBlock
function is straightforward. The BLOCKID of the flash block,
where the data is stored, must be determined and stored at
SRAM address FAh.
Name
KEY1
KEY2
Address
0,F8h
Description
3Ah
0,F9h
Stack Pointer value, when SSC is
executed.
BLOCKID 0,FAh
8KB flash block number (00h–7Fh)
4KB flash block number (00h–3Fh)
3KB flash block number (00h–2Fh)
CLOCK
DELAY
0,FCh
0,FEh
Clock divider used to set the erase
pulse width.
The SRAM address of the first of the 64 bytes to be stored in
flash must be indicated using the POINTER variable in the
parameter block (SRAM address FBh). Finally, the CLOCK and
DELAY value must be set correctly. The CLOCK value deter-
mines the length of the write pulse that is used to store the data
in the flash. The CLOCK and DELAY values are dependent on
the CPU speed and must be set correctly.
For a CPU speed of 12 MHz set to 56h
ProtectBlock Function
The enCoRe II devices offer flash protection on a block by block
basis. Table 25 lists the protection modes available. In this table,
ER and EW indicate the ability to perform external reads and
writes. For internal writes, IW is used. Internal reading is
permitted by way of the ROMX instruction. The ability to read by
way of the SROM ReadBlock function is indicated by SR. The
protection level is stored in two bits according to Table 25. These
bits are bit packed into the 64 bytes of the protection block. As a
result, each protection block byte stores the protection level for
four flash blocks. The bits are packed into a byte, with the lowest
numbered block’s protection level stored in the lowest numbered
bits Table 25.
Table 23. WriteBlock Parameters
Name
KEY1
Address
Description
0,F8h 3Ah
KEY2
0,F9h Stack Pointer value, when SSC is
executed.
BLOCKID
0,FAh 8KB flash block number (00h–7Fh)
4KB flash block number (00h–3Fh)
3KB flash block number (00h–2Fh)
The first address of the protection block contains the protection
level for blocks 0 through 3; the second address is for blocks 4
through 7. The 64th byte stores the protection level for blocks
252 through 255.
POINTER
0,FBh Firstof64addressesinSRAM, where
the data to be stored in flash is
located before calling WriteBlock.
CLOCK
DELAY
0,FCh Clock divider used to set the write
pulse width.
Table 25. Protection Modes
0,FEh For a CPU speed of 12 MHz set to
56h.
Mode
Settings
Description
Marketing
Unprotected
00b SR ER EW IW Unprotected
01b SR ER EW IW Read protect
Factory upgrade
EraseBlock Function
10b SR ER EW IW Disable external write Field upgrade
11b SR ER EW IW Disable internal write Full protection
The EraseBlock function is used to erase a block of 64
contiguous bytes in flash. The EraseBlock function first checks
the protection bits and determines if the desired BLOCKID is
writable. If write protection is turned on, the EraseBlock function
exits setting the accumulator and KEY2 back to 00h. KEY1 has
a value of 01h, indicating a write failure. The EraseBlock function
is only useful as the first step in programming. When a block is
erased, the data in the block is not one hundred percent
unreadable. If the objective is to obliterate data in a block, the
best method is to perform an EraseBlock followed by a Write-
Block of all zeros.
7
6
5
4
3
2
1
0
Block n+3
Block n+2
Block n+1
Block n
The level of protection is only decreased by an EraseAll, which
places zeros in all locations of the protection block. To set the
level of protection, the ProtectBlock function is used. This
function takes data from SRAM, starting at address 80h, and
ORs it with the current values in the protection block. The result
of the OR operation is then stored in the protection block. The
EraseBlock function does not change the protection level for a
block. Because the SRAM location for the protection data is fixed
and there is only one protection block per flash macro, the
ProtectBlock function expects very few variables in the
parameter block to be set before calling the function. The
parameter block values that must be set, besides the keys, are
the CLOCK and DELAY values.
To set up the parameter block for the EraseBlock function,
correct key values must be stored in KEY1 and KEY2. The block
number to be erased must be stored in the BLOCKID variable
and the CLOCK and DELAY values must be set based on the
current CPU speed.
Document Number: 38-08035 Rev. *Q
Page 17 of 91
CY7C63310, CY7C638xx
Table 26. ProtectBlock Parameters
Table 28. Table Read Parameters
Name
KEY1
Address
0,F8h
Description
Name
KEY1
KEY2
Address
0,F8h
Description
3Ah
3Ah
KEY2
0,F9h
Stack Pointer value when SSC is
executed.
0,F9h
Stack Pointer value when SSC is
executed.
CLOCK
DELAY
0,FCh
0,FEh
Clock divider used to set the write pulse
width.
BLOCKID 0,FAh
Table number to read.
For a CPU speed of 12 MHz set to 56h.
The table space for the enCoRe II is simply a 64 byte row broken
up into eight tables of eight bytes. The tables are numbered zero
through seven. All user and hidden blocks in the CY7C638xx
parts consist of 64 bytes.
EraseAll Function
The EraseAll function performs a series of steps that destroy the
user data in the flash macros and resets the protection block in
each flash macro to all zeros (the unprotected state). The
EraseAll function does not affect the three hidden blocks above
the protection block, in each flash macro. The first of these four
hidden blocks is used to store the protection table for its eight
Kbytes of user data.
An internal table (Table 0) holds the Silicon ID and returns the
Revision ID. The Silicon ID is returned in SRAM, while the
Revision and Family IDs are returned in the CPU_A and CPU_X
registers. The Silicon ID is a value placed in the table by
programming the flash and is controlled by Cypress Semicon-
ductor Product Engineering. The Revision ID is hard coded into
the SROM and also redundantly placed in SROM Table 1. This
is discussed in more detail later in this section.
The EraseAll function begins by erasing the user space of the
flash macro with the highest address range. A bulk program of
all zeros is then performed on the same flash macro, to destroy
all traces of the previous contents. The bulk program is followed
by a second erase that leaves the flash macro in a state ready
for writing. The erase, program, erase sequence is then
performed on the next lowest flash macro in the address space
if it exists. After the erase of the user space, the protection block
for the flash macro with the highest address range is erased.
Following the erase of the protection block, zeros are written into
every bit of the protection table. The next lowest flash macro in
the address space then has its protection block erased and filled
with zeros.
SROM Table 1 holds Family/Die ID and Revision ID values for
the device and returns a one-byte internal revision counter. The
internal revision counter starts out with a value of zero and is
incremented when one of the other revision numbers is not
incremented. It is reset to zero when one of the other revision
numbers is incremented. The internal revision count is returned
in the CPU_A register. The CPU_X register is always set to FFh
when Table 1 is read. The CPU_A and CPU_X registers always
return a value of FFh when Tables 2-7 are read. The BLOCKID
value, in the parameter block, indicates which table must be
returned to the user. Only the three least significant bits of the
BLOCKID parameter are used by TableRead function for
enCoRe II devices. The upper five bits are ignored. When the
function is called, it transfers bytes from the table to SRAM
addresses F8h–FFh.
The end result of the EraseAll function is that all user data in the
flash is destroyed and the flash is left in an unprogrammed state,
ready to accept one of the various write commands. The
protection bits for all user data are also reset to the zero state
The parameter block values that must be set, besides the keys,
are the CLOCK and DELAY values.
The M8C’s A and X registers are used by the TableRead function
to return the die’s Revision ID. The Revision ID is a 16-bit value
hard coded into the SROM that uniquely identifies the die’s
design.
Table 27. EraseAll Parameters
Name Address
Description
KEY1
KEY2
0,F8h
0,F9h
3Ah
The return values for corresponding Table calls are tabulated as
shown in Table 29 on page 18
Stack Pointer value when SSC is
executed.
CLOCK 0,FCh
Clock divider used to set the write pulse
width.
Table 29. Return values for Table Read
Return Value
Table Number
DELAY 0,FEh
For a CPU speed of 12 MHz set to 56h
A
X
TableRead Function
Revision ID
Internal revision counter 0xFF
0xFF 0xFF
Family ID
0
1
The TableRead function gives the user access to part specific
data stored in the flash during manufacturing. It also returns a
Revision ID for the die (not to be confused with the Silicon ID).
2-7
Document Number: 38-08035 Rev. *Q
Page 18 of 91
CY7C63310, CY7C638xx
Figure 6. SROM Table
FAh FBh FCh
F8h
F9h
FDh
FEh
FFh
Silicon ID Silicon ID
Table0
Table1
Table2
Table3
Table4
Table5
Table6
Table7
[15-8]
[7-0]
Family/
Die ID
Revision
ID
The Silicon IDs for enCoRe II devices are stored in SROM tables in the part, as shown in Figure 6
The Silicon ID can be read out from the part using SROM Table reads (Table 0). This is demonstrated in the following pseudo code.
As mentioned in the section SROM on page 15, the SROM variables occupy address F8h through FFh in the SRAM. Each of the
variables and their definition is given in the section SROM on page 15.
AREA SSCParmBlkA(RAM,ABS)
org F8h // Variables are defined starting at address F8h
SSC_KEY1:
; F8h supervisory key
blk 1 ; F8h result code
blk 1 ;F9h supervisory stack ptr key
blk 1 ; FAh block ID
blk 1 ; FBh pointer to data buffer
blk 1 ; FCh Clock
blk 1 ; FDh ClockW ClockE multiplier
blk 1 ; FEh flash macro sequence delay count
SSC_RETURNCODE:
SSC_KEY2 :
SSC_BLOCKID:
SSC_POINTER:
SSC_CLOCK:
SSC_MODE:
SSC_DELAY:
SSC_WRITE_ResultCode: blk 1 ; FFh temporary result code
_main:
mov
mov
A, 0
[SSC_BLOCKID], A// To read from Table 0 - Silicon ID is stored in Table 0
//Call SROM operation to read the SROM table
mov
mov
add
mov
X, SP
A, X
A, 3
; copy SP into X
; A temp stored in X
; create 3 byte stack frame (2 + pushed A)
; save stack frame for supervisory code
[SSC_KEY2], A
; load the supervisory code for flash operations
mov
[SSC_KEY1], 3Ah ;flash_OPER_KEY - 3Ah
mov
SSC
A,6
; load A with specific operation. 06h is the code for Table read Table 19
; SSC call the supervisory ROM
// At the end of the SSC command the silicon ID is stored in F8 (MSB) and F9(LSB) of the SRAM
.terminate:
jmp .terminate
Document Number: 38-08035 Rev. *Q
Page 19 of 91
CY7C63310, CY7C638xx
Checksum Function
■ 5 V LP mode: +12% to + 48%
The Checksum function calculates a 16-bit checksum over a
user specifiable number of blocks, within a single flash macro
(Bank) starting from block zero. The BLOCKID parameter is
used to pass in the number of blocks to calculate the checksum
over. A BLOCKID value of 1 calculates the checksum of only
block 0, while a BLOCKID value of 0 calculates the checksum of
all 256 user blocks. The 16-bit checksum is returned in KEY1 and
KEY2. The parameter KEY1 holds the lower eight bits of the
checksum and the parameter KEY2 holds the upper eight bits of
the checksum.
When using the 32 kHz oscillator, the PITMRL/H registers must
be read until 2 consecutive readings match before the result is
considered valid. The following firmware example assumes the
developer is interested in the lower byte of the PIT.
Read_PIT_counter:
mov A, reg[PITMRL]
mov [57h], A
mov A, reg[PITMRL]
mov [58h], A
mov [59h], A
mov A, reg[PITMRL]
mov [60h], A
;;;Start comparison
mov A, [60h]
mov X, [59h]
sub A, [59h]
jz done
The checksum algorithm executes the following sequence of
three instructions over the number of blocks times 64 to be
checksummed.
romx
add [KEY1], A
adc [KEY2], 0
mov A, [59h]
mov X, [58h]
sub A, [58h]
jz done
mov X, [57h]
;;;correct data is in memory location 57h
done:
mov [57h], X
ret
Table 30. Checksum Parameters
Name
KEY1
KEY2
Address
0,F8h
Description
3Ah
0,F9h
Stack Pointer value when SSC is
executed.
BLOCKID 0,FAh
Number of flash blocks to calculate
checksum on.
Clocking
The enCoRe II has two internal oscillators, the Internal 24 MHz
Oscillator and the 32 kHz Low power Oscillator.
The Internal 24 MHz Oscillator is designed such that it may be
trimmed to an output frequency of 24 MHz over temperature and
voltage variation. With the presence of USB traffic, the Internal
24 MHz Oscillator may be set to precisely tune to the USB timing
requirements (24 MHz ± 1.5%). Without USB traffic, the Internal
24 MHz Oscillator accuracy is 24 MHz ± 5% (between
0 °C–70 °C). No external components are required to achieve
this level of accuracy.
The internal low speed oscillator of nominally 32 kHz provides a
slow clock source for the enCoRe II in suspend mode,
particularly to generate a periodic wakeup interrupt and also to
provide a clock to sequential logic during power up and power
down events when the main clock is stopped. In addition, this
oscillator can also be used as a clocking source for the Interval
Timer clock (ITMRCLK) and Capture Timer clock (TCAPCLK).
The 32 kHz Low power Oscillator can operate in low power mode
or can provide a more accurate clock in normal mode. The
Internal 32 kHz Low power Oscillator accuracy ranges
(between 0 °C–70 °C) follow:
■ 5 V Normal mode: –8% to + 16%
Document Number: 38-08035 Rev. *Q
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CY7C63310, CY7C638xx
Figure 7. Clock Block Diagram
CPUCLK
SEL
CLK_EXT
SCALE (divide by 2n,
n = 0-5,7)
CPU_CLK
MUX
CLK_24MHz
EXT
CLK_USB
MUX
24 MHz
SEL
SCALE
OUT
SCALE
SEL
12 MHz
12 MHz
EXT/2
EXT
0
0
1
1
X
X
0
1
LP OSC
32 KHz
CLK_32
KHz
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CY7C63310, CY7C638xx
programmable prescaler of 1, 2, 3, 4 then divides the selected
source.
Clock Architecture Description
The enCoRe II clock selection circuitry allows the selection of
independent clocks for the CPU, USB, Interval Timers and
Capture Timers.
The Timer Capture clock (TCAPCLK) is sourced from an external
clock, Internal 24 MHz Oscillator, or the Internal 32 kHz low
power oscillator.
The CPU clock CPUCLK is sourced from an external clock or the
Internal 24 MHz Oscillator. The selected clock source is
optionally divided by 2n, where n is 0-5,7 (see Table 34 on page
24).
The CLKOUT pin (P0.1) is driven from one of many sources. This
is used for test and is also used in some applications. The
sources that drive the CLKOUT follow:
USBCLK, which must be 12 MHz for the USB SIE to function
properly, is sourced by the Internal 24 MHz Oscillator or an
external 12 MHz/24 MHz clock. An optional divide by two allows
the use of 24 MHz source.
■ CLKIN after the optional EFTB filter
■ Internal 24 MHz Oscillator
■ Internal 32 kHz low power oscillator
■ CPUCLK after the programmable divider
The Interval Timer clock (ITMRCLK), is sourced from an external
clock, the Internal 24 MHz Oscillator, the Internal 32 kHz low
power oscillator, or from the timer capture clock (TCAPCLK). A
Table 31. IOSC Trim (IOSCTR) [0x34] [R/W]
Bit #
Field
7
6
foffset[2:0]
R/W
5
4
3
2
Gain[4:0]
R/W
1
0
Read/Write
Default
R/W
0
R/W
0
R/W
D
R/W
D
R/W
D
R/W
D
0
D
The IOSC Calibrate register calibrates the internal oscillator. The reset value is undefined but during boot the SROM writes a
calibration value that is determined during manufacturing test. This value does not require change during normal use. This is
the meaning of ‘D’ in the Default field.
Bit [7:5]: foffset [2:0]
This value is used to trim the frequency of the internal oscillator. These bits are not used in factory calibration and are zero.
Setting each of these bits causes the appropriate fine offset in oscillator frequency.
foffset bit 0 = 7.5 kHz
foffset bit 1 = 15 kHz
foffset bit 2 = 30 kHz
Bit [4:0]: Gain [4:0]
The effective frequency change of the offset input is controlled through the gain input. A lower value of the gain setting increases
the gain of the offset input. This value sets the size of each offset step for the internal oscillator. Nominal gain change
(kHz/offsetStep) at each bit, typical conditions (24 MHz operation):
Gain bit 0 = –1.5 kHz
Gain bit 1 = –3.0 kHz
Gain bit 2 = –6 kHz
Gain bit 3 = –12 kHz
Gain bit 4 = –24 kHz
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Table 32. LPOSC Trim (LPOSCTR) [0x36] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
32 kHz Low
Power
Reserved
32 kHz Bias Trim [1:0]
32 kHz Freq Trim [3:0]
Read/Write
Default
R/W
0
–
R/W
D
R/W
D
R/W
D
R/W
D
R/W
D
R/W
D
D
This register is used to calibrate the 32 kHz Low speed Oscillator. The reset value is undefined but during boot the SROM writes
a calibration value that is determined during manufacturing tests. This value does not require change during normal use. This
is the meaning of ‘D’ in the Default field. If the 32 kHz Low power bit is written, care must be taken to not disturb the
32 kHz Bias Trim and the 32 kHz Freq Trim fields from their factory calibrated values.
Bit 7: 32 kHz Low Power
0 = The 32 kHz Low speed Oscillator operates in normal mode
1 = The 32 kHz Low speed Oscillator operates in a low power mode. The oscillator continues to function normally, but with
reduced accuracy.
Bit 6: Reserved
Bit [5:4]: 32 kHz Bias Trim [1:0]
These bits control the bias current of the low power oscillator.
0 0 = Mid bias
0 1 = High bias
1 0 = Reserved
1 1 = Reserved
Note Do not program the 32 kHz Bias Trim [1:0] field with the reserved 10b value because the oscillator does not oscillate at all
corner conditions with this setting.
Bit [3:0]: 32 kHz Freq Trim [3:0]
These bits are used to trim the frequency of the low power oscillator.
Table 33. CPU/USB Clock Config (CPUCLKCR) [0x30] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Reserved
USB CLK/2
Disable
USB CLK Select
Reserved
CPUCLK Select
Read/Write
Default
–
0
R/W
0
R/W
0
–
0
–
0
–
0
–
0
R/W
0
Bit 7: Reserved
Bit 6: USB CLK/2 Disable
This bit only affects the USBCLK when the source is the external clock. When the USBCLK source is the Internal 24 MHz
Oscillator, the divide by two is always enabled
0 = USBCLK source is divided by two. This is the correct setting to use when the Internal 24 MHz Oscillator is used, or when
the external source is used with a 24 MHz clock
1 = USBCLK is undivided. Use this setting only with a 12 MHz external clock
Bit 5: USB CLK Select
This bit controls the clock source for the USB SIE.
0 = Internal 24 MHz Oscillator. With the presence of USB traffic, the Internal 24 MHz Oscillator is trimmed to meet the USB
requirement of 1.5% tolerance (see Table 35 on page 25)
1 = External clock—Internal Oscillator is not trimmed to USB traffic. Proper USB SIE operation requires a 12 MHz or 24 MHz
clock accurate to <1.5%.
Bit [4:1]: Reserved
Bit 0: CPU CLK Select
0 = Internal 24 MHz Oscillator.
1 = External clock—External clock at CLKIN (P0.0) pin.
Note The CPU speed selection is configured using the OSC_CR0 Register (Table 34 on page 24).
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Table 34. OSC Control 0 (OSC_CR0) [0x1E0] [R/W]
Bit #
Field
7
6
5
No Buzz
R/W
0
4
3
2
1
0
Reserved
Sleep Timer [1:0]
CPU Speed [2:0]
Read/Write
Default
–
0
–
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit [7:6]: Reserved
Bit 5: No Buzz
During sleep (the Sleep bit is set in the CPU_SCR Register—Table 38 on page 29), the LVD and POR detection circuit is turned
on periodically to detect any POR and LVD events on the VCC pin (the Sleep Duty Cycle bits in the ECO_TR are used to control
the duty cycle—Table 42 on page 34). To facilitate the detection of POR and LVD events, the No Buzz bit is used to force the
LVD and POR detection circuit to be continuously enabled during sleep. This results in a faster response to an LVD or POR
event during sleep at the expense of a slightly higher than average sleep current.
0 = The LVD and POR detection circuit is turned on periodically as configured in the Sleep Duty Cycle.
1 = The Sleep Duty Cycle value is overridden. The LVD and POR detection circuit is always enabled.
Note The periodic Sleep Duty Cycle enabling is independent with the sleep interval shown in the Sleep [1:0] bits below.
Bit [4:3]: Sleep Timer [1:0]
Note Sleep intervals are approximate.
Bit [2:0]: CPU Speed [2:0]
The enCoRe II may operate over a range of CPU clock speeds. The reset value for the CPU Speed bits is zero; as a result, the
default CPU speed is one-eighth of the internal 24 MHz, or 3 MHz
Regardless of the CPU Speed bit’s setting, if the actual CPU speed is greater than 12 MHz, the 24 MHz operating requirements
apply. An example of this scenario is a device that is configured to use an external clock, which supplies a frequency of 20 MHz.
If the CPU speed register’s value is 0b011, the CPU clock is at 20 MHz. Therefore, the supply voltage requirements for the device
are the same as if the part were operating at 24 MHz. The operating voltage requirements are not relaxed until the CPU speed
is at 12 MHz or less.
CPU Speed
[2:0]
CPU when Internal
Oscillator is selected External Clock
000
001
010
011
100
101
110
111
3 MHz (Default)
6 MHz
Clock In/8
Clock In/4
Clock In/2
Clock In/1
Clock In/16
Clock In/32
Clock In/128
Reserved
12 MHz
24 MHz
1.5 MHz
750 kHz
187 kHz
Reserved
Note Correct USB operations require the CPU clock speed be at least 1.5 MHz or not less than USB clock/8. If the two clocks
have the same source, then the CPU clock divider must not be set to divide by more than 8. If the two clocks have different
sources, the maximum ratio of USB Clock/CPU Clock must never exceed 8 across the full specification range of both clock
sources.
Note This register exists in the second bank of I/O space. This requires setting the XIO bit in the CPU flags register.
Document Number: 38-08035 Rev. *Q
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Table 35. USB Osclock Clock Configuration (OSCLCKCR) [0x39] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Reserved
Fine Tune USBOsclock
Only
R/W
0
Disable
R/W
0
Read/Write
Default
–
0
–
0
–
0
–
0
–
0
–
0
This register is used to trim the Internal 24 MHz Oscillator using received low speed USB packets as a timing reference. The
USB Osclock circuit is active when the Internal 24 MHz Oscillator provides the USB clock.
Bit [7:2]: Reserved
Bit 1: Fine Tune Only
0 = Fine and Course tuning
1 = Disable the oscillator lock from performing the coarse-tune portion of its retuning. The oscillator lock must be allowed to
perform a coarse tuning to tune the oscillator for correct USB SIE operation. After the oscillator is properly tuned, this bit is set
to reduce variance in the internal oscillator frequency that would be caused course tuning.
Bit 0: USB Osclock Disable
0 = Enable. With the presence of USB traffic, the Internal 24 MHz Oscillator precisely tunes to 24 MHz ± 1.5%
1 = Disable. The Internal 24 MHz Oscillator is not trimmed based on USB packets. This setting is useful when the internal
oscillator is not sourcing the USBSIE clock.
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Table 36. Timer Clock Config (TMRCLKCR) [0x31] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
TCAPCLK Divider
TCAPCLK Select
ITMRCLK Divider
ITMRCLK Select
Read/Write
Default
R/W
1
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
Bit [7:6]: TCAPCLK Divider [1:0]
TCAPCLK Divider controls the TCAPCLK divisor.
0 0 = Divider Value 2
0 1 = Divider Value 4
1 0 = Divider Value 6
1 1 = Divider Value 8
Bit [5:4]: TCAPCLK Select
The TCAPCLK Select field controls the source of the TCAPCLK.
0 0 = Internal 24 MHz Oscillator
0 1 = External clock—external clock at CLKIN (P0.0) input.
1 0 = Internal 32 kHz low power oscillator
1 1 = TCAPCLK Disabled
Note The 1024 s interval timer is based on the assumption that TCAPCLK is running at 4 MHz. Changes in TCAPCLK frequency
causes a corresponding change in the 1024 s interval timer frequency.
Bit [3:2]: ITMRCLK Divider
ITMRCLK Divider controls the ITMRCLK divisor.
0 0 = Divider value of 1
0 1 = Divider value of 2
1 0 = Divider value of 3
1 1 = Divider value of 4
Bit [1:0]: ITMRCLK Select
0 0 = Internal 24 MHz Oscillator
0 1 = External clock—external clock at CLKIN (P0.0) input.
1 0 = Internal 32 kHz low power oscillator
1 1 = TCAPCLK
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Interval Timer Clock (ITMRCLK)
PITIMER_Divider. The PITIMER_Source is the clock to the timer
and the PITMER_Divider is the value the clock is divided by.
The Interval Timer Clock (TITMRCLK), is sourced from an
external clock, the Internal 24 MHz Oscillator, the Internal 32 kHz
Low power Oscillator, or the Timer Capture clock.
The interval register (PITMR) holds the value that is loaded into
the PIT counter on terminal count. The PIT counter is a down
counter.
A
programmable prescaler of 1, 2, 3 or 4 then divides the selected
source. The 12-bit Programmable Interval Timer is a simple
down counter with a programmable reload value. It provides a
1 s resolution by default. When the down counter reaches zero,
the next clock is spent reloading. The reload value is read and
written while the counter is running, but the counter must not
unintentionally reload when the 12-bit reload value is only
partially stored, that is, between the two writes of the 12-bit value.
The programmable interval timer generates an interrupt to the
CPU on each reload.
The Programmable Interval Timer resolution is configurable. For
example:
TCAPCLK divide by x of CPU clock (for example, TCAPCLK
divide by 2 of a 24 MHz CPU clock gives a frequency of 12 MHz.)
ITMRCLK divide by x of TCAPCLK (for example, ITMRCLK
divide by 3 of TCAPCLK is 4 MHz so resolution is 0.25 s.)
Timer Capture Clock (TCAPCLK)
The parameters to be set show up on the device editor view of
PSoC Designer when the enCoRe II Timer User Module is
placed. The parameters are PITIMER_Source and
The Timer Capture clock is sourced from an external clock,
Internal 24 MHz Oscillator or the Internal 32 kHz Low power
Oscillator. A programmable pre-scaler of 2, 4, 6, or 8 then divides
the selected source.
Figure 8. Programmable Interval Timer Block Diagram
C onfiguration
12-bit
reload
value
System
Status and
C lock
C ontrol
12-bit
reload
counter
12-bit dow n
counter
Interrupt
C ontroller
C lock
Tim er
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CY7C63310, CY7C638xx
Figure 9. Timer Capture Block Diagram
System Clock
Configuration Status
and Control
Captimer Clock
16-bit counter
Prescale Mux
Capture Registers
1ms
Overflow
timer
Interrupt
Capture0 Int
Capture1 Int
Interrupt Controller
Table 37. Clock IO Config (CLKIOCR) [0x32] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Reserved
CLKOUT Select
R/W R/W
Read/Write
Default
–
0
–
0
–
0
-
-
-
0
0
0
0
0
Bit [7:2]: Reserved
Bit [1:0]: CLKOUT Select
0 0 = Internal 24 MHz Oscillator
0 1 = External clock – external clock at CLKIN (P0.0)
1 0 = Internal 32 kHz low power oscillator
1 1 = CPUCLK
CPU Clock During Sleep Mode
When the CPU enters sleep mode the CPUCLK Select (Bit [0], Table 33 on page 23) is forced to the Internal Oscillator, and the
oscillator is stopped. When the CPU comes out of sleep mode it runs on the internal oscillator. The internal oscillator recovery time is
three clock cycles of the Internal 32 kHz Low power Oscillator.
If the system requires the CPU to run off the external clock after awaking from sleep mode, the firmware must switch the clock source
for the CPU.
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Reset
The microcontroller supports two types of resets: Power on Reset (POR) and Watchdog Reset (WDR). When reset is initiated, all
registers are restored to their default states and all interrupts are disabled.
The occurrence of a reset is recorded in the System Status and Control Register (CPU_SCR). Bits within this register record the
occurrence of POR and WDR Reset respectively. The firmware interrogates these bits to determine the cause of a reset.
The microcontroller resumes execution from flash address 0x0000 after a reset. The internal clocking mode is active after a reset,
until changed by the user firmware.
Note The CPU clock defaults to 3 MHz (Internal 24 MHz Oscillator divide-by-8 mode) at POR to guarantee operations at the low VCC
that may be present during the supply ramp.
Table 38. System Status and Control Register (CPU_SCR) [0xFF] [R/W]
Bit #
Field
7
GIES
R
6
5
4
3
Sleep
R/W
0
2
1
0
Reserved
WDRS
PORS
Reserved
Stop
R/W
0
[4]
[4]
Read/Write
Default
–
0
R/C
R/C
–
0
–
0
0
0
1
The bits of the CPU_SCR register are used to convey status and control of events for various functions of an enCoRe II device.
Bit 7: GIES
The Global Interrupt Enable Status bit is a read only status bit and its use is discouraged. The GIES bit is a legacy bit, which
was used to provide the ability to read the GIE bit of the CPU_F register. However, the CPU_F register is now readable. When
this bit is set, it indicates that the GIE bit in the CPU_F register is also set which, in turn, indicates that the microprocessor
services interrupts.
0 = Global interrupts disabled
1 = Global interrupt enabled
Bit 6: Reserved
Bit 5: WDRS
The WDRS bit is set by the CPU to indicate that a WDR event has occurred. The user can read this bit to determine the type of
reset that has occurred. The user can clear but not set this bit.
0 = No WDR
1 = A WDR event has occurred
Bit 4: PORS
The PORS bit is set by the CPU to indicate that a POR event has occurred. The user can read this bit to determine the type of
reset that has occurred. The user can clear but not set this bit
0 = No POR
1 = A POR event has occurred. (Note WDR events do not occur until this bit is cleared)
Bit 3: SLEEP
Set by the user to enable CPU sleep state. CPU remains in sleep mode until any interrupt is pending. The Sleep bit is covered
in more detail in the section Sleep Mode on page 30.
0 = Normal operation
1 = Sleep
Bit [2:1]: Reserved
Bit 0: STOP
This bit is set by the user to halt the CPU. The CPU remains halted until a reset (WDR, POR, or external reset) has taken place.
If an application wants to stop code execution until a reset, the preferred method is to use the HALT instruction rather than writing
to this bit.
0 = Normal CPU operation
1 = CPU is halted (not recommended)
Note
4. C = Clear. This bit is cleared only by the user and cannot be set by firmware.
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The sleep timer is used to generate the sleep time period and the
Watchdog time period. The sleep timer uses the Internal 32 kHz
Low power Oscillator system clock to produce the sleep time
period. The user can program the sleep time period using the
Sleep Timer bits of the OSC_CR0 Register (Table 34 on page
24). When the sleep time elapses (sleep timer overflows), an
interrupt to the Sleep Timer Interrupt Vector is generated.
Power on Reset
POR occurs every time the power to the device is switched on.
POR is released when the supply is typically 2.6 V for the upward
supply transition, with typically 50 mV of hysteresis during the
power on transient. Bit 4 of the System Status and Control
Register (CPU_SCR) is set to record this event (the register
contents are set to 00010000 by the POR). After a POR, the
microprocessor is held off for approximately 20 ms for the VCC
supply to stabilize before executing the first instruction at
address 0x00 in the flash. If the VCC voltage drops below the
POR downward supply trip point, POR is reasserted. The VCC
supply must ramp linearly from 0 to 4V in less than 200 ms.
The Watchdog Timer period is automatically set to be three
counts of the Sleep Timer overflow. This represents between two
and three sleep intervals depending on the count in the Sleep
Timer at the previous WDT clear. When this timer reaches three,
a WDR is generated.
The user can either clear the WDT, or the WDT and the Sleep
Timer. When the user writes to the Reset WDT Register
(RES_WDT), the WDT is cleared. If the data that is written is the
hex value 0x38, the Sleep Timer is also cleared at the same time.
Note The PORS status bit is set at POR and is cleared only by
the user. It cannot be set by firmware.
Watchdog Timer Reset
The user has the option to enable the WDT. The WDT is enabled
by clearing the PORS bit. After the PORS bit is cleared, the WDT
cannot be disabled. The only exception to this is if a POR event
takes place, which disables the WDT.
Table 39. Reset Watchdog Timer (RESWDT) [0xE3] [W]
Bit #
Field
7
6
5
4
3
2
1
0
Reset Watchdog Timer [7:0]
Read/Write
Default
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Any write to this register clears Watchdog Timer; a write of 0x38 also clears the Sleep Timer.
Bit [7:0]: Reset Watchdog Timer [7:0]
When the CPU enters sleep mode the CPUCLK Select (Bit 1,
Table 33 on page 23) is forced to the Internal Oscillator. The
internal oscillator recovery time is three clock cycles of the
Internal 32 kHz Low power Oscillator. The Internal 24 MHz
Oscillator restarts immediately on exiting Sleep mode. If an
external clock is used, firmware switches the clock source for the
CPU.
Sleep Mode
The CPU is put to sleep only by the firmware. This is
accomplished by setting the Sleep bit in the System Status and
Control Register (CPU_SCR). This stops the CPU from
executing instructions, and the CPU remains asleep until an
interrupt comes pending, or there is a reset event (either a Power
on Reset, or a Watchdog Timer Reset).
On exiting sleep mode, after the clock is stable and the delay
time has expired, the instruction immediately following the sleep
instruction is executed before the interrupt service routine (if
enabled).
The Low Voltage Detection circuit (LVD) drops into fully
functional power reduced states, and the latency for the LVD is
increased. The actual latency is traded against power
consumption by changing Sleep Duty Cycle field of the ECO_TR
Register.
The Sleep interrupt allows the microcontroller to wake up
periodically and poll system components while maintaining very
low average power consumption. The Sleep interrupt may also
be used to provide periodic interrupts during non-sleep modes.
The Internal 32 kHz Low speed Oscillator remains running.
Before entering the suspend mode, the firmware can optionally
configure the 32 kHz Low speed Oscillator to operate in a low
power mode to help reduce the over all power consumption
(Using Bit 7, Table 32 on page 23). This helps save
approximately 5 A; however, the trade off is that the 32 kHz Low
speed Oscillator is less accurate.
All interrupts remain active. Only the occurrence of an interrupt
wakes the part from sleep. The Stop bit in the System Status and
Control Register (CPU_SCR) must be cleared for a part to
resume out of sleep. The Global Interrupt Enable bit of the CPU
Flags Register (CPU_F) does not have any effect. Any
unmasked interrupt wakes the system up. As a result, any
interrupts not intended for waking must be disabled through the
Interrupt Mask Registers.
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edge of the CPU clock. The sleep logic waits for the following
negative edge of the CPU clock and then asserts a system
wide Power Down (PD) signal. In Figure 10 on page 31 the
CPU is halted and the system wide power down signal is
asserted.
Sleep Sequence
The SLEEP bit is an input into the sleep logic circuit. This circuit
is designed to sequence the device into and out of the hardware
sleep state. The hardware sequence to put the device to sleep
is shown in Figure 10 and is defined as follows.
3. The system wide PD (power down) signal controls several
major circuit blocks: The flash memory module, the internal
24 MHz oscillator, the EFTB filter and the bandgap voltage
reference. These circuits transition into a zero power state.
The only operational circuits on chip are the Low Power
oscillator, the bandgap refresh circuit, and the supply voltage.
monitor. (POR/LVD) circuit.
1. Firmware sets the SLEEP bit in the CPU_SCR0 register. The
Bus Request (BRQ) signal to the CPU is immediately
asserted. This is a request by the system to halt CPU
operation at an instruction boundary. The CPU samples BRQ
on the positive edge of CPUCLK.
2. Due to the specific timing of the register write, the CPU issues
a Bus Request Acknowledge (BRA) on the following positive
Figure 10. Sleep Timing
On the falling edge of CPUCLK,
PD is asserted. The 24/48 MHz
system clock is halted; the Flash
and bandgap are powered down
CPU
responds with
a BRA
Firmware write to SCR
SLEEP bit causes an
immediate BRQ
CPU captures BRQ
on next CPUCLK
edge
CPUCLK
IOW
SLEEP
BRQ
BRA
PD
3. At the following positive edge of the 32 kHz clock, the current
values for the precision POR and LVD have settled and are
sampled.
Wake up Sequence
Once asleep, the only event that can wake the system up is an
interrupt. The global interrupt enable of the CPU flag register is
not required to be set. Any unmasked interrupt wakes the system
up. It is optional for the CPU to actually take the interrupt after
the wake up sequence. The wake up sequence is synchronized
to the 32 kHz clock for purposes of sequencing a startup delay,
to allow the flash memory module enough time to power up
before the CPU asserts the first read access. Another reason for
the delay is to allow the oscillator, Bandgap, and LVD/POR
circuits time to settle before actually being used in the system.
As shown in Figure 11 on page 32, the wake up sequence is as
follows:
4. At the following negative edge of the 32 kHz clock (after about
15 µS nominal), the BRQ signal is negated by the sleep logic
circuit. On the following CPUCLK, BRA is negated by the CPU
and instruction execution resumes. Note that in Figure 11 on
page 32 fixed function blocks, such as flash, internal oscillator,
EFTB, and bandgap, have about 15 µSec start up. The
wakeup times (interrupt to CPU operational) range from 75
µS to 105 µS.
1. The wake up interrupt occurs and is synchronized by the neg-
ative edge of the 32 kHz clock.
2. At the following positive edge of the 32 kHz clock, the system
wide PD signal is negated. The flash memory module, internal
oscillator, EFTB, and bandgap circuit are all powered up to a
normal operating state.
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The following steps are user configurable and help in reducing
the average suspend mode power consumption.
Low Power in Sleep Mode
To achieve the lowest possible power consumption during
suspend or sleep, the following conditions must be observed in
addition to considerations for the sleep timer:
1. Configure the power supply monitor at a large regular inter-
vals, control register bits are 1,EB[7:6] (Power system sleep
duty cycle PSSDC[1:0]).
1. All GPIOs must be set to outputs and driven low.
2. Configure the Low power oscillator into low power mode,
control register bit is LOPSCTR[7].
2. Clear P11CR[0], P10CR[0] - during USB and Non-USB
operations
For low power considerations during sleep when external clock
is used as the CPUCLK source, the clock source must be held
low to avoid unintentional leakage current. If the clock is held
high, then there may be a leakage through M8C. To avoid current
consumption make sure ITMRCLK, TCPCLK, and USBCLK are
not sourced by either low power 32 kHz oscillator or 24 MHz
crystal-less oscillator. Do not select 24 MHz or 32 kHz oscillator
clocks on to the P01_CLKOUT/P12_VREG pin.
3. Clear the USB Enable USBCR[7] - during USB mode
operations
4. Set P10CR[1] - during non-USB mode operations
5. Make sure 32 kHz oscillator clock is not selected as clock
source to ITMRCLK, TCAPCLK. Not even as clock output
source, onto either P01_CLKOUT or P12_VREG pins.
All the other blocks go to the power down mode automatically on
suspend.
Note In case of a self powered designs, particularly battery
power, the USB suspend current specifications may not be met
because the USB pins are expecting termination.
Figure 11. Wake Up Timing
Interrupt is double sampled by
32K clock and PD is negated to
system
CPU is restarted after
90ms (nominal)
Sleep Timer or GPIO
interrupt occurs
CLK32K
INT
SLEEP
PD
BANDGAP
LVD PPOR
ENABLE
SAMPLE
SAMPLE LVD/
POR
CPUCLK/
24MHz
(Not to Scale)
BRQ
BRA
CPU
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Low Voltage Detect Control
Table 40. Low Voltage Control Register (LVDCR) [0x1E3] [R/W]
Bit #
Field
7
6
5
4
3
2
1
VM[2:0]
R/W
0
0
Reserved
PORLEV[1:0]
Reserved
Read/Write
Default
–
0
–
0
R/W
0
R/W
0
–
0
R/W
0
R/W
0
This register controls the configuration of the Power on Reset/Low voltage Detection block.
Note This register exists in the second bank of IO space. This requires setting the XIO bit in the CPU flags register.
Bit [7:6]: Reserved
Bit [5:4]: PORLEV[1:0]
This field controls the level below which the precision power on reset (PPOR) detector generates a reset.
0 0 = 2.7V Range (trip near 2.6V)
0 1 = 3V Range (trip near 2.9V)
1 0 = 5V Range, >4.75V (trip near 4.65V). This setting must be used when operating the CPU above 12 MHz.
1 1 = PPOR does not generate a reset, but values read from the Voltage Monitor Comparators Register (Table 41) give the internal
PPOR comparator state with trip point set to the 3V range setting.
Bit 3: Reserved
Bit [2:0]: VM[2:0]
LVD Trip
LVD Trip
LVD Trip
VM[2:0]
000
Point (V) Min Point (V) Typ Point (V) Max
Reserved
Reserved
Reserved
Reserved
4.439
Reserved
Reserved
Reserved
Reserved
4.48
Reserved
Reserved
Reserved
Reserved
4.528
001
010
011
100
101
110
111
4.597
4.64
4.689
4.680
4.73
4.774
4.766
4.82
4.862
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CY7C63310, CY7C638xx
Table 41. Voltage Monitor Comparators Register (VLTCMP) [0x1E4] [R]
Bit #
Field
7
6
5
4
3
2
1
LVD
R
0
PPOR
R
Reserved
Read/Write
Default
–
0
–
0
–
0
–
0
–
0
–
0
0
0
This read only register allows reading the current state of the Low-Voltage-Detection and Precision-Power-On-Reset compar-
ators
Bit [7:2]: Reserved
Bit 1: LVD
This bit is set to indicate that the low-voltage-detect comparator has tripped, indicating that the supply voltage has gone below
the trip point set by VM[2:0] (See Table 40)
0 = No low-voltage-detect event
1 = A low-voltage-detect has tripped
Bit 0: PPOR
This bit is set to indicate that the precision-power-on-reset comparator has tripped, indicating that the supply voltage is below
the trip point set by PORLEV[1:0]
0 = No precision-power-on-reset event
1 = A precision-power-on-reset event has occurred
Note This register exists in the second bank of I/O space. This requires setting the XIO bit in the CPU flags register.
ECO Trim Register
Table 42. ECO (ECO_TR) [0x1EB] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Sleep Duty Cycle [1:0]
Reserved
Read/Write
Default
R/W
0
R/W
0
–
0
–
0
–
0
–
0
–
0
–
0
This register controls the ratios (in numbers of 32 kHz clock periods) of “on” time versus “off” time for LVD and POR detection
circuit.
Bit [7:6]: Sleep Duty Cycle [1:0]
0 0 = 1/128 periods of the Internal 32 kHz Low-speed Oscillator
0 1 = 1/512 periods of the Internal 32 kHz Low-speed Oscillator
1 0 = 1/32 periods of the Internal 32 kHz Low-speed Oscillator
1 1 = 1/8 periods of the Internal 32 kHz Low-speed Oscillator
Note This register exists in the second bank of I/O space. This requires setting the XIO bit in the CPU flags register.
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CY7C63310, CY7C638xx
General Purpose I/O (GPIO) Ports
Port Data Registers
Table 43. P0 Data Register (P0DATA)[0x00] [R/W]
Bit #
Field
7
6
P0.6/TIO1
R/W
5
P0.5/TIO0
R/W
4
P0.4/INT2
R/W
3
P0.3/INT1
R/W
2
P0.2/INT0
R/W
1
0
P0.0/CLKIN
R/W
P0.7
R/W
0
P0.1/CLKOUT
Read/Write
Default
R/W
0
0
0
0
0
0
0
This register contains the data for Port 0. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 0 pins.
Bit 7: P0.7 Data
P0.7 only exists in the CY7C638xx
Bit [6:5]: P0.6–P0.5 Data/TIO1 and TIO0
Besides their use as the P0.6–P0.5 GPIOs, these pins are also used for the alternate functions as the Capture Timer input or
Timer output pins (TIO1 and TIO0). To configure the P0.5 and P0.6 pins, refer to the P0.5/TIO0–P0.6/TIO1 Configuration Register
(Table 50 on page 39).
The use of the pins as the P0.6–P0.5 GPIOs and the alternate functions exist in all the enCoRe II parts.
Bit [4:2]: P0.4–P0.2 Data/INT2 – INT0
Besides their use as the P0.4–P0.2 GPIOs, these pins are also used for the alternate functions as the Interrupt pins (INT0–INT2).
To configure the P0.4–P0.2 pins, refer to the P0.2/INT0–P0.4/INT2 Configuration Register (Table 49 on page 39).
The use of the pins as the P0.4–P0.2 GPIOs and the alternate functions exist in all the enCoRe II parts.
Bit 1: P0.1/CLKOUT
Besides its use as the P0.1 GPIO, this pin is also used for an alternate function as the CLK OUT pin. To configure the P0.1 pin,
refer to the P0.1/CLKOUT Configuration Register (Table 48 on page 38).
Bit 0: P0.0/CLKIN
Besides its use as the P0.0 GPIO, this pin is also used for an alternate function as the CLKIN pin. To configure the P0.0 pin,
refer to the P0.0/CLKIN Configuration Register (Table 47 on page 38).
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Table 44. P1 Data Register (P1DATA) [0x01] [R/W]
Bit #
Field
7
6
5
4
P1.4/SCLK
R/W
3
P1.3/SSEL
R/W
2
P1.2/VREG
R/W
1
P1.1/D–
R/W
0
0
P1.0/D+
R/W
0
P1.7
R/W
0
P1.6/SMISO
P1.5/SMOSI
Read/Write
Default
R/W
0
R/W
0
0
0
0
This register contains the data for Port 1. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 1 pins.
Bit 7: P1.7 Data
P1.7 only exists in the CY7C638xx.
Bit [6:3]: P1.6–P1.3 Data/SPI Pins (SMISO, SMOSI, SCLK, SSEL)
Besides their use as the P1.6–P1.3 GPIOs, these pins are also used for the alternate function as the SPI interface pins. To
configure the P1.6–P1.3 pins, refer to the P1.3–P1.6 Configuration Register (Table 55 on page 41).
The use of the pins as the P1.6–P1.3 GPIOs and the alternate functions exist in all the enCoRe II parts.
Bit 2: P1.2/VREG
On the CY7C638x3, this pin is used as the P1.2 GPIO or the VREG output. If the VREG output is enabled (Bit 0
Table 87 on page 61 is set), a 3.3V source is placed on the pin and the GPIO function of the pin is disabled.
The VREG functionality is not present in the CY7C63310 and the CY7C63801 variants. A 1 F min, 2 F max capacitor is
required on VREG output.
Bit [1:0]: P1.1–P1.0/D– and D+
When the USB mode is disabled (Bit 7 in Table 88 on page 62 is clear), the P1.1 and P1.0 bits are used to control the state of
the P1.0 and P1.1 pins. When the USB mode is enabled, the P1.1 and P1.0 pins are used as the D– and D+ pins respectively.
If the USB Force State bit (Bit 0 in Table 87) is set, the state of the D– and D+ pins are controlled by writing to the D– and D+ bits.
Table 45. P2 Data Register (P2DATA) [0x02] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Reserved
P2.1–P2.0
Read/Write
Default
-
-
-
-
-
-
R/W
0
R/W
0
0
0
0
0
0
0
This register contains the data for Port 2. Writing to this register sets the bit values to output on output enabled pins. Reading
from this register returns the current state of the Port 2 pins.
Bit [7:2]: Reserved Data [7:2]
Bit [1:0]: P2 Data [1:0]
P2.1–P2.0 only exist in the CY7C638(2/3)3.
Table 46. P3 Data Register (P3DATA) [0x03] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Reserved
P3.1–P3.0
Read/Write
Default
–
0
–
0
–
0
–
0
–
0
–
0
R/W
0
R/W
0
This register contains the data for Port 3. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 3 pins.
Bit [7:2]: Reserved Data [7:2]
Bit [1:0]: P3 Data [1:0]
P3.1–P3.0 only exist in the CY7C638(2/3)3.
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CY7C63310, CY7C638xx
Open Drain
GPIO Port Configuration
When set, the output on the pin is determined by the Port Data
Register. If the corresponding bit in the Port Data Register is set,
the pin is in high impedance state. If the corresponding bit in the
Port Data Register is clear, the pin is driven low.
All the GPIO configuration registers have common configuration
controls. The following are the bit definitions of the GPIO
configuration registers.
Int Enable
When clear, the output is driven LOW or HIGH.
When set, the Int Enable bit allows the GPIO to generate
interrupts. Interrupt generate can occur regardless of whether
the pin is configured for input or output. All interrupts are edge
sensitive; however for any interrupt that is shared by multiple
sources (that is, Ports 2, 3, and 4) all inputs must be deasserted
before a new interrupt can occur.
Pull-up Enable
When set the pin has a 7 K pull-up to VCC (or VREG for ports
with V3.3 enabled).
When clear, the pull-up is disabled.
When clear, the corresponding interrupt is disabled on the pin.
Output Enable
It is possible to configure GPIOs as outputs, enable the interrupt
on the pin and then generate the interrupt by driving the
appropriate pin state. This is useful in tests and may have value
in applications.
When set, the output driver of the pin is enabled.
When clear, the output driver of the pin is disabled.
For pins with shared functions there are some special cases.
VREG Output/SPI Use
Int Act Low
The P1.2(VREG), P1.3(SSEL), P1.4(SCLK), P1.5(SMOSI) and
P1.6(SMISO) pins are used for their dedicated functions or for
GPIO.
When set, the corresponding interrupt is active on the falling
edge.
When clear, the corresponding interrupt is active on the rising
edge.
To enable the pin for GPIO, clear the corresponding VREG
Output or SPI Use bit. The SPI function controls the output
enable for its dedicated function pins when their GPIO enable bit
is clear. The VREG output is not available on the CY7C63801
and CY7C63310.
TTL Thresh
When set, the input has TTL threshold. When clear, the input has
standard CMOS threshold.
3.3 V Drive
High Sink
The P1.3(SSEL), P1.4(SCLK), P1.5(SMOSI) and P1.6(SMISO)
pins have an alternate voltage source from the voltage regulator.
If the 3.3 V Drive bit is set a high level is driven from the voltage
When set, the output can sink up to 50 mA.
When clear, the output can sink up to 8 mA.
regulator instead of from VCC
.
Only the P1.7–P1.3 have 50 mA sink drive capability. Other pins
have 8 mA sink drive capability.
Setting the 3.3 V Drive bit does not enable the voltage regulator.
That must be done explicitly by setting the VREG Enable bit in
the VREGCR Register (Table 87 on page 61).
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CY7C63310, CY7C638xx
Figure 12. Block Diagram of a GPIO
VCC
VREG
3.3V Drive
Pull-Up Enable
Output Enable
VCC
VREG
RUP
Data Out
Open Drain
Port Data
GPIO
PIN
High Sink
VCC GND
VREG GND
Data In
TTL Threshold
Table 47. P0.0/CLKIN Configuration (P00CR) [0x05] [R/W]
Bit #
Field
7
6
Int Enable
R/W
5
Int Act Low
R/W
4
TTL Thresh
R/W
3
2
Open Drain
R/W
1
0
Reserved
Reserved
Pull-up Enable
Output Enable
Read/Write
Default
–
0
–
0
R/W
0
R/W
0
0
0
0
0
This pin is shared between the P0.0 GPIO use and the CLKIN pin for an external clock. When the external clock input is enabled
(Bit[0] in register CPUCLKCR Table 33 on page 23) the settings of this register are ignored.
The use of the pin as the P0.0 GPIO is available in all the enCoRe II parts.
Table 48. P0.1/CLKOUT Configuration (P01CR) [0x06] R/W]
Bit #
Field
7
CLK Output
R/W
6
Int Enable
R/W
5
Int Act Low
R/W
4
TTL Thresh
R/W
3
2
Open Drain
R/W
1
0
Reserved
Pull-up Enable
Output Enable
Read/Write
Default
–
0
R/W
0
R/W
0
0
0
0
0
0
This pin is shared between the P0.1 GPIO use and the CLKOUT pin. When CLK output is set, the internally selected clock is
sent out onto P0.1CLKOUT pin.
The use of the pin as the P0.1 GPIO is available in all the enCoRe II parts.
Bit 7: CLK Output
0 = The clock output is disabled.
1 = The clock selected by the CLK Select field (Bit [1:0] of the CLKIOCR Register (Table 37 on page 28) is driven out to the pin.
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CY7C63310, CY7C638xx
Table 49. P0.2/INT0–P0.4/INT2 Configuration (P02CR–P04CR) [0x07–0x09] [R/W]
Bit #
Field
7
6
5
Int Act Low
R/W
4
TTL Thresh
R/W
3
2
Open Drain
R/W
1
0
Reserved
Reserved
Pull-up Enable
Output Enable
Read/Write
Default
–
0
–
0
–
0
R/W
0
R/W
0
0
0
0
These registers control the operation of pins P0.2–P0.4 respectively. The pins are shared between the P0.2–P0.4 GPIOs and
the INT0–INT2. These registers exist in all enCoRe II parts. The INT0–INT2 interrupts are different from all the other GPIO
interrupts. These pins are connected directly to the interrupt controller to provide three edge sensitive interrupts with independent
interrupt vectors. These interrupts occur on a rising edge when Int act Low is clear and on a falling edge when Int act Low is set.
The pins are enabled as interrupt sources in the interrupt controller registers (Table 84 on page 59 and Table 82 on page 57).
To use these pins as interrupt inputs, configure them as inputs by clearing the corresponding Output Enable. If the INT0–INT2
pins are configured as outputs with interrupts enabled, firmware can generate an interrupt by writing the appropriate value to the
P0.2, P0.3 and P0.4 data bits in the P0 Data Register.
Regardless of whether the pins are used as Interrupt or GPIO pins the Int Enable, Int act Low, TTL Threshold, Open Drain, and
Pull-up Enable bits control the behavior of the pin.
The P0.2/INT0–P0.4/INT2 pins are individually configured with the P02CR (0x07), P03CR (0x08), and P04CR (0x09) respec-
tively.
Note Changing the state of the Int Act Low bit can cause an unintentional interrupt to be generated. When configuring these
interrupt sources, it is best to follow the following procedure:
1. Disable interrupt source
2. Configure interrupt source
3. Clear any pending interrupts from the source
4. Enable interrupt source
Table 50. P0.5/TIO0 – P0.6/TIO1 Configuration (P05CR–P06CR) [0x0A–0x0B] [R/W]
Bit #
Field
7
6
Int Enable
R/W
5
Int Act Low
R/W
4
TTL Thresh
R/W
3
2
Open Drain
R/W
1
0
TIO Output
Reserved
Pull-up Enable
Output Enable
Read/Write
Default
–
0
–
0
R/W
0
R/W
0
0
0
0
0
These registers control the operation of pins P0.5 through P0.6, respectively. These registers exist in all enCoRe II parts.
P0.5 and P0.6 are shared with TIO0 and TIO1, respectively. To use these pins as Capture Timer inputs, configure them as inputs
by clearing the corresponding Output Enable. To use TIO0 and TIO1 as Timer outputs, set the TIOx Output and Output Enable
bits. If these pins are configured as outputs and the TIO Output bit is clear, firmware can control the TIO0 and TIO1 inputs by
writing the value to the P0.5 and P0.6 data bits in the P0 Data Register.
Regardless of whether either pin is used as a TIO or GPIO pin the Int Enable, Int act Low, TTL Threshold, Open Drain, and
Pull-up Enable control the behavior of the pin.
TIO0(P0.5) when enabled outputs a positive pulse from the Free Running Timer. This is the same signal that is used internally
to generate the 1024 s timer interrupt. This signal is not gated by the interrupt enable state. The pulse is active for one cycle
of the capture timer clock.
TIO1(P0.6) when enabled outputs a positive pulse from the programmable interval timer. This is the same signal that is used
internally to generate the programmable timer interval interrupt. This signal is not gated by the interrupt enable state. The pulse
is active for one cycle of the interval timer clock.
The P0.5/TIO0 and P0.6/TIO1 pins are individually configured with the P05CR (0x0A) and P06CR (0x0B), respectively.
Document Number: 38-08035 Rev. *Q
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CY7C63310, CY7C638xx
Table 51. P0.7 Configuration (P07CR) [0x0C] [R/W]
Bit #
Field
7
6
Int Enable
R/W
5
Int Act Low
R/W
4
TTL Thresh
R/W
3
2
Open Drain
R/W
1
0
Reserved
Reserved
Pull-up Enable
Output Enable
Read/Write
Default
–
0
–
0
R/W
0
R/W
0
0
0
0
0
This register controls the operation of pin P0.7. The P0.7 pin only exists in the CY7C638(1/2/3)3.
Table 52. P1.0/D+ Configuration (P10CR) [0x0D] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Reserved
Int Enable
Int Act Low
Reserved
PS/2 Pull-up
Enable
Output Enable
Read/Write
Default
R/W
0
R/W
0
R/W
0
–
0
–
0
–
0
R/W
0
R/W
0
This register controls the operation of the P1.0 (D+) pin when the USB interface is not enabled, allowing the pin to be used as
a PS2 interface or a GPIO. See Table 88 on page 62 for information on enabling the USB. When the USB is enabled, none of
the controls in this register have any affect on the P1.0 pin.
Note The P1.0 is an open drain only output. It can actively drive a signal low, but cannot actively drive a signal high.
Bit 1: PS/2 Pull-up Enable
0 = Disable the 5K ohm pull-up resistors
1 = Enable 5K ohm pull-up resistors for both P1.0 and P1.1. Enable the use of the P1.0 (D+) and P1.1 (D–) pins as a PS2 style
interface.
Table 53. P1.1/D– Configuration (P11CR) [0x0E] [R/W]
Bit #
Field
7
6
Int Enable
R/W
5
Int Act Low
R/W
4
3
2
Open Drain
R/W
1
0
Reserved
Reserved
Reserved
Output Enable
Read/Write
Default
–
0
–
0
–
0
–
0
R/W
0
0
0
0
This register controls the operation of the P1.1 (D–) pin when the USB interface is not enabled, allowing the pin to be used as
a PS2 interface or a GPIO. See Table 88 on page 62 for information on enabling USB. When USB is enabled, none of the controls
in this register have any affect on the P1.1 pin. When USB is disabled, the 5K ohm pull-up resistor on this pin may be enabled
by the PS/2 Pull-up Enable bit of the P10CR Register (Table 52)
Note There is no 2 mA sourcing capability on this pin. The pin can only sink 5 mA at VOL3 (See section DC Characteristics on
page 73)
Table 54. P1.2 Configuration (P12CR) [0x0F] [R/W]
Bit #
Field
7
CLK Output
R/W
6
Int Enable
R/W
5
Int Act Low
R/W
4
3
2
Open Drain
R/W
1
0
TTL Threshold
Reserved
Pull-up Enable
Output Enable
Read/Write
Default
R/W
0
–
0
R/W
0
R/W
0
0
0
0
0
This register controls the operation of the P1.2.
Bit 7: CLK Output
0 = The internally selected clock is not sent out onto P1.2 pin
1 = When CLK Output is set, the internally selected clock is sent out onto P1.2 pin
Note:Table 37, “Clock IO Config (CLKIOCR) [0x32] [R/W],” on page 28 is used to select the external or internal clock in enCoRe
II devices
Document Number: 38-08035 Rev. *Q
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CY7C63310, CY7C638xx
Table 55. P1.3 Configuration (P13CR) [0x10] [R/W]
Bit #
Field
7
6
Int Enable
R/W
5
Int Act Low
R/W
4
3.3V Drive
R/W
3
High Sink
R/W
2
Open Drain
R/W
1
0
Reserved
Pull-up Enable
Output Enable
Read/Write
Default
–
0
R/W
0
R/W
0
0
0
0
0
0
This register controls the operation of the P1.3 pin. This register exists in all enCoRe II parts.
The P1.3 GPIO’s threshold is always set to TTL.
When the SPI hardware is enabled or disabled, the pin is controlled by the Output Enable bit and the corresponding bit in the
P1 data register.
Regardless of whether the pin is used as an SPI or GPIO pin the Int Enable, Int act Low, 3.3V Drive, High Sink, Open Drain, and
Pull-up Enable control the behavior of the pin.
Table 56. P1.4–P1.6 Configuration (P14CR–P16CR) [0x11–0x13] [R/W]
Bit #
Field
7
SPI Use
R/W
0
6
Int Enable
R/W
5
Int Act Low
R/W
4
3.3V Drive
R/W
3
High Sink
R/W
2
Open Drain
R/W
1
0
Pull-up Enable
Output Enable
Read/Write
Default
R/W
0
R/W
0
0
0
0
0
0
These registers control the operation of pins P1.4–P1.6, respectively. These registers exist in all enCoRe II parts.
Bit 7: SPI Use
0 = Disable the SPI alternate function. The pin is used as a GPIO
1 = Enable the SPI function. The SPI circuitry controls the output of the pin
The P1.4–P1.6 GPIO’s threshold is always set to TTL.
When the SPI hardware is enabled, pins that are configured as SPI Use have their output enable and output state controlled by
the SPI circuitry. When the SPI hardware is disabled or a pin has its SPI Use bit clear, the pin is controlled by the Output Enable
bit and the corresponding bit in the P1 data register.
Regardless of whether any pin is used as an SPI or GPIO pin the Int Enable, Int act Low, 3.3V Drive, High Sink, Open Drain,
and Pull-up Enable control the behavior of the pin.
Note for Comm Modes 01 or 10 (SPI Master or SPI Slave, see Table 61 on page 43)
When configured for SPI (SPI Use = 1 and Comm Modes [1:0] = SPI Master or SPI Slave mode), the input and output direction
of pins P1.5, and P1.6 is set automatically by the SPI logic. However, pin P1.4's input and output direction is NOT automatically
set; it must be explicitly set by firmware. For SPI Master mode, pin P1.4 must be configured as an output; for SPI Slave mode,
pin P1.4 must be configured as an input.
Table 57. P1.7 Configuration (P17CR) [0x14] [R/W]
Bit #
Field
7
6
Int Enable
R/W
5
Int Act Low
R/W
4
3
High Sink
R/W
2
Open Drain
R/W
1
0
Reserved
Reserved
Pull-up Enable
Output Enable
Read/Write
Default
–
0
–
0
R/W
1
R/W
0
0
0
0
0
This register controls the operation of pin P1.7. This register only exists in CY7C638(1/2/3)3. The P1.7 GPIO’s threshold is
always set to TTL.
Table 58. P2 Configuration (P2CR) [0x15] [R/W]
Bit #
Field
7
6
Int Enable
R/W
5
Int Act Low
R/W
4
TTL Thresh
R/W
3
2
Open Drain
R/W
1
0
Reserved
Reserved
Pull-up Enable
Output Enable
Read/Write
Default
–
0
–
0
R/W
0
R/W
0
0
0
0
0
This register only exists in CY7C638(2/3)3. This register controls the operation of pins P2.0–P2.1.
Document Number: 38-08035 Rev. *Q
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CY7C63310, CY7C638xx
Table 59. P3 Configuration (P3CR) [0x16] [R/W]
Bit #
Field
7
6
Int Enable
R/W
5
Int Act Low
R/W
4
TTL Thresh
R/W
3
2
Open Drain
R/W
1
0
Reserved
Reserved
Pull-up Enable
Output Enable
Read/Write
Default
–
0
–
0
R/W
1
R/W
0
0
0
0
0
This register exists in CY7C638(2/3)3. This register controls the operation of pins P3.0–P3.1.
Serial Peripheral Interface (SPI)
The SPI Master/Slave Interface core logic runs on the SPI clock domain, so that its functionality is independent of system clock speed.
SPI is a four pin serial interface comprised of a clock, an enable and two data pins.
SPI Data Register
Table 60. SPI Data Register (SPIDATA) [0x3C] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
SPIData[7:0]
Read/Write
Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
When read, this register returns the contents of the receive buffer. When written, it loads the transmit holding register.
Bit [7:0]: SPI Data [7:0]
When an interrupt occurs to indicate to the firmware that a byte of receive data is available, or the transmitter holding register is empty,
the firmware has 7 SPI clocks to manage the buffers: to empty the receiver buffer or to refill the transmit holding register. Failure to
meet this timing requirement results in incorrect data transfer.
Document Number: 38-08035 Rev. *Q
Page 42 of 91
CY7C63310, CY7C638xx
SPI Configure Register
Table 61. SPI Configure Register (SPICR) [0x3D] [R/W]
Bit #
Field
7
Swap
R/W
0
6
LSB First
R/W
5
4
3
CPOL
R/W
0
2
CPHA
R/W
0
1
0
Comm Mode
SCLK Select
Read/Write
Default
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit 7: Swap
0 = Swap function disabled.
1 = The SPI block swaps its use of SMOSI and SMISO. This is useful in implementing single wire communications similar to SPI.
Bit 6: LSB First
0 = The SPI transmits and receives the MSB (Most Significant Bit) first.
1 = The SPI transmits and receives the LSB (Least Significant Bit) first.
Bit [5:4]: Comm Mode [1:0]
0 0: All SPI communication disabled.
0 1: SPI master mode
1 0: SPI slave mode
1 1: Reserved
Bit 3: CPOL
This bit controls the SPI clock (SCLK) idle polarity.
0 = SCLK idles low
1 = SCLK idles high
Bit 2: CPHA
The Clock Phase bit controls the phase of the clock on which data is sampled. Table 63 on page 44 shows the timing for the
various combinations of LSB First, CPOL, and CPHA.
Bit [1:0]: SCLK Select
This field selects the speed of the master SCLK. When in master mode, SCLK is generated by dividing the base CPUCLK.
Note for Comm Modes 01b or 10b (SPI Master or SPI Slave)
When configured for SPI, (SPI Use = 1 Table 56 on page 41), the input/output direction of pins P1.3, P1.5, and P1.6 is set auto-
matically by the SPI logic. However, pin P1.4's input/output direction is NOT automatically set; it must be explicitly set by firm-
ware. For SPI Master mode, pin P1.4 must be configured as an output; for SPI Slave mode, pin P1.4 must be configured as an
input.
Table 62. SPI SCLK Frequency
SCLK Frequency when CPUCLK =
SCLK
Select
CPUCLK
Divisor
12 MHz
2 MHz
24 MHz
4 MHz
00
01
10
11
6
12
48
96
1 MHz
2 MHz
250 kHz
125 kHz
500 kHz
250 kHz
Document Number: 38-08035 Rev. *Q
Page 43 of 91
CY7C63310, CY7C638xx
SPI Interface Pins
The SPI interface uses the P1.3–P1.6 pins. These pins are configured using the P1.3 and P1.4–P1.6 Configuration.
Table 63. SPI Mode Timing vs. LSB First, CPOL and CPHA
LSB First CPHA CPOL
Diagram
0
0
0
0
0
1
0
1
0
SCLK
SSEL
DAT A
X
MSB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
LSB
X
SC LK
SSEL
D AT A
X
MS B
B it 7
B it 6
B it 5
B it 4
B it 3
B it 2
LS B
X
SCLK
SSEL
DAT A
X
MSB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
LSB
X
0
1
1
SCLK
SSEL
DATA
X
MSB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
LSB
X
1
1
0
0
0
1
SCLK
SSEL
DATA
X
LSB
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
MSB
X
SCLK
SSEL
DATA
X
LSB
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
MSB
X
1
1
1
1
0
1
SCLK
SSEL
DATA
X
LSB
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
MSB
X
SCLK
SSEL
DATA
X
LSB
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
MSB
X
Document Number: 38-08035 Rev. *Q
Page 44 of 91
CY7C63310, CY7C638xx
Timer Registers
All timer functions of the enCoRe II are provided by a single timer block. The timer block is asynchronous from the CPU clock.
Registers
Free Running Counter
The 16 bit free-running counter is clocked by the Timer Capture Clock (TCAPCLK). It is read in software for use as a general purpose
time base. When the low order byte is read, the high order byte is registered. Reading the high order byte reads this register, allowing
the CPU to read the 16-bit value atomically (loads all bits at one time). The free-running timer generates an interrupt at 1024 s rate
when clocked by a 4 MHz source. It also generates an interrupt when the free running counter overflow occurs every 16.384 ms (with
a 4 MHz source). This allows extending the length of the timer in software.
Figure 13. 16-Bit Free Running Counter Block Diagram
Overflow
Interrupt/Wrap
Interrupt
Timer Capture
Clock
16-bit Free
Running Counter
1024µs Timer
Interrupt
Table 64. Free Running Timer Low order Byte (FRTMRL) [0x20] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Free running Timer [7:0]
Read/Write
Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit [7:0]: Free running Timer [7:0]
This register holds the low order byte of the 16-bit free running timer. Reading this register causes the high order byte to be
moved into a holding register allowing an automatic read of all 16 bits simultaneously.
For reads, the actual read occurs in the cycle when the low order is read. For writes, the actual time the write occurs is the cycle
when the high order is written.
When reading the Free Running Timer, the low order byte must be read first and the high order second. When writing, the low
order byte must be written first then the high order byte.
Document Number: 38-08035 Rev. *Q
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CY7C63310, CY7C638xx
Table 65. Free Running Timer High-order Byte (FRTMRH) [0x21] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Free-running Timer [15:8]
Read/Write
Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit [7:0]: Free-running Timer [15:8]
When reading the Free-running Timer, the low order byte must be read first and the high order second. When writing, the low
order byte must be written first then the high order byte.
Table 66. Timer Capture 0 Rising (TIO0R) [0x22] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Capture 0 Rising [7:0]
Read/Write
Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit [7:0]: Capture 0 Rising [7:0]
This register holds the value of the Free-running Timer when the last rising edge occurred on the TIO0 input. When Capture 0
is in 8-bit mode, the bits that are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When
Capture 0 is in 16-bit mode this register holds the lower order 8 bits of the 16-bit timer.
Table 67. Timer Capture 1 Rising (TIO1R) [0x23] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Capture 1 Rising [7:0]
Read/Write
Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit [7:0]: Capture 1 Rising [7:0]
This register holds the value of the Free-running Timer when the last rising edge occurred on the TIO1 input in the 8-bit mode.
The bits that are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When Capture 0 is in
16-bit mode this register holds the high order 8 bits of the 16-bit timer from the last Capture 0 rising edge.
Table 68. Timer Capture 0 Falling (TIO0F) [0x24] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Capture 0 Falling [7:0]
Read/Write
Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit [7:0]: Capture 0 Falling [7:0]
This register holds the value of the Free-running Timer when the last falling edge occurred on the TIO0 input. When Capture 0
is in 8-bit mode, the bits that are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When
Capture 0 is in 16-bit mode this register holds the lower order 8 bits of the 16-bit timer.
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Table 69. Timer Capture 1 Falling (TIO1F) [0x25] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Capture 1 Falling [7:0]
Read/Write
Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit [7:0]: Capture 1Falling [7:0]
This register holds the value of the Free-running Timer when the last falling edge occurred on the TIO1 input in the 8-bit mode.
The bits that are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When capture 0 is in
16-bit mode this register holds the high order 8 bits of the 16-bit timer from the last Capture 0 falling edge.
Table 70. Programmable Interval Timer Low (PITMRL) [0x26] [R]
Bit #
Field
7
6
5
4
3
2
1
0
Prog Interval Timer [7:0]
Read/Write
Default
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit [7:0]: Prog Interval Timer [7:0]
This register holds the low order byte of the 12-bit programmable interval timer. Reading this register causes the high order byte
to be moved into a holding register allowing an automatic read of all 12 bits simultaneously.
Table 71. Programmable Interval Timer High (PITMRH) [0x27] [R]
Bit #
Field
7
6
5
4
3
2
1
0
Reserved
Prog Interval Timer [11:8]
Read/Write
Default
–
0
–
0
–
0
–
0
R
0
R
0
R
0
R
0
Bit [7:4]: Reserved
Bit [3:0]: Prog Internal Timer [11:8]
This register holds the high order nibble of the 12-bit programmable interval timer. Reading this register returns the high order
nibble of the 12-bit timer at the instant that the low order byte was last read.
Table 72. Programmable Interval Reload Low (PIRL) [0x28] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Prog Interval [7:0]
Read/Write
Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit [7:0]: Prog Interval [7:0]
This register holds the lower 8 bits of the timer. When writing into the 12-bit reload register, write the lower byte first then the higher
nibble.
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CY7C63310, CY7C638xx
Table 73. Programmable Interval Reload High (PIRH) [0x29] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Reserved
Prog Interval[11:8]
Read/Write
Default
–
0
–
0
–
0
–
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit [7:4]: Reserved
Bit [3:0]: Prog Interval [11:8]
This register holds the higher 4 bits of the timer. While writing into the 12-bit reload register, write the lower byte first then the higher
nibble.
Figure 14. Programmable Interval Timer Block Diagram
C o n fig u r a tio n
S ta tu s a n d
C o n tr o l
1 2 - b it
r e lo a d
v a lu e
S y s te m
C lo c k
1 2 - b it
r e lo a d
c o u n te r
1 2 - b it d o w n
c o u n te r
In te r r u p t
C o n tr o lle r
C lo c k
T im e r
Timer Capture
Cypress enCoRe II has two 8-bit captures. Each capture has separate registers for the rising and falling time. The two eight bit captures
can be configured as a single 16-bit capture. When configured, the capture 1 registers hold the high order byte of the 16-bit timer
capture value. Each of the four capture registers may be programmed to generate an interrupt when it is loaded.
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Table 74. Timer Configuration (TMRCR) [0x2A] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
First Edge
Hold
8-bit Capture Prescale [2:0]
Cap0 16bit
Enable
Reserved
Read/Write
Default
R/W
0
R/W
R/W
0
R/W
R/W
0
–
0
–
0
–
0
0
0
Bit 7: First Edge Hold
The First Edge Hold function applies to all four capture timers.
0 = The time of the most recent edge is held in the Capture Timer Data Register. If multiple edges have occurred since reading
the capture timer, the time for the most recent one is read.
1 = The time of the first occurrence of an edge is held in the Capture Timer Data Register until the data is read. Subsequent
edges are ignored until the Capture Timer Data Register is read.
Bit [6:4]: 8-bit Capture Prescale [2:0]
This field controls which 8 bits of the 16 Free Running Timer are captured when in bit mode.
0 0 0 = capture timer[7:0]
0 0 1 = capture timer[8:1]
0 1 0 = capture timer[9:2]
0 1 1 = capture timer[10:3]
1 0 0 = capture timer[11:4]
1 0 1 = capture timer[12:5]
1 1 0 = capture timer[13:6]
1 1 1 = capture timer[14:7]
Bit 3: Cap0 16-bit Enable
0 = Capture 0 16-bit mode is disabled
1 = Capture 0 16-bit mode is enabled. Capture 1 is disabled and the Capture 1 rising and falling registers are used as an extension
to the Capture 0 registers–extending them to 16 bits
Bit [2:0]: Reserved
Table 75. Capture Interrupt Enable (TCAPINTE) [0x2B] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Reserved
Cap1 Fall
Enable
Cap1 Rise
Enable
Cap0 Fall
Enable
Cap0 Rise
Enable
Read/Write
Default
–
0
–
0
–
0
–
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit [7:4]: Reserved
Bit 3: Cap1 Fall Enable
0 = Disable the capture 1 falling edge interrupt
1 = Enable the capture 1 falling edge interrupt
Bit 2: Cap1 Rise Enable
0 = Disable the capture 1 rising edge interrupt
1 = Enable the capture 1 rising edge interrupt
Bit 1: Cap0 Fall Enable
0 = Disable the capture 0 falling edge interrupt
1 = Enable the capture 0 falling edge interrupt
Bit 0: Cap0 Rise Enable
0 = Disable the capture 0 rising edge interrupt
1 = Enable the capture 0 rising edge interrupt
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CY7C63310, CY7C638xx
Table 76. Capture Interrupt Status (TCAPINTS) [0x2C] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Reserved
TIO1 Fall
Active
TIO1 Rise
Active
TIO0 Fall
Active
TIO0 Rise
Active
Read/Write
Default
–
0
–
0
–
0
–
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit [7:4]: Reserved
Bit 3: TIO1 Fall Active
0 = No event
1 = A falling edge has occurred on TIO1
Bit 2: TIO1 Rise Active
0 = No event
1 = A rising edge has occurred on TIO1
Bit 1: TIO0 Fall Active
0 = No event
1 = A falling edge has occurred on TIO0
Bit 0: TIO0 Rise Active
0 = No event
1 = A rising edge has occurred on TIO0
Note The interrupt status bits must be cleared by firmware to enable subsequent interrupts. This is achieved by writing a ‘1’ to
the corresponding Interrupt status bit.
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Figure 15. Timer Functional Sequence Diagram
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CY7C63310, CY7C638xx
Figure 16. 16-Bit Free Running Counter Loading Timing Diagram
clk_sys
write
valid
addr
write data
FRT reload
ready
Clk Timer
12b Prog Timer
12b reload
interrupt
12-bit programmable timer load timing
Capture timer
clk
16b free running
counter load
16b free
running counter
00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AB 00AC 00AD 00AE 00AF 00B0 00B1 00B2 ACBE ACBF ACC0
16-bit free running counter loading timing
Figure 17. Memory Mapped Registers Read/Write Timing Diagram
clk_sys
rd_wrn
Valid
Addr
rdata
wdata
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Architectural Description
Interrupt Controller
An interrupt is posted when its interrupt conditions occur. This
results in the flip-flop in Figure 18 on page 54 clocking in a ‘1’.
The interrupt remains posted until the interrupt is taken or until it
is cleared by writing to the appropriate INT_CLRx register.
The interrupt controller and its associated registers allow the
user’s code to respond to an interrupt from almost every
functional block in the enCoRe II devices. The registers
associated with the interrupt controller allow disabling interrupts
globally or individually. The registers also provide a mechanism
by which a user may clear all pending and posted interrupts, or
clear individual posted or pending interrupts.
A posted interrupt is not pending unless it is enabled by setting
its interrupt mask bit (in the appropriate INT_MSKx register). All
pending interrupts are processed by the Priority Encoder to
determine the highest priority interrupt which is taken by the M8C
if the Global Interrupt Enable bit is set in the CPU_F register.
The following table lists all interrupts and the priorities that are
available in the enCoRe II devices.
Disabling an interrupt by clearing its interrupt mask bit (in the
INT_MSKx register) does not clear a posted interrupt, nor does
it prevent an interrupt from being posted. It prevents a posted
interrupt from becoming pending.
Table 77. Interrupt Numbers, Priorities, Vectors
Interrupt Interrupt
Name
Priority
0
Address
0000h
0004h
0008h
000Ch
0010h
0014h
0018h
001Ch
0020h
0024h
0028h
002Ch
0030h
0034h
0038h
003Ch
0040h
0044h
0048h
004Ch
0050h
0054h
0058h
005Ch
0060h
0064h
Nested interrupts are accomplished by re-enabling interrupts
inside an interrupt service routine. To do this, set the IE bit in the
Flag Register.
Reset
1
POR/LVD
A block diagram of the enCoRe II Interrupt Controller is shown in
Figure 18 on page 54.
2
INT0
3
SPI transmitter empty
SPI receiver full
GPIO Port 0
GPIO Port 1
INT1
4
5
6
7
8
EP0
9
EP1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
EP2
USB reset
USB active
1 ms interval timer
Programmable Interval Timer
Timer capture 0
Timer capture 1
16-bit free running timer wrap
INT2
PS2 data low
GPIO Port 2
GPIO Port 3
Reserved
Reserved
Reserved
Sleep timer
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Figure 18. Interrupt Controller Block Diagram
Priority
Encoder
Interrupt Vector
InterruptTaken
or
INT_CLRxWrite
Posted
Interrupt
Pending
Interrupt
Interrupt
Request
M8C Core
R
1
D
Q
Interrupt
Source
(Timer,
CPU_F[0]
GIE
GPIO,etc.)
INT_MSKx
MaskBit Setting
3. The ISR ends with a RETI instruction which restores the
Program Counter and Flag registers (CPU_PC and CPU_F).
The restored Flag register re-enables interrupts, because
GIE = 1 again.
Interrupt Processing
The sequence of events that occur during interrupt processing
follows:
1. An interrupt becomes active, because:
a. The interrupt condition occurs (for example, a timer expires).
b. A previously posted interrupt is enabled through an update
of an interrupt mask register.
4. Execution resumes at the next instruction, after the one that
occurred before the interrupt. However, if there are more
pending interrupts, the subsequent interrupts are processed
before the next normal program instruction.
c. An interrupt is pending and GIE is set from 0 to 1 in the CPU
Flag register.
Interrupt Trigger Conditions
Trigger conditions for most interrupts in Table 77 on page 53
have been explained in the relevant sections. However,
conditions under which the USB Active (interrupt address 0030h)
and PS2 Data Low (interrupt address 004Ch) interrupts are
triggered are explained follow.
1. The current executing instruction finishes.
2. The internal interrupt is dispatched, taking 13 cycles. During
this time, the following actions occur: the MSB and LSB of
Program Counter and Flag registers (CPU_PC and CPU_F)
are stored onto the program stack by an automatic CALL
instruction (13 cycles) generated during the interrupt
acknowledge process.
1. USB Active Interrupt: Triggered when the D+/- lines are in a
non-idle state, that is, K-state or SE0 state.
a. The PCH, PCL, and Flag register (CPU_F) are stored onto
the program stack (in that order) by an automatic CALL
instruction (13 cycles) generated during the interrupt
acknowledge process
b. The CPU_F register is then cleared. Because this clears the
GIE bit to 0, additional interrupts are temporarily disabled.
2. PS2 Data Low Interrupt: Triggered when SDATA becomes low
when the SDATA pad is in the input mode for at least 6-7
32 kHz cycles.
3. The GPIO interrupts are edge triggered.
Interrupt Latency
c. The PCH (PC[15:8]) is cleared to zero.
The time between the assertion of an enabled interrupt and the
start of its ISR is calculated from the following equation.
d. The interrupt vector is read from the interrupt controller and
its value placed into PCL (PC[7:0]). This sets the program
counter to point to the appropriate address in the interrupt
table (for example, 0004h for the POR/LVD interrupt).
Latency = Time for current instruction to finish + Time for internal
interrupt routine to execute + Time for LJMP instruction in
interrupt table to execute.
1. Program execution vectors to the interrupt table. Typically, a
LJMP instruction in the interrupt table sends execution to the
user's Interrupt Service Routine (ISR) for this interrupt.
For example, if the 5 cycle JMP instruction is executing when an
interrupt becomes active, the total number of CPU clock cycles
before the ISR begins is as follows:
2. The ISR executes. Note that interrupts are disabled because
GIE = 0. In the ISR, interrupts are re-enabled by setting
GIE = 1 (care must be taken to avoid stack overflow).
(1 to 5 cycles for JMP to finish) + (13 cycles for interrupt routine)
+ (7 cycles for LJMP) = 21 to 25 cycles.
In the previous example, at 24 MHz, 25 clock cycles take
1.042 s.
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Interrupt Registers
The Interrupt Clear Registers (INT_CLRx) are used to enable the individual interrupt sources’ ability to clear posted interrupts.
When an INT_CLRx register is read, any bits that are set indicates an interrupt has been posted for that hardware resource. Therefore,
reading these registers gives the user the ability to determine all posted interrupts.
Table 78. Interrupt Clear 0 (INT_CLR0) [0xDA] [R/W]
Bit #
Field
7
6
5
4
3
2
1
INT0
R/W
0
0
POR/LVD
R/W
GPIO Port 1 Sleep Timer
INT1
R/W
0
GPIO Port 0 SPI Receive SPI Transmit
Read/Write
Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
When reading this register,
0 = There is no posted interrupt for the corresponding hardware
1 = Posted interrupt for the corresponding hardware present
Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT
(Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt.
Table 79. Interrupt Clear 1 (INT_CLR1) [0xDB] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
TCAP0
Prog Interval 1-ms Timer USB Active USB Reset
Timer
USB EP2
USB EP1
USB EP0
Read/Write
Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
When reading this register,
0 = There is no posted interrupt for the corresponding hardware.
1 = Posted interrupt for the corresponding hardware present.
Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits and to the ENSWINT
(Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt.
Table 80. Interrupt Clear 2 (INT_CLR2) [0xDC] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Reserved
Reserved GPIO Port 3 GPIO Port 2 PS/2 Data
Low
INT2
16-bit
Counter
Wrap
TCAP1
Read/Write
Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
When reading this register,
0 = There is no posted interrupt for the corresponding hardware.
1 = Posted interrupt for the corresponding hardware present.
Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT
(Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt.
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Interrupt Mask Registers
The Enable Software Interrupt (ENSWINT) bit in INT_MSK3[7]
determines the way an individual bit value written to an
INT_CLRx register is interpreted. When it is cleared, writing 1's
to an INT_CLRx register has no effect. However, writing 0's to an
INT_CLRx register, when ENSWINT is cleared, causes the
corresponding interrupt to clear. If the ENSWINT bit is set, any
0s written to the INT_CLRx registers are ignored. However, 1s
written to an INT_CLRx register, when ENSWINT is set, causes
an interrupt to post for the corresponding interrupt.
The Interrupt Mask Registers (INT_MSKx) enable the individual
interrupt sources’ ability to create pending interrupts.
There are four Interrupt Mask Registers (INT_MSK0,
INT_MSK1, INT_MSK2, and INT_MSK3) which may be referred
to in general as INT_MSKx. If cleared, each bit in an INT_MSKx
register prevents a posted interrupt from becoming a pending
interrupt (input to the priority encoder). However, an interrupt can
still post even if its mask bit is zero. All INT_MSKx bits are
independent of all other INT_MSKx bits.
Software interrupts can aid in debugging interrupt service
routines by eliminating the need to create system level
interactions that are sometimes necessary to create a hardware
only interrupt.
If an INT_MSKx bit is set, the interrupt source associated with
that mask bit may generate an interrupt that becomes a pending
interrupt.
Table 81. Interrupt Mask 3 (INT_MSK3) [0xDE] [R/W]
Bit #
Field
7
ENSWINT
R/W
6
5
4
3
2
1
0
Reserved
Read/Write
Default
–
0
–
0
–
0
–
0
–
0
–
0
–
0
0
Bit 7: Enable Software Interrupt (ENSWINT)
0= Disable. Writing 0s to an INT_CLRx register, when ENSWINT is cleared, causes the corresponding interrupt to clear
1= Enable. Writing 1s to an INT_CLRx register, when ENSWINT is set, causes the corresponding interrupt to post.
Bit [6:0]: Reserved
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Table 82. Interrupt Mask 2 (INT_MSK2) [0xDF] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Reserved
Reserved GPIO Port 3 GPIO Port 2 PS/2 Data
INT2
Int Enable
16-bit
Counter
Wrap Int
Enable
TCAP1
Int Enable
Int Enable
Int Enable
Low
Int Enable
Read/Write
Default
–
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit 7: Reserved
Bit 6: GPIO Port 4 Interrupt Enable
0 = Mask GPIO Port 4 interrupt
1 = Unmask GPIO Port 4 interrupt
Bit 5: GPIO Port 3 Interrupt Enable
0 = Mask GPIO Port 3 interrupt
1 = Unmask GPIO Port 3 interrupt
Bit 4: GPIO Port 2 Interrupt Enable
0 = Mask GPIO Port 2 interrupt
1 = Unmask GPIO Port 2 interrupt
Bit 3: PS/2 Data Low Interrupt Enable
0 = Mask PS/2 Data Low interrupt
1 = Unmask PS/2 Data Low interrupt
Bit 2: INT2 Interrupt Enable
0 = Mask INT2 interrupt
1 = Unmask INT2 interrupt
Bit 1: 16-bit Counter Wrap Interrupt Enable
0 = Mask 16-bit Counter Wrap interrupt
1 = Unmask 16-bit Counter Wrap interrupt
Bit 0: TCAP1 Interrupt Enable
0 = Mask TCAP1 interrupt
1 = Unmask TCAP1 interrupt
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Table 83. Interrupt Mask 1 (INT_MSK1) [0xE1] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
TCAP0
Int Enable
Prog Interval 1 ms Timer USB Active USB Reset
Timer
Int Enable
USB EP2
Int Enable
USB EP1
Int Enable
USB EP0
Int Enable
Int Enable
Int Enable
Int Enable
Read/Write
Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit 7: TCAP0 Interrupt Enable
0 = Mask TCAP0 interrupt
1 = Unmask TCAP0 interrupt
Bit 6: Prog Interval Timer Interrupt Enable
0 = Mask Prog Interval Timer interrupt
1 = Unmask Prog Interval Timer interrupt
Bit 5: 1-ms Timer Interrupt Enable
0 = Mask 1-ms interrupt
1 = Unmask 1-ms interrupt
Bit 4: USB Active Interrupt Enable
0 = Mask USB Active interrupt
1 = Unmask USB Active interrupt
Bit 3: USB Reset Interrupt Enable
0 = Mask USB Reset interrupt
1 = Unmask USB Reset interrupt
Bit 2: USB EP2 Interrupt Enable
0 = Mask EP2 interrupt
1 = Unmask EP2 interrupt
Bit 1: USB EP1 Interrupt Enable
0 = Mask EP1 interrupt
1 = Unmask EP1 interrupt
Bit 0: USB EP0 Interrupt Enable
0 = Mask EP0 interrupt
1 = Unmask EP0 interrupt
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Table 84. Interrupt Mask 0 (INT_MSK0) [0xE0] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
GPIO Port 1 Sleep Timer
Int Enable
INT1
Int Enable
GPIO Port 0 SPI Receive SPITransmit
Int Enable
INT0
Int Enable
POR/LVD
Int Enable
Int Enable
Int Enable
Int Enable
Read/Write
Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit 7: GPIO Port 1 Interrupt Enable
0 = Mask GPIO Port 1 interrupt
1 = Unmask GPIO Port 1 interrupt
Bit 6: Sleep Timer Interrupt Enable
0 = Mask Sleep Timer interrupt
1 = Unmask Sleep Timer interrupt
Bit 5: INT1 Interrupt Enable
0 = Mask INT1 interrupt
1 = Unmask INT1 interrupt
Bit 4: GPIO Port 0 Interrupt Enable
0 = Mask GPIO Port 0 interrupt
1 = Unmask GPIO Port 0 interrupt
Bit 3: SPI Receive Interrupt Enable
0 = Mask SPI Receive interrupt
1 = Unmask SPI Receive interrupt
Bit 2: SPI Transmit Interrupt Enable
0 = Mask SPI Transmit interrupt
1 = Unmask SPI Transmit interrupt
Bit 1: INT0 Interrupt Enable
0 = Mask INT0 interrupt
1 = Unmask INT0 interrupt
Bit 0: POR/LVD Interrupt Enable
0 = Mask POR/LVD interrupt
1 = Unmask POR/LVD interrupt
Table 85. Interrupt Vector Clear Register (INT_VC) [0xE2] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Pending Interrupt [7:0]
Read/Write
Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
The Interrupt Vector Clear Register (INT_VC) holds the interrupt vector for the highest priority pending interrupt when read, and
when written clears all pending interrupts.
Bit [7:0]: Pending Interrupt [7:0]
8-bit data value holds the interrupt vector for the highest priority pending interrupt. Writing to this register clears all pending
interrupts.
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Regulator Output
VREG Control
Table 86. VREG Control Register (VREGCR) [0x73] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Reserved
Keep Alive
VREG
Enable
Read/Write
Default
–
0
–
0
–
0
–
0
–
0
–
0
R/W
0
R/W
0
Bit [7:2]: Reserved
Bit 1: Keep Alive
Keep Alive, when set, allows the voltage regulator to source up to 20 µA of current when the voltage regulator is disabled.
P12CR[0],P12CR[7] must be cleared.
0 = Disabled
1 = Enabled
Bit 0: VREG Enable
This bit turns on the 3.3 V voltage regulator. The voltage regulator only functions within specifications when VCC is above 4.35 V.
This block must not be enabled when VCC is below 4.35V—although no damage or irregularities occur if it is enabled below 4.35 V.
0 = Disable the 3.3 V voltage regulator output on the VREG/P1.2 pin.
1 = Enable the 3.3 V voltage regulator output on the VREG/P1.2 pin. GPIO functionality of P1.2 is disabled.
Note Use of the alternate drive on pins P1.3–P1.6 requires that the VREG Enable bit be set to enable the regulator and provide
the alternate voltage.
Document Number: 38-08035 Rev. *Q
Page 60 of 91
CY7C63310, CY7C638xx
USB/PS2 Transceiver
Although the USB transceiver has features to assist in interfacing to PS/2, these features are not controlled using these registers. The
registers only control the USB interfacing features. PS/2 interfacing options are controlled by the D+ and D– GPIO Configuration
register (See Table 44 on page 36).
USB Transceiver Configuration
Table 87. USB Transceiver Configure Register (USBXCR) [0x74] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
USB Pull-up
Enable
Reserved
USB Force State
Read/Write
Default
R/W
0
–
0
–
0
–
0
–
0
–
0
–
0
R/W
0
Bit 7: USB Pull-up Enable
0 = Disable the pull-up resistor on D–
1 = Enable the pull-up resistor on D–. This pull-up is to VCC if the PHY’s internal voltage regulator is not enabled or to the internally
generated 3.3V when VREG is enabled.
Bit [6:1]: Reserved
Bit 0: USB Force State
This bit allows the state of the USB IO pins D– and D+ to be forced to a state when USB is enabled.
0 = Disable USB Force State
1 = Enable USB Force State. Allows the D– and D+ pins to be controlled by P1.1 and P1.0 respectively when the USBIO is in
USB mode. Refer to Table 44 on page 36 for more information.
Note The USB transceiver has a dedicated 3.3 V regulator for USB signalling purposes and to provide for the 1.5 K D– pull-up.
Unlike the other 3.3 V regulator, this regulator cannot be controlled or accessed by firmware. When the device is suspended,
this regulator is disabled along with the bandgap (which provides the reference voltage to the regulator) and the D– line is
pulled up to 5 V through an alternate 6.5 K resistor. During wake up following a suspend, the band gap and the regulator are
switched on in any order. Under an extremely rare case when the device wakes up following a bus reset condition and the volt-
age regulator and the band gap turn on in that particular order, there is possibility of a glitch or low pulse occurring on the D–
line. The host can misinterpret this as a detach condition. This condition, although rare, is avoided by keeping the bandgap cir-
cuitry enabled during sleep. This is achieved by setting the ‘No Buzz’ bit, bit[5] in the OSC_CR0 register. This is an issue only
if the device is put to sleep during a bus reset condition.
■ Bit stuffing and unstuffing.
USB Serial Interface Engine (SIE)
Firmware is required to handle the rest of the USB interface with
The SIE allows the microcontroller to communicate with the USB
the following tasks:
host at low speed data rates (1.5 Mbps). The SIE simplifies the
■ Coordinate enumeration by decoding USB device requests.
■ Fill and empty the FIFOs.
interface between the microcontroller and the USB by
incorporating hardware that handles the following USB bus
activity independently of the microcontroller.
■ Suspend and Resume coordination.
■ Verify and select Data toggle values.
■ Translate the encoded received data and format the data to be
transmitted on the bus.
■ CRC checking and generation. Flag the microcontroller if errors
exist during transmission.
■ Address checking. Ignore the transactions not addressed to
the device.
■ Send appropriate ACK/NAK/STALL handshakes.
■ Token type identification (SETUP, IN, or OUT). Set the
appropriate token bit after a valid token is received.
■ Place valid received data in the appropriate endpoint FIFOs.
■ Send and update the data toggle bit (Data1/0).
Document Number: 38-08035 Rev. *Q
Page 61 of 91
CY7C63310, CY7C638xx
USB Device
USB Device Address
Table 88. USB Device Address (USBCR) [0x40] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
USB Enable
Device Address[6:0]
Read/Write
Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit 7: USB Enable
This bit must be enabled by firmware before the serial interface engine (SIE) responds to the USB traffic at the address specified
in Device Address [6:0]. When this bit is cleared, the USB transceiver enters power down state. User’s firmware must clear this
bit before entering sleep mode to save power.
0 = Disable USB device address and put the USB transceiver into power down state.
1 = Enable USB device address and put the USB transceiver into normal operating mode.
Bit [6:0]: Device Address [6:0]
These bits must be set by firmware during the USB enumeration process (that is, SetAddress) to the nonzero address assigned
by the USB host.
Endpoint 0, 1, and 2 Count
Table 89. Endpoint 0, 1, and 2 Count (EP0CNT–EP2CNT) [0x41, 0x43, 0x45] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Data Toggle Data Valid
Reserved
Byte Count[3:0]
R/W R/W
Read/Write
Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
Bit 7: Data Toggle
This bit selects the DATA packet's toggle state. For IN transactions, firmware must set this bit to select the transmitted Data
Toggle. For OUT or SETUP transactions, the hardware sets this bit to the state of the received Data Toggle bit.
0 = DATA0
1 = DATA1
Bit 6: Data Valid
This bit is used for OUT and SETUP tokens only. This bit is cleared to ‘0’ if CRC, bitstuff, or PID errors have occurred. This bit
does not update for some endpoint mode settings.
0 = Data is invalid. If enabled, the endpoint interrupt occurs even if invalid data is received.
1 = Data is valid
Bit [5:4]: Reserved
Bit [3:0]: Byte Count Bit [3:0]
Byte Count Bits indicate the number of data bytes in a transaction: For IN transactions, firmware loads the count with the number
of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8 inclusive. For OUT or SETUP transactions,
the count is updated by hardware to the number of data bytes received, plus 2 for the CRC bytes. Valid values are 2–10 inclusive.
For Endpoint 0 Count Register, when the count updates from a SETUP or OUT transaction, the count register locks and cannot
be written by the CPU. Reading the register unlocks it. This prevents firmware from overwriting a status update on it.
Document Number: 38-08035 Rev. *Q
Page 62 of 91
CY7C63310, CY7C638xx
Endpoint 0 Mode
Because both firmware and the SIE are allowed to write to the Endpoint 0 Mode and Count Registers, the SIE provides an interlocking
mechanism to prevent accidental overwriting of data.
When the SIE writes to these registers they are locked and the processor cannot write to them until after it has read them. Writing to
this register clears the upper four bits regardless of the value written.
Table 90. Endpoint 0 Mode (EP0MODE) [0x44] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Setup
Received
IN Received
OUT
Received
ACK’d Trans
Mode[3:0]
Read/Write
Default
R/C[5]
R/C[5]
0
R/C[5]
R/C[5]
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
Bit 7: SETUP Received
This bit is set by hardware when a valid SETUP packet is received. It is forced HIGH from the start of the data packet phase of
the SETUP transactions until the end of the data phase of a control write transfer, and cannot be cleared during this interval.
While this bit is set to ‘1’, the CPU cannot write to the EP0 FIFO. This prevents firmware from overwriting an incoming SETUP
transaction before firmware has a chance to read the SETUP data.
This bit is cleared by any nonlocked writes to the register.
0 = No SETUP received
1 = SETUP received
Bit 6: IN Received
This bit when set indicates a valid IN packet has been received. This bit is updated to ‘1’ after the host acknowledges an IN data
packet. When clear, it indicates either no IN has been received or that the host did not acknowledge the IN data by sending ACK
handshake.
This bit is cleared by any nonlocked writes to the register.
0 = No IN received
1 = IN received
Bit 5: OUT Received
This bit when set indicates a valid OUT packet has been received and ACKed. This bit is updated to ‘1’ after the last received
packet in an OUT transaction. When clear, it indicates no OUT received.
This bit is cleared by any nonlocked writes to the register.
0 = No OUT received
1 = OUT received
Bit 4: ACK’d Transaction
The ACK’d transaction bit is set when the SIE engages in a transaction to the register’s endpoint, which completes with a ACK
packet.
This bit is cleared by any nonlocked writes to the register.
1 = The transaction completes with an ACK.
0 = The transaction does not complete with an ACK.
Bit [3:0]: Mode [3:0]
The endpoint modes determine how the SIE responds to the USB traffic that the host sends to the endpoint. The mode controls
how the USB SIE responds to traffic, and how the USB SIE changes the mode of that endpoint as a result of host packets to the
endpoint.
Note
5. C = Clear. This bit is cleared only by the user and cannot be set by firmware.
Document Number: 38-08035 Rev. *Q
Page 63 of 91
CY7C63310, CY7C638xx
Endpoint 1 and 2 Mode
Table 91. Endpoint 1 and 2 Mode (EP1MODE – EP2MODE) [0x45, 0x46] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Stall
Reserved
NAK Int
Enable
ACK’d
Transaction
Mode[3:0]
Read/Write
Default
R/W
0
R/W
0
R/W
0
R/C (Note 4)
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit 7: Stall
When this bit is set the SIE stalls an OUT packet if the Mode Bits are set to ACK-OUT, and the SIE stalls an IN packet if the
mode bits are set to ACK-IN. This bit must be clear for all other modes
Bit 6: Reserved
Bit 5: NAK Int Enable
This bit when set causes an endpoint interrupt to be generated even when a transfer completes with a NAK. Unlike enCoRe,
enCoRe II family members do not generate an endpoint interrupt under these conditions unless this bit is set.
0 = Disable interrupt on NAK’d transactions
1 = Enable interrupt on NAK’d transaction
Bit 4: ACK’d Transaction
The ACK’d transaction bit is set when the SIE engages in a transaction to the register’s endpoint that completes with an ACK
packet.
This bit is cleared by any writes to the register.
0 = The transaction does not complete with an ACK
1 = The transaction completes with an ACK
Bit [3:0]: Mode [3:0]
The endpoint modes determine how the SIE responds to USB traffic that the host sends to the endpoint. The mode controls how
the USB SIE responds to traffic, and how the USB SIE changes the mode of that endpoint as a result of host packets to the
endpoint.
Note When the SIE writes to the EP1MODE or the EP2MODE register, it blocks firmware writes to the EP2MODE or the
EP1MODE registers respectively (if both writes occur in the same clock cycle). This is because the design employs only one
common ‘update’ signal for both EP1MODE and EP2MODE registers. As a result, when SIE writes to say EP1MODE register,
the update signal is set and this prevents firmware writes to EP2MODE register. SIE writes to the endpoint mode registers have
higher priority than firmware writes. This mode register write block situation can put the endpoints in incorrect modes. Firmware
must read the EP1/2MODE registers immediately following a firmware write and rewrite if the value read is incorrect.
Table 92. Endpoint 0 Data (EP0DATA) [0x50-0x57] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Endpoint 0 Data Buffer [7:0]
Read/Write
Default
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
The Endpoint 0 buffer is comprised of 8 bytes located at address 0x50 to 0x57.
Document Number: 38-08035 Rev. *Q
Page 64 of 91
CY7C63310, CY7C638xx
Table 93. Endpoint 1 Data (EP1DATA) [0x58-0x5F] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Endpoint 1 Data Buffer [7:0]
Read/Write
Default
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
The Endpoint 1 buffer is comprised of 8 bytes located at address 0x58 to 0x5F.
Table 94. Endpoint 2 Data (EP2DATA) [0x60-0x67] [R/W]
Bit #
Field
7
6
5
4
3
2
1
0
Endpoint 2 Data Buffer [7:0]
Read/Write
Default
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
The Endpoint 2 buffer is comprised of 8 bytes located at address 0x60 to 0x67.
The three data buffers are used to hold data for both IN and OUT transactions. Each data buffer is 8 bytes long.
The reset values of the Endpoint Data Registers are unknown.
Unlike past enCoRe parts the USB data buffers are only accessible in the IO space of the processor.
Document Number: 38-08035 Rev. *Q
Page 65 of 91
CY7C63310, CY7C638xx
USB Mode Tables
Mode
Encoding
SETUP
IN
OUT
Comments
DISABLE
0000
Ignore
Ignore
Ignore
Ignore all USB traffic to this endpoint. Used by Data and
Control endpoints.
NAK IN/OUT
0001
0010
Accept
Accept
NAK
NAK
NAK IN and OUT token. Control endpoint only.
STATUS OUT ONLY
STALL
Check
STALL IN and ACK zero byte OUT. Control endpoint
only.
STALL IN/OUT
0011
0110
Accept
Accept
STALL
STALL
STALL
STALL IN and OUT token. Control endpoint only.
STATUS IN ONLY
TX0 byte
STALL OUT and send zero byte data for IN token. Con-
trol endpoint only.
ACK OUT – STATUS
IN
1011
1111
Accept
Accept
TX0 byte
TX Count
ACK
ACK the OUT token or send zero byte data for IN token.
Control endpoint only.
ACK IN – STATUS
OUT
Check
Respond to IN data or Status OUT. Control endpoint on-
ly.
NAK OUT
1000
1001
Ignore
Ignore
Ignore
Ignore
NAK
ACK
Send NAK handshake to OUT token. Data endpoint on-
ly.
ACK OUT (STALL = 0)
This mode is changed by the SIE to mode 1000 on is-
suance of ACK handshake to an OUT. Data endpoint
only.
ACK OUT (STALL = 1)
NAK IN
1001
1100
1101
Ignore
Ignore
Ignore
Ignore
NAK
STALL
Ignore
Ignore
STALL the OUT transfer.
Send NAK handshake for IN token. Data endpoint only.
ACK IN (STALL = 0)
TX Count
This mode is changed by the SIE to mode 1100 after
receiving ACK handshake to an IN data. Data endpoint
only.
ACK IN (STALL = 1)
1101
Ignore
STALL
Ignore
STALL the IN transfer. Data endpoint only.
Reserved
Reserved
Reserved
Reserved
Reserved
0101
0111
1010
0100
1110
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
These modes are not supported by SIE. Firmware must
not use this mode in Control and Data endpoints.
Mode Column
SETUP, IN, and OUT Columns
The 'Mode' column contains the mnemonic names given to the
modes of the endpoint. The mode of the endpoint is determined
by the 4-bit binaries in the 'Encoding' column as discussed in the
following sections. The Status IN and Status OUT represent the
status IN or OUT stage of the control transfer.
Depending on the mode specified in the 'Encoding' column, the
'SETUP', 'IN', and 'OUT' columns contain the SIE's responses
when the endpoint receives SETUP, IN, and OUT tokens,
respectively.
A 'Check' in the Out column means that upon receiving an OUT
token the SIE checks to see whether the OUT is of zero length
and has a Data Toggle (Data1/0) of 1. If these conditions are true,
the SIE responds with an ACK. If any of the these conditions is
not met, the SIE responds with a STALL or Ignore.
Encoding Column
The contents of the 'Encoding' column represent the Mode
Bits [3:0] of the Endpoint Mode Registers (Table 90 on page 63
and Table 91 on page 64). The endpoint modes determine how
the SIE responds to different tokens that the host sends to the
endpoints. For example, if the Mode Bits [3:0] of the Endpoint 0
Mode Register are set to '0001', which is NAK IN/OUT mode, the
SIE sends an ACK handshake in response to SETUP tokens and
NAK any IN or OUT tokens.
A 'TX Count' entry in the IN column means that the SIE transmits
the number of bytes specified in the Byte Count Bit [3:0] of the
Endpoint Count Register (Table 89) in response to any IN token.
Document Number: 38-08035 Rev. *Q
Page 66 of 91
CY7C63310, CY7C638xx
Details of Mode for Differing Traffic Conditions
Control Endpoint
SIE
Bus Event
SIE
EP0 Mode Register
EP0 Count Register
EP0 Interrupt Comments
Mode Token
DISABLED
Count
Dval
D0/1 Response S
I
O
A
MODE DTOG DVAL COUNT FIFO
0000
x
x
x
x
Ignore All
STALL_IN_OUT
0011 SETUP
0011 SETUP
0011 SETUP
>10
<=10
<=10
x
x
invalid
valid
x
x
x
junk
junk
Ignore
Ignore
x
x
x
x
x
ACK
1
1
1
1
0001 update
1
1
1
update data
Yes
ACK SETUP
Stall IN
0011
0011
0011
0011
IN
STALL
OUT
OUT
OUT
>10
x
Ignore
<=10
<=10
invalid
valid
Ignore
STALL
Stall OUT
NAK_IN_OUT
0001 SETUP
0001 SETUP
0001 SETUP
>10
<=10
<=10
x
x
invalid
valid
x
x
x
x
x
x
x
x
junk
junk
Ignore
Ignore
ACK
NAK
1
0001 update
update data
Yes
ACK SETUP
NAK IN
Ignore
0001
0001
0001
0001
IN
OUT
OUT
OUT
>10
x
<=10
<=10
invalid
valid
Ignore
NAK
NAK OUT
ACK_IN_STATUS_OUT
1111 SETUP
1111 SETUP
1111 SETUP
>10
<=10
<=10
x
x
invalid
valid
x
x
x
x
x
x
x
x
x
0
1
junk
junk
Ignore
Ignore
ACK
TX
1
1
0001 update
0001
update data
Yes
Yes
ACK SETUP
Host Not ACK'd
Host ACK'd
Ignore
1111
1111
1111
1111
1111
1111
1111
IN
IN
x
x
TX
1
OUT
OUT
>10
<=10
x
invalid
Ignore
OUT <=10, <>2 valid
STALL
STALL
ACK
0011
0011
Yes
Yes
Yes
Bad Status
Bad Status
Good Status
OUT
OUT
2
2
valid
valid
1
1
1
0010
1
1
1
2
STATUS_OUT
0010 SETUP
0010 SETUP
0010 SETUP
>10
<=10
<=10
x
x
invalid
valid
x
x
x
x
x
x
x
x
0
1
junk
junk
Ignore
Ignore
ACK
1
0001 update
0011
update data
Yes
Yes
ACK SETUP
Stall IN
0010
0010
0010
0010
0010
0010
IN
STALL
OUT
OUT
>10
<=10
x
Ignore
invalid
Ignore
OUT <=10, <>2 valid
STALL
STALL
ACK
0011
0011
1
Yes
Yes
Yes
Bad status
Bad status
Good status
OUT
OUT
2
2
valid
valid
1
1
1
1
1
2
ACK_OUT_STATUS_IN
1011 SETUP
1011 SETUP
1011 SETUP
>10
<=10
<=10
x
x
x
x
junk
junk
Ignore
invalid
valid
Ignore
ACK
1
0001 update
update data
Yes
ACK SETUP
Document Number: 38-08035 Rev. *Q
Page 67 of 91
CY7C63310, CY7C638xx
Details of Mode for Differing Traffic Conditions (continued)
Control Endpoint
SIE
Bus Event
SIE
EP0 Mode Register
EP0 Count Register
EP0 Interrupt Comments
Mode Token
Count
x
Dval
D0/1 Response S
I
O
A
MODE DTOG DVAL COUNT FIFO
1011
1011
1011
1011
1011
IN
x
x
x
x
x
x
x
TX 0
TX 0
Host not ACK'd
Host ACK'd
Ignore
IN
x
1
1
0011
Yes
Yes
OUT
OUT
OUT
>10
<=10
<=10
x
junk
junk
invalid
valid
Ignore
ACK
1
1
0001 update
1
1
update data
Good OUT
STATUS_IN
0110 SETUP
0110 SETUP
0110 SETUP
>10
<=10
<=10
x
x
invalid
valid
x
x
x
x
x
x
x
x
x
junk
junk
Ignore
Ignore
ACK
TX 0
TX 0
1
1
1
0001 update
0011
update data
Yes
Yes
ACK SETUP
Host not ACK'd
Host ACK'd
Ignore
0110
0110
0110
0110
0110
IN
IN
x
x
1
OUT
OUT
OUT
>10
<=10
<=10
x
invalid
valid
Ignore
STALL
0011
Yes
Stall OUT
Data Out Endpoints
ACK OUT (STALL Bit = 0)
1001
1001
1001
1001
IN
x
x
x
x
x
Ignore
OUT
OUT
OUT
>MAX
junk
junk
Ignore
<=MAX invalid invalid
Ignore
<=MAX
valid
valid
ACK
STALL
NAK
1
1000 update
1
update data
Yes
ACK OUT
ACK OUT (STALL Bit = 1)
1001
1001
1001
1001
IN
x
x
x
x
x
Ignore
OUT
OUT
OUT
>MAX
Ignore
<=MAX invalid invalid
Ignore
<=MAX
valid
valid
Stall OUT
NAK OUT
1000
IN
x
x
x
x
x
Ignore
Ignore
Ignore
1000
1000
1000
OUT
OUT
OUT
>MAX
<=MAX invalid invalid
<=MAX
valid
valid
If Enabled NAK OUT
Data In Endpoints
ACK IN (STALL Bit = 0)
1101
1101
1101
OUT
IN
x
x
x
x
x
x
x
x
x
Ignore
Host Not ACK'd
Host ACK'd
IN
TX
1
1100
Yes
ACK IN (STALL Bit = 1)
1101
1101
OUT
IN
x
x
x
x
x
x
Ignore
STALL
NAK
Stall IN
NAK IN
1100
OUT
IN
x
x
x
x
x
x
Ignore
1100
If Enabled NAK IN
Document Number: 38-08035 Rev. *Q
Page 68 of 91
CY7C63310, CY7C638xx
Register Summary
The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF.
Addr
Name
7
6
5
4
3
2
1
0
R/W
Default
00
P0DATA
P0.7
P0.6/TIO1 P0.5/TIO0 P0.4/INT2 P0.3/INT1 P0.2/INT0 P0.1/CLK- P0.0/CLKI
bbbbbbbb
00000000
OUT
N
01
P1DATA
P1.7
P1.6/SMI P1.5/SMO P1.4/SCLK P1.3/SSEL P1.2/VREG
P1.1/D–
P1.0/D+
bbbbbbbb
00000000
SO
SI
02
03
04
05
P2DATA
P3DATA
P4DATA
P00CR
Res
Res
P2.1–P2.0
P3.1–P3.0
bbbbbbbb
bbbbbbbb
----bbbb
00000000
00000000
00000000
00000000
Res
Res
Reserved
Int
Enable
Int Act TTL Thresh Reserved Open Drain
Low
Pull-up
Output
Enable
-bbbbbbb
Enable
06
07–09
0A–0B
0C
P01CR
CLK
Int
Int Act TTL Thresh Reserved Open Drain
Low
Pull-up
Enable
Output
Enable
bbbbbbbb
--bbbbbb
bbbbbbbb
-bbbbbbb
-bb---bb
00000000
00000000
00000000
00000000
00000000
Output
Enable
P02CR–
P04CR
Reserved Reserved
Int Act TTL Thresh Reserved Open Drain
Low
Pull-up
Enable
Output
Enable
P05CR–
P06CR
TIO
Output
Int
Enable
Int Act TTL Thresh Reserved Open Drain
Low
Pull-up
Enable
Output
Enable
P07CR
Reserved
Reserved
Int
Enable
Int Act TTL Thresh Reserved Open Drain
Low
Pull-up
Enable
Output
Enable
0D
P10CR
Int
Enable
Int Act
Low
Reserved
PS/2
Pull-up
Enable
Output
Enable
0E
0F
P11CR
P12CR
P13CR
Reserved
Int
Int Act
Low
Reserved
Open Drain Reserved
Output
Enable
-bb--b-b
bbbbbbbb
-bbbbbbb
bbbbbbbb
-bbbbbbb
-bbbbbbb
-bbbbbbb
00000000
00000000
00000000
00000000
00000000
00000000
00000000
Enable
CLK
Output
Int
Enable
Int Act TTL Thresh Reserved Open Drain
Low
Pull-up
Enable
Output
Enable
10
Reserved
Int
Enable
Int Act
Low
3.3 V Drive High Sink Open Drain
Pull-up
Enable
Output
Enable
11–13
14
P14CR–
P16CR
SPI Use
Int
Enable
Int Act
Low
3.3 V Drive High Sink Open Drain
Pull-up
Enable
Output
Enable
P17CR
P2CR
P3CR
Reserved
Reserved
Reserved
Int
Enable
Int Act TTL Thresh High Sink Open Drain
Low
Pull-up
Enable
Output
Enable
15
Int
Enable
Int Act TTL Thresh Reserved Open Drain
Low
Pull-up
Enable
Output
Enable
16
Int
Enable
Int Act TTL Thresh Reserved Open Drain
Low
Pull-up
Enable
Output
Enable
20
21
22
23
24
25
26
27
28
29
2A
FRTMRL
FRTMRH
TCAP0R
TCAP1R
TCAP0F
TCAP1F
PITMRL
PITMRH
PIRL
Free Running Timer [7:0]
Free Running Timer [15:8]
Capture 0 Rising [7:0]
Capture 1 Rising [7:0]
Capture 0 Falling [7:0]
Capture 1 Falling [7:0]
Prog Interval Timer [7:0]
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
----bbbb
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
Reserved
Prog Interval Timer [11:8]
Prog Interval [7:0]
bbbbbbbb
----bbbb
PIRH
Reserved
Prog Interval [11:8]
Reserved
TMRCR
First Edge
Hold
8-bit capture Prescale
Cap0 16bit
Enable
bbbbb---
2B
2C
30
TCAPINTE
TCAPINTS
Reserved
Reserved
Cap1 Fall
Active
Cap1 Rise Cap0 Fall Cap0 Rise
Active Active Active
----bbbb
----bbbb
-bb----b
00000000
00000000
00010000
Cap1 Fall
Active
Cap1 Rise Cap0 Fall Cap0 Rise
Active
Active
Active
CPUCLKCR Reserved
USB
USB CLK
Select
Reserved
CPU
CLK Select
CLK/2
Disable
31
32
34
ITMRCLKCR
CLKIOCR
IOSCTR
TCAPCLK Divider
Reserved
TCAPCLK Select
ITMRCLK Divider
Reserved
ITMRCLK Select
CLKOUT Select
bbbbbbbb
---bbbbb
10001111
00000000
000ddddd
foffset[2:0]
Gain[4:0]
bbbbbbbb
Document Number: 38-08035 Rev. *Q
Page 69 of 91
CY7C63310, CY7C638xx
Register Summary (continued)
The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF.
Addr
Name
7
6
5
4
3
2
1
0
R/W
Default
36
LPOSCTR
32 kHz Reserved 32 kHz Bias Trim [1:0]
32 kHz Freq Trim [3:0]
b-bbbbbb
dddddddd
Low
Power
39
OSCLCKCR
Reserved
Fine Tune
Only
USB
Osclock
Disable
------bb
00000000
3C
3D
40
SPIDATA
SPICR
SPIData[7:0]
CPOL
bbbbbbbb
bbbbbbbb
bbbbbbbb
00000000
00000000
00000000
Swap
LSB First
Comm Mode
CPHA
SCLK Select
USBCR
USB
Enable
Device Address[6:0]
41
42
43
44
45
46
EP0CNT
EP1CNT
Data
Data Valid
Data Valid
Data Valid
Reserved
Reserved
Reserved
Byte Count[3:0]
Byte Count[3:0]
Byte Count[3:0]
Mode[3:0]
bbbbbbbb
bbbbbbbb
bbbbbbbb
ccccbbbb
b-bcbbbb
b-bcbbbb
00000000
00000000
00000000
00000000
00000000
00000000
Toggle
Data
Toggle
EP2CNT
Data
Toggle
EP0MODE
EP1MODE
EP2MODE
Setup
rcv’d
IN rcv’d OUT rcv’d ACK’d trans
Stall
Reserved NAK Int Ack’d trans
Enable
Mode[3:0]
Stall
Reserved NAK Int Ack’d trans
Enable
Mode[3:0]
50–57
58–5F
60–67
73
EP0DATA
EP1DATA
EP2DATA
VREGCR
Endpoint 0 Data Buffer [7:0]
bbbbbbbb
bbbbbbbb
bbbbbbbb
------bb
????????
????????
????????
00000000
Endpoint 1 Data Buffer [7:0]
Endpoint 2 Data Buffer [7:0]
Reserved
Keep Alive
VREG
Enable
74
USBXCR
USB
Pull-up
Enable
Reserved
USB Force
State
b------b
00000000
DA
DB
INT_CLR0 GPIOPort
1
Sleep
Timer
INT1
GPIO Port
SPI
Receive
SPI Transmit
INT0
POR/LVD
bbbbbbbb
bbbbbbbb
00000000
00000000
0
INT_CLR1
TCAP0
Prog
Interval
Timer
1-ms
Timer
USB Active USB Reset USB EP2
USB EP1 USB EP0
DC
INT_CLR2 Reserved Reserved GPIOPort GPIO Port 2 PS/2 Data
INT2
16-bit
Counter
Wrap
TCAP1
-bbbbbbb
00000000
3
Low
DE
DF
INT_MSK3 ENSWINT
Reserved
b-------
00000000
00000000
INT_MSK2 Reserved Reserved GPIOPort GPIO Port 2 PS/2 Data
INT2
Int Enable
16-bit
TCAP1
-bbbbbbb
3
Int Enable
Low Int
Enable
Counter Int Enable
Wrap
Int Enable
Int Enable
E1
E0
INT_MSK1
TCAP0
Prog
1-ms
Timer
USB Active USB Reset USB EP2
USB EP1 USB EP0
bbbbbbbb
bbbbbbbb
00000000
00000000
Int Enable Interval
Timer
Int Enable Int Enable Int Enable Int Enable Int Enable
Int Enable
Int Enable
INT_MSK0 GPIOPort
1
Sleep
Timer
INT1
GPIOPort0
SPI
Receive
Int Enable
SPI Transmit
Int Enable Int Enable Int Enable
INT0
POR/LVD
Int Enable Int Enable
Int Enable Int Enable
E2
E3
--
INT_VC
RESWDT
CPU_A
Pending Interrupt [7:0]
Reset Watchdog Timer [7:0]
Temporary Register T1 [7:0]
X[7:0]
bbbbbbbb
wwwwwwww
--------
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000010
00010000
--
CPU_X
--------
--
CPU_PCL
CPU_PCH
CPU_SP
CPU_F
Program Counter [7:0]
Program Counter [15:8]
Stack Pointer [7:0]
--------
--
--------
--
--------
-
Reserved
Reserved WDRS
XOI
Super
Sleep
Carry
Zero
Global IE
Stop
---brwww
r-ccb--b
FF
CPU_SCR
GIES
PORS
Reserved
Reserved
Document Number: 38-08035 Rev. *Q
Page 70 of 91
CY7C63310, CY7C638xx
Register Summary (continued)
The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF.
Addr
1E0
1E3
1EB
1E4
Name
OSC_CR0
LVDCR
7
6
5
4
3
2
1
0
R/W
Default
Reserved
Reserved
No Buzz
Sleep Timer [1:0]
Reserved
Reserved
CPU Speed [2:0]
VM[2:0]
--bbbbbb
--bb-bbbb
bb------
00000000
00000000
00000000
00000000
PORLEV[1:0]
ECO_TR
VLTCMP
Sleep Duty Cycle [1:0]
Reserved
LVD
PPOR
------rr
Legend
In the R/W column,
b = Both Read and Write
r = Read Only
w = Write Only
c = Read/Clear
? = Unknown
d = calibration value. Must not change during normal use.
Document Number: 38-08035 Rev. *Q
Page 71 of 91
CY7C63310, CY7C638xx
Voltage versus CPU Frequency Characteristics
Figure 19. Voltage versus CPU Frequency Characteristics
5.50
4.75
4.00
24 MHz
93 KHz
12 MHz
CPU Frequency
Running the CPU at 24 MHz requires a minimum voltage of
4.75 V. This applies to any CPU speed above 12 MHz, so using
an external clock between 12–24 MHz must also adhere to this
requirement. Operating the CPU at 24MHz when the supply
voltage is below 4.75 V can cause undesired behavior and must
be avoided.
■ Monitor the LVD until voltage is above the trip point (Register
VLTCMP 0x1E4, bit 1 is clear).
■ Debounce the indication to ensure that voltage is above the set
point for possible noisy supplies.
■ Set the POR to the high set point.
■ Shift CPU speed to 24 MHz.
Many enCoRe II applications use USB Vbus 5 V as the power
source for the device. According to the USB specification,
voltage can be less than 4.75 V on Vbus (if the USB port is a low
power port the voltage can be between 4.4 V and 5.25 V). Even
for externally powered 5 V applications, developers must
consider that on power up and power down voltage is less than
4.75V for some time. Firmware must be implemented properly to
prevent undesired behavior.
If the supply voltage dips below 4.75 V and the application can
tolerate running at a CPU speed of 12 MHz, then application
firmware may also implement the following to minimize the
chance of a reset event due to a voltage transient:
■ Set the LVD for one of the desired high setting (~4.73 V or
~4.82 V).
Use of 24 MHz requires the use of the high POR trip point of
■ Enable the LVD interrupt.
approximately 4.55–4.65
V
(Register LVDCR 0x1E3,
PORLEV[1:0] = 10b). This setting is sufficient to protect the
device from problems due to operating at low voltage with CPU
speeds above 12 MHz. This must be set before setting the CPU
speed to greater than 12 MHz. For devices with slow power
ramps, changing the POR threshold to the high level may result
in one or more resets of the device as power ramps through the
chip default POR set point of approximately 2.6 V up through the
high POR set point.
■ In the LVD ISR, reduce CPU speed to 12 MHz and shift the
POR to a lower threshold.
■ Firmware can monitor for VLTCMP to clear within the normal
application main loop.
■ Debounce the indication to ensure voltage is above the set
point.
■ Shift the POR to the high set point.
■ Shift the CPU to 24 MHz.
If multiple resets are undesirable for slow power ramps, then
firmware must do the following:
■ Set the Low Voltage Detection circuit (Register LVDCR 0x1E3,
VM[2:0]) for one of the set points above the POR (VM[2:0] =
110 b ~4.73 V or 111b ~4.82 V).
Document Number: 38-08035 Rev. *Q
Page 72 of 91
CY7C63310, CY7C638xx
Maximum Total Sink Current into Port 0
and Port 1 pins ........................................................... 70 mA
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Maximum Total Source Output Current
into GPIO Pins ............................................................ 30 mA
Storage Temperature ................................. –40 °C to +90 °C
Maximum On-chip Power Dissipation
on any GPIO Pin ........................................................ 50 mW
Ambient Temperature
with Power Applied ..................................... –0 °C to +70 °C
Power Dissipation .................................................... 300 mW
Static Discharge Voltage ............................................ 2200 V
Latch Up Current ..................................................... 200 mA
Supply Voltage on VCC Relative to VSS .......–0.5 V to +7.0 V
DC Input Voltage .............................–0.5 V to + VCC + 0.5 V
DC Voltage Applied to Outputs in
High-Z State .................................... –0.5 V to + VCC + 0.5 V
DC Characteristics
Description
Parameter
General
Conditions
Min
Typical
Max
Unit
VCC1
VCC2
VCC3
VCC4
Operating voltage
Operating voltage
Operating voltage
Operating voltage
No USB activity, CPU speed < 12 MHz
USB activity, CPU speed < 12 MHz
Flash programming
4.0
4.35
4.0
–
–
–
–
5.5
5.25
5.5
V
V
V
V
No USB activity, CPU speed is
between 12 MHz and 24 MHz
4.75
5.5
TFP
Operating temp
Flash programming
0
–
–
–
70
40
°C
ICC1
VCC operating supply current
VCC = 5.25 V, no GPIO loading,
24 MHz
mA
ICC2
ISB1
VCC operating supply current
Standby current
VCC = 5.0 V, no GPIO loading, 6 MHz
–
–
10
–
mA
Internal and external oscillators,
bandgap, flash, CPU clock, timer
clock, USB clock all disabled
10
A
Low Voltage Detect
VLVD Low-voltage detect trip voltage
(8 programmable trip points)
3.3V Regulator
IVREG Max regulator output current
IKA
–
2.681
–
4.872
V
4.35 V < VCC < 5.5 V
–
–
–
–
125
20
mA
Keep alive current
When regulator is disabled with
“keep alive” enable
A
VKA
Keep alive voltage
VREG output voltage
Keep alive bit set in VREGCR
2.35
3.0
–
–
3.8
3.6
V
V
VREG1
VCC > 4.35 V, 0 < temp < 40 °C,
25 mA < IVREG < 125 mA (3.3V ± 8%)
T = 0 to 70 °C
VREG2
VREG output voltage
VCC > 4.35 V, 0 < temp < 40 °C,
1 mA < IVREG < 25 mA (3.3V ± 4%)
T = 0 to 40 °C
3.15
–
3.45
V
CLOAD
LNREG
LDREG
Capacitive load on Vreg pin
Line regulation
–
–
–
1
–
–
–
–
–
2
1
F
%/V
Load regulation
0.04
%/mA
USB Interface
VON
Static output high
Static output low
15 K ± 5% Ohm to VSS
RUP is enabled
2.8
–
–
–
3.6
0.3
V
V
VOFF
Document Number: 38-08035 Rev. *Q
Page 73 of 91
CY7C63310, CY7C638xx
DC Characteristics (continued)
Description
Parameter
General
Conditions
Min
Typical
Max
Unit
VDI
VCM
VSE
CIN
IIO
Differential input sensitivity
–
–
–
–
0.2
0.8
0.8
–
–
–
–
–
–
–
2.5
2
V
V
Differential input common mode range
Single ended receiver threshold
Transceiver capacitance
V
20
10
pF
A
Hi-Z state data line leakage
0V < VIN < 3.3 V
–10
PS/2 Interface
VOLP
RPS2
Static output low
Internal PS/2 pull-up resistance
SDATA or SCLK pins
–
3
–
–
0.4
7
V
SDATA, SCLK pins, PS/2 Enabled
K
General Purpose IO Interface
RUP
Pull-up resistance
4
–
–
12
K
VICR
Input threshold voltage low, CMOS
mode[8]
Low to High edge
High to Low edge
High to low edge
40%
65%
VCC
VICF
VHC
Input threshold voltage low, CMOS
mode[8]
30%
3%
–
–
55%
10%
0.8
VCC
VCC
Input hysteresis voltage, CMOS
Mode[8]
VILTTL
VIHTTL
VOL1
Input low voltage, TTL mode[9]
Input high voltage, TTL mode[9]
Output low voltage, high drive[7]
Output low voltage, high drive[7]
Output low voltage, low drive[8]
Output high voltage[8]
I/O pin Supply = 4.0–5.5 V
I/O pin Supply = 4.0–5.5 V
IOL1 = 50 mA
–
–
–
–
–
–
–
V
V
2.0
–
0.8
0.4
0.4
–
V
VOL2
IOL1 = 25 mA
–
V
VOL3
IOL2 = 8 mA
–
VCC –0.5
–
V
VOH
IOH = 2 mA
V
CLOAD
Maximum load capacitance[9]
–
50
pF
Notes
7. Available only in CY7C638xx P1.3, P1.4, P1.5, P1.6, P1.7.
8. Except for pins P1.0 and P1.1 in the GPIO mode.
9. Except for pins P1.0 and P1.1.
Document Number: 38-08035 Rev. *Q
Page 74 of 91
CY7C63310, CY7C638xx
AC Characteristics
Parameter
Clock
Description
Conditions
Min
Typical
Max
Unit
TECLKDC
TECLK1
External clock duty cycle
External clock frequency
–
45
–
–
55
24
%
External clock is the source of the
CPUCLK
0.187
MHz
TECLK2
External clock frequency
External clock is not the source of the
CPUCLK
0
–
24
MHz
FIMO1
FIMO2
FILO1
FILO2
Internal main oscillator frequency
Internal main oscillator frequency
Internal low power oscillator
Internal low power oscillator
No USB present
With USB present
Normal mode
22.8
23.64
29.44
35.84
–
–
–
–
25.2
24.3
MHz
MHz
kHz
kHz
37.12
47.36
Low power mode
3.3 V Regulator
VORIP
USB Driver
TR1
Output ripple voltage
10 Hz to 100 MHz at CLOAD = 1 F
–
–
200
mVp-p
Transition rise time
CLOAD = 200 pF
CLOAD = 600 pF
CLOAD = 200 pF
CLOAD = 600 pF
–
75
75
–
–
–
–
–
–
–
ns
ns
ns
ns
%
V
TR2
Transition rise time
300
TF1
Transition fall time
TF2
Transition fall time
300
125
2.0
TR
Rise/fall time matching
Output signal crossover voltage
80
VCRS
–
1.3
USB Data Timing
TDRATE
TDJR1
TDJR2
TDEOP
TEOPR1
TEOPR2
TEOPT
TUDJ1
TUDJ2
TLST
Low speed data rate
Average Bit Rate (1.5 Mbps ± 1.5%) 1.4775
–
–
–
–
–
–
–
–
–
–
1.5225 Mbps
Receiver data jitter tolerance
Receiver data jitter tolerance
Differential to EOP transition skew
EOP width at receiver
To next transition
To pair transition
–75
–45
–40
75
45
ns
ns
ns
ns
ns
s
ns
ns
ns
–
–
100
330
Rejects as EOP
Accept as EOP
EOP width at receiver
675
1.25
–95
–95
–
Source EOP width
1.5
95
Differential driver jitter
To next transition
To pair transition
Differential driver jitter
95
Width of SE0 during diff. transition
–
–
210
Non-USB Mode Driver Characteristics
TFPS2 SDATA/SCK transition fall time
GPIO Timing
TR_GPIO
Output rise time[8]
50
–
300
ns
Measured between 10 and 90%
Vdd/Vreg with 50 pF load
–
–
–
–
50
15
ns
ns
TF_GPIO
Output fall time[8]
Measured between 10 and 90%
Vdd/Vreg with 50 pF load
Document Number: 38-08035 Rev. *Q
Page 75 of 91
CY7C63310, CY7C638xx
AC Characteristics (continued)
Parameter
SPI Timing
TSMCK
Description
Conditions
Min
Typical
Max
Unit
SPI master clock rate
FCPUCLK/6
–
–
–
–
–
–
–
2
2.2
–
MHz
MHz
ns
TSSCK
SPI slave clock rate
SPI clock high time
SPI clock low time
–
–
TSCKH
High for CPOL = 0, Low for CPOL = 1
Low for CPOL = 0, High for CPOL = 1
SCK to data valid
125
125
–25
100
TSCKL
–
ns
TMDO
Master data output time[10]
50
–
ns
TMDO1
Master data output time,
First bit with CPHA = 0
Time before leading SCK edge
ns
TMSU
TMHD
TSSU
TSHD
TSDO
TSDO1
Master input data setup time
Master input data hold time
Slave input data setup time
Slave input data hold time
Slave data output time
–
50
50
50
50
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
–
–
–
–
–
SCK to data valid
Time after SS LOW to data valid
100
100
Slave data output time,
First bit with CPHA = 0
–
TSSS
TSSH
Slave select setup time
Slave select hold time
Before first SCK edge
After last SCK edge
150
150
–
–
–
–
ns
ns
Note
10. In Master mode, first bit is available 0.5 SPICLK cycle before Master clock edge available on the SCLK pin.
Document Number: 38-08035 Rev. *Q
Page 76 of 91
CY7C63310, CY7C638xx
Figure 20. Clock Timing
TCYC
TCH
CLOCK
90%
TCL
Figure 21. GPIO Timing Diagram
GPIO Pin Output
Voltage
10%
TR_GPIO
TF_GPIO
Figure 22. USB Data Signal Timing
TF
TR
D
D
Voh
90%
90%
Vcrs
10%
10%
Vol
Figure 23. Receiver Jitter Tolerance
TPERIOD
Differential
Data Lines
TJR
TJR1
TJR2
Consecutive
Transitions
N * TPERIOD + TJR1
Paired
Transitions
N * TPERIOD + TJR2
Document Number: 38-08035 Rev. *Q
Page 77 of 91
CY7C63310, CY7C638xx
Figure 24. Differential to EOP Transition Skew and EOP Width
TPERIOD
Crossover Point
Extended
Crossover
Point
Differential
Data Lines
Diff. Data to
SE0 Skew
N * TPERIOD + TDEOP
Source EOP Width: TEOPT
Receiver EOP Width: TEOPR1, TEOPR2
Figure 25. Differential Data Jitter
TPERIOD
Crossover
Points
Differential
Data Lines
Consecutive
Transitions
N * TPERIOD + TxJR1
Paired
Transitions
N * TPERIOD + TxJR2
Document Number: 38-08035 Rev. *Q
Page 78 of 91
CY7C63310, CY7C638xx
Figure 26. SPI Master Timing, CPHA = 1
(SS is under firmware control in SPI Master mode)
SS
TSCKL
SCK (CPOL=0)
TSCKH
SCK (CPOL=1)
MOSI
TMDO
MSB
LSB
LSB
MSB
MISO
TMSU TMHD
Figure 27. SPI Slave Timing, CPHA = 1
SS
TSSS
TSSH
TSCKL
SCK (CPOL=0)
TSCKH
SCK (CPOL=1)
MOSI
MSB
LSB
TSSU TSHD
MSB
TSDO
LSB
MISO
Document Number: 38-08035 Rev. *Q
Page 79 of 91
CY7C63310, CY7C638xx
Figure 28. SPI Master Timing, CPHA = 0
(SS is under firmware control in SPI Master mode)
SS
TSCKL
SCK (CPOL=0)
SCK (CPOL=1)
TSCKH
TMDO
TMDO1
MSB
LSB
MOSI
MISO
MSB
LSB
TMSU TMHD
Figure 29. SPI Slave Timing, CPHA = 0
SS
TSSH
TSSS
TSCKL
SCK (CPOL=0)
TSCKH
SCK (CPOL=1)
MOSI
MSB
LSB
TSHD
TSSU
TSDO
TSDO1
MISO
MSB
LSB
Document Number: 38-08035 Rev. *Q
Page 80 of 91
CY7C63310, CY7C638xx
Ordering Information
Ordering Code
CY7C63310-SXC
FLASH Size
RAM Size
128
Package Type
3K
4K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
16-pin SOIC
16-pin SOIC
16-pin SOIC
CY7C63801-SXC
256
CY7C63803-SXC
256
CY7C63803-SXCT
CY7C63813-PXC
256
16-pin SOIC, Tape and Reel
18-pin PDIP
256
CY7C63813-SXC
256
18-pin SOIC
CY7C63823-QXC
256
24-pin QSOP
CY7C63823-SXC
256
24-pin SOIC
CY7C63823-SXCT
CY7C63803-LQXC
CY7C63833-LTXC
CY7C63833-LTXCT
Ordering Code Definitions
256
24-pin SOIC, Tape and Reel
24-pin QFN Sawn
32-pin QFN Sawn
32-pin QFN Sawn, Tape and Reel
256
256
256
CY
7 C XXXXX XX X CT
Temperature Grade: C = Commercial, I = Industrial
Pb-free
Package Type
Family
Technology: CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Package Handling
Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving
the factory. A label on the packaging has details about actual bake temperature and the minimum bake time to remove this moisture.
The maximum bake time is the aggregate time that the parts are exposed to the bake temperature. Exceeding this exposure time may
degrade device reliability.
Parameter
TBAKETEMP
TBAKETIME
Description
Bake temperature
Bake time
Min
Typical
125
Max
See package label
72
Unit
°C
–
See package label
–
hours
Document Number: 38-08035 Rev. *Q
Page 81 of 91
CY7C63310, CY7C638xx
Package Diagrams
Figure 30. 16-pin SOIC (150 Mils) S16.15/SZ16.15 Package Outline, 51-85068
51-85068 *E
Figure 31. 18-pin PDIP (300 Mils) P18.3 Package Outline, 51-85010
51-85010 *E
Document Number: 38-08035 Rev. *Q
Page 82 of 91
CY7C63310, CY7C638xx
Package Diagrams (continued)
Figure 32. 18-pin SOIC (0.463 × 0.300 × 0.0932 Inches) Package Outline, 51-85023
51-85023 *D
Figure 33. 24-pin SOIC (0.615 × 0.300 × 0.0932 Inches) Package Outline, 51-85025
51-85025 *E
Document Number: 38-08035 Rev. *Q
Page 83 of 91
CY7C63310, CY7C638xx
Package Diagrams (continued)
Figure 34. 24-pin QSOP (8.65 × 3.9 × 1.44 mm) O241 Package Outline, 51-85055
51-85055 *D
Figure 35. 24-pin QFN (4 × 4 × 0.55 mm) LQ24A 2.65 × 2.65 E-Pad (Sawn) Package Outline, 001-13937
001-13937 *E
Document Number: 38-08035 Rev. *Q
Page 84 of 91
CY7C63310, CY7C638xx
Package Diagrams (continued)
Figure 36. 32-pin QFN (5 × 5 × 1.0 mm) LT32B 3.5 × 3.5 E-Pad (Sawn) Package Outline, 001-30999
001-30999 *D
Document Number: 38-08035 Rev. *Q
Page 85 of 91
CY7C63310, CY7C638xx
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
CMOS
CE
complementary metal oxide semiconductor
chip enable
Unit of Measure
°C
µA
mA
ns
pF
V
degree Celsius
I/O
input/output
microampere
milliampere
nanosecond
pico Farad
volt
OE
output enable
SRAM
TSOP
WE
static random access memory
thin small outline package
write enable
W
watt
Document Number: 38-08035 Rev. *Q
Page 86 of 91
CY7C63310, CY7C638xx
Document History Page
Document Title: CY7C63310, CY7C638xx, enCoRe™ II Low Speed USB Peripheral Controller
Document Number: 38-08035
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
131323
221881
XGR
KKU
12/11/03
See ECN
New data sheet
*A
Added Register descriptions and package information, changed from
advance information to preliminary
*B
*C
271232
299179
BON
BON
See ECN
See ECN
Reformatted. Updated with the latest information
Corrected 24-PDIP pinout typo in Table on page 7 Added Table 31 on page
22. Updated Table 23 on page 17, Table 33 on page 23, Table 40 on page 33,
Table 78 on page 55, Table 80 on page 55, Table 82 on page 57. and Table
61 on page 43. Added various updates to the GPIO Section (General Purpose
I/O (GPIO) Ports on page 35) Corrected Table 63 on page 44. Corrected
Figure 26 on page 79 and Figure 27 on page 79. Added the 16-pin PDIP
package diagram (section Package Diagrams on page 82)
*D
322053
TVR
See ECN
Introduction on page 4: Removed Low-voltage reset in last paragraph. There
is no LVR, only LVD (Low voltage detect). Explained more about LVD and
POR.
Changed capture pins from P0.0,P0.1 to P0.5,P0.6.
Table 1 on page 8: Changed table heading (Removed Mnemonics and made
as Register names).
Table 23 on page 17: Included #of rows for different flash sizes.
Clock Architecture Description on page 22: Changed CPUCLK selectable
options from n=0-5,7,8 to n=0-5,7.
Clocking on page 20: Changed ITMRCLK division to 1,2,3,4. Updated the
sources to ITMRCLK, TCAPCLKs. Mentioned P17 is TTL enabled perma-
nently. Corrected FRT, PIT data write order. Updated INTCLR, INTMSK
registers in the register table also.
DC Characteristics on page 73: changed LVR to LVD included max min
programmable trip points based on char data. Updated the 50ma sink pins on
638xx, 63903. Keep-alive voltage mentioned corresponding to Keep-alive
current of 20uA. Included Notes regarding VOL,VOH on P1.0,P1.1 and TMDO
spec.
AC Characteristics on page 75: TMDO1, TSDO1 In description column changed
Phase to 0.
BON
Pinouts on page 5: Removed the VREG from the CY7C63310 and
CY7C63801 Removed SCLK and SDATA. Created a separate pinout diagram
for the CY7C63813.
Added the GPIO Block Diagram (Figure 12 on page 38)
Table 34 on page 24: Changed the Sleep Timer Clock unit from 32 kHz count
to Hz.
Table 88 on page 62: Added more descriptions to the register.
*E
*F
341277
408017
BHA
TYJ
See ECN
See ECN
Corrected VIH TTL value in DC Characteristics on page 73.
Updated VIL TTL value.
Added footnote to pin description table for D+/D– pins.
Added Typical Values to Low Voltage Detect table.
Corrected Pin label on 16-pin PDIP package.
Corrected minor typos.
Table on page 7: Corrected pin assignment for the 24-pin QSOP package -
GPIO port 3
New Assignments: Pin 19 assigned to P3.0 and pin 20 to P3.1
Table 83 on page 58: INT_MASK1 changed to 0xE1
Table 84 on page 59: INT_MASK0 changed to 0xE0
Register Summary on page 69: Register Summary, address E0 assigned to
INT_MASK0 and address E1 assigned to INT_MASK1
Document Number: 38-08035 Rev. *Q
Page 87 of 91
CY7C63310, CY7C638xx
Document History Page (continued)
Document Title: CY7C63310, CY7C638xx, enCoRe™ II Low Speed USB Peripheral Controller
Document Number: 38-08035
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*G
424790
TYJ
See ECN
Minor text changes to make document more readable
Removed CY7C639xx
Removed CY7C639xx from Ordering Information on page 81
Added text concerning current draw for P0.0 and P0.1 in Table on page 7
Corrected Figure 20 on page 16 to represent single stack
Added comment about availability of 3.3V IO on P1.3-P1.6 iTable on page 7
Added information on flash endurance and data retention to section Flash on
page 15
Added block diagrams and timing diagrams
Added CY7C638xx die form diagrams, Pad assignment tables and Ordering
information
Keyboard references removed
CY7C63923-XC die diagram removed, removed references to the 639xx parts
Updated part numbers in the header
*H
*I
491711
504691
TYJ
TYJ
See ECN
See ECN
Minor text changes
32-QFN part added
Removed 638xx die diagram and die form pad assignment
Removed GPIO port 4 configuration details
Corrected GPIO characteristics of P0.0 and P0.1 to P1.0 and P1.1 respec-
tively
Minor text changes
Removed all residual references to external crystal oscillator and GPIO4
Documented the dedicated 3.3V regulator for USB transceiver
Documented bandgap/voltage regulator behavior on wake up
Voltage regulator line/load regulation documented
USB Active and PS2 Data low interrupt trigger conditions documented.
GPIO capacitance and timing diagram included
Method to clear Capture Interrupt Status bit discussed
Sleep and Wake up sequence documented.
EP1MODE/EP2MODE register issue discussed.
Document Number: 38-08035 Rev. *Q
Page 88 of 91
CY7C63310, CY7C638xx
Document History Page (continued)
Document Title: CY7C63310, CY7C638xx, enCoRe™ II Low Speed USB Peripheral Controller
Document Number: 38-08035
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*J
2147747
VGT /
AESA
05/20/2008 TID number entered on page 1. Also changed the sentence“Highcurrentdrive
on GPIO pins” to “2mA source current on all GPIO pins”.
Point 26.0, DC Characteristics on page 73, changed the min. and max.
voltages of Vcc3 (line 3) to 4.0 and 5.5 respectively.
Point 19.0, title modified to “Regulator Output”, instead of “USB Regulator
Output”.
Added a point # 3 under Point 17.3.
Changed the storage temperature to “-40C to 90C” in Point # 25.0 (Absolute
Maximum Ratings on page 73).
Added the die form after the end of page 4.
In line 3, under “Bit 2: P1.2/VREG” of Table 44 on page 36, the changes made
were “CY7C63310/CY7C638xx” instead of “CY7C63813.
In line 1, under “Bit 6: USB CLK/2 Disable” of Table 33 on page 23, entered
the word “clock” instead of “crystal oscillator”.
Entered the word “Reserved” and left its corresponding fields blank in the
sub-table under “Bit[2:0]: VM[2:0]” of Table 40 on page 33.
Under “Bit [7:6]: Sleep Duty Cycle[1:0]”, made the following changes:
0 0 = 1/128 periods of the internal 32 kHz low speed oscillator.
0 1 = 1/512 periods of the internal 32 kHz low speed oscillator.
1 0 = 1/32 periods of the internal 32 kHz low speed oscillator.
1 1 = 1/8 periods of the internal 32 kHz low speed oscillator.
In Table 79 on page 55, in line 4, deleted “57”, and made the word “AND” to
lower case.
Added 32-Pin Sawn QFN Pin Diagram, package diagram, and ordering
information.
Removed references to 3V for the 32 kHz oscillator in Section 10. Clocking.
Added information on SROM Table read - section 9.6.
Updated section 12.3 Low-Power in Sleep Mode - Included Set P10CR[1] -
during non-USB mode operations.
Added section 25 - Voltage Vs CPU Frequency char.
P1DATA register information updated. Vreg can operate independent of USB
connection.
Included IMO and ILO characteristics in the AC char section.
Updated to data sheet template *E.
*K
*L
2620679
2964259
CMCC /
PYRS
12/12/08
06/29/10
Added Package Handling information
AJHA
Added partnumber CY7C63803-LQXC to the ordering information table and
added package diagram (spec 001-13937)
Removed inactive parts from ordering information table.
CY7C63310-PXC
CY7C63801-PXC
CY7C63833-LFXC
Updated package diagrams.
*M
*N
3074654
3193555
NXZ
10/29/10
03/14/11
Added Ordering Code Definition, Acronyms, and Document Conventions.
KKCN
Added part CY7C63823-3XW14C to the ordering information table.
Updated Figure 33.
*O
*P
3243324
3269535
NXZ
NXZ
04/29/2011 Added CY7C63803 24-pin QFN pinout details.
06/06/2011 Removed "CY7C63801, CY7C63310 16-Pin PDIP" from Figure 5-1
Removed “16 PDIP” column from Table 5-2
Removed Figure 5-3 (32-pin QFN)
Removed Figure 31-1 (16-pin PDIP) and Figure 31-8 (32-pin QFN)
Updated description field for P1.0/D+ and P1.1/D- in Table , “Pin Descrip-
tions,” on page 7
Document Number: 38-08035 Rev. *Q
Page 89 of 91
CY7C63310, CY7C638xx
Document History Page (continued)
Document Title: CY7C63310, CY7C638xx, enCoRe™ II Low Speed USB Peripheral Controller
Document Number: 38-08035
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*Q
3815825
ANKC
11/19/2012 Updated Pinouts (removed figure “CY7C63823 Die Form” and table “Die Pad
Summary”).
Updated Pin Descriptions.
Updated Instruction Set Summary.
Updated Memory Organization (Updated Table 24).
Updated Clocking (Updated Figure 7).
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams (spec 51-85068 (Changed revision from *C to
*E), spec 51-85010 (Changed revision from *C to *E), spec 51-85023
(Changed revision from *C to *D), spec 51-85055 (Changed revision from *C
to *D), spec 001-13937 (Changed revision from *C to *E), spec 001-30999
(Changed revision from *C to *D)).
Updated in new template.
Document Number: 38-08035 Rev. *Q
Page 90 of 91
CY7C63310, CY7C638xx
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/psoc
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2003-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-08035 Rev. *Q
Revised November 19, 2012
Page 91 of 91
®
®
PSoC Designer™ is a trademark and PSoC and CapSense are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may
be the trademarks of their respective holders.
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