CY7C65221-24LTXI [CYPRESS]
Dual I2C Slave Bridge;
| 型号： | CY7C65221-24LTXI |
| 厂家： | 
CYPRESS |
| 描述： | Dual I2C Slave Bridge |
| 文件： | 总24页 (文件大小：534K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C65221
Dual I2C Slave Bridge
Dual I2
C Slave Bridge
■ RoHS compliant package
Features
■ 24-pin QFN (4 mm × 4 mm, 0.5 mm pitch, 0.55 mm height)
■ Ordering part number CY7C65221-24LTXI
■ Dual channel I2C slaves
❐ 400 kHz I2C clock rate
❐ 1 byte sub-addressing
❐ 256 byte register space
Applications
❐ Configurable slave port base address
❐ Interrupt line only for I2C_B (INT_B)
■ Test and measurement systems
■ Industrial
■ Clocking: Integrated 48 MHz clock oscillator
■ Operating voltage: 1.71 to 5.5 V
Functional Description
■ Operating temperature: –40 °C to 85 °C
■ ESD protection: 2.2 kV HBM
CY7C65221 is an I2C bus bridge. It functions as an I2C slave for
two masters, allowing them exchange data. This bridge is to
have a communication path between the Cypress FX3S RAID
solution and the Dell board controller.
Block Diagram
VDDD
VCCD
Voltage
Regulator
RESET
nXRES
Controller
Serial
Communication
Block
Serial
Communication
Block
8 bytes
TX
FIFO
8 bytes
TX
FIFO
I2C_SCL_A
I2C_SDA_A
I2C_SCL_B
I2C_SDA_B
INT_B#
B_ADDR0
B_ADDR1
I2C
Slave
PORT A
I2C
Slave
PORT B
A_ADDR0
A_ADDR1
8 bytes
RX
FIFO
8 bytes
RX
FIFO
256 byte Register
Space
nFS
GPIO
Cypress Semiconductor Corporation
Document Number: 001-89547 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 7, 2017
CY7C65221
Contents
Pin Configuration .............................................................3
Pin Description .................................................................4
Functional Overview ........................................................5
Bridge register space ..................................................5
Bridge I2C Interface ..................................................13
I2C slave address ......................................................14
Bridge BMC-FX3S Communication ...........................15
Data protection ..........................................................16
Clock stretching .........................................................16
Register write-enable masks .....................................16
Bridge Firmware upgrade ..........................................16
Electrical Specifications ................................................17
Absolute Maximum Ratings .......................................17
Operating Conditions .................................................17
Device-Level Specifications ......................................17
GPIO .........................................................................18
nXRES .......................................................................19
I2C Specifications ......................................................19
Flash Memory Specifications ....................................19
Ordering Information ......................................................20
Ordering Code Definitions .........................................20
Package Information ......................................................21
Acronyms ........................................................................22
Document Conventions .................................................22
Units of Measure .......................................................22
Document History Page .................................................23
Sales, Solutions, and Legal Information ......................24
Worldwide Sales and Design Support .......................24
Products ....................................................................24
PSoC®Solutions .......................................................24
Cypress Developer Community .................................24
Technical Support .....................................................24
Document Number: 001-89547 Rev. *C
Page 2 of 24
CY7C65221
Pin Configuration
24 23 22 21 20 19
NC
NC
18
17
B_ADDR0
VSSA
1
2
CY7C65221
24-pin QFN
TOP View
VSSD
I2C_SCL_A
I2C_SDA_A
3
4
5
6
16
15
VSSD
VDDD
XRES#
14
13
SWD Data
VSSD
7
8
9
10 11 12
Document Number: 001-89547 Rev. *C
Page 3 of 24
CY7C65221
Pin Description
Pin
1
Type
NC
Name
NC
Description
2
NC
NC
3
Power
Input
VSSD
Digital Ground
4
I2C_SCL_A
I2C_SDA_A
SWD Data
SWD Clock
A_ADDR0
A_ADDR1
VSSD
Port A I2C Clock. 400 KHz max
Port A I2C data
5
Input / Output
Input / Output
Input
6
In-system serial programming and debug data
In-system serial programming and debug Clock
Port A I2C base address select, bit 0
Port A I2C base address select, bit 1
Digital Ground
7
8
Input
9
Input
10
11
12
Power
Power
Power
VSSD
Digital Ground
VCCD
This pin is an output of an internal regulator and cannot drive external devices.
Decouple this pin to ground using 1 µF capacitor when the VCCIO voltage is greater
then 2 V. Connect this pin to VCCIO supply when the VCCIO voltage is less then 2 V.
13
14
Power
Input
VSSD
Digital Ground
XRES#
Chip reset, active low. Can be left unconnected or have a pull-up resistor connected
to VCCIO supply.
15
16
17
18
19
20
21
22
23
24
Power
Power
VDDD
VSSD
Supply to the device core. 3.3 V to 5.5 V
Digital Ground
Power
VSSA
Analog Ground
Input
B_ADDR0
B_ADDR1
INT_B#
Port B I2C base address select, bit 0
Port B I2C base address select, bit 0
Port B I2C interrupt request
Port B I2C Clock. 400 KHz max
Port B I2C data
Input
Output
Input
I2C_SCL_B
I2C_SDA_B
FS#
Input / Output
Input / Output
Power
Fail safe Input
VDDD
Supply to the device core and interface, 1.71 V to 5.5 V
Document Number: 001-89547 Rev. *C
Page 4 of 24
CY7C65221
only provides the required field mask option for the data bytes
and does not decode the writes to this address space except for
Functional Overview
two
specific
registers
provided
by
the
Bridge
Bridge register space
(I2C_A_WRITE_ADDR and I2C_A_WRITE_SIZE). Whenever
there is a write operation from the BMC interface, the Bridge
updates I2C_A_WRITE_ADDR and I2C_A_WRITE_SIZE
registers and interrupts FX3S by asserting the INT_B line. The
I2C_A interface shall be clock stretched until the FX3S
de-asserts the INT_B line.
The 256 byte address space is divided into three areas:
BMC-FX3S register space, Bridge register space and Bridge
buffer space. The legend used in the following register definitions
are:
Table 1. Register Space Legend
Bridge register space
Legend
Description
I2C_A (BMC) interface
The Bridge register space occupies locations 0x1E, 0x1F and
0x60-0x7F. This space is maintained by the Bridge and allows
for configuration and operation of the Bridge. These are special
registers which are expected to be used only from the I2C_B
(FX3S) interface. However, the Bridge does not prevent access
A
B
I2C_B (FX3S) interface
Bridge
Br
RW
RS
Read write access
Read and Set only
to
these
registers
from
I2C_A
interface.
The
I2C_A_WRITE_ADDR and I2C_A_WRITE_SIZE registers are
placed at 0x1E and 0x1F so that FX3S can read the complete
32 byte BMC register space in a single read.
BMC-FX3S register space
The following are the Bridge special function registers:
The BMC-FX3S register space occupies locations 0x00 to 0x5F.
This space is maintained by FX3S (I2C_B) interface. The Bridge
I2C_A_WRITE_ADDR
This register along with I2C_A_WRITE_SIZE register allows FX3S to easily identify the last modified address from the BMC side. The
Bridge updates the ADDR field whenever BMC finishes a write to the BMC-FX3S register space on I2C_A interface.
I2C_A_WRITE_ADDR
Field Field Name
Bit [7:0] ADDR
0x1E
A
Br
B
Description
R
RW
R
The register holds the last updated start
address from I2C_A interface to BMC register
space. This allows FX3S to identify the write
location from BMC side.
I2C_A_WRITE_SIZE
This register along with I2C_A_WRITE_ADDR register allows FX3S to easily identify the last modified register space from the BMC
side. The Bridge updates this register whenever the BMC finishes a write to the BMC-FX3SA register space on I2C_A interface.
I2C_A_WRITE_SIZE
Field Field Name
Bit [7:0] SIZE
0x1F
A
Br
B
Description
R
RW
R
Theregister holds the size of the last write from
I2C_A interface to BMC register space. This
allows FX3S to identify the write location from
BMC side.
Document Number: 001-89547 Rev. *C
Page 5 of 24
CY7C65221
BRIDGE_VERSION
The register holds the Bridge firmware version information. This is a read-only field from both I2C interfaces. This field can be used
to determine whether the Bridge firmware matches the FX3S firmware and whether the Bridge requires a firmware upgrade.
BRIDGE_VERSION
Field Field Name
Byte[0]
0x60–0x63
Description
A
Br
B
MAJOR_ VERSION
MINOR_ VERSION
PATCH_ VERSION
R
–
R
The byte represents the major firmware
revision number.
Byte[1]
R
R
–
–
R
R
The byte represents the minor firmware
revision number.
Byte[3-2]
The word represents the patch revision
number.
BRIDGE_BUILD
The register holds the Bridge firmware build number. This is a read-only register from the I2C interfaces.
BRIDGE_BUILD
0x64–0x67
Description
Field
Byte[3-0]
Field Name
A
Br
B
BUILD_ NUMBER
R
–
R
The byte represents the Bridge firmware build
number.
BRIDGE_MODE
The register holds the active firmware number. This is a read-only register from the I2C interfaces.
BRIDGE_MODE
Field Field Name
Bit [7:0] OP_MODE
0x68
A
Br
B
Description
R
–
R
0 – Primary (fail-safe) firmware active
1 – Secondary firmware active.
Document Number: 001-89547 Rev. *C
Page 6 of 24
CY7C65221
I2C_CTRL
The register allows the FX3S interface to configure I2C_A interface. The lower nibble holds configuration for I2C_A interface and
upper nibble holds configuration information for I2C_B interface.
I2C_CTRL
Field Name
0x69
Field
Bit [0]
A
Br
B
Description
I2C_A_ENABLE
R
–
RW 0 – Disable I2C_A interface. When
disabled, the interface shall NAK any
request.
1 – Enable I2C_A interface. The reset
value of this field is 0.
Bit [4:1]
Bit [5]
Reserved
R
R
–
–
R
Reserved.
INT_B_CLEAR
RW This bit is used by FX3S interface to
de-assert the INT_B line.
0 – Do nothing
1 – Bridge shall de-assert INT_B and clear
this bit.
Read of this bit shall indicate the current
status of the INTR line. If INTR line is
asserted the bit shall be set, otherwise it
shall be 0.
Bit [7:6]
Reserved
R
–
R
Reserved.
BRIDGE_RESET
The register allows the I2C interfaces to reset the Bridge. The reset operation only performs a soft reset and a hard reset can only be
done by asserting the XRES line on the Bridge.
BRIDGE_RESET
Field Name
RESET_ SIGNATURE RW
0x6A–0x6B
Description
Field
Byte [0]
A
Br
B
RW
RW The Bridge shall allow reset only if this
byte is loaded with 0xAD (~R). The default
value for this field is 0. Once the Bridge
acts on the reset request, the field is again
reset to 0. This is to prevent spurious
reset.
Byte[1]: Bit [0]
RESET
RW
R
–
–
RW Request a reset.
0 – Do nothing
1 – Request for a reset. A read to this field
will always return 0.
Byte[1]: Bit [7:1] Reserved
R
Reserved.
Document Number: 001-89547 Rev. *C
Page 7 of 24
CY7C65221
BRIDGE_MODE_RQT
The register allows the I2C interfaces to request to Bridge to jump to fail-safe mode. This operation shall result in resetting the Bridge.
On subsequent power cycle or reset, the device shall boot back to secondary image if a valid secondary image is available. This
register is required for doing a firmware upgrade.
BRIDGE_MODE_RQT
Field Field Name
0x6C–0x6D
Description
A
Br
B
Byte [0]
MODE_RQT_
SIGNATURE
RW
RW
RW The Bridge shall honor the request only if
this byte is loaded with 0xB2 (~M). The
default value for this field is 0. Once the
Bridge acts on the request, the field is
again reset to 0.
Byte[1]: Bit [0]
MODE_RQT
RW
–
–
RW Request a fail-safe entry.
0 – Do nothing
1 – Request for a fail-safe entry. The
Bridge shall jump to primary firmware if
running in secondary firmware mode.
Otherwise nothing is done.
A read to this field will always return 0.
Byte[1]: Bit [7:1] Reserved
R
R
Reserved.
Document Number: 001-89547 Rev. *C
Page 8 of 24
CY7C65221
BRIDGE_SPL_RQT
The register allows for various special functions which use the upper 128 byte buffer area of the Bridge. The I2C interfaces are first
expected to load the information into the upper 128 byte buffer area and then indicate the completion by writing to this register. Only
one bit in the register can be set at a time. If more than one bit is set, the Bridge shall treat it as a bad request. On completion of a
request, the Bridge shall clear the request bits and then load the status of the request into the signature field. If the request was
completed successfully, the signature field shall be made zero. The field shall be non-zero if the request failed. The return error codes
are:
Error code
SUCCESS
Value
Description
Request was completed successfully.
Request had bad arguments.
Device is not ready to take the request.
Request handling timed out.
0
1
BAD_ARGUMENT
NOT_CONFIGURED
TIMEOUT
3
8
NOT_SUPPORTED
ERROR_FAILURE
10
14
Request currently not supported.
General request failure.
BRIDGE_SPL_RQT
Field Name
0x6E–0x6F
Description
Field
Byte [0]
A
Br
B
SPL_RQT_ SIGNATURE
RW
RW
RW The Bridge shall honor the request only if this byte is
loaded with 0xB9 (~F). The default value for this field is 0.
Once the Bridge acts on the request, the field is again
reset to 0.
Byte[1]: Bit [0]
Byte[1]: Bit [1]
Byte[1]: Bit [2]
FW_IMG_RQT
RW
RW
RW
–
–
–
RW Indicate to the Bridge that 128 bytes of firmware image for
upgrade has been loaded into the buffer area.
0 – Do nothing
1 – FW image indication. The Bridge shall clear the field
on programming the flash.
A read to this field will always return 0.
I2C_A_MASK_ RQT
I2C_B_MASK_ RQT
RW Indicate to the Bridge that 96 bytes of field write enable
mask for I2C_A interface is loaded into the buffer area.
0 – Do nothing
1 – Buffer available indication. The Bridge shall clear the
field on programming the flash.
A read to this field will always return 0.
RW Indicate to the Bridge that 96 bytes of field write enable
mask for I2C_B interface is loaded into the buffer area.
0 – Do nothing
1 – Buffer available indication. The Bridge shall clear the
field on programming the flash.
A read to this field will always return 0.
Byte[1]: Bit [3]
Byte[1]: Bit [4]
FW_IMG_ ABORT
RW
R
–
–
RW Abort any in progress firmware upgrade operation. After
this the secondary image cannot be used.
FW_IMG_ IN_PROG
R
Firmware upgrade is in progress. The secondary image is
valid only after the complete image is sent across over the
I2C interface. This bit is set when Bridge starts updating
the first section of the secondary image and is cleared on
receiving the last section or in case of any error.
Byte[1]: Bit [7:5] Reserved
R
–
R
Reserved.
Document Number: 001-89547 Rev. *C
Page 9 of 24
CY7C65221
BRIDGE_MEMORY_OP
This register allows the bridge to read and update the Flash and RAM locations. For write operation, the I2C master shall first load
the data in the buffer area and then indicate the completion by writing to this register. For read operation, the I2C master is first
expected to write to the register with read request. Bridge shall update the buffer area with the requested data bytes. Similar to
BRIDGE_SPL_RQT, on completion of a request, the Bridge shall clear the request bits and then load the status of the request into
the signature field. If the request was completed successfully, the signature field shall be made zero. The field shall be non zero, if
the request failed. For flash operation, data size shall always be 128(Flash Row Size). The flash address should be a 128 bytes
multiple. Flash operations are supported only in FAIL SAFE mode.
BRIDGE_MEMORY_OP
Field Name
0x72–0x78
Field
Byte [0]
A
Br
B
Description
MEMORY_OP_ SIGNATURE
R
RW
RW The Bridge shall honor the request only if
this byte is loaded with 0xBA. The default
value for this field is 0. Once the Bridge acts
on the request, the field is again reset to 0.
Byte[1]: Bit [0]
Byte[1]: Bit [1]
WRITE_READ
R
R
–
–
RW Indicates to the bridge if the request is for
memory read or write.
0 – Read
1 – Write
A read to this field will always return 0.
FLASH_RAM
RW Indicates to the bridge if the request is for
FLASH or RAM operation.
0 – RAM
1 – FLASH
A read to this field will always return 0.
Byte[1]: Bit [2:7] Reserved
R
R
–
–
R
Reserved.
Byte[2:5]:
ADDRESS
RW The memory address for read or update. As
mentioned above, the address shall be
multiple of 128 for FLASH operations. For
RAM operations, address should be 32 bit
aligned.
Byte[6]:
COUNT
R
–
RW The count of bytes (4 Bytes) to read or write.
For FLASH operation, this field is ignored as
flash operations shall be 128 bytes only. For
RAM operations, the count shall be 32 or
less as the size of bridge buffer area is 128
bytes (32 words).
Document Number: 001-89547 Rev. *C
Page 10 of 24
CY7C65221
BRIDGE_TIMEOUT_RQT
This register allows the bridge to update the timeout duration for both the interfaces. The default timeout is 500 ms. On completion of
a request, bridge shall load the status of the request into the signature field. If the request was completed successfully, the signature
field shall be made zero. The field shall be non zero, if the request failed.
BRIDGE_TIMEOUT_RQT
Field Name
0x7B–0x7D
Field
Byte [0]
A
Br
B
Description
TIMEOUT_RQT SIGNATURE
R
RW
RW The Bridge shall honor the request only if
this byte is loaded with 0xBB. The default
value for this field is 0. Once the Bridge
successfully acts on the request, the field is
again reset to 0.
Byte[1:2]
TIMEOUT_VALUE (ms)
R
–
RW This field shall be set with the timeout value.
The minimum timeout supported by the
bridge is 100ms. Any value less than that
will be flagged as an error. To disable
timeout detection feature this field shall be
set with 0xFFFF. The timeout value shall be
updated after the completion of the current
I2C write request and I2C master on both
interface shall read this field to determine
the current timeout value The byte order is
little endian.
Document Number: 001-89547 Rev. *C
Page 11 of 24
CY7C65221
BRIDGE_STATUS
This register shall be used to determine the current status of both I2C interfaces. It shall flag any I2C bus, timeout and state machine
errors detected on the interfaces. The lower nibble shall be reserved for I2C_A interface and the upper nibble for I2C_B interface. In
case of any error bridge shall reset the corresponding I2C interface.
BRIDGE_STATUS
Field Name
0x7E
Field
A
Br
B
Description
Bit[0]
I2C_A_TIMEOUT_ERROR
R
RW
RW The bit shall be set if a timeout error is
encounteredonI2C_Ainterface. Thebridge
shall de-assert the INT _B line and reset the
I2C_A interface. Write with 1 to clear the bit.
Bit[1]
Bit[2]
I2C_A_BUS_ERROR
R
R
RW
RW
RW This bit shall be set by bridge if an I2C Bus
error or arbitration error is detected on
I2C_A interface. Write with 1 to clear the bit.
I2C_A_INVALID_CMD_ERROR
RW This bit shall be set by bridge if a state
machine error is detected due to invalid
sequence of I2C commands from the
master on I2C_A interface. Write Restart,
Write across register boundaries and Write
rollback to 0 are examples of such error.
Write with 1 to clear the bit.
Bit[3]
Bit[4]
RESERVED
–
–
–
Reserved for future use.
I2C_B_TIMEOUT_ERROR
R
RW
RW The bit shall be set if a timeout error is
encountered on I2C_B interface. Write with
1 to clear the bit.
Bit[5]
Bit[6]
I2C_B_BUS_ERROR
R
R
RW
RW
RW This bit shall be set by bridge if an I2C Bus
error or arbitration error is detected on
I2C_B interface. Write with 1 to clear the bit.
I2C_B_INVALID_CMD_ERROR
RW This bit shall be set by bridge if a state
machine error is detected due to invalid
sequence of I2C commands from the
master on I2C_B interface. Write Restart,
Write across register boundaries and Write
rollback are examples of such error. Write
with 1 to clear the bit.
Bit[7]
RESERVED
–
–
–
Reserved for future use.
Document Number: 001-89547 Rev. *C
Page 12 of 24
CY7C65221
Bridge Buffer Space
Figure 2 shows the bus sequence for a random read operation
of two data bytes from the Bridge. The read operation consists
of two parts: 1) Address update sequence; 2) followed by read
operation. The address update sequence is essentially a write
operation without any data bytes. The read operation follows this
with a re-start signal on the bus. The read option allows for
reading one or more bytes from the Bridge from the address
specified. For read operation, if the read address overflows the
256 byte boundary, then the address shall wrap around and the
current address shall be made as zero. The read operation is not
failed in this case. This read operation model is the
recommended read operation mode as it uses re-start instead of
a start followed by a stop. On a multi-master bus, a re-start bit is
generally treated as an atomic operation and the bus is freed
only on seeing a stop bit. So the address phase and the data
phase stay in sync.
The Bridge provides 128 bytes of buffer space (0x80–0xFF). The
buffer area is used for FX3S firmware upgrade.
2
Bridge I C Interface
The Bridge provides EEPROM like access to its internal registers
/ buffers. It exposes a byte addressed 8 bit register space. The
lower 128 byte space is expected to be used as control / status
registers for the Bridge communication while the upper 128 byte
space is expected to be used as data buffer space for
communication. The Bridge I2C interfaces support EEPROM like
read / writes access. The following are the operations supported
at the I2C interface:
WRITE
Figure 1. Bridge Write Sequence
SEQUENTIAL READ
S
T
A M
R S
T
W
R
I
T
E
S
T
O
P
Figure 3. Bridge Sequential Read Sequence
M
S
B
M
S
B
M
S
B
DEVICE ADDR
ADDR
S
B
DATA0
DATA1
R
E
A
D
S
T
O
P
T
A
R
T
N
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
DEVICE ADDR
A
C
K
M
S
B
M
S
B
DATA0
DATA1
Figure 1 shows the bus sequence for a write operation of two
data bytes to the Bridge. The first byte following a write preamble
shall always be the start address of the write operation. Any
subsequent data bytes shall be written down to the register area.
While the data is being received on the I2C bus, the Bridge stores
the information in a temporary buffer and updates the register
space only on receiving a stop signal on the bus. The writes are
done after validating the write and only the fields which are
write-enabled are updated. A write operation always needs to be
terminated by a stop signal and a re-start after a write operation
is not allowed. The write request allows for one or more register
location writes in a single operation. The maximum allowed write
size is 128 bytes. Any write that crosses the 256 byte boundary
shall result in a failed write and none of the bytes in the write
operation shall get updated. Any write which crosses boundaries
(BMC-FX3S register space – Bridge register space – Buffer
space), shall result in a failed write and none of the bytes in the
write operation shall get updated.
Figure 3 shows the bus sequence for a sequential read operation
of two data bytes. A sequential read allows reading data from the
current read location. The current read location gets updated on
any read / write operation. The address is incremented on every
byte read / written from / to the Bridge interface. The read
operation is similar to the random read operation but on a
multi-master bus, there shall be no guarantee that the read
address shall not get modified between transactions resulting in
wrong address location to be read back.
SET ADDRESS
Figure 4. Bridge Set Address Sequence
S
T
A
R
T
W
R
I
S
T
O
P
M
S
B
T
E
DEVICE ADDR
REG ADDR
RANDOM READ
Figure 2. Bridge Random Read Sequence
A
C
K
A
C
K
S
T
A
R
T
W
R
I
T
E
S
T
A
R
T
R
E
A
D
S
T
O
P
M
S
B
M
S
B
A
C
K
N
C
K
DEVICE ADDR
REG ADDR
DEVICE ADDR
A
C
K
A
C
K
A
C
K
M
S
B
M
S
B
DATA0
DATA1
The SET ADDRESS operation is a partial write / random read
operation, where only the address location gets updated
followed by a stop signal on the bus.
Document Number: 001-89547 Rev. *C
Page 13 of 24
CY7C65221
2
I C slave address
The Bridge I2C address is derived during boot and is not dynamically changed. The address has two components: 1) Fixed 5 MS bits
and 2) Configurable 2 LS bits. The following tables indicate the I2C slave address used for each interface.
I2C_A interface address
A_ADDR1 and A_ADDR0 are the states of the I/O lines at boot.
I2C_A Address
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
0
0
0
A_ADDR1
A_ADDR0
I2C_B interface address
B_ADDR1 and B_ADDR0 are the states of the I/O lines at boot.
I2C_A Address
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
0
0
0
B_ADDR1
B_ADDR0
Document Number: 001-89547 Rev. *C
Page 14 of 24
CY7C65221
Bridge BMC-FX3S Communication
The BMC communicates with the Bridge through the I2C_A interface while the FX3S uses the I2C_B interface. The BMC and FX3S
have full read access to the 256 byte register space of the Bridge. The BMC and FX3S have different read only fields which cannot
be updated.
Actual protocol to be used for FX3S Raid Solution is documented in “Internal Dual Secure Digital Module Specification” provided by
Dell. Figure 5 describes a typical operation sequence for a BMC request to the FX3S.
Figure 5. BMC Request Operation Sequence
BRIDGE
I2C_B MASTER
I2C_A MASTER
START REQUEST
INITIATE REQUEST
UPDATE
I2C_A_WR_ADDR
AND
I2C_A_WR_SIZE
ASSERT INT_B
READ BRIDGE
REGISTER SPACE
READ STATUS
REGISTER
PERFORM
REQUESTED
OPERATION
UPDATE STATUS
REGISTERS
SLAVE
CLOCK
STRETCH
REQUEST CLEAR
INT_B
DE-ASSERT INT_B
END REQUEST
BMC initiates a request by writing into the Bridge register space.
Once BMC completes the register write with a stop signal on the
I2C bus, the Bridge updates the register memory and then
updates the I2C_A_WRITE_ADDR and I2C_A_WRITE_SIZE
registers with information about the BMC write. Once this is
done, it initiates an interrupt to FX3S by asserting the INT_B line.
It shall then perform the requested operation and then update the
Bridge register space with the status information. Once FX3S
has updated the status register space, it is expected to clear the
INT_B interrupt. On clearing the INT_B interrupt, the Bridge shall
de-assert the INT_B line.
The BMC needs to poll the Bridge status register for completion
of the request.
FX3S on receiving an interrupt on INT_B line shall read the
Bridge register space to determine the type of request received.
Document Number: 001-89547 Rev. *C
Page 15 of 24
CY7C65221
Bridge. The Bridge uses this mask information to allow writes to
go through to the register space. The 32 byte area above this is
Bridge register information and cannot be modified. The upper
128 byte is fully writeable from both directions. Addresses 0x1E
and 0x1F are always read-only from both interfaces. The Bridge
by default allows writes to the first 96 bytes from both sides. The
mask information has to be updated by FX3S on boot every time
using the BRIDGE_SPL_RQT register based on the Dell register
space requirement. For updating the write enable mask
information for I2C_A interface, load the 96 byte mask
information into the buffer space and then set the
I2C_A_MASK_RQT bit in BRIDGE_SPL_RQT register. The
Bridge firmware on receiving the request, shall update the local
RAM copy with the new information. I2C_B interface mask
information can be updated similarly. This information is not
retained across Bridge reset and has to be loaded every time.
Data protection
The Bridge register space can be accessed from both I2C_A and
I2C_B interface. This results in possibility of the same register
being accessed at the same time from both the interface. The
Bridge allows only one interface to access the Bridge at one time.
The first access is accepted and the second interface in the
event of a contention is clock stretched in the preamble phase.
The preamble shall not be ACKd and the clock line stretched until
the first interface completes the access.
Additionally, since the Bridge status register has to be updated
by FX3S, once BMC completes a write to the lower 128 byte
area, the Bridge shall clock stretch any further request from BMC
until FX3S clears the INT_B interrupt. This allows FX3S time to
update the status register before BMC can read the status
registers.
Clock stretching
Bridge Firmware upgrade
The Bridge shall use clock stretching on both I2C interfaces until
it is ready to take any new request. The clock shall be stretched
at the following modes:
The Bridge firmware upgrade can be done by loading the
firmware image 128 byte at a time into the Bridge buffer area and
trigger the flash programming by writing to the FW_IMG_RQT bit
of the BRIDGE_SPL_RQT register. The Bridge shall decode the
firmware image and then load the data to the required location.
On receiving the last 128 byte packet of firmware image, the
Bridge shall update the checksum and signature information to
the checksum page in flash for the corresponding image.
1. At the ACK / NAK phase of preamble / data bytes.
2. After DATA ACK If the RX FIFO is full and cannot receive any
more data.
Register write-enable masks
The I2C_A interface as well as I2C_B interface has two different
write enable masks for the first 96 byte register area in the
Document Number: 001-89547 Rev. *C
Page 16 of 24
CY7C65221
Electrical Specifications
Static discharge voltage ESD protection levels:
Absolute Maximum Ratings
Exceeding maximum ratings[1] may shorten the useful life of the
device.
■ 2.2-KV HBM per JESD22-A114
Latch-up current ........................................................... 140 mA
Current per GPIO ........................................................... 25 mA
Storage temperature .................................... –55 °C to +100 °C
Ambient temperature with
Operating Conditions
power supplied (Industrial) ............................ –40 °C to +85 °C
Supply voltage to ground potential
VDDD ................................................................................. 6.0 V
TA (ambient temperature under bias)
Industrial ........................................................ –40 °C to +85 °C
VCCD ............................................................................... 1.95 V
VGPIO ....................................................................... VDDD + 0.5
V
DDD supply voltage ........................................ 1.71 V to 5.50 V
VCCD supply voltage ........................................ 1.71 V to 1.89 V
Device-Level Specifications
All specifications are valid for –40 °C TA 85 °C, TJ 100 °C, and 1.71 V to 5.50 V, except where noted.
Table 2. DC Specifications
Parameter
VDDD
Description
Min
1.71
2.0
Typ
1.80
3.3
Max
1.89
5.5
Units
Details/Conditions
VDDD supply voltage
V
V
Used to set I/O and core voltage. Set
and configure the correct voltage
range using a configuration utility for
VDDD. Default 3.3 V.
VCCD
Output voltage (for core logic)
–
1.80
–
V
Do not use this supply to drive the
external device.
• 1.71 V VDDD 1.89 V: Short the
VCCD pin with the VDDD pin
• VDDD > 2 V – connect a 1-µF
capacitor (Cefc) between the VCCD
pin and ground
Cefc
IDD1
External regulator voltage bypass
Operating Supply Current
1.00
–
1.30
7.25
1.60
12
µF
X5R ceramic or better
I2C at 400 kHz dual channel
mA
Table 3. AC Specifications
Parameter
Description
Min
Typ
Max
48.96
Units
MHz I2C Bridge
Details/Conditions
F1
Frequency
47.04
48
Note
1. Usage above the Absolute Maximum conditions may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of
time may affect device reliability. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 001-89547 Rev. *C
Page 17 of 24
CY7C65221
GPIO
Table 4. GPIO DC Specification
Parameter
Description
Min
Typ
–
Max
Units
Details/Conditions
CMOS Input
CMOS Input
[2]
VIH
Input voltage high threshold
Input voltage low threshold
LVTTL input, VDDD < 2.7 V
LVTTL input, VDDD < 2.7 V
LVTTL input, VDDD > 2.7 V
LVTTL input, VDDD > 2.7 V
0.7 × VDDD
–
V
V
V
V
V
V
V
VIL
VIH
VIL
VIH
VIL
–
–
0.3 × VDDD
[2]
[2]
0.7 × VDDD
–
–
–
–
0.3 × VDDD
2
–
–
–
0.8
–
–
VOH
VOH
VOH
VOL
VOL
VOL
Output voltage high level CMOS
Output
VDDD –0.4
–
IOH = 4 mA,
VDDD = 5 V +/- 10%
Output voltage high level CMOS
Output
VDDD –0.6
–
–
–
–
–
–
V
V
V
V
V
IOH = 4 mA,
VDDD = 3.3 V +/- 10%
Output voltage high level CMOS
Output
VDDD –0.5
–
IOH = 1 mA,
VDDD = 1.8 V +/- 5%
Output voltage low level CMOS
Output
–
–
–
0.4
0.6
0.6
IOL = 8 mA,
VDDD = 5 V +/- 10%
Output voltage low level CMOS
Output
IOL = 8 mA,
VDDD = 3.3 V +/- 10%
Output voltage low level CMOS
Output
IOL = 4 mA,
VDDD = 1.8 V +/- 5%
Rpullup
Rpulldown
IIL
Pull-up resistor
3.5
3.5
–
5.6
5.6
–
8.5
8.5
2
kΩ
kΩ
Pull-down resistor
Input leakage current (absolute
value)
nA 25 °C, VDDD = 3.0 V
CIN
Input capacitance
–
–
7
pF
Vhysttl
Input hysteresis LVTTL; VDDD
2.7 V
>
25
40
C
mV
Vhyscmos
Input hysteresis CMOS
0.05 × VDDD
–
mV
–
Table 5. GPIO AC Specification
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
TRiseFast1
Rise Time in Fast mode
Fall Time in Fast mode
Rise Time in Slow mode
Fall Time in Slow mode
2
–
12
ns VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
TFallFast1
TRiseSlow1
TFallSlow1
2
–
–
–
12
60
60
ns VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
10
10
ns VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
ns VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
TRiseFast2
TFallFast2
TRiseSlow2
TFallSlow2
Rise Time in Fast mode
Fall Time in Fast mode
Rise Time in Slow mode
Fall Time in Slow mode
2
20
2
–
–
–
–
20
100
20
ns VDDD = 1.8 V, Cload = 25 pF
ns VDDD = 1.8 V, Cload = 25 pF
ns VDDD = 1.8 V, Cload = 25 pF
ns VDDD = 1.8 V, Cload = 25 pF
20
100
Note
2.
V
must not exceed V
+ 0.2 V.
IH
DDD
Document Number: 001-89547 Rev. *C
Page 18 of 24
CY7C65221
nXRES
Table 6. nXRES DC Specifications
Parameter
VIH
Description
Min
Typ
–
Max
Units
V
Details/Conditions
Input voltage high threshold
Input voltage low threshold
Pull-up resistor
0.7 × VDDD
–
VIL
–
3.5
–
–
0.3 × VDDD
V
Rpullup
CIN
5.6
5
8.5
–
kΩ
pF
Input capacitance
Vhysxres
Input voltage hysteresis
–
100
–
mV
Table 7. nXRES AC Specifications
Parameter
Description
Reset pulse width
Min
Typ
Max
Units
Details/Conditions
Details/Conditions
Details/Conditions
Tresetwidth
1
–
–
µs
2
I C Specifications
Table 8. I2C AC Specifications
Parameter
FI2C
Description
I2C frequency
Min
Typ
Max
Units
1
–
400
kHz
Flash Memory Specifications
Table 9. Flash Memory Specifications
Parameter
Fend
Fret
Description
Flash endurance
Min
100K
10
Typ
Max
–
Units
cycles
years
–
–
Flash retention. TA 85 °C, 10 K
program/erase cycles
–
Document Number: 001-89547 Rev. *C
Page 19 of 24
CY7C65221
Ordering Information
Table 10 lists the key package features and ordering codes of the CY7C65211. For more information, contact your local sales repre-
sentative.
Table 10. Key Features and Ordering Information
Package
Ordering Code
Operating Range
24-pin QFN (4.00 × 4.00 × 0.55 mm, 0.5 mm pitch) (Pb-free)
CY7C65221-24LTXI
Industrial
Ordering Code Definitions
CY
7
C
65 xxx
-
xxLT
X
I
Industrial
Pb-free
Package type: 24-pin QFN
221
Family Code
Technology Code: C = CMOS
Marketing Code: 7 = Cypress products
Company Code: CY = Cypress
Document Number: 001-89547 Rev. *C
Page 20 of 24
CY7C65221
Package Information
Support currently is planned for the 24-pin QFN package.
Figure 6. 24-pin QFN (4 × 4 × 0.55 mm) LQ24A 2.65 × 2.65 E-Pad (Sawn) Package Outline, 001-13937
001-13937 *F
Table 11. Package Characteristics
Parameter
TA
THJ
Description
Operating ambient temperature
Package JA
Min
–40
–
Typ
25
Max
85
–
Units
°C
18.4
°C/W
Table 12. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time at Peak Temperature
24-pin QFN
260 °C
30 seconds
Table 13. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
24-pin QFN
MSL 3
Document Number: 001-89547 Rev. *C
Page 21 of 24
CY7C65221
Acronyms
Document Conventions
Table 14. Acronyms used
Acronym
Units of Measure
Description
Table 15. Units of Measure
CMOS
ESD
GPIO
HBM
I/O
Complementary Metal Oxide Semiconductor
Electrostatic Discharge
Symbol
Unit of Measure
C
degree Celsius
kilohm
General Purpose Input/Output
Human-Body Model
k
kHz
kV
kilohertz
kilovolt
Input/Output
I2C
Inter-Integrated Circuit
MHz
µF
megahertz
microfarad
milliampere
millimeter
millivolt
LVTTL
QFN
RoHS
Low-Voltage Transistor-Transistor Logic
Quad-Flat No-lead
mA
mm
mV
nA
ns
Restriction of Hazardous Substances
nanoampere
nanosecond
picofarad
volt
pF
V
W
watt
Document Number: 001-89547 Rev. *C
Page 22 of 24
CY7C65221
Document History Page
Document Title: CY7C65221, Dual I2C Slave Bridge
Document Number: 001-89547
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
4150932
4340874
DTNK
MVTA
10/08/2013 New data sheet.
*A
04/11/2014 Changed status from Preliminary to Final.
Updated Pin Description:
Updated description of pin 12 and pin 14.
Updated Functional Overview:
Updated Bridge register space:
Updated BMC-FX3S register space:
Updated description.
Updated Bridge register space:
Updated description corresponding to “I2C_A_WRITE_ADDR”.
Updated table corresponding to “I2C_CTRL”.
Updated table corresponding to “BRIDGE_SPL_RQT”.
Added details corresponding to “BRIDGE_MEMORY_OP”.
Added details corresponding to “BRIDGE_TIMEOUT_RQT”.
Added details corresponding to “BRIDGE_STATUS”.
Updated Bridge I2C Interface:
Updated WRITE:
Updated description.
Added Register write-enable masks.
Added Bridge Firmware upgrade.
Updated Electrical Specifications:
Updated Device-Level Specifications:
Updated Table 2:
Added IDD1 parameter and its details.
Updated GPIO:
Updated Table 4:
Updated description of VOH and VOL parameters.
Updated Table 5:
Updated all the details.
*B
*C
5473879
RAJV
10/13/2016 Updated Package Information:
spec 001-13937 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
5987021 AESATMP9 12/07/2017 Updated logo and copyright.
Document Number: 001-89547 Rev. *C
Page 23 of 24
CY7C65221
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2013-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-89547 Rev. *C
Revised December 7, 2017
Page 24 of 24
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