CY7S1041G [CYPRESS]
4-Mbit (256K words à 16 bit) Static RAM with PowerSnooze⢠and Error Correcting Code (ECC);
| 型号： | CY7S1041G |
| 厂家： | 
CYPRESS |
| 描述： | 4-Mbit (256K words à 16 bit) Static RAM with PowerSnooze⢠and Error Correcting Code (ECC) |
| 文件： | 总21页 (文件大小：664K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7S1041G
CY7S1041GE
4-Mbit (256K words × 16 bit) Static RAM
with PowerSnooze™ and Error Correcting Code (ECC)
4-Mbit (256K words
× 16 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC)
Deep-Sleep input (DS) must be deasserted HIGH for normal
operating mode.
Features
■ High speed
❐ Access time (tAA) = 10 ns / 15 ns
To perform data writes, assert the Chip Enable (CE) and Write
Enable (WE) inputs LOW, and provide the data and address on
device data pins (I/O0 through I/O15) and address pins (A0
through A17) respectively. The Byte High Enable (BHE) and Byte
Low Enable (BLE) inputs control byte writes, and write data on
the corresponding I/O lines to the memory location specified.
BHE controls I/O8 through I/O15 and BLE controls I/O0 through
I/O7.
■ Ultra-low power Deep-Sleep (DS) current
❐ IDS = 15 µA
■ Low active and standby currents
❐ Active Current ICC = 38-mA typical
❐ Standby Current ISB2 = 6-mA typical
■ Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V,
To perform data reads, assert the Chip Enable (CE) and Output
Enable (OE) inputs LOW and provide the required address on
the address lines. Read data is accessible on the I/O lines (I/O0
through I/O15). You can perform byte accesses by asserting the
required byte enable signal (BHE or BLE) to read either the
upper byte or the lower byte of data from the specified address
location
4.5 V to 5.5 V
■ Embedded ECC for single-bit error correction[1]
■ 1.0-V data retention
■ TTL- compatible inputs and outputs
■ Error indication (ERR) pin to indicate 1-bit error detection and
correction
The device is placed in a low-power Deep-Sleep mode when the
Deep-Sleep input (DS) is asserted LOW. In this state, the device
is disabled for normal operation and is placed in a low power data
retention mode. The device can be activated by deasserting the
Deep-Sleep input (DS) to HIGH.
■ Available in Pb-free 44-pin TSOP II and 48-ball VFBGA
Functional Description
The CY7S1041G is a high-performance PowerSnooze™ static
RAM organized as 256K words × 16 bits. This device features
fast access times (10 ns) and a unique ultra-low power
Deep-Sleep mode. With Deep-Sleep mode currents as low as
15 µA, the CY7S1041G/ CY7S1041GE devices combine the
best features of fast and low- power SRAMs in industry-standard
package options. The device also features embedded ECC. logic
which can detect and correct single-bit errors in the accessed
location.
The CY7S1041G is available in 44-pin TSOP II, 48-ball VFBGA
and 44-pin (400-mil) Molded SOJ.
Product Portfolio
Power Dissipation
Operating ICC
,
Speed
(ns)
Standby, ISB2
Deep-Sleep
current (µA)
Product [2]
Range
VCC Range (V)
(mA)
(mA)
f = fmax
Typ [3] Max Typ [3] Max Typ [3] Max
CY7S1041G(E)18
1.65 V–2.2 V
2.2 V–3.6 V
4.5–5.5 V
15
10
10
–
40
45
45
6
8
–
15
CY7S1041G(E)30 Industrial
CY7S1041G(E)
38
38
Notes
1. This device does not support automatic write back on error detection.
2. ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information for details.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for V range of 1.65 V – 2.2 V),
CC
CC
V
= 3 V (for V range of 2.2 V – 3.6 V), and V = 5 V (for V range of 4.5 V – 5.5 V), T = 25 °C.
CC
CC CC CC A
Cypress Semiconductor Corporation
Document Number: 001-92576 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 19, 2015
CY7S1041G
CY7S1041GE
Logic Block Diagram – CY7S1041G / CY7S1041GE
ECC ENCODER
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ERR (Optional)
I/O0‐I/O7
MEMORY
ARRAY
I/O8‐I/O15
COLUMN DECODER
BHE
WE
CE2
CE1
POWER MANAGEMENT
BLOCK
DS
OE
BLE
Document Number: 001-92576 Rev. *E
Page 2 of 21
CY7S1041G
CY7S1041GE
Contents
Pin Configurations ...........................................................4
Maximum Ratings .............................................................6
Operating Range ...............................................................6
DC Electrical Characteristics ..........................................6
Capacitance ......................................................................7
Thermal Resistance ..........................................................7
AC Test Loads and Waveforms .......................................7
Data Retention Characteristics .......................................8
Data Retention Waveform ................................................8
Deep-Sleep Mode Characteristics ...................................9
AC Switching Characteristics .......................................10
Switching Waveforms ....................................................11
Truth Table ......................................................................15
ERR Output – CY7S1041GE ...........................................15
Ordering Information ......................................................16
Ordering Code Definitions .........................................16
Package Diagrams ..........................................................17
Acronyms ........................................................................19
Document Conventions .................................................19
Units of Measure .......................................................19
Document History Page .................................................20
Sales, Solutions, and Legal Information ......................21
Worldwide Sales and Design Support .......................21
Products ....................................................................21
PSoC® Solutions ......................................................21
Cypress Developer Community .................................21
Technical Support .....................................................21
Document Number: 001-92576 Rev. *E
Page 3 of 21
CY7S1041G
CY7S1041GE
Pin Configurations
Figure 1. 44-pin TSOP II pinout, CY7S1041G
A0
A1
A17
A16
1
2
44
43
A2
3
42 A15
/OE
41
A3
4
A4
5
40 /BHE
39 /BLE
38 I/O15
/CE
I/O0
I/O1
I/O2
I/O3
VCC
6
7
I/O14
I/O13
I/O12
VSS
8
37
36
35
34
9
10
11
VSS 12
33 VCC
I/O4
I/O5
I/O6
I/O7
/WE
A5
I/O11
I/O10
I/O9
I/O8
/DS
13
14
15
16
17
18
19
20
21
32
31
30
29
28
27
26
25
24
23
A14
A13
A12
A11
A10
A6
A7
A8
A9 22
Figure 2. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable Figure 3. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable
without ERR, CY7S1041G [4], Package/Grade ID: BVJXI [6] with ERR, CY7S1041GE [4, 5], Package/Grade ID: BVJXI [6]
1
BLE
I/O8
I/O9
2
OE
3
4
A1
5
A2
6
1
BLE
I/O8
I/O9
2
OE
3
4
A1
5
A2
6
A0
A0
DS
I/O0
I/O2
VCC
VSS
I/O6
A
B
C
D
DS
I/O0
I/O2
VCC
VSS
I/O6
A
B
C
D
BHE
I/O10
A3
A5
A4
CE
BHE
I/O10
A3
A5
A4
CE
I/O1
I/O3
I/O4
I/O5
WE
A11
A6
I/O1
I/O3
I/O4
I/O5
WE
A11
A6
VSS I/O11
VCC I/O12
I/O14 I/O13
A17
NC
A14
A12
A9
A7
VSS I/O11
A17
A7
A16
A15
A13
A10
VCC I/O12 ERR
A16
A15
A13
A10
E
F
E
F
I/O14 I/O13
A14
A12
A9
I/O15
NC
NC
A8
I/O7
NC
I/O15
NC
NC
A8
I/O7
NC
G
H
G
H
Notes
4. NC pins are not connected internally to the die.
5. ERR is an output pin.
6. Package type BVJXI is JEDEC compliant compared to package type BVXI. The difference between the two is that the higher and lower byte I/Os (I/O
balls are swapped.
and I/O
[15:8]
[7:0]
Document Number: 001-92576 Rev. *E
Page 4 of 21
CY7S1041G
CY7S1041GE
Pin Configurations (continued)
Figure 4. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable Figure 5. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable
without ERR, CY7S1041G [7], Package/Grade ID: BVXI [9] with ERR, CY7S1041GE [7, 8], Package/Grade ID: BVXI [9]
1
BLE
I/O0
I/O1
VSS
VCC
I/O6
I/O7
NC
2
OE
3
4
A1
5
A2
6
DS
1
2
3
4
A1
5
A2
6
DS
A0
A
B
C
D
BLE
OE
A0
A
B
C
D
BHE
I/O2
I/O3
I/O4
I/O5
NC
A3
A5
A4
CE
I/O8
I/O9
I/O0 BHE
A3
A5
A4
CE
I/O8
A6
I/O10
I/O1
I/O2
I/O3
A6
I/O10 I/O9
I/O11 VCC
I/O12 VSS
I/O13 I/O14
A17
NC
A14
A12
A9
A7
I/O11 VCC
I/O12 VSS
I/O13 I/O14
VSS
A17
A7
VCC I/O4 ERR
A16
A15
A13
A10
A16
A15
A13
A10
E
F
E
F
I/O6
I/O7
NC
I/O5
NC
A8
A14
A12
A9
WE
A11
I/O15
NC
WE
A11
I/O15
NC
G
H
G
H
A8
Notes
7. NC pins are not connected internally to the die.
8. ERR is an output pin.
9. Package type BVJXI is JEDEC compliant compared to package type BVXI. The difference between the two is that the higher and lower byte I/Os (I/O
balls are swapped.
and I/O
[15:8]
[7:0]
Document Number: 001-92576 Rev. *E
Page 5 of 21
CY7S1041G
CY7S1041GE
DC input voltage [10] ........................... –0.5 V to VCC + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static discharge voltage
(MIL-STD-883, Method 3015) .................................> 2001 V
Storage temperature ................................ –65 C to +150 C
Latch-up current ....................................................> 140 mA
Ambient temperature
with power applied ................................... –55 C to +125 C
Operating Range
Supply voltage
Range
Ambient Temperature
VCC
on VCC relative to GND [10] .........................–0.5 V to + 6.0 V
1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC voltage applied to outputs
Industrial
–40 C to +85 C
in HI-Z State [10] ..................................–0.5 V to VCC + 0.5 V
DC Electrical Characteristics
Over the Operating Range of –40 C to +85 C
10 ns/ 15 ns
Parameter
VOH
Description
Test Conditions
Unit
Max
Min
Typ[11]
Output HIGH
1.65 V to 2.2 V
2.2 V to 2.7 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
1.65 V to 2.2 V
2.2 V to 2.7 V
2.7 V to 3.6 V
3.6 V to 5.5 V
1.65 V to 2.2 V
2.2 V to 2.7 V
2.7 V to 3.6 V
3.6 V to 5.5 V
VCC = Min, IOH = –0.1 mA
VCC = Min, IOH = –1.0 mA
1.4
–
–
–
–
voltage
2
V
V
V
CC = Min, IOH = –4.0 mA
CC = Min, IOH = –4.0 mA
CC = Min, IOH = –0.1 mA
2.2
–
–
V
2.4
VCC-0.5[13]
–
–
–
–
VOL
Output LOW
voltage
VCC = Min, IOL = 0.1 mA
–
–
–
0.2
V
V
V
CC = Min, IOL = 2 mA
CC = Min, IOL = 8 mA
CC = Min, IOL = 8 mA
–
0.4
V
V
V
–
–
0.4
–
–
0.4
[10, 12]
VIH
Input HIGH
voltage
1.4
2
–
VCC + 0.2
–
V
V
V
CC + 0.3
CC + 0.3
CC + 0.5
0.4
2
–
2.2
–0.2
–0.3
–0.3
–0.5
–1
–1
–
–
[10, 12]
VIL
Input LOW voltage 1.65 V to 2.2 V
2.2 V to 2.7 V
–
–
0.6
2.7 V to 3.6 V
–
0.8
3.6 V to 5.5 V
–
0.8
IIX
Input leakage current
Output leakage current
VCC operating supply current
GND < VIN < VCC
–
+1
A
A
IOZ
ICC
GND < VOUT < VCC, Output disabled
–
+1
VCC = Max,
OUT = 0 mA,
CMOS levels
f = 100 MHz
f = 66.7 MHz
38
40
45
I
mA
mA
mA
µA
–
40
ISB1
ISB2
Standby current – TTL inputs
Standby current – CMOS inputs
Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX
–
–
–
–
6
–
15
8
Max VCC, CE > VCC – 0.2 V,
DS > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
IDS
Deep-Sleep current
Max VCC, CE > VCC – 0.2 V, DS < 0.2 V,
IN > VCC – 0.2 V or VIN < 0.2 V, f = 0
15
V
Notes
10. V (min) = –2.0 V and V (max) = V + 2 V for pulse durations of less than 2 ns.
IL
IH
CC
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for V range of 1.65 V – 2.2 V),
CC
CC
V
= 3 V (for V range of 2.2V – 3.6 V), and V = 5 V (for V range of 4.5 V – 5.5 V), T = 25 °C.
CC
CC CC CC A
12. For the DS pin, V (min) is V – 0.2 V and V (max) is 0.2 V.
IH
CC
IL
13. This parameter is guaranteed by design and not tested.
Document Number: 001-92576 Rev. *E
Page 6 of 21
CY7S1041G
CY7S1041GE
Capacitance
Parameter [14]
Description
Input capacitance
I/O capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC(typ)
All packages Unit
CIN
10
10
pF
pF
COUT
Thermal Resistance
Parameter [14]
Description
Test Conditions
48-ball VFBGA 44-pin TSOP II Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch, four
layer printed circuit board
31.35
68.85
C/W
JC
Thermal resistance
(junction to case)
14.74
15.97
C/W
AC Test Loads and Waveforms
Figure 6. AC Test Loads and Waveforms [15]
HI-Z Characteristics:
VCC
Output
R1
50
Output
VTH
Z = 50
R2
30 pF*
0
5 pF*
* Including
JIG and
Scope
(a)
(b)
* Capacitive Load Consists
of all Components of the
Test Environment
All Input Pulses
V
HIGH
90%
10%
90%
10%
GND
Fall Time:
> 1 V/ns
Rise Time:
> 1 V/ns
(c)
Parameters
R1
1.8 V
1667
1538
VCC/2
1.8
3.0 V
317
351
1.5
5.0 V
Unit
317
351
1.5
R2
VTH
V
VHIGH
3.0
3.0
V
Notes
14. Tested initially and after any design or process changes that may affect these parameters.
15. Full-device AC operation assumes a 100-s ramp time from 0 to V
or 100-s wait time after V stabilization.
CC(min)
CC
Document Number: 001-92576 Rev. *E
Page 7 of 21
CY7S1041G
CY7S1041GE
Data Retention Characteristics
Over the Operating Range of –40C to +85 C
Parameter
VDR
Description
Conditions[16]
Min
Max
Unit
VCC for data retention
1.0
–
V
VCC = VDR, CE > VCC – 0.2 V, DS > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
ICCDR
Data retention current
–
0
8
–
mA
ns
Chip deselect to data retention
time
[17]
tCDR
2.2 V < VCC < 5.5 V
VCC < 2.2 V
10
15
–
–
ns
ns
[17, 18]
tR
Operation recovery time
Data Retention Waveform
Figure 7. Data Retention Waveform [18]
DATA RETENTION MODE
VDR = 1.0 V
VCC
VCC(min)
tCDR
VCC(min)
tR
CE
Notes
16. DS signal must be HIGH during Data Retention Mode.
17. These parameters are guaranteed by design
18. Full-device operation requires linear V ramp from V to V
100 s or stable at V
100 s.
CC(min)
CC
DR
CC(min)
Document Number: 001-92576 Rev. *E
Page 8 of 21
CY7S1041G
CY7S1041GE
Deep-Sleep Mode Characteristics
Over the Operating Range of –40 C to +85 C
Parameter
IDS
Description
Conditions
Min
Max
Unit
VCC = VCC (max), DS < 0.2 V,
IN > VCC – 0.2 V or VIN < 0.2 V
Deep-Sleep mode current
–
15
µA
V
Minimum time for DS to be LOW
for part to successfully exit
Deep-Sleep mode
[19]
tPDS
100
–
–
1
ns
DS assertion to Deep-Sleep
mode transition time
[20]
tDS
ms
If tPDS > tPDS(min)
If tPDS < tPDS(min)
If tPDS > tPDS(min)
If tPDS < tPDS(min)
–
–
100
0
s
s
[19]
tDSCD
DS deassertion to chip disable
DS deassertion to chip access
(Active/Standby)
tDSCA
300
–
s
Figure 8. Active, Standby, and Deep-Sleep Operation Modes
Chip
Access
Allowed
Not Allowed
Allowed
ENABLE/
DISABLE
ENABLE/
DISABLE
CE
DS
DON’T CARE
tPDS
DISABLE
tDS
tDSCD
tDSCA
Active/Standby
Mode
Standby
Mode
Active/Standby
Mode
Standby
Mode
Mode
Deep Sleep Mode
Note
19. CE must be pulled HIGH within t
time of DS deassertion to avoid SRAM data loss.
DSCD
20. After assertion of DS signal, device will take a maximum of t time to stabilize to Deep-Sleep current I . During this period, DS signal must continue to be asserted
DS
DS
to logic level LOW to keep the device in Deep-Sleep mode.
Document Number: 001-92576 Rev. *E
Page 9 of 21
CY7S1041G
CY7S1041GE
AC Switching Characteristics
Over the Operating Range of –40 C to +85 C
10 ns
15 ns
Unit
Parameter [21]
Description
Min
Max
Min
Max
Read Cycle
tRC
Read cycle time
10
–
3
–
–
0
–
3
–
0
–
–
0
–
–
10
–
15
–
3
–
–
0
–
3
–
0
–
–
0
–
–
15
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
tOHA
Data hold from address change
CE LOW to data valid
tACE
10
4.5
–
15
8
tDOE
OE LOW to data valid
tLZOE
tHZOE
tLZCE
tHZCE
tPU
OE LOW to low impedance [22, 23, 24]
OE HIGH to HI-Z [22, 23, 24]
CE LOW to low impedance [22, 23, 24]
CE HIGH to HI-Z [22, 23, 24]
CE LOW to power-up [ 24]
CE HIGH to power-down [ 24]
Byte enable to data valid
–
5
8
–
–
5
8
–
–
tPD
10
4.5
–
15
8
tDBE
tLZBE
tHZBE
Write Cycle [25, 26]
Byte enable to low impedance [22, 23, 24]
Byte disable to HI-Z [22, 23, 24]
–
6
8
tWC
tSCE
tAW
Write cycle time
10
7
7
0
0
7
5
0
3
–
7
–
–
–
–
–
–
–
–
–
5
–
15
12
12
0
–
–
–
–
–
–
–
–
–
8
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
tHA
tSA
0
tPWE
tSD
12
8
Data setup to write end
tHD
Data hold from write end
WE HIGH to low impedance [22, 23, 24]
WE LOW to HI-Z [22, 23, 24]
Byte Enable to End of Write
0
tLZWE
tHZWE
tBW
3
–
12
Notes
21. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for V > 3 V) and V /2 (for V < 3 V), and input pulse
CC
CC
CC
levels of 0 to 3 V (for V > 3 V) and 0 to V (for V < 3 V). Testconditionsforthereadcycleuseoutputloadingshowninpart(a)ofFigure6onpage7, unlessspecifiedotherwise.
CC
CC
CC
22. t
, t
, t
, t
, t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in (b) of Figure 6 on page 7. Transition is measured 200 mV from steady
HZOE HZCE HZWE HZBE LZOE LZCE LZWE
LZBE
state voltage.
23. At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
24. These parameters are guaranteed by design
25. The internal write time of the memory is defined by the overlap of WE = V , CE = V ,DS = V and BHE or BLE = V . WE, CE, BHE and BLE signals must be LOW
IL
IL
IH
IL
and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE, BHE and BLE signals or LOW transition on DS signal can terminate the operation.
The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
26. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be the sum of t
and t
.
HZWE
SD
Document Number: 001-92576 Rev. *E
Page 10 of 21
CY7S1041G
CY7S1041GE
Switching Waveforms
Figure 9. Read Cycle No. 1 of CY7S1041G (Address Transition Controlled) [27, 28, 29]
tRC
ADDRESS
DATA I/O
tAA
tOHA
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 10. Read Cycle No. 2 of CY7S1041GE (Address Transition Controlled) [27, 28, 29]
tRC
ADDRESS
tAA
tOHA
PREVIOUS DATAOUT
VALID
DATA I/O
ERR
DATAOUT VALID
ERR VALID
tAA
tOHA
PREVIOUS ERR VALID
Notes
27. The device is continuously selected. OE = V , CE = V , BHE or BLE or both = V .
IL
IL
IL
28. WE is HIGH for read cycle.
29. DS is HIGH for chip access.
Document Number: 001-92576 Rev. *E
Page 11 of 21
CY7S1041G
CY7S1041GE
Switching Waveforms (continued)
Figure 11. Read Cycle No. 3 (OE Controlled) [30, 31, 32]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE
BLE
/
tDBE
tLZBE
tHZBE
HIGH
HIGH IMPEDANCE
tLZCE
tPU
DATA I /O
DATA OUT VALID
IMPEDANCE
VCC
SUPPLY
CURRENT
ISB
Notes
30. WE is HIGH for read cycle.
31. Address valid prior to or coincident with CE LOW transition.
32. DS must be HIGH for chip access
Document Number: 001-92576 Rev. *E
Page 12 of 21
CY7S1041G
CY7S1041GE
Switching Waveforms (continued)
Figure 12. Write Cycle No. 1 (CE Controlled) [33, 34, 35]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tBW
BHE/
BLE
OE
tHZOE
tHD
tSD
DATA I/O
DATAIN VALID
Figure 13. Write Cycle No. 2 (WE Controlled, OE LOW) [33, 34, 35, 36]
tWC
ADDRESS
tSCE
CE
tBW
BHE/
BLE
tAW
tHA
tSA
tPWE
WE
tLZWE
tSD
t
HZWE
tHD
DATA I/O
DATAIN VALID
Notes
33. The internal write time of the memory is defined by the overlap of WE = V , CE = V ,DS = V and BHE or BLE = V . WE, CE, BHE and BLE signals must be LOW
IL
IL
IH
IL
and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE, BHE and BLE signals or LOW transition on DS signal can terminate the operation.
The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
34. Data I/O is in HI-Z state if CE = V , or OE = V or BHE, and/or BLE = V
.
IH
IH
IH
35. DS must be HIGH for chip access.
36. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be sum of t
and t
.
HZWE
SD
Document Number: 001-92576 Rev. *E
Page 13 of 21
CY7S1041G
CY7S1041GE
Switching Waveforms (continued)
Figure 14. Write Cycle No. 3 (WE Controlled) [37, 38, 39]
tW C
A D D R E S S
tS C E
C E
tA W
tS A
tH A
tP W E
W E
tB W
B H E /B L E
O E
tH Z O E
tH D
tS D
Note 40
D A T A I/O
D A T A IN V A LID
Figure 15. Write Cycle No. 4 (BLE or BHE Controlled) [37, 38, 39]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tBW
BHE/
BLE
tPWE
WE
tHZWE
tHD
tSD
tLZWE
Note 40
DATA I/O
DATAIN VALID
Notes
37. The internal write time of the memory is defined by the overlap of WE = V , CE = V ,DS = V and BHE or BLE = V . WE, CE, BHE and BLE signals must be LOW
IL
IL
IH
IL
and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE, BHE and BLE signals or LOW transition on DS signal can terminate the operation.
The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
38. Data I/O is in HI-Z state if CE = V , or OE = V or DS = V or BHE, and/or BLE = V
.
IH
IH
IL
IH
39. DS must be HIGH for chip access.
40. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-92576 Rev. *E
Page 14 of 21
CY7S1041G
CY7S1041GE
Truth Table
DS CE OE WE BLE BHE I/O0–I/O7 I/O8–I/O15
Mode
Power
H
H
H
L
L
L
L
L
L
L
X
X[41] X[41] X[41] X[41] HIGH-Z
HIGH-Z
Data out
HI-Z
Standby
Standby (ISB)
L
L
H
H
H
L
L
L
L
H
L
Data out
Data out
HI-Z
Read all bits
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
)
)
H
Read lower bits only
Read upper bits only
Write all bits
H
L
H
L
Data out
Data in
HI-Z
H
X
X
X
H
X
L
Data in
Data in
HI-Z
H
L
L
H
L
Write lower bits only
Write upper bits only
Selected, outputs disabled
Deep-Sleep
H
L
H
X
X
Data in
HI-Z
H
H
X
X
X
HI-Z
L[42]
HI-Z
HI-Z
Deep-Sleep Ultra Low Power
(IDS
)
ERR Output – CY7S1041GE
Output [43]
Mode
0
1
Read operation, no single-bit error in the stored data.
Read operation, single-bit error detected and corrected.
Device deselected or outputs disabled or Write operation
HI-Z
Notes
41. The input voltage levels on these pins should be either at V or V .
IH
IL
42. V on DS must be < 0.2 V.
IL
43. ERR is an Output pin.If not used, this pin should be left floating.
Document Number: 001-92576 Rev. *E
Page 15 of 21
CY7S1041G
CY7S1041GE
Ordering Information
Speed
(ns)
Voltage
Range
Package
Diagram
Operating
Range
Ordering Code
Package Type (All Pb-free)
10 2.2 V–3.6 V CY7S1041GE30-10BVXI 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), ERR output
Industrial
CY7S1041G30-10BVXI
CY7S1041G30-10ZSXI
51-85150 48-ball VFBGA (6 × 8 × 1.0 mm)
51-85087 44-pin TSOP II
4.5 V–5.5 V CY7S1041G-10ZSXI
51-85087 44-pin TSOP II
Ordering Code Definitions
CY 7 1 04 1
S
G
XX X
I
E
30 - 10
Temperature Range:
I = Industrial
Pb-free
Package Type: XX = BV or ZS
BV = 48-ball VFBGA;
ZS = 44-pin TSOP II
Speed: 10 ns
Voltage Range: No digits or 30 or 18
No digits = 4.5 V to 5.5 V; 30 = 2.2 V to 3.6 V;18 = 1.65 V to 2.2 V
ERR output
Process Technology: Revision Code “G” = 65 nm Technology
Data Width: 1 = × 16-bits
Density: 04 = 4-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
S = Deep-Sleep feature
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-92576 Rev. *E
Page 16 of 21
CY7S1041G
CY7S1041GE
Package Diagrams
Figure 16. 44-pin TSOP II Package Outline, 51-85087
51-85087 *E
Document Number: 001-92576 Rev. *E
Page 17 of 21
CY7S1041G
CY7S1041GE
Package Diagrams (continued)
Figure 17. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 001-92576 Rev. *E
Page 18 of 21
CY7S1041G
CY7S1041GE
Acronyms
Document Conventions
Units of Measure
Acronym
Description
BHE
BLE
Byte High Enable
Symbol
°C
Unit of Measure
Byte Low Enable
Chip Enable
degrees Celsius
megahertz
microampere
microsecond
milliampere
millimeter
nanosecond
ohm
MHz
A
s
CE
CMOS
ECC
I/O
Complementary Metal Oxide Semiconductor
Error Correcting Code
mA
mm
ns
Input/Output
OE
Output Enable
SRAM
TSOP
TTL
Static Random Access Memory
Thin Small Outline Package
Transistor-Transistor Logic
Very Fine-Pitch Ball Grid Array
Write Enable
%
percent
pF
V
picofarad
volt
VFBGA
WE
W
watt
Document Number: 001-92576 Rev. *E
Page 19 of 21
CY7S1041G
CY7S1041GE
Document History Page
Document Title: CY7S1041G/CY7S1041GE, 4-Mbit (256K words × 16 bit) Static RAM with PowerSnooze™ and Error
Correcting Code (ECC)
Document Number: 001-92576
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*D
4867081
NILE
07/31/2015 Changed status from Preliminary to Final.
*E
5020880
VINI
11/19/2015 Updated Pin Configurations:
Removed 44-pin SOJ package related information.
Updated Thermal Resistance:
Removed 44-pin SOJ package related information.
Added 48-ball VFBGA package related information.
Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Updated Package Diagrams:
Removed spec 51-85082 *E.
Document Number: 001-92576 Rev. *E
Page 20 of 21
CY7S1041G
CY7S1041GE
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
cypress.com/go/psoc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Clocks & Buffers
Interface
Cypress Developer Community
Lighting & Power Control
Memory
Community | Forums | Blogs | Video | Training
Technical Support
PSoC
cypress.com/go/support
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2014-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-92576 Rev. *E
Revised November 19, 2015
Page 21 of 21
All products and company names mentioned in this document may be the trademarks of their respective holders.
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