CY8C21645_技术文档

CY8C21345, CY8C21645

CY8C22345, CY8C22345H, CY8C22645

®

Automotive PSoC

Programmable System-on-Chip™

❐ Two dedicated clock resources for CapSense

❐ Two dedicated 16-bit timers/counters for CapSense

scanning

Features

■ Automotive Electronics Council (AEC) Q100 qualified

■ Powerful Harvard-architecture processor

❐ M8C processor speeds up to 24 MHz

❐ 8 × 8 multiply, 32-bit accumulate

❐ Low power at high speed

❐ Automotive A-grade: 3.0 V to 5.25 V operation at –40 °C to

+85 °C temperature range

■ Versatile analog mux

❐ Common internal analog bus

❐ Simultaneous connection of I/O combinations

■ Programmable pin configurations

❐ 25 mA sink, 10 mA drive on all GPIOs

❐ Pull-up, pull-down, high Z, strong, or open drain drive modes

on all GPIOs

❐ Analog input on all GPIOs

❐ Configurable interrupt on all GPIOs

■ Additional system resources:

❐ I²C master, slave, or multi-master

• Operation up to 400 kHz

• Hardware address detection feature

❐ Watchdog and sleep timers

❐ User-configurable low voltage detection

❐ Integrated supervisory circuit

❐ Automotive E-grade: 4.75 V to 5.25 V operation at –40 °C to

+125 °C temperature range

■ Advanced peripherals (PSoC^®blocks)

❐ Six analog Type ‘E’ PSoC blocks provide:

• Up to four comparators with digital-to-analog converters

(DAC) references

• Up to 10-bit single or dual analog-to-digital converters

(ADCs)

❐ Up to eight digital PSoC blocks provide:

• 8 to 32-bit timers, counters, and pulse width modulators

(PWMs)

❐ On-chip precision voltage reference

❐ Hardware real time clock (RTC) block

• One-shot, multi-shot mode in timers and PWMs

• PWM with deadband in one digital block

• Shift register, cyclical redundancy check (CRC), and

pseudo random sequence (PRS) modules

Block Diagram

• Full- or half-duplex UARTs

Port 4 Port 3 Port 2 Port 1 Port 0

• SPI masters or slaves, 8- to 16-bit variable data length

• Connectable to all general-purpose I/O (GPIO) pins

PSoC CORE

❐ Complex peripherals by combining blocks

❐ Powerfulsynchronizationsupport,analogmoduleoperations

can be synchronized by digital blocks or external signals.

System Bus

Global Digital

Global Analog Interconnect

Interconnect

■ High-speed 10-bit successive approximation register (SAR)

ADC with sample and hold optimized for embedded control

■ CY8C22345H devices integrate Immersion^®TouchSense^®

SRAM

SROM Flash 16K/8K

1KB/512B

Sleep and

Watchdog

CPU Core (M8C)

Interrupt

Controller

haptics technology for ERM drive control

■ Precision, programmable clocking

❐ Internal oscillator up to 24 MHz

Multiple Clock Sources

(Includes IMO, ILO, PLL, and ECO)

❐ High accuracy 24 MHz with optional 32-kHz crystal and

phase locked loop (PLL)

❐ Optional external oscillator, up to 24 MHz

❐ Internal low speed, low-power oscillator for watchdog and

sleep functionality

DIGITAL SYSTEM

ANALOG SYSTEM

Analog

Ref

10-bit SAR

ADC

Digital Block

Array

Analog

Input

■ Flexible on-chip memory

Muxing

❐ Up to 16 KB flash program storage, 1000 erase/write cycles

❐ Up to 1 KB SRAM data storage

❐ In-System Serial Programming (ISSP)

❐ Partial flash updates

Analog

Block

Array

CapSense Digital

Resources

❐ Flexible protection modes

❐ EEPROM emulation in flash

■ Optimized CapSense^®resource

❐ Supports two CapSense channels with simultaneous

scanning

❐ Two current DACs provide programmable sensor tuning in

firmware

POR and LVD

System Resets

Internal

Voltage

Ref.

Digital

Clocks

Multiply

Accum.

I²C

RTC

SYSTEM RESOURCES

Cypress Semiconductor Corporation

Document Number: 001-55397 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 18, 2011

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Contents

PSoC Functional Overview ..............................................3

PSoC Core ..................................................................3

Digital System .............................................................3

Analog System ............................................................4

Haptics TS2000 Controller ..........................................4

Additional System Resources .....................................5

PSoC Device Characteristics ......................................5

Getting Started ..................................................................6

Application Notes ........................................................6

Development Kits ........................................................6

Training .......................................................................6

CYPros Consultants ....................................................6

Solutions Library ..........................................................6

Technical Support .......................................................6

Development Tools ..........................................................6

PSoC Designer Software Subsystems ........................6

Designing with PSoC Designer .......................................7

Select User Modules ...................................................7

Configure User Modules ..............................................7

Organize and Connect ................................................7

Generate, Verify, and Debug .......................................7

Pinouts ..............................................................................8

28-Pin Part Pinout .......................................................8

48-Pin Part Pinout .......................................................9

Registers .........................................................................11

Register Conventions ................................................11

Register Mapping Tables ..........................................11

Electrical Specifications ................................................14

Absolute Maximum Ratings .......................................15

Operating Temperature ............................................15

DC Electrical Characteristics .....................................16

AC Electrical Characteristics .....................................21

Packaging Information ...................................................26

Package Dimensions .................................................26

Thermal Impedances ................................................27

Capacitance on Crystal Pins ....................................27

Solder Reflow Peak Temperature .............................27

Tape and Reel Information ........................................28

Development Tool Selection .........................................30

Software ....................................................................30

Development Kits ......................................................30

Evaluation Tools ........................................................30

Device Programmers .................................................31

Accessories (Emulation and Programming) ..............31

Ordering Information ......................................................32

Ordering Code Definitions ........................................33

Document Conventions .................................................34

Acronyms Used .........................................................34

Units of Measure .......................................................34

Numeric Naming ........................................................34

Document History Page .................................................35

Sales, Solutions, and Legal Information ......................36

Worldwide Sales and Design Support .......................36

Products ....................................................................36

PSoC Solutions .........................................................36

Document Number: 001-55397 Rev. *I

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Digital System

PSoC Functional Overview

The digital system is composed of eight digital PSoC blocks.

Each block is an 8-bit resource that may be used alone or

combined with other blocks to form 8-, 16-, 24-, and 32-bit

peripherals, which are called user modules.

The PSoC programmable system-on-chip series of products

consists of many devices. These devices are designed to

replace multiple traditional MCU-based system components with

one low cost single-chip programmable device. PSoC devices

include configurable blocks of analog and digital logic, as well as

programmable interconnects. This architecture enables the user

to create customized peripheral configurations that match the

requirements of each individual application. Additionally, a fast

CPU, flash program memory, SRAM data memory, and

configurable I/O are included in a range of convenient pinouts

and packages.

Figure 1. Digital System Block Diagram^[1]

Port 3

Port 1

Port 4

Port 2

Port 0

To System Bus

Digital Clocks

From Core

To Analog

System

The PSoC architecture, shown in the Block Diagram on page 1,

consists of four main areas: PSoC core, digital system, analog

system, and system resources. Configurable global busing

allows the combining of all the device resources into a complete

custom system. The PSoC family can have up to five I/O ports

connecting to the global digital and analog interconnects,

providing access to eight digital blocks^[1]and six analog blocks.

DIGITAL SYSTEM

Digital PSoC Block Array

Row 0

4

DBC00

DBC01 DCC02 DCC03

4

8

PSoC Core

8

The PSoC core is a powerful engine that supports a rich feature

set. The core includes a CPU, memory, clocks, and configurable

GPIO.

Row 1

DBC01 DCC02 DCC03

DBC00

The M8C CPU core is a powerful processor with speeds up to

24 MHz (up to 12 MHz for E-grade devices), providing four MIPS

(two MIPS for E-grade devices) 8-bit Harvard architecture micro-

processor. The CPU uses an interrupt controller to simplify the

programming of real time embedded events.

GIE[7:0]

GIO[7:0]

GOE[7:0]

GOO[7:0]

Global Digital

Interconnect

Program execution is timed and protected using the included

Sleep Timer and Watch Dog Timer (WDT).

Memory encompasses 16 KB of flash (8 KB for CY8C21x45

devices) for program storage, 1 KB of SRAM (512 bytes for

CY8C21x45 devices) for data storage, and EEPROM emulation

using the flash. Program flash uses four protection levels on

blocks of 64 bytes, allowing customized software IP protection.

Digital peripheral configurations are:

■ PWMs (8- to 32-bit)

■ PWMs with deadband (8- to 32-bit)

■ Counters (8- to 32-bit)

The PSoC device incorporates flexible internal clock generators,

including a 24-MHz internal main oscillator (IMO). For A-grade

devices the 24-MHz IMO can also be doubled to 48 MHz for use

by the digital system. A low-power 32-kHz internal low-speed

oscillator (ILO) is provided for the Sleep Timer and WDT. If

crystal accuracy is required, the 32.768 kHz external crystal

oscillator (ECO) is available for use as a RTC, and can optionally

generate a crystal-accurate 24-MHz system clock using a PLL.

The clocks, together with programmable clock dividers (as a

system resource), provide the flexibility to integrate almost any

timing requirement into the PSoC device.

■ Timers (8- to 32-bit)

■ One-shot and multi-shot modules

■ Full or half-duplex 8-bit UART with selectable parity (up to two

full-duplex or four half-duplex)

■ SPI master and slave (up to four total) with programmable data

length from 8 to 16 bits.

■ Shift register (1- to 32-bit)

■ I²C master, slave, or multi-master (one available)

PSoC GPIOs provide connection to the CPU, digital, and analog

resources of the device. Each pin’s drive mode may be selected

from eight options, allowing great flexibility in external

interfacing. Each pin can also generate a system interrupt.

■ CRC/generator (16-bit)

■ IrDA (up to two)

■ PRS generators (8- to 32-bit)

Note

1. CY8C22x45 devices have 2 digital rows with 8 digital blocks. CY8C21x45 devices only have 1 digital row with 4 digital blocks.

Document Number: 001-55397 Rev. *I

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The digital blocks may be connected to any GPIO through a

series of global buses that can route any signal to any pin. The

buses also allow for signal multiplexing and performing logic

operations. This configurability frees your designs from the

constraints of a fixed peripheral controller.

Figure 2. Analog System Block Diagram

Array Input Configuration

Digital blocks are provided in rows of four, where the number of

blocks varies by PSoC device family. This provides a choice of

system resources for your application. Family resources are

shown in Table 1 on page 5.

ACI0[1:0]

ACI1[1:0]

Analog System

The Analog System of CY8C21x45 and CY8C22x45 PSoC

devices consists of a 10-bit SAR ADC and six configurable

analog blocks.

ACE00

ASE10

ACE01

ASE11

ACE10

ACE11

Block Array

The programmable 10-bit SAR ADC is an optimized ADC with a

fast maximum sample rate. External filters are required on ADC

input channels for antialiasing. This ensures that any out-of-band

content is not folded into the input signal band.

AmuxL

AmuxR

P0[0:7]

Reconfigurable analog resources allow creating complex analog

signal flows. Analog peripherals are very flexible and may be

customized to support specific application requirements. Some

of the more common PSoC analog functions (most available as

user modules) are:

ACI2[3:0]

10 bit SAR ADC

Analog Reference

■ Analog-to-digital converters (single or dual, with up to 10-bit

resolution)

Interface to

Reference

Digital System

Generators

AGND

Bandgap

■ Pin-to-pin comparator

■ Single-ended comparators (up to four) with absolute (1.3 V)

reference or DAC reference

M8C Interface (Address Bus, Data Bus, Etc.)

■ Precision voltage reference (1.3 V nominal)

CY8C21x45 and CY8C22x45 devices have six limited-function-

ality Type 'E' analog blocks. These analog blocks are arranged

in four columns. Each column contains one continuous time (CT)

Type E block. The first two columns also have a switched

capacitor (SC) type E block. Refer to the PSoC Technical

Reference Manual for CY8C21x45 and CY8C22x45 devices for

detailed information on the Type E analog blocks.

Haptics TS2000 Controller

The CY8C22x45H family of devices features an easy-to-use

Haptics controller resource with up to 14 different effects. These

effects are available for use with three different, selectable ERM

modules.

Document Number: 001-55397 Rev. *I

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Additional System Resources

PSoC Device Characteristics

System Resources, some of which are listed in the previous

sections, provide additional capability useful for complete

systems. Additional resources include a MAC, low voltage

detection, and power on reset. The merits of each system

resource are:

Depending on your PSoC device characteristics, the digital and

analog systems can have varying numbers of digital and analog

blocks. The following table lists the resources available for

specific PSoC device groups. The PSoC families covered by this

datasheet are highlighted in the table.

Table 1. PSoC Device Characteristics

■ Digital clock dividers provide three customizable clock

frequencies for use in applications. The clocks may be routed

to both the digital and analog systems. Additional clocks can

be generated using digital PSoC blocks as clock dividers.

PSoC Part

Number

[2]

■ Additional digital resources and clocks dedicated to and

optimized for CapSense.

CY8C29x66

CY8C28xxx

CY8C27x43

CY8C24x94

up to

64

4

16 up to

12

4

12

2 KB 32 KB

up to up to upto up to up to upto up to 1 KB 16 KB

44

■ RTC hardware block.

3

12

44

4

6

16

up to

44

2

8

up to

12

4

12

256 16 KB

Bytes

■ A multiply accumulate (MAC) provides a fast 8-bit multiplier

with 32-bit accumulate, to assist in both general math and

digital filters.

[2]

up to

56

1

2

1

0

4

8

4

0

up to

48

2

0

2

4

2

0

6

1 KB 16 KB

[2]

CY8C24x23A

up to

24

up to

12

256

4 KB

8 KB

■ The I²C module provides 0 to 400 kHz communication over two

wires. Slave, master, and multi-master modes are all

supported.

Bytes

CY8C23x33

up to

25

up to

12

4

256

Bytes

[2]

[3]

CY8C22x45

CY8C21x45

CY8C21x34

CY8C21x23

CY8C20x34

up to

38

up to

38

6

1 KB 16 KB

■ Low voltage detection (LVD) interrupts can signal the

application of falling voltage levels, while the advanced power

on reset (POR) circuit eliminates the need for a system

supervisor.

[3]

up to

38

up to

38

6

4

512

8 KB

4 KB

8 KB

Bytes

up to

28

up to

28

512

Bytes

■ An internal voltage reference provides an absolute reference

for the analog system, including ADCs and DACs.

up to

16

up to

8

256

Bytes

[2]

[3, 4]

up to

28

up to

28

3

512

Bytes

Notes

2. Automotive qualified devices available in this group.

3. Limited analog functionality.

®

4. Two analog blocks and one CapSense block.

Document Number: 001-55397 Rev. *I

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Getting Started

Development Tools

For in depth information, along with detailed programming

PSoC Designer™ is the revolutionary Integrated Design

Environment (IDE) that you can use to customize PSoC to meet

your specific application requirements. PSoC Designer software

accelerates system design and time to market. Develop your

applications using a library of precharacterized analog and digital

peripherals (called user modules) in a drag-and-drop design

environment. Then, customize your design by leveraging the

dynamically generated application programming interface (API)

libraries of code. Finally, debug and test your designs with the

integrated debug environment, including in-circuit emulation and

standard software debug features. PSoC Designer includes:

details, see the PSoC^®Technical Reference Manual.

For up-to-date ordering, packaging, and electrical specification

information, see the latest PSoC device datasheets on the web.

Application Notes

Cypress application notes are an excellent introduction to the

wide variety of possible PSoC designs.

Development Kits

PSoC Development Kits are available online from and through a

growing number of regional and global distributors, which

include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and

Newark.

■ Application editor graphical user interface (GUI) for device and

user module configuration and dynamic reconfiguration

■ Extensive user module catalog

■ Integrated source-code editor (C and assembly)

■ Free C compiler with no size restrictions or time limits

■ Built-in debugger

Training

Free PSoC technical training (on demand, webinars, and

workshops), which is available online via www.cypress.com,

covers a wide variety of topics and skill levels to assist you in

your designs.

■ In-circuit emulation

CYPros Consultants

■ Built-in support for communication interfaces:

❐ Hardware and software I²C slaves and masters

❐ Full-speed USB 2.0

❐ Up to four full-duplex universal asynchronous receiver/trans-

mitters (UARTs), SPI master and slave, and wireless

Certified PSoC consultants offer everything from technical assis-

tance to completed PSoC designs. To contact or become a PSoC

consultant go to the CYPros Consultants web site.

Solutions Library

PSoC Designer supports the entire library of PSoC 1 devices and

runs on Windows XP, Windows Vista, and Windows 7.

Visit our growing library of solution focused designs. Here you

can find various application designs that include firmware and

hardware design files that enable you to complete your designs

quickly.

PSoC Designer Software Subsystems

Design Entry

Technical Support

In the chip-level view, choose a base device to work with. Then

select different onboard analog and digital components that use

the PSoC blocks, which are called user modules. Examples of

user modules are analog-to-digital converters (ADCs),

digital-to-analog converters (DACs), amplifiers, and filters.

Configure the user modules for your chosen application and

connect them to each other and to the proper pins. Then

generate your project. This prepopulates your project with APIs

and libraries that you can use to program your application.

Technical support – including a searchable Knowledge Base

articles and technical forums – is also available online. If you

cannot find an answer to your question, call our Technical

Support hotline at 1-800-541-4736.

The tool also supports easy development of multiple configura-

tions and dynamic reconfiguration. Dynamic reconfiguration

makes it possible to change configurations at run time. In

essence, this allows you to use more than 100 percent of PSoC's

resources for a given application.

Code Generation Tools

The code generation tools work seamlessly within the

PSoC Designer interface and have been tested with a full range

of debugging tools. You can develop your design in C, assembly,

or a combination of the two.

Assemblers. The assemblers allow you to merge assembly

code seamlessly with C code. Link libraries automatically use

absolute addressing or are compiled in relative mode, and linked

with other software modules to get absolute addressing.

Document Number: 001-55397 Rev. *I

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C Language Compilers. C language compilers are available

that support the PSoC family of devices. The products allow you

to create complete C programs for the PSoC family devices. The

optimizing C compilers provide all of the features of C, tailored

to the PSoC architecture. They come complete with embedded

libraries providing port and bus operations, standard keypad and

display support, and extended math functionality.

Configure User Modules

Each user module that you select establishes the basic register

settings that implement the selected function. They also provide

parameters and properties that allow you to tailor their precise

configuration to your particular application. For example, a pulse

width modulator (PWM) User Module configures one or more

digital PSoC blocks, one for each 8 bits of resolution. The user

module parameters permit you to establish the pulse width and

duty cycle. Configure the parameters and properties to corre-

spond to your chosen application. Enter values directly or by

selecting values from drop-down menus. All the user modules

are documented in datasheets that may be viewed directly in

PSoC Designer or on the Cypress website. These user module

datasheets explain the internal operation of the user module and

provide performance specifications. Each datasheet describes

the use of each user module parameter, and other information

you may need to successfully implement your design.

Debugger

PSoC Designer has a debug environment that provides

hardware in-circuit emulation, allowing you to test the program in

a physical system while providing an internal view of the PSoC

device. Debugger commands allow you to read and program and

read and write data memory, and read and write I/O registers.

You can read and write CPU registers, set and clear breakpoints,

and provide program run, halt, and step control. The debugger

also allows you to create a trace buffer of registers and memory

locations of interest.

Organize and Connect

Online Help System

You build signal chains at the chip level by interconnecting user

modules to each other and the I/O pins. You perform the

selection, configuration, and routing so that you have complete

control over all on-chip resources.

The online help system displays online, context-sensitive help.

Designed for procedural and quick reference, each functional

subsystem has its own context-sensitive help. This system also

provides tutorials and links to FAQs and an Online Support

Forum to aid the designer.

Generate, Verify, and Debug

When you are ready to test the hardware configuration or move

on to developing code for the project, you perform the “Generate

Configuration Files” step. This causes PSoC Designer to

generate source code that automatically configures the device to

your specification and provides the software for the system. The

generated code provides application programming interfaces

(APIs) with high-level functions to control and respond to

hardware events at run time and interrupt service routines that

you can adapt as needed.

In-Circuit Emulator

A low-cost, high-functionality In-Circuit Emulator (ICE) is

available for development support. This hardware can program

single devices.

The emulator consists of a base unit that connects to the PC

using a USB port. The base unit is universal and operates with

all PSoC devices. Emulation pods for each device family are

available separately. The emulation pod takes the place of the

PSoC device in the target board and performs full-speed

(24-MHz) operation.

A complete code development environment allows you to

develop and customize your applications in either C, assembly

language, or both.

Designing with PSoC Designer

The last step in the development process takes place inside

PSoC Designer’s debugger (access by clicking the Connect

icon). PSoC Designer downloads the HEX image to the ICE

where it runs at full speed. PSoC Designer debugging capabil-

ities rival those of systems costing many times more. In addition

to traditional single-step, run-to-breakpoint and watch-variable

features, the debug interface provides a large trace buffer and

allows you to define complex breakpoint events that include

monitoring address and data bus values, memory locations and

external signals.

The development process for the PSoC® device differs from that

of a traditional fixed function microprocessor. The configurable

analog and digital hardware blocks give the PSoC architecture a

unique flexibility that pays dividends in managing specification

change during development and by lowering inventory costs.

These configurable resources, called PSoC Blocks, have the

ability to implement a wide variety of user-selectable functions.

The PSoC development process is summarized in four steps:

1. Select User Modules.

2. Configure user modules.

3. Organize and connect.

4. Generate, verify, and debug.

Select User Modules

PSoC Designer provides a library of prebuilt, pretested hardware

peripheral components called “user modules.” User modules

make selecting and implementing peripheral devices, both

analog and digital, simple.

Document Number: 001-55397 Rev. *I

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Pinouts

The automotive CY8C21x45 and CY8C22x45 PSoC devices are available in a variety of packages which are listed and illustrated in

the following tables. Every port pin (labeled with a “P”) is capable of digital I/O and connection to the common analog mux bus.

However, V_SS, V_DD, and XRES are not capable of digital I/O.

28-Pin Part Pinout

Table 2. 28-Pin Part Pinout (SSOP)

Type

Pin Name

Description

Figure 3. CY8C21345, CY8C22345, and CY8C22345H

28-Pin PSoC Device

No.

Digital Analog

1

I/O

I, MR

I, ML

P0[7]

P0[5]

Analog column mux input, C

capacitor pin

MOD

AI, MR, P0[7]

AI, ML, P0[5]

AI, ML, P0[3]

AI, ML, P0[1]

AI, ML, P2[7]

EXTREF, ML, P2[5]

ML, P2[3]

V_DD

1

2

28

2

Analog column mux input, C

capacitor pin

27 P0[6], MR, AI

26 P0[4], MR, AI

3

4

5

6

I/O

I, ML

ML

P0[3]

P0[1]

P2[7]

P2[5]

Analog column mux input

Direct input to analog block

P0[2], MR, AI

P0[0], MR, AI

P2[6], MR, AI

4

25

24

23

5

6

7

22 P2[4], MR

21 P2[2], MR

SSOP

Optional SAR ADC external reference

(EXTREF)

ML, P2[1]

8

V_SS

P2[0], MR

XRES

9

20

19

18

I2C SCL, ML, P1[7]

I2C SDA, ML, P1[5]

10

11

7

8

I/O

ML

P2[3]

P2[1]

P1[6], MR

ML, P1[3] 12

17 P1[4], MR, EXTCLK

16 P1[2], MR

9

Power

V

Ground connection

XTALin, I2C SCL, ML, P1[1] 13

SS

2

V_SS

P1[0], MR, I2C SDA, XTALout

14

15

10

11

12

13

I/O

ML

P1[7]

P1[5]

P1[3]

P1[1]

I C Serial Clock (SCL)

2

I C Serial Data (SDA)

2

Crystal Input (XTALin), I C SCL,

ISSP-SCLK

[5]

14

15

Power

V

Ground Connection

SS

2

I/O

MR

P1[0]

Crystal Output (XTALout), I C SDA,

[5]

ISSP-SDATA

16

17

18

19

I/O

MR

P1[2]

P1[4]

P1[6]

XRES

Optional external clock input (EXTCLK)

Input

Active high external reset with internal

pull-down

20

21

22

23

24

25

26

27

28

I/O

MR

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

I, MR

Direct input to analog block

Analog column mux input

Supply voltage

Power

V

DD

LEGEND: A = Analog, I = Input, O = Output, MR= Right analog mux bus input, ML= Left analog mux bus input.

Note

5. These are the ISSP pins, which are not High Z after exiting a reset state. See the PSoC Technical Reference Manual for CY8C21x45 and CY8C22x45 devices for details.

Document Number: 001-55397 Rev. *I

Page 8 of 36

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48-Pin Part Pinout

Table 3. 48-Pin Part Pinout (SSOP)

Type

No.

Pin Name

Description

Digital Analog

1

I/O

I, MR

P0[7]

Analog column mux input, C

capacitor pin

Figure 4. CY8C21645 and CY8C22645

48-Pin PSoC Device

MOD

2

I/O

I, ML

P0[5]

Analog column mux input, C

capacitor pin

AI, MR, P0[7]

AI, ML, P0[5]

AI, ML, P0[3]

AI, ML, P0[1]

AI, ML, P2[7]

EXTREF, ML, P2[5]

ML, P2[3]

V_DD

1

2

48

47

P0[6], MR, AI

3

I/O

I, ML

ML

P0[3]

P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

Analog column mux input

Direct input to analog block

3

46 P0[4], MR, AI

P0[2], MR, AI

4

45

5

44 P0[0], MR, AI

43 P2[6], MR, AI

42 P2[4], MR

41 P2[2], MR

40 P2[0], MR

39 V_SS

6

Optional SAR ADC external reference

6

7

ML

ML, P2[1]

8

ML

V_DD

9

Power

V

DD

Supply voltage

ML, P4[5]

10

11

10

11

12

13

14

15

16

17

18

19

20

21

22

23

I/O

ML

P4[5]

P4[3]

P4[1]

ML, P4[3]

38 P4[4], MR

37 P4[2], MR

36 P4[0], MR

35 XRES

ML, P4[1] 12

V_SS13

SSOP

ML, P3[7]

ML, P3[5]

14

15

Power

V

Ground connection

SS

34 P3[6], MR

33 P3[4], MR

32 P3[2], MR

31 P3[0], MR

I/O

ML

P3[7]

P3[5]

P3[3]

P3[1]

NC

ML, P3[3] 16

ML, P3[1]

NC

17

18

19

20

21

NC

30

NC

I2C SCL, ML, P1[7]

I2C SDA, ML, P1[5]

29 NC

Not connected

28 P1[6], MR

NC

ML, P1[3] 22

27 P1[4], MR, EXTCLK

26 P1[2], MR

2

I/O

ML

P1[7]

P1[5]

P1[3]

P1[1]

I C Serial Clock

XTALin, I2C SCL, ML, P1[1]

V_SS

23

24

2

I C Serial Data

25 P1[0], MR, I2C SDA, XTALout

2

Crystal Input (XTALin), I C SCL,

[6]

ISSP-SCLK

24

25

Power

V

SS

2

I/O

MR

P1[0]

Crystal Output (XTALout), I C SDA,

[6]

ISSP-SDATA

26

27

28

29

30

31

32

33

34

35

I/O

MR

P1[2]

P1[4]

P1[6]

NC

Optional external clock input

Not connected

NC

I/O

MR

P3[0]

P3[2]

P3[4]

P3[6]

XRES

Input

Active high external reset with internal

pull-down

36

37

38

39

40

I/O

MR

P4[0]

P4[2]

P4[4]

Power

MR

V

Ground Connection

SS

I/O

P2[0]

Note

6. These are the ISSP pins, which are not High Z after exiting a reset state. See the PSoC Technical Reference Manual for CY8C21x45 and CY8C22x45 devices for

details.

Document Number: 001-55397 Rev. *I

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CY8C22345, CY8C22345H, CY8C22645

Table 3. 48-Pin Part Pinout (SSOP) (continued)

Type

No.

Pin Name

Description

Digital Analog

41

42

43

44

45

46

47

48

I/O

MR

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

MR

I, MR

Direct input to analog block

Analog column mux input

Supply voltage

Power

V

DD

LEGEND: A = Analog, I = Input, O = Output, MR= Right analog mux bus input, ML= Left analog mux bus input

Document Number: 001-55397 Rev. *I

Page 10 of 36

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CY8C21345, CY8C21645

CY8C22345, CY8C22345H, CY8C22645

Registers

This section lists the registers of this PSoC device family by mapping tables. For detailed register information, refer to the PSoC

Technical Reference Manual for CY8C21x45 and CY8C22x45 devices.

Register Conventions

Register Mapping Tables

The register conventions specific to this section are listed in the

following table.

The PSoC device has a total register address space of 512

bytes. The register space is referred to as I/O space and is

divided into two banks. The XIO bit in the Flag register (CPU_F)

determines which bank the user is currently in. When the XIO bit

is set the user is in Bank 1.

Table 4. Abbreviations

Convention

RW

Description

Read and write register or bit(s)

Read register or bit(s)

Note In the following register mapping tables, blank fields are

Reserved and must not be accessed.

R

W

L

Write register or bit(s)

Logical register or bit(s)

Clearable register or bit(s)

Access is bit specific

C

#

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Table 5. Register Map Bank 0 Table: User Space

Addr

(0,Hex)

Addr

(0,Hex)

Name

Access

Name

Access

Name

ASE10CR0

Access

Name

Access

(0,Hex)

PRT0DR

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

40

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

PRT0IE

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

PRT0GS

PRT0DM2

PRT1DR

PRT1IE

ASE11CR0

RW

PRT1GS

PRT1DM2

PRT2DR

PRT2IE

PWMVREF0

PWMVREF1

IDAC_MODE

PWM_SRC

TS_CR0

#

PRT2GS

PRT2DM2

PRT3DR

PRT3IE

RW

#

RW

TS_CMPH

TS_CMPL

TS_CR1

PRT3GS

PRT3DM2

PRT4DR

PRT4IE

CSD0_DR0_L

CSD0_DR1_L

CSD0_CNT_L

CSD0_CR0

CSD0_DR0_H

CSD0_DR1_H

CSD0_CNT_H

CSD0_CR1

CSD1_DR0_L

CSD1_DR1_L

CSD1_CNT_L

CSD1_CR0

CSD1_DR0_H

CSD1_DR1_H

CSD1_CNT_H

CSD1_CR1

AMX_IN

R

W

R

CUR PP

STK_PP

PRT4GS

PRT4DM2

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

#

IDX_PP

RW

#

R

MVR_PP

W

R

MVW_PP

I2C0_CFG

I2C0_SCR

I2C0_DR

I2C0_MSCR

INT_CLR0

INT_CLR1

INT_CLR2

INT_CLR3

INT_MSK3

INT_MSK2

INT_MSK0

INT_MSK1

INT_VC

RW

R

RW

#

W

R

RW

RC

W

#

R

W

R

RW

#

DBC00DR0

DBC00DR1

DBC00DR2

DBC00CR0

DBC01DR0

DBC01DR1

DBC01DR2

DBC01CR0

DCC02DR0

DCC02DR1

DCC02DR2

DCC02CR0

DCC03DR0

DCC03DR1

DCC03DR2

DCC03CR0

DBC10DR0

DBC10DR1

DBC10DR2

DBC10CR0

DBC11DR0

DBC11DR1

DBC11DR2

DBC11CR0

DCC12DR0

DCC12DR1

DCC12DR2

DCC12CR0

DCC13DR0

DCC13DR1

DCC13DR2

DCC13CR0

#

W

RW

#

AMUX_CFG

PWM_CR

ARF_CR

RES_WDT

#

CMP_CR0

W

RW

#

ASY_CR

#

CMP_CR1

RW

DEC _CR0

DEC_CR1

MUL0_X

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

RW

W

#

ADC0_CR

ADC1_CR

SADC_DH

SADC_DL

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

#

W

RW

#

W

MUL0_Y

RW

R

MUL0_DH

MUL0_DL

ACC0_DR1

ACC0_DR0

ACC0_DR3

ACC0_DR2

R

#

RW

W

RW

#

RDI0RI

RW

W

RW

#

RDI0SYN

RDI0IS

ACE00CR1

ACE00CR2

RW

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

RDI0DSM

RDI1RI

#

W

RW

#

ACE01CR1

ACE01CR2

RW

CPU_F

RL

#

W

RW

#

RDI1SYN

RDI1IS

RDI1LT0

RDI1LT1

RDI1RO0

RDI1RO1

#

IDACR_D

IDACL_D

RW

#

W

RW

#

CPU_SCR1

CPU_SCR0

RDI1DSM

#

Blank fields are Reserved and must not be accessed.

# Access is bit specific.

Document Number: 001-55397 Rev. *I

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Table 6. Register Map Bank 1 Table: Configuration Space

Addr

(1,Hex)

Addr

(1,Hex)

Name

Access

Name

Access

Name

ASE10CR0

Access

Name

Access

(1,Hex)

PRT0DM0

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

PRT0DM1

PRT0IC0

PRT0IC1

PRT1DM0

PRT1DM1

PRT1IC0

PRT1IC1

PRT2DM0

PRT2DM1

PRT2IC0

PRT2IC1

PRT3DM0

PRT3DM1

PRT3IC0

PRT3IC1

PRT4DM0

PRT4DM1

PRT4IC0

PRT4IC1

ASE11CR0

RW

CMP0CR1

RW

GDI_O_IN

RW

CMP0CR2

GDI_E_IN

GDI_O_OU

GDI_E_OU

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

VDAC50CR0

CMP1CR1

CMP1CR2

RW

VDAC51CR0

CSCMPCR0

CSCMPGOEN

CSLUTCR0

CMPCOLMUX

CMPPWMCR

CMPFLTCR

CMPCLK1

CMPCLK0

CLK_CR0

RW

#

MUX_CR0

MUX_CR1

MUX_CR2

MUX_CR3

DAC_CR1#

OSC_GO_EN

OSC_CR4

OSC_CR3

OSC_CR0

OSC_CR1

OSC_CR2

VLT_CR

RW

R

RW

DBC00FN

DBC00IN

RW

GDI_O_IN_CR

GDI_E_IN_CR

GDI_O_OU_CR

GDI_E_OU_CR

RTC_H

RW

CLK_CR1

DBC00OU

DBC00CR1

DBC01FN

DBC01IN

ABF_CR0

AMD_CR0

CMP_GO_EN

CMP_GO_EN1

AMD_CR1

ALT_CR0

VLT_CMP

ADC0_TR

ADC1_TR

V2BG_TR

IMO_TR

RTC_M

RW

W

DBC01OU

DBC01CR1

DCC02FN

DCC02IN

DCC02OU

DBC02CR1

DCC03FN

DCC03IN

DCC03OU

DBC03CR1

DBC10FN

DBC10IN

RTC_S

RTC_CR

ALT_CR1

SADC_CR0

SADC_CR1

SADC_CR2

SADC_CR3TRIM

SADC_CR4

I2C0_AD

CLK_CR2

ILO_TR

W

AMUX_CFG1

CLK_CR3

BDG_TR

RW

W

ECO_TR

TMP_DR0

MUX_CR4

RW

TMP_DR1

TMP_DR2

TMP_DR3

RDI0RI

RW

RDI0SYN

RDI0IS

DBC10OU

DBC10CR1

DBC11FN

DBC11IN

ACE00CR1

ACE00CR2

RW

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

RDI0DSM

RDI1RI

DBC11OU

DBC11CR1

DCC12FN

DCC12IN

DCC12OU

DBC12CR1

DCC13FN

DCC13IN

DCC13OU

DBC13CR1

ACE01CR1

ACE01CR2

RW

CPU_F

RL

RDI1SYN

RDI1IS

FLS_PR1

RW

RDI1LT0

RDI1LT1

RDI1RO0

RDI1RO1

DAC_CR0#

CPU_SCR1

CPU_SCR0

RW

#

RDI1DSM

#

Blank fields are Reserved and must not be accessed.

# Access is bit specific.

Document Number: 001-55397 Rev. *I

Page 13 of 36

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CY8C22345, CY8C22345H, CY8C22645

Electrical Specifications

This section presents the DC and AC electrical specifications for automotive CY8C21x45 and CY8C22x45 PSoC devices. For the

latest electrical specifications, check the most recent data sheet by visiting the web at http://www.cypress.com.

Specifications are valid for A-grade devices at –40 °C  T  85 °C, T  100 °C, and for E-grade devices at –40 °C  T  125 °C,

A

J

A

T  150 °C, unless noted otherwise.

J

Figure 5. Voltage vs. CPU Frequency for A-grade Devices

Figure 6. Voltage vs. CPU Frequency for E-grade Devices

5.25

4.75

3.0

0

93 kHz

12 MHz

24 MHz

93 kHz

12 MHz

24 MHz

CPU Frequency

(nominal setting)

CPU Frequency

(nominal setting)

Figure 7. IMO Frequency Trim Options (A-grade Devices Only)

5.25

SLIMO

Mode=1

Mode=0

4.75

3.6

3.0

SLIMO

Mode=1

SLIMO

Mode=0

0

6 MHz

12 MHz

IMO Frequency

24 MHz

Document Number: 001-55397 Rev. *I

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Absolute Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.

Table 7. Absolute Maximum Ratings

Symbol

T_STG

Description

Storage temperature

Min

Typ

Max

Units

Notes

–55

25

+150

°C

Recommended storage

temperature is 25 °C ±

25 °C. Higher storage

temperatures reduce

data retention time.

T_BAKETEMPBake temperature

T_BAKETIMEBake time

–

125

–

See

package

label

C

See

package

label

72

Hours

T_A

Ambient temperature with power applied

A-grade devices

E-grade devices

–40

–

+85

+125

°C

V_DD

V_IO

Supply voltage on V_DDrelative to V_SS

DC input voltage

–0.5

V_SS– 0.5

–25

–

+6.0

V_DD+ 0.5

+50

V

V_IOz

I_MIO

ESD

LU

DC voltage applied to tristate

Maximum current into any port pin

Electrostatic discharge voltage

Latch up current

V

mA

V

2000

–

Human body model ESD

–

200

mA

Operating Temperature

Table 8. Operating Temperature

Symbol

Description

Min

Typ

Max

Units

Notes

T_A

Ambient temperature

A-grade devices

E-grade devices

–40

–

+85

+125

°C

T_J

Junction temperature

A-grade devices

E-grade devices

The temperature rise

–40

–

+100

+135

°C

from ambient to junction

is package specific. See

Table24onpage27. The

user must limit the power

consumption to comply

with this requirement.

Document Number: 001-55397 Rev. *I

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DC Electrical Characteristics

DC Chip Level Specifications

Table 9 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise

noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C

to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices

for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,

unless specified otherwise, and are for design guidance only.

Table 9. DC Chip Level Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

V_DD

Supply voltage

A-grade devices

E-grade devices

See Table 14 on page 19

3.0

4.75

–

5.25

V

I_DD

Supply current

CPU = 3 MHz, 48 MHz disabled.

A-grade devices, 3.0 V  V_DD 3.6 V

A-grade devices, 4.75 V  V_DD 5.25 V

E-grade devices

–

4

7

8

7

12

15

mA VC1=1.5MHz, VC2=93.75kHz,

mA VC3 = 93.75 kHz, Analog blocks

mA disabled

I_SB

Sleep (mode) current

Everything disabled except ILO,

A POR, LVD, Sleep Timer, and

A WDT circuits

A-grade devices, 3.0 V  V_DD 3.6 V

A-grade devices, 4.75 V  V_DD 5.25 V

E-grade devices

–

3

4

12

25

A

I_SBXTL

Sleep (mode) current with ECO

A-grade devices, 3.0 V  V_DD 3.6 V

A-grade devices, 4.75 V  V_DD 5.25 V

E-grade devices

Everything disabled except ECO,

A POR, LVD, Sleep Timer, and

A WDT circuits

–

4

5

13

26

A

V_REF

Reference voltage (Bandgap)

1.275

1.30

1.325

V

Trimmed for appropriate V_DD

setting.

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DC General Purpose I/O Specifications

Table 10 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise

noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C

to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices

for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,

unless specified otherwise, and are for design guidance only.

Table 10. DC GPIO Specifications

Symbol

R_PU

Description

Pull-up resistor

Min

4

Typ

5.6

–

Max

Units

k

Notes

8

–

R_PD

V_OH

Pull-down resistor

High output level

V_DD– 1.0

V

I_OH= 10 mA, V_DD= 4.75 to 5.25 V

(80 mA maximum combined I_OH

budget)

V_OL

I_OH

I_OL

Low output level

–

0.75

–

V

I_OL= 25 mA, V_DD= 4.75 to 5.25 V

(100 mA maximum combined I_OL

budget)

High-level source current

Low-level sink current

10

25

mA V_OH V_DD– 1.0 V, see the limitations

of the total current in the note for

V_OH

.

–

mA V_OL 0.75 V, see the limitations

of the total current in the note for

V_OL

.

V_IL

V_IH

V_H

I_IL

Input low level

–

2.1

–

0.8

V

Input high level

Input hysteresis

60

1

–

mV

Input leakage (absolute value)

Capacitive load on pins as input

–

nA Gross tested to 1 A

pF Package and pin dependent.

Temp = 25 °C

C_IN

–

3.5

10

C_OUT

Capacitive load on pins as output

–

3.5

10

pF Package and pin dependent.

Temp = 25 °C

DC Operational Amplifier Specifications

The following table lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless

otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V

and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade

devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V

at 25°C, unless specified otherwise, and are for design guidance only.

Table 11. DC Operational Amplifier Specifications

Symbol

V_OSOA

I_SOA

Description

Input offset voltage (absolute value)

Min

–

Typ

2.5

Max

15

Units

mV

Notes

Supply current (absolute value)

A-grade devices

E-grade devices

–

30

35

A

µA

TCV_OSOAAverage input offset voltage drift

–

10

200

4.5

–

V/°C

[7]

I_EBOA

Input leakage current (Port 0 analog pins)

Input capacitance (Port 0 analog pins)

pA Gross tested to 1 A

pF Package and pin dependent.

Temp = 25 °C

C_INOA

9.5

V_CMOA

Common mode voltage range

0.5

–

V_DD– 1

V

Note

7. Atypical behavior: I

of Port 0 Pin 0 is below 1 nA at 25 °C; 50 nA over temperature. Use Port 0 Pins 1 – 7 for the lowest leakage of 200 nA.

EBOA

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DC SAR10 ADC Specifications

Table 12 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise

noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C

to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices

for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,

unless specified otherwise, and are for design guidance only.

Table 12. DC SAR10 ADC Specifications

Symbol

V_ADCREF

Description

Min

Typ

Max Units

5.25

Notes

Reference voltage at pin P2[5] when configured

as ADC reference voltage

3.0

–

V

When V_REFis buffered inside

ADC, the voltage level at P2[5]

(when configured as ADC

reference voltage) must be

always maintained to be at least

300mVlessthanthechipsupply

voltage level on V_DDpin.

(V_ADCREF< V_DD

)

I_ADCREF

INL_ADC

Current into P2[5] when configured as ADC V_REF

–

100

µA Disables the internal voltage

reference buffer

Integral nonlinearity

A-grade devices

E-grade devices

10-bit resolution

–3.0

–5.0

–

3.0

5.0

LSbit

DNL_ADC

Differential nonlinearity

A-grade devices

E-grade devices

10-bit resolution

–1.5

–4.0

–

1.5

4.0

LSbit

DC Analog Mux Bus Specifications

Table 13 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise

noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C

to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices

for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,

unless specified otherwise, and are for design guidance only.

Table 13. DC Analog Mux Bus Specifications

Symbol

R_SW

R_GND

Description

Min

–

Typ

–

Max

400

800

Units



Notes

Switch resistance to common analog bus

Resistance of initialization switch to GND

–



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DC POR and LVD Specifications

Table 14 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise

noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C

to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices

for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,

unless specified otherwise, and are for design guidance only.

Table 14. DC POR and LVD Specifications

Symbol

Description

V_DDvalue for PPOR trip

Min

Typ

Max

Units

Notes

V

_DDmust be greater than or

V_PPOR1

V_PPOR2

PORLEV[1:0] = 01b

PORLEV[1:0] = 10b

–

2.82

4.55

2.95

4.73

V

equal to 3.0 V during startup,

reset from the XRES pin, or

reset from Watchdog. V_PPOR1is

only applicable to A-grade

devices.

V_DDvalue for LVD trip

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

V_LVD2

V_LVD3

V_LVD4

V_LVD5

V_LVD6

V_LVD7

2.95

3.06

4.37

4.50

4.62

4.71

3.02

3.13

4.48

4.64

4.73

4.81

3.09

3.20

4.55

4.75

4.83

4.95

V

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DC Programming Specifications

Table 15 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise

noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C

to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices

for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,

unless specified otherwise, and are for design guidance only.

Table 15. DC Programming Specifications

Symbol

Description

Min

3.0

–

Typ

–

Max

–

Units

V

Notes

V_DDIWRITESupply voltage for flash write operations

I_DDP

V_ILP

V_IHP

I_ILP

Supply current during programming or verify

Input low voltage during programming or verify

Input high voltage during programming or verify

5

25

0.8

–

mA

V

–

2.2

–

V

Input current when applying V_ILPto P1[0] or

P1[1] during programming or verify

–

0.2

mA Driving internal pull-down

resistor

I_IHP

Input current when applying V_IHPto P1[0] or

P1[1] during programming or verify

–

1.5

0.75

V_DD

mA Driving internal pull-down

resistor

V_OLV

V_OHV

Output low voltage during programming or

verify

V

Output high voltage during programming or

verify

V_DD– 1.0

V

Flash_ENPBFlash endurance (per block)^{[8, 9]}

A-grade devices

Erase/write cycles per block

1,000

100

–

E-grade devices

Flash_ENTFlash endurance (total)^{[9, 10]}

CY8C21x45 A-grade devices

CY8C22x45 A-grade devices

CY8C21x45 E-grade devices

CY8C22x45 E-grade devices

Erase/write cycles

128,000

256,000

12,800

25,600

–

Flash_DR

Flash data retention^[9]

A-grade devices

E-grade devices

10

–

Years

Notes

8. The erase/write cycle limit per block (Flash

) is only guaranteed if the device operates within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to

ENPB

5.25 V.

9. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor and feed the result to the temperature

argument before writing. Refer to the Flash APIs Application Note AN2015 for more information.

10. The maximum total number of allowed erase/write cycles is the minimum Flash

value multiplied by the number of flash blocks in the device.

ENPB

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AC Electrical Characteristics

AC Chip Level Specifications

The following tables list the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless

otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V

and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade

devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V

at 25 °C, unless specified otherwise, and are for design guidance only.

Table 16. AC Chip-Level Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

F

Trimmed for 5 V or 3.3 V operation

Internal main oscillator frequency for 24 MHz

IMO24

[11]

22.8

22.5

22.3

24

MHz using factory trim values. See

MHz Figure 7 on page 14.

MHz

25.2

25.5

25.7

A-grade devices, 4.75 V  V  5.25 V

DD

A-grade devices, 3.0 V  V  3.6 V

DD

E-grade devices

F

Internal main oscillator frequency for 6 MHz

A-grade devices

Trimmed for 5 V or 3.3 V operation

MHz using factory trim values. See

MHz Figure 7 on page 14.

IMO6

[11]

5.5

6

6.5

E-grade devices

CPU frequency (5 V V operation)

CPU1

DD

[11]

A-grade devices

E-grade devices

0.089

–

MHz

25.2

12.6

[11]

F

CPU frequency (3.3 V V operation)

0.089

–

MHz A-grade devices only

Refer to Table 19 on page 23.

12.6

CPU2

DD

0

Digital PSoC block frequency (5 V V

operation)

BLK5

DD

[11, 12]

A-grade devices

0

48

24

MHz

50.4

25.2

E-grade devices

[11]

F

Digital PSoC block frequency (3.3 V V

operation)

0

15

5

24

32

–

MHz A-grade devices only

24.6

BLK33

DD

ILO frequency

75

–

kHz This specification applies when

the ILO has been trimmed.

32K1

ILO untrimmed frequency

kHz After a reset and before the M8C

processor starts to execute, the ILO

is not trimmed.

32KU

Jitter32k

32 kHz RMS period jitter

External reset pulse width

–

100

–

ns

µs

T

10

XRST

DC24M

DC

24 MHz duty cycle

ILO duty cycle

40

20

45.6

–

50

60

80

%

ILO

[11]

Fout48M

48 MHz output frequency

48.0

300

–

50.4

600

MHz

ps

Jitter24M1 24 MHz period jitter (IMO)

F

Maximum frequency of signal on row input or

row output

–

12.6

MHz

MAX

SR

Power supply slew rate

–

250

100

V/ms

ms

V

slew rate during power-up.

DD

POWERUP

T

Time between end of POR state and CPU code

execution

16

Power-up from 0 V.

POWERUP

Figure 8. 24 MHz Period Jitter (IMO) Timing Diagram

Jitter24M1

F_24M

Notes

11. Accuracy derived from IMO with appropriate trim for V range

DD

12. Refer to the individual user module data sheets for information on maximum frequencies for user modules.

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Figure 9. 32 kHz Period Jitter (ILO) Timing Diagram

Jitter32k

F_32K1

AC General Purpose I/O Specifications

Table 17 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise

noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C

to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices

for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,

unless specified otherwise, and are for design guidance only.

Table 17. AC GPIO Specifications

Symbol

F_GPIO

Description

GPIO operating frequency

Min

Typ

Max

Units

Notes

0

–

12.6

MHz Normal strong mode

TRiseF

TFallF

TRiseS

TFallS

Rise time, normal strong mode, Cload = 50 pF

A-grade devices

E-grade devices

Refer to Figure 10

3

–

18

24

ns

Fall time, normal strong mode, Cload = 50 pF

A-grade devices

E-grade devices

Refer to Figure 10

2

–

18

28

ns

Rise time, slow strong mode, Cload = 50 pF

A-grade devices

E-grade devices

Refer to Figure 10

7

27

32

–

ns

Fall time, slow strong mode, Cload = 50 pF

A-grade devices

E-grade devices

Refer to Figure 10

7

22

28

–

ns

Figure 10. GPIO Timing Diagram

90%

GPIO

Output

Voltage

10%

TRiseF

T RiseS

TFallF

TFallS

AC Operational Amplifier Specifications

Table 18 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise

noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C

to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices

for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,

unless specified otherwise, and are for design guidance only.

Table 18. AC Operational Amplifier Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

T_COMP

Comparator mode response time, 50 mV

–

100

ns

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AC Digital Block Specifications

The following tables list the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless

otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V

and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade

devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V

at 25 °C, unless specified otherwise, and are for design guidance only.

Table 19. AC Digital Block Specifications

Function

All

Functions

Description

Min

–

Typ

–

Max

50.4

25.2

Units

Notes

Maximum block clocking frequency ( 4.75 V)

Maximum block clocking frequency (< 4.75 V)

MHz Note [14]

–

MHz V_DD< 4.75 V and/or temperature

> 85 °C

Timer

Capture pulse width

50^[13]

–

ns

Maximum frequency, no capture

Maximum frequency, with or without capture

Enable pulse width

–

50.4

25.2

–

MHz Note [14]

–

50^[13]

–

MHz

Counter

ns

Maximum frequency, no enable input

Maximum frequency, enable input

Kill pulse width:

50.4

25.2

MHz Note [14]

MHz

–

Dead Band

Asynchronous restart mode

Synchronous restart mode

Disable mode

20

50^[13]

–

ns

–

ns

Maximum frequency

50.4

MHz Note [14]

CRCPRS

(PRS Mode)

Maximum input clock frequency

–

CRCPRS

(CRC Mode)

Maximum input clock frequency

–

25.2

8.4

MHz

SPIM

SPIS

MHz Maximum nominal data rate is

4 Mbps due to 2 x overclocking

–

4.2

–

MHz

ns

Width of SS_ negated between transmissions 50^[13]

Transmitter

Maximum input clock frequency

–

25.2

MHz Maximum nominal baud rate is

3 Mbaud due to 8 × overclocking

MHz Maximum nominal baud rate is

6 Mbaud due to 8 × overclocking

Maximum input clock frequency with

V_DD4.75 V, 2 stop bits

–

50.4

Receiver

Maximum input clock frequency

–

25.2

50.4

MHz Maximum nominal baud rate is

3 Mbaud due to 8 × overclocking

MHz Maximum nominal baud rate is

6 Mbaud due to 8 × overclocking

Maximum input clock frequency with

V_DD4.75 V, 2 stop bits

Notes

13. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

14. 4.75 V  V  5.25 V at –40 °C to 85 °C

DD

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AC External Clock Specifications

The following tables list the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless

otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V

and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade

devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V

at 25 °C, unless specified otherwise, and are for design guidance only.

Table 20. AC External Clock Specifications

Symbol

Description

Min

0.093

20.0

150

Typ

–

Max

24.6

5300

–

Units

MHz

ns

Notes

F_OSCEXT

Frequency

High period

Low period

–

ns

Power-up IMO to switch

–

s

AC SAR10 ADC Specifications

Table 21 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise

noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C

to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices

for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,

unless specified otherwise, and are for design guidance only.

Table 21. AC SAR10 ADC Specifications

Symbol

F_INADC

Description

Min

Typ

Max

Units

Notes

SAR ADC input clock frequency

–

2

MHz The sample rate of the SAR10

ADC is equal to F_INADCdivided

by 13.

AC Programming Specifications

Table 22 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise

noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C

to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices

for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,

unless specified otherwise, and are for design guidance only.

Table 22. AC Programming Specifications

Symbol

T_RSCLK

Description

Min

1

Typ

–

Max

20

Units

Notes

Rise time of SCLK

Fall time of SCLK

ns

T_FSCLK

T_SSCLK

T_HSCLK

F_SCLK

1

–

20

ns

Data setup time to falling edge of SCLK

Data hold time from falling edge of SCLK

Frequency of SCLK

40

0

–

ns

–

ns

–

8

MHz

F_SCLK3

T_ERASEB

T_WRITE

T_DSCLK

T_DSCLK3

T_PRGH

Frequency of SCLK

0

–

6

MHz V_DD 3.6 V

Flash erase time (block)

–

10

40

–

40^[15]

160^[15]

55

ms

Flash block write time

–

Data out delay from falling edge of SCLK

–

ns V_DD> 3.6 V, 30 pF load

ns 3.0 V V_DD3.6 V, 30 pF load

ms T_J 0 °C

–

65

100^[15]

Total flash block program time

(T_ERASEB+ T_WRITE), Hot

–

T_PRGC

Total flash block program time

(T_ERASEB+ T_WRITE), Cold

–

200^[15]

ms T_J0 °C

Note

15. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor and feed the result to the

temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information.

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AC I²C Specifications

Table 23 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise

noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C

to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices

for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,

unless specified otherwise, and are for design guidance only.

Table 23. AC Characteristics of the I²C SDA and SCL Pins

Standard Mode

Min Max

Fast Mode

Max

Symbol

Description

SCL clock frequency

Units

Min

0

F_SCLI2C

0

100^[16]

400^[16]

kHz

T_HDSTAI2CHold time (repeated) START condition. After this

period, the first clock pulse is generated.

4.0

–

0.6

–

s

T_LOWI2C

T_HIGHI2C

LOW period of the SCL clock

HIGH period of the SCL clock

4.7

4.0

4.7

0

–

1.3

0.6

–

s

ns

s

T_SUSTAI2CSetup time for a repeated START condition

T_HDDATI2CData hold time

0.6

0

T_SUDATI2CData setup time

250

4.0

4.7

100^[17]

T_SUSTOI2CSetup time for STOP condition

0.6

T_BUFI2C

Bus-free time between a STOP and START

condition

1.3

T_SPI2C

Pulse width of spikes are suppressed by the

input filter

–

0

50

ns

Figure 11. Definition for Timing for Fast/Standard Mode on the I²C Bus

SDA

SCL

T_SPI2C

T_LOWI2C

T_SUDATI2C

T_HDSTAI2C

T_BUFI2C

T_SUSTOI2C

T_SUSTAI2C

T_HDDATI2C

T_HDSTAI2C

T_HIGHI2C

S

Sr

P

S

Notes

16. F

is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the

specification adjusts accordingly.

SCLI2C

F

2

17. A Fast-Mode I C-bus device can be used in a Standard-Mode I C-bus system, but the requirement T

 250 ns must then be met. This is automatically the

SUDATI2C

case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit

2

to the SDA line t

+ T

= 1000 + 250 = 1250 ns (according to the standard-mode I C-bus specification) before the SCL line is released.

rmax

SUDATI2C

Document Number: 001-55397 Rev. *I

Page 25 of 36

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CY8C21345, CY8C21645

CY8C22345, CY8C22345H, CY8C22645

Packaging Information

This section provides the packaging specifications for the automotive CY8C21x45 and CY8C22x45 PSoC devices. The thermal

impedances for each package and the typical package capacitance on crystal pins are given.

Package Dimensions

Figure 12. 28-Pin (210-Mil) SSOP

51-85079 *D

Document Number: 001-55397 Rev. *I

Page 26 of 36

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CY8C21345, CY8C21645

CY8C22345, CY8C22345H, CY8C22645

Figure 13. 48-Pin (300-Mil) SSOP

.020

24

1

0.395

0.420

0.292

0.299

DIMENSIONS IN INCHES MIN.

MAX.

25

48

0.620

0.630

0.005

0.010

SEATING PLANE

.010

0.088

0.092

0.095

0.110

GAUGE PLANE

0.024

0.040

0.004

0.025

BSC

0°-8°

0.008

0.016

0.008

0.0135

51-85061 *D

Thermal Impedances

Table 24. Thermal Impedances per Package

Capacitance on Crystal Pins

Table 25. Typical Package Capacitance on Crystal Pins

[18]

Package

Typical _JA

Package

Package Capacitance

28-pin SSOP

48-pin SSOP

97.6 °C/W

69 °C/W

28-pin SSOP

48-pin SSOP

2.8 pF

3.3 pF

Solder Reflow Peak Temperature

Following is the minimum solder reflow peak temperature to achieve good solderability.

Table 26. Solder Reflow Peak Temperature

Package

Minimum Peak Temperature^[19]Maximum Peak Temperature

28-pin SSOP

48-pin SSOP

240 °C

260 °C

Notes

18. T = T + POWER x 

JA

J

A

19. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu

paste. Refer to the solder manufacturer specifications.

Document Number: 001-55397 Rev. *I

Page 27 of 36

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CY8C21345, CY8C21645

CY8C22345, CY8C22345H, CY8C22645

Tape and Reel Information

Figure 14. 28-Pin SSOP Carrier Tape Drawing

51-51100 *B

Document Number: 001-55397 Rev. *I

Page 28 of 36

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CY8C21345, CY8C21645

CY8C22345, CY8C22345H, CY8C22645

Figure 15. 48-Pin SSOP Carrier Tape Drawing

51-51104 *D

Table 27. Tape and Reel Specifications

Minimum

Trailing Empty

Pockets

Cover Tape

Package

Hub Size

(inches)

Minimum Leading

Empty Pockets

Standard Full Reel

Width (mm)

Quantity

28-Pin SSOP

48-Pin SSOP

13.3

25.5

7

4

42

32

25

19

1000

Document Number: 001-55397 Rev. *I

Page 29 of 36

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CY8C21345, CY8C21645

CY8C22345, CY8C22345H, CY8C22645

Development Tool Selection

This section presents the development tools available for the automotive CY8C21x45 and CY8C22x45 families.

CY3280-22X45 Universal CapSense Controller Board

Software

The CY3280-22X45 controller board is an additional controller

board for the CY3280-BK1 Universal CapSense Controller Kit.

The Universal CapSense Controller kit is designed for easy

prototyping and debug of CapSense designs with pre-defined

control circuitry and plug-in hardware. The CY3280-22X45 kit

contains no plug-in hardware. Therefore, it is only usable if

plug-in hardware is purchased as part of the CY3280-BK1 kit or

other separate kits. The kit includes:

PSoC Designer

At the core of the PSoC development software suite is PSoC

Designer. Utilized by thousands of PSoC developers, this robust

software has been facilitating PSoC designs for years. PSoC

Designer is available free of charge at http://www.cypress.com.

PSoC Designer comes with a free C compiler.

PSoC Programmer

■ CY3280-22X45 universal CapSense controller board

■ CY3280-22X45 universal CapSense controller board CD

■ DC power supply

Flexible enough to be used on the bench in development, yet

suitable for factory programming, PSoC Programmer works

either as a standalone programming application or it can operate

directly from PSoC Designer. PSoC Programmer software is

compatible with both PSoC ICE-Cube In-Circuit Emulator and

PSoC MiniProg. PSoC programmer is available free of charge at

http://www.cypress.com.

■ Printed documentation

CY3280-CPM1 CapSensePlus Module

The CY3280-CPM1 CapSensePlus Module is a plug-in module

board for the CY3280-22X45 CapSense controller board kit. This

plug-in module has no capacitive sensors on it. Instead, it has

other general circuitry (such as a seven-segment display,

potentiometer, LEDs, buttons, thermistor) that can be used to

develop applications that require capacitive sensing along with

other additional functionality. To use this kit, a CY3280-22X45 kit

is required.

Development Kits

All development kits can be purchased from the Cypress Online

Store. The online store also has the most up to date information

on kit contents, descriptions, and availability.

CY3215-DK Basic Development Kit

The CY3215-DK is for prototyping and development with PSoC

Designer. This kit supports in-circuit emulation and the software

interface allows users to run, halt, and single step the processor

and view the contents of specific memory locations. Advanced

emulation features are also supported through PSoC Designer.

The kit includes:

Evaluation Tools

All evaluation tools can be purchased from the Cypress online

store. The online store also has the most up-to-date information

on kit contents, descriptions, and availability.

■ ICE-Cube unit

CY3210-PSoCEval1

■ 28-pin PDIP emulation pod for CY8C29466-24PXI

■ 28-pin CY8C29466-24PXI PDIP PSoC device samples (two)

■ PSoC Designer software CD

The CY3210-PSoCEval1 kit features an evaluation board and

the MiniProg1 programming unit. The evaluation board includes

an LCD module, potentiometer, LEDs, an RS-232 port, and

plenty of breadboarding space to meet all of your evaluation

needs. The kit includes:

■ ISSP cable

■ Evaluation board with LCD module

■ MiniProg programming unit

■ MiniEval socket programming and evaluation board

■ Backward compatibility cable (for connecting to legacy pods)

■ Universal 110/220 power supply (12 V)

■ European plug adapter

■ 28-pin CY8C29466-24PXI PDIP PSoC device sample (two)

■ PSoC Designer software CD

■ Getting Started guide

■ USB 2.0 cable

■ Getting Started guide

■ Development kit registration form

Document Number: 001-55397 Rev. *I

Page 30 of 36

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CY8C21345, CY8C21645

CY8C22345, CY8C22345H, CY8C22645

CY3207ISSP In-System Serial Programmer

Device Programmers

The CY3207ISSP is a production programmer. It includes

protection circuitry and an industrial case that is more robust than

the MiniProg in a production-programming environment.

All device programmers can be purchased from the Cypress

Online Store.

CY3210-MiniProg1

Note CY3207ISSP needs special software and is not compatible

with PSoC Programmer. This software is free and can be

downloaded from http://www.cypress.com. The kit includes:

The CY3210-MiniProg1 kit allows the user to program PSoC

devices through the MiniProg1 programming unit. The MiniProg

is a small, compact prototyping programmer that connects to the

PC through a provided USB 2.0 cable. The kit includes:

■ CY3207 programmer unit

■ PSoC ISSP software CD

■ MiniProg programming unit

■ 110 ~ 240-V power supply, Euro-Plug adapter

■ USB 2.0 cable

■ MiniEval socket programming and evaluation board

■ 28-pin CY8C29466-24PXI PDIP PSoC device sample

■ PSoC Designer software CD

■ Getting Started guide

■ USB 2.0 cable

Accessories (Emulation and Programming)

Table 28. Emulation and Programming Accessories

Prototyping

Module

Part Number

Pin Package

Pod Kit^[20]

Foot Kit^[21]

Adapter^[22]

CY8C21345-24PVXA

CY8C21345-12PVXE

CY8C22345-24PVXA

CY8C22345H-24PVXA

CY8C22345-12PVXE

28-pin SSOP

CY3250-22345

CY3250-28SSOP-FK

–

AS-28-28-02SS-6ENP-GANG

CY8C21645-24PVXA

CY8C21645-12PVXE

CY8C22645-24PVXA

CY8C22645-12PVXE

48-pin SSOP

–

AS-48-48-01SS-6-GANG

Notes

20. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples.

21. Foot kit includes surface mount feet that can be soldered to the target PCB.

22. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at

http://www.emulation.com.

Document Number: 001-55397 Rev. *I

Page 31 of 36

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CY8C21345, CY8C21645

CY8C22345, CY8C22345H, CY8C22645

Ordering Information

The following table lists the key package features and ordering codes of the automotive CY8C21x45 and CY8C22x45 device families.

Table 29. PSoC Device Family Key Features and Ordering Information

28-pin (210-Mil) SSOP CY8C21345-24PVXA

8 K

512

4

6

24

0

Yes

–40 °C to +85 °C

28-pin (210-Mil) SSOP CY8C21345-24PVXAT

(Tape and Reel)

28-pin (210-Mil) SSOP CY8C21345-12PVXE

8 K

512

4

6

24

0

Yes

–40 °C to +125 °C

28-pin (210-Mil) SSOP CY8C21345-12PVXET

(Tape and Reel)

28-pin (210-Mil) SSOP CY8C22345-24PVXA

16 K 1 K

8

6

24

0

Yes

–40 °C to +85 °C

28-pin (210-Mil) SSOP CY8C22345-24PVXAT

(Tape and Reel)

28-pin (210-Mil) SSOP CY8C22345H-24PVXA

16 K 1 K

8

6

24

0

Yes

–40 °C to +85 °C

28-pin (210-Mil) SSOP CY8C22345H-24PVXAT 16 K 1 K

(Tape and Reel)

28-pin (210-Mil) SSOP CY8C22345-12PVXE

16 K 1 K

8

6

24

0

Yes

–40 °C to +125 °C

28-pin (210-Mil) SSOP CY8C22345-12PVXET

(Tape and Reel)

48-pin (300-Mil) SSOP CY8C21645-24PVXA

8 K

512

4

6

38

0

Yes

–40 °C to +85 °C

48-pin (300-Mil) SSOP CY8C21645-24PVXAT

(Tape and Reel)

48-pin (300-Mil) SSOP CY8C21645-12PVXE

8 K

512

4

6

38

0

Yes

–40 °C to +125 °C

48-pin (300-Mil) SSOP CY8C21645-12PVXET

(Tape and Reel)

48-pin (300-Mil) SSOP CY8C22645-24PVXA

16 K 1 K

8

6

38

0

Yes

–40 °C to +85 °C

48-pin (300-Mil) SSOP CY8C22645-24PVXAT

(Tape and Reel)

48-pin (300-Mil) SSOP CY8C22645-12PVXE

16 K 1 K

8

6

38

0

Yes

–40 °C to +125 °C

48-pin (300-Mil) SSOP CY8C22645-12PVXET

(Tape and Reel)

Document Number: 001-55397 Rev. *I

Page 32 of 36

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CY8C21345, CY8C21645

CY8C22345, CY8C22345H, CY8C22645

Ordering Code Definitions

CY 8 C 2x xxx x-SPxx

Package type:

Thermal rating:

PX = PDIP Pb-free

SX = SOIC Pb-free

PVX = SSOP Pb-free

A = Automotive –40 °C to +85 °C

C = Commercial

E = Automotive Extended –40 °C to +125 °C

LFX/LTX = QFN Pb-free I = Industrial

AX = TQFP Pb-free

CPU Speed: 12/24 MHz

Optional part number modifier: H = Integrated Immersion^®TouchSense^®technology

Part number

Family code (21, 22)

Technology code: C = CMOS

Marketing code: 8 = PSoC

Company ID: CY = Cypress Semiconductor

Document Number: 001-55397 Rev. *I

Page 33 of 36

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CY8C21345, CY8C21645

CY8C22345, CY8C22345H, CY8C22645

Document Conventions

Acronyms Used

Units of Measure

Table 30. Acronyms

Table 31. Units of Measure

Acronym

AC

Description

Symbol

°C

Unit of Measure

degree Celsius

alternating current

dB

decibels

ADC

AEC

API

analog-to-digital converter

Automotive Electronics Council

application programming interface

central processing unit

cyclic redundancy check

continuous time

fF

femto farad

hertz

Hz

KB

1024 bytes

CPU

CRC

CT

Kbit

kHz

k

LSbit

Mbaud

Mbps

MHz

M

A

F

H

s

V

1024 bits

kilohertz

kilohm

DAC

DC

digital-to-analog converter

direct current

least significant bit

megabaud

ECO

EEPROM

external crystal oscillator

megabits per second

megahertz

electrically erasable programmable read-only

memory

megaohm

ERM

FSR

GPIO

ICE

eccentric rotating motor

full scale range

microampere

microfarad

general purpose I/O

microhenry

microsecond

microvolts

in-circuit emulator

IDE

integrated development environment

input/output

I/O

Vrms

W

mA

ms

microvolts root-mean-square

microwatts

ILO

internal low-speed oscillator

internal main oscillator

imprecise power on reset

least significant bit

IMO

milliampere

millisecond

millivolts

IPOR

LSbit

LVD

mV

nA

nanoampere

nanosecond

nanovolts

low voltage detect

ns

MSbit

PC

most significant bit

nV

program counter



pA

ohm

PCB

POR

PPOR

PRS

PSoC

PWM

RAM

ROM

SC

printed circuit board

picoampere

picofarad

power on reset

pF

precision power on reset

pseudo-random sequence

Programmable System-on-Chip

pulse width modulator

random access memory

read only memory

pp

peak-to-peak

parts per million

picosecond

samples per second

sigma: one standard deviation

volts

ppm

ps

sps



V

switched capacitor

Numeric Naming

SMP

SPI

switch mode pump

Hexadecimal numbers are represented with all letters in

uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or

‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’

prefix, the C coding convention. Binary numbers have an

appended lowercase ‘b’ (for example, ‘01010100b’ or

‘01000011b’). Numbers not indicated by an ‘h’, ‘0x’, or ‘b’ are

decimal.

serial peripheral interface

universal asynchronous receiver/transmitter

UART

Document Number: 001-55397 Rev. *I

Page 34 of 36

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CY8C22345, CY8C22345H, CY8C22645

Document History Page

Document Title: CY8C21345, CY8C21645, CY8C22345, CY8C22345H, CY8C22645 Automotive PSoC^®

Programmable System-on-Chip™

Document Number: 001-55397

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

2759868

2788690

VIVG

09/04/09

10/20/09

New Datasheet

*A

Added 48 SSOP to the marketing part numbers.

Corrected the I_SOAspec in table 13/14.

Changed the ThetaJA values based on PE inputs.

*B

*C

2792800

2822630

VIVG

BTK

10/26/09

12/07/09

Corrected typo in ordering information table (Digital I/O for 48-SSOP devices)

Added CY8C22345H devices and updated Features section and PSoC

Functional Overview section to include haptics device information. Updated

Features section. Added Contents section. Updated PSoC Functional Overview

section. Updated Block Diagram of device. Updated PSoC Device Character-

istics table. Updated Pinouts section. Fixed issues with the Register Map tables.

Added a figure for SLIMO configuration. Updated footnotes for the DC

Programming Specifications table. Corrected V_DDIWRITEand Flash_ENTelectrical

specifications. Updated Ordering Information section. Added Development Tool

Selection section. Combined 5 V DC Operational Amplifier Specifications table

with 3.3 V DC Operational Amplifier Specifications table. Updated all AC speci-

fications to conform to 5% IMO accuracy and 8.33% SLIMO accuracy. Split up

electrical specifications for A-grade and E-grade devices in the Absolute

Maximum Ratings, Operating Temperature, DC Chip Level Specifications, DC

Programming Specifications, and AC Chip-Level Specifications tables. Added

Solder Reflow Peak Temperature table. Added T_PRGH, T_PRGC, I_OL, I_OH, F_32KU

DC_ILO, and T_POWERUPelectrical specifications. Added maximum values and

updated typical values for T_ERASEBand T_WRITEelectrical specifications.

,

Replaced T_RAMPelectrical specification with SR_POWERUPelectrical specification.

This revision fixes CDT 62018.

*D

2905459

NJF

04/06/10

Updated Cypress website links

Added T_BAKETEMP, T_BAKETIME, and Fout48M electrical specifications

Removed sections ‘Third Party Tools’ ‘Build a PSoC Emulator into your Board’

Updated package diagrams

Updated Ordering Information table

Updated Solder Reflow Peak Temperature specifications.

Updated the Getting Started and Designing with PSoC Designer sections.

Converted data sheet from Preliminary to Final

Fixes from CDT 72358: Deleted 5% oscillator accuracy reference in the Features

section. Deleted reference to a specific SAR10 ADC sample rate in the Analog

System section. Updated the following Electrical Specifications: I_DD, I_SB, I_SBXTL

,

V_REF, V_CMOA, I_ADCREF, INL_ADC, DNL_ADC, V_PPOR2, Flash_DR, F_IMO24, TRiseF,

TFallF, TRiseS, TFallS. Deleted the SPS

electrical specification, the DC Low

ADC

Power Comparator Specifications, the AC Low Power Comparator Specifica-

tions, and the AC Analog Mux Bus Specifications.

*E

*F

2915673

2991841

VIVG

BTK

04/16/10

07/23/10

Post to external web

Added a clarifying note to the V_PPOR1electrical specification.

Added CY8C22345-12PVXE(T) devices.

Moved Document Conventions to the end of the document.

This revision fixes the following CDTs: 72476, 75127, 78329.

*G

*H

3037161

3085024

BTK

09/23/10

11/12/10

Added CY8C21345-12PVXE(T) devices to the Ordering Information section.

Added CY8C21645-12PVXE(T), CY8C21645-24PVXA(T),

CY8C22645-12PVXE(T), and CY8C22645-24PVXA(T) devices to the Ordering

Information section. Refer to CDT 87793.

*I

3200275

BTK

03/18/11

Added tape and reel packaging information (CDT 96026).

Document Number: 001-55397 Rev. *I

Page 35 of 36

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CY8C21345, CY8C21645

CY8C22345, CY8C22345H, CY8C22645

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

Automotive

cypress.com/go/automotive

cypress.com/go/clocks

cypress.com/go/interface

cypress.com/go/powerpsoc

cypress.com/go/plc

PSoC Solutions

Clocks & Buffers

Interface

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 5

Lighting & Power Control

Memory

cypress.com/go/memory

cypress.com/go/image

cypress.com/go/psoc

Optical & Image Sensing

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/go/touch

cypress.com/go/USB

cypress.com/go/wireless

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-55397 Rev. *I

Revised March 18, 2011

Page 36 of 36

PSoC Designer™ is a trademark and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective

corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C

system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their

respective holders.

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型号：	CY8C21645
厂家：	CYPRESS
描述：	Automotive PSoC? Programmable System-on-Chip? 汽车的PSoC ？可编程系统级芯片？
文件：	总36页 (文件大小：914K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C21645 [CYPRESS]

相关型号：

CY8C21645-12PVXE

CY8C21645-24PVXA

CY8C21X23

CY8C21X34

CY8C21X34B

CY8C21X45

CY8C22045

CY8C22113

CY8C22113-24PI

CY8C22113-24PXI

CY8C22113-24SI

CY8C22113-24SIT