CY8C22045_技术文档

CY8C21345

CY8C22345

CY8C22545

PSoC^®Programmable System-on-Chip

■ Programmable pin configurations:

❐ 25 mA sink, 10 mA source on all GPIOs

Features

■ Powerful Harvard-architecture processor:

❐ M8C processor speeds up to 24 MHz

❐ 8 × 8 multiply, 32-bit accumulate

❐ Pull-up, pull-down, high Z, Strong, or open-drain drive modes

on all GPIOs

❐ Up to 38 analog inputs on GPIOs

❐ Configurable interrupt on all GPIOs

❐ Low power at high speed

❐ 3.0 V to 5.25 V operating voltage

❐ Industrial temperature range: –40 °C to +85 °C

■ Advanced peripherals (PSoC^®Blocks)

❐ Six analog type “E” PSoC blocks provide:

• Single or dual 8-Bit ADC

• Comparators (up to four)

❐ Up to eight digital PSoC blocks provide:

• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width

modulators (PWMs)

■ Additional system resources:

❐ I²C slave, master, and multimaster to 400 kHz

❐ Supports hardware addressing feature

❐ Watchdog and sleep timers

❐ User configurable low voltage detection

❐ Integrated supervisory circuit

❐ On-Chip precision voltage reference

❐ Supports RTC block into digital peripheral logic

• One shot, multi-shot mode support in timers and PWMs

• PWM with deadband support in one digital block

• Shift register, CRC, and PRS modules

• Full duplex UART

• Multiple SPI masters or slaves, variable data length

Support: 8- to 16-Bit

Top Level Block Diagram

Analog

Drivers

Port 4

Port 3

Port 2 Port 1 Port 0

PSoC Core

• Can be connected to all GPIO pins

❐ Complex peripherals by combining blocks

❐ Shift function support for FSK detection

❐ Powerful synchronize feature support. Analog module

operations can be synchronized by digital blocks or external

signals.

Global Digital Interconnect

Global Analog Interconnect

Flash 16K

SRAM

1K

SROM

Sleep and

Watchdog

CPU Core (M8C)

Interrupt

■ High speed 10-bit SAR ADC with sample and hold optimized for

Controller

embedded control

Multiple Clock Sources

(Includes IMO, ILO, PLL, and ECO)

■ Precision, programmable clocking:

❐ Internal ± 5% 24/48 MHz oscillator across the industrial

temperature range

❐ High accuracy 24 MHz with optional 32 kHz crystal and PLL

❐ Optional external oscillator, up to 24 MHz

ANALOG SYSTEM

DIGITAL SYSTEM

Digital Block Array

Analog Input

Muxing(L,R)

Analog

Ref

❐ Internal/external oscillator for watchdog and sleep

=

DBC DBC DCC DCC

ROW 1

■ Flexible on-chip memory:

❐ Up to 16 KB flash program storage 50,000 erase/write cycles

❐ Up to 1-KB SRAM data storage

❐ In-system serial programming (ISSP)

❐ Partial flash updates

❐ Flexible protection modes

❐ EEPROM emulation in flash

Analog Block Array

CTE CTE CTE CTE

SCE SCE

DBC DBC DCC DCC

ROW 2

CapSense

Digital Resource

10-bit SAR

ADC

■ Optimized CapSense^®resource:

❐ Two IDAC support up to 640 µA source current to replace

external resistor

❐ Two dedicated clock resources for CapSense:

• CSD_CLK: 1/2/4/8/16/32/128/256 derive from SYSCLK

• CNT_CLK: 1/2/4/8 Derive from CSD_CLK

❐ Dedicated 16-bit timers/counters for CapSense scanning

❐ Support dual CSD channels simultaneous scanning

POR and LVD

System Resets

Internal

Voltage

Ref.

I²C

Digital

Clocks

MACs

SYSTEM RESOURCES

Cypress Semiconductor Corporation

Document Number: 001-43084 Rev. *Q

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 9, 2013

CY8C21345

CY8C22345

CY8C22545

Contents

PSoC Functional Overview ..............................................3

PSoC Core ..................................................................3

Digital System .............................................................3

Analog System ............................................................4

Additional System Resources .....................................4

PSoC Device Characteristics ......................................5

Getting Started ..................................................................5

Application Notes ........................................................5

Development Kits ........................................................5

Training .......................................................................5

CYPros Consultants ....................................................5

Solutions Library ..........................................................5

Technical Support .......................................................5

Development Tools ..........................................................6

PSoC Designer Software Subsystems ........................6

Designing with PSoC Designer .......................................7

Select User Modules ...................................................7

Configure User Modules ..............................................7

Organize and Connect ................................................7

Generate, Verify, and Debug .......................................7

Pinouts ..............................................................................8

CY8C22345, CY8C21345 28-pin SOIC ......................8

CY8C22545 44-pin TQFP ...........................................9

Registers .........................................................................10

Register Conventions ................................................10

Register Mapping Tables ..........................................10

Electrical Specifications ................................................13

Absolute Maximum Ratings .......................................14

Operating Temperature .............................................14

DC Electrical Characteristics .....................................15

AC Electrical Characteristics .....................................21

Packaging Information ...................................................27

Thermal Impedances .................................................28

Solder Reflow Specifications .....................................28

Ordering Information ......................................................28

Ordering Code Definitions .........................................28

Acronyms ........................................................................29

Reference Documents ....................................................29

Document Conventions .................................................30

Units of Measure .......................................................30

Numeric Conventions ....................................................30

Glossary ..........................................................................30

Appendix: Silicon Errata for the PSoC® CY8C21x45,

CY8C22x45 Product Family ...........................................35

Part Numbers Affected ..............................................35

CY8C21x45, CY8C22x45 Qualification Status ..........35

Errata Summary ........................................................35

Document History Page .................................................37

Sales, Solutions, and Legal Information ......................39

Worldwide Sales and Design Support .......................39

Products ....................................................................39

PSoC Solutions .........................................................39

Document Number: 001-43084 Rev. *Q

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Digital System

PSoC Functional Overview

The Digital System is composed of eight digital PSoC blocks.

Each block is an 8-bit resource that may be used alone or

combined with other blocks to form 8, 16, 24, and 32-bit

peripherals, which are called user module references.

The PSoC family consists of many On-Chip Controller devices.

These devices are designed to replace multiple traditional

MCU-based system components with one low cost single-chip

programmable device. PSoC devices include configurable

blocks of analog and digital logic, and programmable

interconnects. This architecture enables the user to create

customized peripheral configurations that match the

requirements of each individual application. Additionally, a fast

CPU, Flash program memory, SRAM data memory, and

configurable I/O are included in a range of convenient pinouts

and packages.

Figure 1. Digital System Block Diagram

Port 3

Port 1

Port 4

Port 2

Port 0

To System Bus

Digital Clocks

From Core

To Analog

System

The PSoC architecture, shown in Figure 1, consists of four main

areas: PSoC Core, Digital System, Analog System, and System

Resources. Configurable global busing allows the combining of

all the device resources into a complete custom system. The

PSoC family can have up to five I/O ports connecting to the

global digital and analog interconnects, providing access to eight

digital blocks and six analog blocks.

DIGITAL SYSTEM

Digital PSoC Block Array

Row 0

4

DBC00

DBC01 DCC02 DCC03

4

8

PSoC Core

8

The PSoC Core is a powerful engine that supports a rich feature

set. The core includes a CPU, memory, clocks, and configurable

general-purpose I/O (GPIO).

Row 1

DBC01 DCC02 DCC03

DBC00

The M8C CPU core is a powerful processor with speeds up to

24 MHz, providing a four MIPS 8-bit Harvard architecture

microprocessor. The CPU uses an interrupt controller with 21

vectors, to simplify the programming of real time embedded

events.

GIE[7:0]

GIO[7:0]

GOE[7:0]

GOO[7:0]

Global Digital

Interconnect

Program execution is timed and protected using the included

Sleep and watchdog timers (WDT).

Memory encompasses 16 KB of Flash for program storage, 1 K

bytes of SRAM for data storage, and up to 2 KB of EEPROM

emulated using the Flash. Program Flash uses four protection

levels on blocks of 64 bytes, allowing customized software IP

protection.

Digital peripheral configurations are:

■ PWMs (8- and 16-Bit)

■ PWMs with Dead band (8- and 16-Bit)

■ Counters (8 to 32-Bit)

The PSoC device incorporates flexible internal clock generators,

including a 24 MHz IMO (internal main oscillator). The 24 MHz

IMO can also be doubled to 48 MHz for use by the digital system.

A low power 32 kHz internal low-speed oscillator (ILO) is

provided for the Sleep timer and WDT. If crystal accuracy is

required, the ECO (32.768 kHz external crystal oscillator) is

available for use as a Real Time Clock (RTC), and can optionally

generate a crystal-accurate 24 MHz system clock using a PLL.

The clocks, together with programmable clock dividers (as a

System Resource), provide the flexibility to integrate almost any

timing requirement into the PSoC device.

■ Timers (8 to 32-Bit)

■ UART 8 Bit with Selectable Parity (Up to Two)

■ SPI Master and Slave (Up to Two)

■ Shift Register (1 to 32-Bit)

■ I2C Slave and Master (One Available as a System Resource)

■ Cyclical Redundancy Checker/Generator (8 to 32-Bit)

■ IrDA (Up to Two)

PSoC GPIOs provide connection to the CPU, digital, and analog

resources of the device. Each pin’s drive mode may be selected

from eight options, allowing great flexibility in external

interfacing. Every pin can also generate a system interrupt on

high level, low level, and change from last read.

■ Pseudo Random Sequence Generators (8 to 32-Bit)

The digital blocks may be connected to any GPIO through a

series of global buses that can route any signal to any pin. The

buses also allow for signal multiplexing and performing logic

operations. This configurability frees your designs from the

constraints of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of

blocks varies by PSoC device family. This provides a choice of

system resources for your application. Family resources are

shown in Table 1 on page 5.

Document Number: 001-43084 Rev. *Q

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Analog System

Additional System Resources

The Analog System consists of a 10-bit SAR ADC and six

configurable blocks.

System Resources, some of which are listed in the previous

sections, provide additional capability useful to complete

systems. Additional resources include a MAC, low voltage

detection, and power on reset. The merits of each system

resource are:

The programmable 10-bit SAR ADC is an optimized ADC that

can be run up to 200 ksps with ± 1.5 LSB DNL and ± 2.5 LSB INL

(true for V_DD 3.0 V and Vref  3.0 V). External filters are

required on ADC input channels for antialiasing. This ensures

that any out-of-band content is not folded into the input signal

band.

■ Digital clock dividers provide three customizable clock

frequencies for use in applications. The clocks may be routed

to both the digital and analog systems. Additional clocks can

be generated using digital PSoC blocks as clock dividers.

Reconfigurable analog resources allow creating complex analog

signal flows. Analog peripherals are very flexible and may be

customized to support specific application requirements. Some

of the more common PSoC analog functions (most available as

user modules) are:

■ Additional Digital resources and clocks optimized for CSD.

■ Support “RTC” block into digital peripheral logic.

■ A multiply accumulate (MAC) provides a fast 8-bit multiplier

with 32-bit accumulate, to assist in both general math and

digital filters.

■ Analog-to-Digital converters (Single or Dual, with 8-bit

resolution)

■ Pin-to-pin Comparator

■ TheI2Cmoduleprovides100and400kHzcommunicationover

two wires. Slave, master, and multi-master modes are all

supported.

■ Single ended comparators with absolute (1.3 V) reference or

5-bit DAC reference

■ Low Voltage Detection (LVD) interrupts can signal the

application of falling voltage levels, while the advanced POR

(Power On Reset) circuit eliminates the need for a system

supervisor.

■ 1.3 V reference (as a System Resource)

Analog blocks are provided in columns of four, which include

CT-E (Continuous Time) and SC-E (Switched Capacitor) blocks.

These devices provide limited functionality Type “E” analog

blocks.

■ An internal 1.3 V reference provides an absolute reference for

the analog system, including ADCs and DACs.

Figure 2. Analog System Block Diagram

Array Input Configuration

ACI0[1:0]

ACI1[1:0]

ACE00

ASE10

ACE01

ASE11

ACE10

ACE11

Block Array

AmuxL

AmuxR

P0[0:7]

ACI2[3:0]

10 bit SAR ADC

Analog Reference

Interface to

Reference

Digital System

Generators

AGND

Bandgap

M8C Interface (Address Bus, Data Bus, Etc.)

Document Number: 001-43084 Rev. *Q

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PSoC Device Characteristics

Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3

analog blocks. The following table lists the resources available for specific PSoC device groups.

Table 1. PSoC Device Characteristics

PSoC Part

Number

Digital

I/O

Digital

Rows

Digital

Blocks

Analog

Inputs

Analog

SRAM

Size

Flash

Size

Outputs Columns Blocks

[1]

CY8C29x66

CY8C28xxx

up to 64

up to 44

4

16

up to 12

up to 44

4

12

2 K

1 K

32 K

16 K

up to 3

up to 12

up to 4

up to 6

up to

12 + 4

[2]

CY8C27x43

up to 44

up to 56

up to 24

up to 26

up to 38

up to 24

up to 28

up to 16

up to 28

up to 36

2

1

2

1

0

8

4

8

4

0

up to 12

up to 48

up to 12

up to 38

up to 24

up to 28

4

2

0

4

2

4

2

0

12

6

256

1 K

16 K

4 K

[1]

CY8C24x94

[1]

CY8C24x23A

6

256

CY8C23x33

4

256

8 K

[1]

[2]

CY8C22x45

CY8C21x45

CY8C21x34

6

1 K

16 K

8 K

[1]

[2]

6

512

[2]

4

512

8 K

[2]

CY8C21x23

up to

8

4

256

4 K

[1]

[2,3]

CY8C20x34

CY8C20xx6

up to 28

up to 36

3

512

8 K

[2,3]

3

up to 2 K

up to 32 K

Getting Started

For in-depth information, along with detailed programming

covers a wide variety of topics and skill levels to assist you in

your designs.

details, see the PSoC^®Technical Reference Manual.

For up-to-date ordering, packaging, and electrical specification

information, see the latest PSoC device datasheets on the web.

CYPros Consultants

Certified PSoC consultants offer everything from technical

assistance to completed PSoC designs. To contact or become a

PSoC consultant go to the CYPros Consultants web site.

Application Notes

Cypress application notes are an excellent introduction to the

wide variety of possible PSoC designs.

Solutions Library

Development Kits

Visit our growing library of solution focused designs. Here you

can find various application designs that include firmware and

hardware design files that enable you to complete your designs

quickly.

PSoC Development Kits are available online from and through a

growing number of regional and global distributors, which

include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and

Newark.

Technical Support

Training

Technical support – including a searchable Knowledge Base

articles and technical forums – is also available online. If you

cannot find an answer to your question, call our Technical

Support hotline at 1-800-541-4736.

Free PSoC technical training (on demand, webinars, and

workshops), which is available online via www.cypress.com,

Notes

1. Automotive qualified devices available in this group.

2. Limited analog functionality.

®

3. Two analog blocks and one CapSense block.

Document Number: 001-43084 Rev. *Q

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CY8C21345

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time. In essence, this allows you to use more than 100 percent

of PSoC's resources for an application.

Development Tools

PSoC Designer™ is the revolutionary integrated design

environment (IDE) that you can use to customize PSoC to meet

your specific application requirements. PSoC Designer software

accelerates system design and time to market. Develop your

applications using a library of precharacterized analog and digital

peripherals (called user modules) in a drag-and-drop design

environment. Then, customize your design by leveraging the

dynamically generated application programming interface (API)

libraries of code. Finally, debug and test your designs with the

integrated debug environment, including in-circuit emulation and

standard software debug features. PSoC Designer includes:

Code Generation Tools

The code generation tools work seamlessly within the

PSoC Designer interface and have been tested with a full range

of debugging tools. You can develop your design in C, assembly,

or a combination of the two.

Assemblers. The assemblers allow you to merge assembly

code seamlessly with C code. Link libraries automatically use

absolute addressing or are compiled in relative mode, and are

linked with other software modules to get absolute addressing.

C Language Compilers. C language compilers are available

that support the PSoC family of devices. The products allow you

to create complete C programs for the PSoC family devices. The

optimizing C compilers provide all of the features of C, tailored

to the PSoC architecture. They come complete with embedded

libraries providing port and bus operations, standard keypad and

display support, and extended math functionality.

■ Application editor graphical user interface (GUI) for device and

user module configuration and dynamic reconfiguration

■ Extensive user module catalog

■ Integrated source-code editor (C and assembly)

■ Free C compiler with no size restrictions or time limits

■ Built-in debugger

Debugger

PSoC Designer has a debug environment that provides

hardware in-circuit emulation, allowing you to test the program in

a physical system while providing an internal view of the PSoC

device. Debugger commands allow you to read and program and

read and write data memory, and read and write I/O registers.

You can read and write CPU registers, set and clear breakpoints,

and provide program run, halt, and step control. The debugger

also allows you to create a trace buffer of registers and memory

locations of interest.

■ In-circuit emulation

■ Built-in support for communication interfaces:

❐ Hardware and software I²C slaves and masters

❐ Full-speed USB 2.0

❐ Up

to

four

full-duplex

universal

asynchronous

receiver/transmitters (UARTs), SPI master and slave, and

wireless

PSoC Designer supports the entire library of PSoC 1 devices and

runs on Windows XP, Windows Vista, and Windows 7.

Online Help System

The online help system displays online, context-sensitive help.

Designed for procedural and quick reference, each functional

subsystem has its own context-sensitive help. This system also

provides tutorials and links to FAQs and an online support Forum

to aid the designer.

PSoC Designer Software Subsystems

Design Entry

In the chip-level view, choose a base device to work with. Then

select different onboard analog and digital components that use

the PSoC blocks, which are called user modules. Examples of

user modules are ADCs, DACs, amplifiers, and filters. Configure

the user modules for your chosen application and connect them

to each other and to the proper pins. Then generate your project.

This prepopulates your project with APIs and libraries that you

can use to program your application.

In-Circuit Emulator

A

low-cost, high-functionality in-circuit emulator (ICE) is

available for development support. This hardware can program

single devices.

The emulator consists of a base unit that connects to the PC

using a USB port. The base unit is universal and operates with

all PSoC devices. Emulation pods for each device family are

available separately. The emulation pod takes the place of the

PSoC device in the target board and performs full-speed

(24 MHz) operation.

The tool also supports easy development of multiple

configurations and dynamic reconfiguration. Dynamic

reconfiguration makes it possible to change configurations at run

Document Number: 001-43084 Rev. *Q

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specifications. Each datasheet describes the use of each user

module parameter, and other information you may need to

successfully implement your design.

Designing with PSoC Designer

The development process for the PSoC device differs from that

of a traditional fixed function microprocessor. The configurable

analog and digital hardware blocks give the PSoC architecture a

unique flexibility that pays dividends in managing specification

change during development and by lowering inventory costs.

These configurable resources, called PSoC Blocks, have the

ability to implement a wide variety of user-selectable functions.

The PSoC development process is summarized in four steps:

Organize and Connect

You build signal chains at the chip level by interconnecting user

modules to each other and the I/O pins. You perform the

selection, configuration, and routing so that you have complete

control over all on-chip resources.

Generate, Verify, and Debug

1. Select User Modules.

When you are ready to test the hardware configuration or move

on to developing code for the project, you perform the “Generate

Configuration Files” step. This causes PSoC Designer to

generate source code that automatically configures the device to

your specification and provides the software for the system. The

generated code provides application programming interfaces

(APIs) with high-level functions to control and respond to

hardware events at run-time and interrupt service routines that

you can adapt as needed.

2. Configure User Modules.

3. Organize and Connect.

4. Generate, Verify, and Debug.

Select User Modules

PSoC Designer provides a library of prebuilt, pretested hardware

peripheral components called “user modules.” User modules

make selecting and implementing peripheral devices, both

analog and digital, simple.

A complete code development environment allows you to

develop and customize your applications in either C, assembly

language, or both.

Configure User Modules

Each user module that you select establishes the basic register

settings that implement the selected function. They also provide

parameters and properties that allow you to tailor their precise

configuration to your particular application. For example, a PWM

User Module configures one or more digital PSoC blocks, one

for each 8 bits of resolution. The user module parameters permit

you to establish the pulse width and duty cycle. Configure the

parameters and properties to correspond to your chosen

application. Enter values directly or by selecting values from

drop-down menus. All the user modules are documented in

datasheets that may be viewed directly in PSoC Designer or on

the Cypress website. These user module datasheets explain the

internal operation of the user module and provide performance

The last step in the development process takes place inside

PSoC Designer’s debugger (access by clicking the Connect

icon). PSoC Designer downloads the HEX image to the ICE

where it runs at full speed. PSoC Designer debugging

capabilities rival those of systems costing many times more. In

addition to traditional single-step, run-to-breakpoint, and

watch-variable features, the debug interface provides a large

trace buffer and allows you to define complex breakpoint events.

These include monitoring address and data bus values, memory

locations, and external signals.

Document Number: 001-43084 Rev. *Q

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Pinouts

This PSoC device family is available in a variety of packages that are listed in the following tables. Every port pin (labeled with a “P”)

is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O.

CY8C22345, CY8C21345 28-pin SOIC

Table 2. Pin Definitions

Type

Figure 3. Pin Diagram

Pin No.

Pin Name

Description

Digital Analog

1

2

I/O

I, MR

I, ML

ML

P0[7]

P0[5]

P0[3]

P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

Vss

Integration Capacitor for MR

Integration Capacitor for ML

AI, MR, P0[7]

AI, ML, P0[5]

AI, ML, P0[3]

AI, ML, P0[1]

AI, ML, P2[7]

ADC_Ext_Vref, ML, P2[5]

ML, P2[3]

Vdd

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

P0[6], MR, AI

P0[4], MR, AI

P0[2], MR, AI

P0[0], MR, AI

P2[6], MR, AI

P2[4], MR

3

4

5

To Compare Column 0

SOIC

6

Optional ADC External Vref

ML, P2[1]

P2[2], MR

Vss

P2[0], MR

7

ML

I2C SCL, ML, P1[7]

I2C SDA, ML, P1[5]

ML, P1[3]

XRES

8

ML

P1[6], MR

P1[4], MR, EXTCLK

P1[2], MR

9

Power

Ground Connection

I2C serial clock (SCL)

I2C serial data (SDA)

I2C SCL, ML, P1[1]

Vss

P1[0], MR, I2C SDATA

10

11

12

13

I/O

ML

P1[7]

P1[5]

P1[3]

P1[1]

I2C serial clock (SCL),

ISSP-SCLK^[4]

14

15

Power

Vss

Ground Connection

I/O

MR

P1[0]

I2C serial Clock (SCL),

ISSP-SDATA^[4]

16

17

I/O

MR

P1[2]

P1[4]

Optional external clock input

(EXT-CLK)

18

19

I/O

MR

P1[6]

Input

XRES

Active High Pin Reset with

Internal Pull Down

20

21

22

23

24

25

26

27

28

I/O

MR

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

I, MR

To Compare Column 1

Power

Supply Voltage

LEGEND: A = Analog, I = Input, O = Output, M=Analog Mux input, MR= Analog Mux right input, ML= Analog Mux left input.

Note

4. ISSP pin which is not HI-Z at POR.

Document Number: 001-43084 Rev. *Q

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Table 3. Pin Definitions

Type

Figure 4. Pin Diagram

Pin No.

Pin Name

Description

Digital

I/O

Analog

1

2

ML

P2[5]

P2[3]

P2[1]

Vdd

Optional ADC External Vref

I/O

3

I/O

4

Power

Supply Voltage

5

I/O

ML

P4[5]

P4[3]

P4[1]

Vss

6

ADC_Ext_Vref, ML, P2[5]

1

2

3

4

5

33

P2[4], MR

P2[2], MR

P2[0], MR

7

ML, P2[3]

ML, P2[1]

Vdd

32

31

8

Ground Connection

30 Vss

9

I/O

ML

P3[7]

P3[5]

P3[3]

P3[1]

P1[7]

P1[5]

P1[3]

P1[1]

Vss

ML, P4[5]

P4[4], MR

29

28

27

26

25

ML, P4[3]

P4[2], MR

P4[0], MR

6

7

8

9

TQFP

10

11

12

13

14

15

16

17

18

ML, P4[1]

Vss

ML, P3[7]

XRES

P3[6], MR

ML, P3[5]

ML, P3[3]

10

11

24 P3[4], MR

23

I2C serial clock (SCL)

I2C serial data (SDA)

P3[2], MR

[4]

Crystal (XTALin), I2C SCL, TC SCLK

Ground Connection

Power

I/O

MR

P1[0]

Crystal (XTALout), I2C SDA, TC

]

[4

SDATA

19

P1[2]

20

21

22

23

24

25

26

I/O

MR

P1[4]

P1[6]

P3[0]

P3[2]

P3[4]

P3[6]

XRES

Optional external clock input (EXTCLK)

Input

Active High Pin Reset with Internal Pull

Down

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

I/O

MR

P4[0]

P4[2]

P4[4]

Vss

Power

Ground Connection

I/O

MR

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

MR

I, MR

To Compare Column 1

Power

Supply Voltage

I/O

I, MR

I, ML

P0[7]

P0[5]

P0[3]

P0[1]

P2[7]

Integration Capacitor for MR

Integration Capacitor for ML

To Compare Column 0

LEGEND: A = Analog, I = Input, O = Output, M=Analog Mux input, MR= Analog Mux right input, ML= Analog Mux left input.

Document Number: 001-43084 Rev. *Q

Page 9 of 39

CY8C21345

CY8C22345

CY8C22545

Registers

This section lists the registers of this PSoC device family by mapping tables. For detailed register information, refer the PSoC

Programmable System-on Chip Technical Reference Manual.

Register Conventions

Table 4. Abbreviations

Convention

Register Mapping Tables

The PSoC device has a total register address space of 512

bytes. The register space is also referred to as I/O space and is

broken into two parts. The XIO bit in the Flag register determines

which bank the user is currently in. When the XIO bit is set, the

user is said to be in the “extended” address space or the

“configuration” registers.

Description

RW

R

Read and write register or bit(s)

Read register or bit(s)

W

L

Write register or bit(s)

Note In the following register mapping tables, blank fields are

Reserved and must not be accessed.

Logical register or bit(s)

Clearable register or bit(s)

Access is bit specific

C

#

Document Number: 001-43084 Rev. *Q

Page 10 of 39

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CY8C22545

Table 5. Register Map Bank 0 Table: User Space

Name

PRT0DR

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

Name

ASC10CR0*

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

#

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72*

73*

74

75

76*

77*

78

79

7A

7B

7C

7D

7E

7F

#

80*

RW

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

RW

#

PRT0IE

W

81

PRT0GS

PRT0DM2

PRT1DR

PRT1IE

RW

#

82

83

#

ASD11CR0*

84*

85

W

PRT1GS

PRT1DM2

PRT2DR

PRT2IE

RW

#

86

87

#

88

PWMVREF0

PWMVREF1

IDAC_MODE

PWM_SRC

TS_CR0

W

89

#

PRT2GS

PRT2DM2

PRT3DR

PRT3IE

RW

#

8A

8B

8C

8D

8E

8F

90

RW

#

RW

#

W

TS_CMPH

TS_CMPL

TS_CR1

PRT3GS

PRT3DM2

PRT4DR

PRT4IE

RW

#

CSD0_DR0_L

CSD0_DR1_L

CSD0_CNT_L

CSD0_CR0

CSD0_DR0_H

CSD0_DR1_H

CSD0_CNT_H

CSD0_CR1

CSD1_DR0_L

CSD1_DR1_L

CSD1_CNT_L

CSD1_CR0

CSD1_DR0_H

CSD1_DR1_H

CSD1_CNT_H

CSD_CR1

R

CUR PP

W

91

STK_PP

PRT4GS

PRT4DM2

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

R

92

PRV PP

#

93

IDX_PP

R

94

MVR_PP

W

95

MVW_PP

I2C0_CFG

I2C0_SCR

I2C0_DR

I2C0_MSCR

INT_CLR0

INT_CLR1

INT_CLR2

INT_CLR3

INT_MSK3

INT_MSK2

INT_MSK0

INT_MSK1

INT_VC

R

96

RW

R

97

98

RW

#

W

99

R

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

RC

W

#

R

W

R

RW

#

DBC00DR0

DBC00DR1

DBC00DR2

DBC00CR0

DBC01DR0

DBC01DR1

DBC01DR2

DBC01CR0

DCC02DR0

DCC02DR1

DCC02DR2

DCC02CR0

DCC03DR0

DCC03DR1

DCC03DR2

DCC03CR0

DBC10DR0

DBC10DR1

DBC10DR2

DBC10CR0

DBC11DR0

DBC11DR1

DBC11DR2

DBC11CR0

DCC12DR0

DCC12DR1

DCC12DR2

DCC12CR0

DCC13DR0

DCC13DR1

DCC13DR2

DCC13CR0

AMX_IN

W

AMUX_CFG

PWM_CR

RW

#

ARF_CR

RES_WDT

DEC_DH

#

CMP_CR0

RW

W

ASY_CR

#

DEC_DL

RW

#

CMP_CR1

RW

#

DEC _CR0*

DEC_CR1*

MUL0_X

#

ADC0_CR

ADC1_CR

SADC_DH

SADC_DL

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

W

#

W

MUL0_Y

W

RW

#

RW

R

MUL0_DH

MUL0_DL

ACC0_DR1

ACC0_DR0

ACC0_DR3

ACC0_DR2

CPU A

R

#

RW

#

W

RW

#

RDI0RI

W

RDI0SYN

RDI0IS

CPU_T1

#

RW

#

ACB00CR1*

ACB00CR2*

CPU_T2

#

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

RDI0DSM

RDI1RI

CPU_X

#

CPU PCL

CPU_PCH

CPU_SP

#

W

#

RW

#

ACB01CR1*

ACB01CR2*

#

CPU_F

I

#

CPU_TST0

CPU_TST1

CPU_TST2

CPU TST3

DAC1_D

RW

#

W

RDI1SYN

RDI1IS

RW

#

RDI1LT0

RDI1LT1

RDI1RO0

RDI1RO1

RDI1DSM

#

RW

#

W

DAC0_D

RW

#

CPU_SCR1

CPU_SCR0

#

Shaded fields are Reserved and must not be accessed.

# Access is bit specific. * has a different meaning.

Document Number: 001-43084 Rev. *Q

Page 11 of 39

CY8C21345

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CY8C22545

Table 6. Register Map Bank 1 Table: Configuration Space

Name

Addr (1,Hex) Access Name

Addr (1,Hex) Access

PRT0DM0

0

RW

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

RW

ASC10CR0*

80*

81

82

83

84*

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

RW

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

RW

#

PRT0DM1

PRT0IC0

PRT0IC1

PRT1DM0

PRT1DM1

PRT1IC0

PRT1IC1

PRT2DM0

PRT2DM1

PRT2IC0

PRT2IC1

PRT3DM0

PRT3DM1

PRT3IC0

PRT3IC1

PRT4DM0

PRT4DM1

PRT4IC0

PRT4IC1

1

2

3

4

RW

ASD11CR0*

5

6

7

8

RW

9

RW

#

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

RW

R

CMP0CR1

CMP0CR2

RW

#

GDI_O_IN

GDI_E_IN

GDI_O_OU

GDI_E_OU

VDAC50CR0

CMP1CR1

CMP1CR2

VDAC51CR0

CSCMPCR0

CSCMPGOEN

CSLUTCR0

CMPCOLMUX

CMPPWMCR

CMPFLTCR

CMPCLK1

MUX_CR0

MUX_CR1

MUX_CR2

MUX_CR3

DAC_CR1#

OSC_GO_EN

OSC_CR4

OSC_CR3

OSC_CR0

OSC_CR1

OSC_CR2

VLT_CR

RW

CMPCLK0

DBC00FN

DBC00IN

CLK_CR0

GDI_O_IN_CR

GDI_E_IN_CR

CLK_CR1

DBC00OU

DBC00CR1

DBC01FN

DBC01IN

ABF_CR0

GDI_O_OU_CR A2

GDI_E_OU_CR A3

AMD_CR0

CMP_GO_EN

RTC_H

A4

A5

A6

A7

A8

A9

AA

VLT_CMP

ADC0_TR*

ADC1_TR*

V2BG_TR

IMO_TR

CMP_GO_EN1 65

RTC_M

RW

W

DBC01OU

DBC01CR1

DCC02FN

DCC02IN

DCC02OU

DBC02CR1

DCC03FN

DCC03IN

DCC03OU

DBC03CR1

DBC10FN

DBC10IN

AMD_CR1

ALT_CR0

ALT_CR1

CLK_CR2

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76*

77*

78

79

7A

7B

7C

7D

7E

7F

RTC_S

RTC_CR

SADC_CR0

SADC_CR1

SADC_CR2

ILO_TR

W

BDG_TR

ECO_TR

MUX_CR4

MUX_CR5

MUX_CR6

MUX_CR7

CPU A

RW

W

CLK_CR3

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

SADC_CR3TRIM AB

SADC_CR4

I2C0_AD

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

#

RDI0RI

RDI0SYN

RDI0IS

CPU_T1

#

DBC10OU

DBC10CR1

DBC11FN

DBC11IN

ACB00CR1*

ACB00CR2*

CPU_T2

#

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

RDI0DSM

RDI1RI

CPU_X

#

CPU_PCL

CPU_PCH

CPU_SP

CPU_F

#

DBC11OU

DBC11CR1

DCC12FN

DCC12IN

DCC12OU

DBC12CR1

DCC13FN

DCC13IN

DCC13OU

DBC13CR1

ACB01CR1*

ACB01CR2*

#

I

FLS_PR0

FLS TR

RW

W

RDI1SYN

RDI1IS

FLS_PR1

RW

RDI1LT0

RDI1LT1

RDI1RO0

RDI1RO1

RDI1DSM

FAC_CR0

SW

RW

#

DAC_CR0#

CPU_SCR1

CPU_SCR0

#

Shaded fields are Reserved and must not be accessed.

# Access is bit specific. * has a different meaning.

Document Number: 001-43084 Rev. *Q

Page 12 of 39

CY8C21345

CY8C22345

CY8C22545

Electrical Specifications

This section presents the DC and AC electrical specifications of this PSoC device family. For the latest electrical specifications, check

the most recent data sheet by visiting http://www.cypress.com.

Specifications are valid for –40 °C  T  85 °C and T  100 °C, except where noted. Specifications for devices running at greater

A

J

than 12 MHz are valid for –40 °C  T  70 °C and T  82 °C.

A

J

Figure 5. Voltage versus Operating Frequency

5.25

4.75

3.00

93 kHz

12 MHz

24 MHz

CPU Frequency

Document Number: 001-43084 Rev. *Q

Page 13 of 39

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CY8C22545

Absolute Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.

Table 7. Absolute Maximum Ratings

Symbol

T_STG

Description

Storage temperature

Min

Typ

Max

Units

Notes

–55

–

+100

°C

Higher storage

temperatures reduce

data retention time

T_BAKETEMPBake temperature

–

125

–

See Package

label

°C

T_BAKETIME

Bake time

See package

label

72

Hours

T_A

Ambient temperature with power applied

Supply voltage on Vdd relative to Vss

DC input voltage

–40

–0.5

–

+85

+6.0

°C

V

Vdd

V_IO

V_IOz

I_MIO

ESD

LU

Vss - 0.5

–25

Vdd + 0.5

+50

V

DC voltage applied to tristate

Maximum current into any port pin

Electr static discharge voltage

Latch up current

V

mA

V

2000

–

Human Body Model ESD

–

200

mA

Operating Temperature

Table 8. Operating Temperature

Symbol

T_A

T_J

Description

Min

–40

Typ

–

Max

+85

Units

Notes

Ambient temperature

Junction temperature

°C

–

+100

°C The temperature rise

from ambient to junction

is package specific. See

Table 29 on page 28. The

user must limit the power

consumption to comply

with this requirement.

Document Number: 001-43084 Rev. *Q

Page 14 of 39

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CY8C22545

DC Electrical Characteristics

DC Chip Level Specifications

Table 9 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T_A 85 °C, or 3.0 V to 3.6 V and –40 °C  T_A 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C, and

are for design guidance only, unless specified otherwise.

Table 9. DC Chip Level Specifications

Symbol

Vdd

Description

Min

3.0

–

Typ

–

Max

5.25

12

Units

Notes

Supply voltage

Supply current

V

See Table 16 on page 19

I_DD

7

mA Conditions are Vdd = 5.0 V,

25°C, CPU = 3 MHz, 48 MHz disabled.

VC1 = 1.5 MHz

VC2 = 93.75 kHz

VC3 = 93.75 kHz

I_DD3

Supply current

–

4

7

mA Conditions are Vdd = 3.3 V

T_A= 25 °C, CPU = 3 MHz

48 MHz = Disabled

VC1 = 1.5 MHz, VC2 = 93.75 kHz

VC3 = 93.75 kHz

I_SB

Sleep (Mode) Current with POR, LVD,

Sleep Timer, and WDT^[5]

–

3

4

6.5

25

A Conditions are with internal slow speed

oscillator, Vdd = 3.3 V

–40°C <= T_A<= 55°C

I_SBH

Sleep (Mode) Current with POR, LVD,

Sleep Timer, and WDT at high

temperature^[5]

–

A Conditions are with internal slow speed

oscillator, Vdd = 3.3 V

55 °C < T_A<= 85 °C

I_SBXTL

I_SBXTLH

V_REF

Sleep (Mode) Current with POR, LVD,

Sleep Timer, WDT, and external crystal^[5]

4

7.5

A Conditions are with properly loaded,

1 W max, 32.768 kHz crystal.

Vdd = 3.3 V, –40 °C <= T_A<= 55 °C

Sleep (Mode) Current with POR, LVD,

Sleep Timer, WDT, and external crystal at

high temperature ^[5]

–

5

26

A Conditions are with properly loaded,

1W max, 32.768 kHz crystal.

Vdd = 3.3 V, 55 °C < T_A<= 85 °C

Reference Voltage (Bandgap)

1.275

1.3

1.325

V

Trimmed for appropriate Vdd

Note

5. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar

functions enabled.

Document Number: 001-43084 Rev. *Q

Page 15 of 39

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CY8C22545

DC GPIO Specifications

Table 10 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T_A 85 °C, or 3.0 V to 3.6 V and –40 °C  T_A 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and

are for design guidance only, unless otherwise specified.

Table 10. DC GPIO Specifications

Symbol

R_PU

Description

Pull-up resistor

Min

Typ

5.6

–

Max

Units

k

Notes

4

8

–

R_PD

V_OH

Pull-down resistor

High output level

k

Vdd – 1.0

V

I_OH= 10 mA, Vdd = 4.75 to 5.25 V

(8 total loads, 4 on even port pins (for

example, P0[2], P1[4]), 4 on odd port

pins (for example, P0[3], P1[5])).

80 mA maximum combined I_OHbudget

V_OL

Low output level

–

0.75

V

I_OL= 25 mA, Vdd = 4.75 to 5.25 V

(8 total loads, 4 on even port pins (for

example, P0[2], P1[4]), 4 on odd port

pins (for example, P0[3], P1[5])).

150 mA maximum combined I_OLbudget.

I_OH

I_OL

High level source current

Low level sink current

10

25

–

mA V_OH= Vdd – 1.0 V, see the limitations of

the total current in the note for V_OH.

mA V_OL= 0.75 V, see the limitations of the

total current in the note for V_OL.

V_IL

V_IH

V_H

I_IL

Input Low level

–

2.1

–

0.8

V

Vdd = 3.0 to 5.25

Input High level

Input hysterisis

60

1

–

mV

Input leakage (absolute value)

Capacitive load on pins as input

–

nA Gross tested to 1 A

C_IN

–

3.5

10

pF Package and pin dependent.

Temp = 25 °C

C_OUT

Capacitive load on pins as output

–

3.5

10

pF Package and pin dependent.

Temp = 25 °C

Document Number: 001-43084 Rev. *Q

Page 16 of 39

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CY8C22545

DC Operational Amplifier Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to

5.25 V and –40 °C  T_A 85 °C, 3.0 V to 3.6 V and –40 °C  T_A 85 °C respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C

and are for design guidance only.

Table 11. 5 V DC Operational Amplifier Specifications

Symbol

Description

Min

–

Typ

2.5

10

Max

15

–

Units

mV

Notes

V_OSOA

Input offset voltage (absolute value)

TCV_OSOAAverage input offset voltage drift

–

V/°C

[6]

I_EBOA

Input leakage current (Port 0 Analog Pins)

Input capacitance (Port 0 Analog Pins)

–

200

4.5

–

pA Gross tested to 1 A

C_INOA

–

9.5

pF Package and pin dependent.

Temp = 25 °C

V_CMOA

Common mode Voltage Range

0.0

–

Vdd - 1

V

Table 12. 3.3 V DC Operational Amplifier Specifications

Symbol

Description

Min

–

Typ

2.5

10

Max

15

–

Units

Notes

V_OSOA

Input offset voltage (absolute value)

mV

TCV_OSOAAverage input offset voltage drift

–

V/°C

[6]

I_EBOA

Input leakage current (Port 0 Analog Pins)

Input capacitance (Port 0 Analog Pins)

–

200

4.5

–

pA Gross tested to 1 A

C_INOA

–

9.5

pF Package and pin dependent.

Temp = 25 °C

V_CMOA

Common mode voltage range

0

–

Vdd – 1

V

Note

6. Atypical behavior: I

of Port 0 Pin 0 is below 1 nA at 25 °C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA.

EBOA

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DC Low Power Comparator Specifications

Table 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T_A 85 °C, 3.0 V to 3.6 V and –40 °C  T_A 85 °C respectively. Typical parameters apply to 5 V at 25 °C and are for design

guidance only.

Table 13. DC Low Power Comparator Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

V_REFLPC

Low power comparator (LPC) reference

voltage range

0.2

–

Vdd – 1

V

V_OSLPC

LPC voltage offset

–

2.5

30

mV

SAR10 ADC DC Specifications

Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T_A 85 °C, or 3.0 V to 3.6 V and –40 °C  T_A 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and

are for design guidance only.

Table 14. SAR10 ADC DC Specifications

Symbol

V_adcvref

Description

Min

Typ

Max Units

5.25

Notes

Reference voltage at pin P2[5] when configured

as ADC reference voltage

3.0

–

V

When V_REFis buffered inside

ADC, the voltage level at P2[5]

(when configured as ADC

reference voltage) must be

always maintained to be at least

300mVlessthanthechipsupply

voltage level on Vdd pin.

(V_adcvref< Vdd)

I_adcvref

Current when P2[5] is configured as ADC V_REF

–

0.5

mA Disables the internal voltage

reference buffer

INL at 10 bits Integral Nonlinearity

DNL at 10 bits Differential Nonlinearity

–2.5

–5.0

–1.5

–4.0

–

2.5

5.0

1.5

4.0

150

LSB For V_DD 3.0 V and Vref  3.0 V

LSB For V_DD< 3.0 V or Vref < 3.0 V

LSB For V_DD 3.0 V and Vref  3.0 V

LSB For V_DD< 3.0 V or Vref < 3.0 V

ksps Resolution 10 bits

SPS

Sample per second

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DC Analog Mux Bus Specifications

Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T_A 85 °C or 3.0 V to 3.6 V and –40 °C  T_A 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and

are for design guidance only.

Table 15. DC Analog Mux Bus Specifications

Symbol

R_SW

R_gnd

Description

Min

–

Typ

–

Max Units

Notes

Switch Resistance to Common Analog Bus

Resistance of Initialization Switch to gnd

400

800



Vdd 3.00

–

DC POR and LVD Specifications

Table 16 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T_A 85 °C or 3.0 V to 3.6 V and –40 °C  T_A 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and

are for design guidance only.

Table 16. DC POR and LVD Specifications

Symbol

Description

Vdd Value for PPOR Trip

PORLEV[1:0] = 01b

PORLEV[1:0] = 10b

Min

Typ

Max Units

Notes

Vdd must be greater than or

equal to 3.0 V during startup,

reset from the XRES pin, or

reset from Watchdog.

V_PPOR1

V_PPOR2

–

2.82

4.55

2.95

4.70

V

Vdd Value for LVD Trip

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

V_LVD2

V_LVD3

V_LVD4

V_LVD5

V_LVD6

V_LVD7

2.95

3.06

4.37

4.50

4.62

4.71

3.02

3.13

4.48

4.64

4.73

4.81

3.09

3.20

4.55

4.75

4.83

4.95

V

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DC Programming Specifications

Table 17 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T_A 85 °C or 3.0 V to 3.6 V and –40 °C  T_A 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and

are for design guidance only.

Table 17. DC Programming Specifications

Symbol

V_DDP

Description

Min

Typ

Max

Units

Notes

4.5

5.0

5.5

V

V_DDfor programming and erase

This specification applies to

the functional requirements of

external programmer tools

3.0

5.1

3.0

3.1

5.2

–

3.2

5.3

V

V_DDLV

Low V_DDfor verify

High V_DDfor verify

This specification applies to

the functional requirements of

external programmer tools

V_DDHV

This specification applies to

the functional requirements of

external programmer tools

5.25

V_DDIWRITESupply voltage for flash write operation

This specification applies to

this device when it is executing

internal flash writes

I_DDP

V_ILP

Supply Current during Programming or Verify

–

5

–

25

mA

V

Input Low Voltage during Programming or

Verify

0.8

V_IHP

I_ILP

Input High Voltage during Programming or

Verify

2.2

–

0.2

V

Input Current when Applying V_ILPto P1[0] or

P1[1] during Programming or Verify

–

mA Driving internal pull down

resistor

I_IHP

Input Current when Applying V_IHPto P1[0] or

P1[1] during Programming or Verify

–

1.5

mA Driving internal pull down

resistor

V_OLV

V_OHV

Output Low Voltage during Programming or

Verify

Vss + 0.75

Vdd

V

Output High Voltage during Programming or

Verify

Vdd - 1.0

V

Flash_ENPBFlash Endurance (per block)^[8]

Flash_ENTFlash Endurance (total)^[7]

50,000

1,800,000

10

–

Erase/write cycles per block

Erase/write cycles

Flash_DR

Flash Data Retention

Years

DC I²C Specifications

Table 18 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T_A 85 °C or 3.0 V to 3.6 V and –40 °C  T_A 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and

are for design guidance only.

Table 18. DC I²C Specifications

Parameter

Description

Min

Typ

–

Max

0.3 × V_DD

0.25 × V_DD

–

Units

Notes

[9]

V_ILI2C

Input low level

Input high level

–

V

3.0 V  V_DD3.6 V

4.75 V  V_DD5.25 V

3.0 V V_DD5.25 V

–

[9]

V_IHI2C

0.7 × V_DD

–

Note

7. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2

blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block

ever sees more than 50,000 cycles).

For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.

Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

8. The 50,000 cycle Flash endurance per block is guaranteed only if the Flash operates within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to 5.25 V

2

9. All GPIOs meet the DC GPIO V and V specifications found in the DC GPIO specifications sections.The I C GPIO pins also meet the above specs.

IL

IH

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AC Electrical Characteristics

AC Chip Level Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to

5.25 V and –40 °C  T_A 85 °C or 3.0 V to 3.6 V and –40 °C  T_A 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at

25 °C and are for design guidance only.

Table 19. 5 V and 3.3 V AC Chip-Level Specifications

Symbol

Description

Min Min(%) Typ

Max

Max(%) Units

Notes

[10,11,12]

F

Internal Main Oscillator Frequency for 22.8

24 MHz

–

24

–

MHz Trimmed for 5 V or 3.3 V

operation using factory trim

values. See Figure 5 on page

13. SLIMO mode = 0 < 85

25.2

IMO24

[10,11,12]

F

Internal Main Oscillator Frequency for

6 MHz

5.5

6

MHz Trimmed for 5 V or 3.3 V

operation using factory trim

values. See Figure 5 on page

13.

8

6.5

8

IMO6

SLIMO mode = 0 < 85.

[10,11]

F

CPU Frequency (5 V Nominal)

CPU Frequency (3.3 V Nominal)

0.089

–

24

–

MHz 24 MHz only for

SLIMO mode = 0.

24.6

12.3

CPU1

[11,12]

F

0.089

0

–

12

48

–

MHz SLIMO mode = 0.

CPU2

0

[10,11,13]

Digital PSoC Block Frequency (5 V

MHz Refer to Table 23 on page 23.

49.2

BLK5

Nominal)

[11,13]

F

Digital PSoC Block Frequency (3.3 V

Nominal)

0

15

5

–

24

32

–

MHz

kHz

24.6

BLK33

32K1

Internal Low Speed Oscillator

Frequency

85

Untrimmed Internal Low Speed Oscil-

lator Frequency

100

kHz The ILO is not adjusted with

the factory trim values until

after the CPU starts running.

See the “System Resets”

section in the Technical

32KU

Reference Manual.

T

External Reset Pulse Width

24 MHz Duty Cycle

10

–

µs

XRST

DC24M

40

20

–

50

60

80

–

%

DC

Internal Low Speed Oscillator Duty

Cycle

ILO

F

48 MHz Output Frequency

46.8

–

48.0

49.2

12.3

250

100

–

MHz Trimmed. Utilizing factory trim

values.

OUT48M

MAX

Maximum frequency of signal on row

input or row output

–

MHz

SR

Power supply slew rate

V/ms Vdd slew rate during power

up.

POWERUP

T

Time from end of POR to CPU

executing code

ms

POWERUP

[14]

tjit_IMO

24 MHz IMO cycle-to-cycle jitter (RMS)

–

200

300

700

900

–

ps

24 MHz IMO long term N cycle-to-cycle

jitter (RMS)

ps N = 32

24 MHz IMO period jitter (RMS)

–

100

200

300

400

800

–

ps

[14]

tjit_PLL

24 MHz IMO cycle-to-cycle jitter (RMS)

ps

24 MHz IMO long term N cycle-to-cycle

jitter (RMS)

1200

ps N = 32

24 MHz IMO period jitter (RMS)

–

100

700

–

ps

Notes

10. Valid only for 4.75 V < Vdd < 5.25 V.

11. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.

12. 3.0 V < Vdd < 3.6 V.

13. Refer to the individual user module data sheets for information on maximum frequencies for user modules.

14. Refer to Cypress Jitter Specifications, Understanding Datasheet Jitter Specifications for Cypress Timing Products for more information.

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AC GPIO Specifications

Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T_A 85 °C or 3.0 V to 3.6 V and –40 °C  T_A 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and

are for design guidance only.

Table 20. 5 V and 3.3 V AC GPIO Specifications

Symbol

F_GPIO

Description

GPIO operating frequency

Min

0

Typ

–

Max

12

18

–

Units

Notes

MHz Normal Strong Mode

TRiseF

TFallF

TRiseS

TFallS

Rise time, normal strong mode, Cload = 50 pF

Fall time, normal strong mode, Cload = 50 pF

Rise time, slow strong mode, Cload = 50 pF

Fall time, slow strong mode, Cload = 50 pF

3

–

ns

Vdd = 4.5 to 5.25 V, 10% to 90%

2

–

Vdd = 4.5 to 5.25 V, 10% to 90%

Vdd = 3 to 5.25 V, 10% to 90%

7

27

22

7

–

Figure 6. GPIO Timing Diagram

90%

GPIO

Output

Voltage

10%

TRiseF

TRiseS

TFallF

TFallS

AC Operational Amplifier Specifications

Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T_A 85 °C or 3.0 V to 3.6 V and –40 °C  T_A 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and

are for design guidance only.

Table 21. AC Operational Amplifier Specifications

Symbol

T_COMP

Description

Min

Typ

Max

Units

ns Vdd  3.0 V

Notes

Comparator Mode Response Time, 50 mV

100

AC Low Power Comparator Specifications

Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T_A 85 °C or 3.0 V to 3.6 V and –40 °C  T_A 85 °C, respectively. Typical parameters apply to 5 V at 25 °C and are for

design guidance only.

Table 22. AC Low Power Comparator Specifications

Symbol

T_RLPC

Description

LPC response time

Min

Typ

Max

Units

Notes

–

50

s  50 mV overdrive comparator

reference set within V_REFLPC

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AC Digital Block Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to

5.25 V and –40 °C  T_A 85 °C or 3.0 V to 3.6 V and –40 °C  T_A 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V, at

25 °C and are for design guidance only.

Table 23. AC Digital Block Specifications

Function

Description

Min

Typ

Max

Units

Notes

All functions Block Input Clock Frequency

Vdd  4.75 V

–

50.4^[15]MHz

25.2^[15]MHz

Vdd < 4.75 V

Timer

Input Clock Frequency

No Capture, Vdd  4.75 V

No Capture, Vdd < 4.75 V

With Capture

–

50.4^[15]MHz

25.2^[15]MHz

–

Capture Pulse Width

Input Clock Frequency

No Enable Input, Vdd  4.75 V

No Enable Input, Vdd < 4.75 V

With Enable Input

50^[16]

–

ns

Counter

Dead Band

–

50.4^[15]MHz

25.2^[15]MHz

–

Enable Input Pulse Width

Kill Pulse Width

50^[16]

–

ns

Asynchronous Restart Mode

Synchronous Restart Mode

Disable Mode

20

–

ns

50^[16]

Input Clock Frequency

Vdd  4.75 V

–

50.4^[15]MHz

25.2^[15]MHz

Vdd < 4.75 V

CRCPRS

(PRS Mode)

Input Clock Frequency

Vdd  4.75 V

–

50.4^[15]MHz

25.2^[15]MHz

Vdd < 4.75 V

CRCPRS

Input Clock Frequency

(CRC Mode)

SPIM

Input Clock Frequency

–

8.4^[15]

MHz The SPI serial clock (SCLK)

frequency is equal to the input

clock frequency divided by 2.

SPIS

Input Clock (SCLK) Frequency

–

4.2^[15]

–

MHz The input clock is the SPI SCLK in

SPIS mode.

Width of SS_Negated Between Transmissions 50^[16]

Input Clock Frequency

ns

Transmitter

Receiver

The baud rate is equal to the input

clock frequency divided by 8.

Vdd  4.75 V, 2 Stop Bits

Vdd  4.75 V, 1 Stop Bit

Vdd < 4.75 V

–

50.4^[15]MHz

25.2^[15]MHz

Input Clock Frequency

Vdd  4.75 V, 2 Stop Bits

Vdd  4.75 V, 1 Stop Bit

Vdd < 4.75 V

The baud rate is equal to the input

clock frequency divided by 8.

–

50.4^[15]MHz

25.2^[15]MHz

Notes

15. Accuracy derived from IMO with appropriate trim for V range.

DD

16. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

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AC External Clock Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to

5.25 V and –40 °C  T_A 85 °C, or 3.0 V to 3.6 V and –40 °C  T_A 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at

25 °C and are for design guidance only.

Table 24. 5 V AC External Clock Specifications

Symbol

Description

Min

0.093

20.6

150

Typ

–

Max

24.6

5300

–

Units

MHz

ns

Notes

F_OSCEXT

Frequency

High Period

Low Period

–

ns

Power Up IMO to Switch

–

s

Table 25. 3.3 V AC External Clock Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

F_OSCEXT

Frequency with CPU Clock divide by 1

0.093

–

12.3

MHz Maximum CPU frequency is

12 MHz at 3.3 V. With the CPU

clock divider set to 1, the

external clock must adhere to

the maximum frequency and

duty cycle requirements.

F_OSCEXT

Frequency with CPU Clock divide by 2 or greater 0.186

–

24.6

MHz If the frequency of the external

clock is greater than 12 MHz,

the CPU clock divider must be

set to 2 or greater. In this case,

the CPU clock divider ensures

that the fifty percent duty cycle

requirement is met.

–

High Period with CPU Clock divide by 1

Low Period with CPU Clock divide by 1

Power Up IMO to Switch

41.7

150

–

5300

ns

s

–

SAR10 ADC AC Specifications

Table 26 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T_A 85 °C, or 3.0 V to 3.6 V and –40 °C  T_A 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and

are for design guidance only.

Table 26. SAR10 ADC AC Specifications

Symbol

Freq₃

Freq₅

Description

Input clock frequency 3 V

Input clock frequency 5 V

Min

–

Typ

–

Max

2.7

Units

MHz

Notes

–

2.7

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AC Programming Specifications

Table 27 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T_A 85 °C, or 3.0 V to 3.6 V and –40 °C  T_A 85 °C, respectively. Typical parameters apply to 5 V, or 3.3 V at 25 °C and

are for design guidance only.

Table 27. AC Programming Specifications

Symbol

T_RSCLK

Description

Rise Time of SCLK

Min

1

Typ

–

Max

20

–

Units

Notes

ns

T_FSCLK

T_SSCLK

T_HSCLK

F_SCLK

Fall Time of SCLK

1

–

ns

Data Set up Time to Falling Edge of SCLK

Data Hold Time from Falling Edge of SCLK

Frequency of SCLK

40

0

–

ns

–

ns

–

8

MHz

F_SCLK3

T_ERASEB

T_WRITE

T_DSCLK

T_DSCLK3

T_ERASEALL

Frequency of SCLK3

0

–

6

MHz V_DD< 3.6 V

Flash Erase Time (Block)

–

10

40

–

ms

Flash Block Write Time

–

Data Out Delay from Falling Edge of SCLK

Flash Erase Time (Bulk)

–

55

65

–

ns 3.6 < Vdd; at 30 pF Load

–

ns 3.0 Vdd 3.6; at 30 pF Load

–

40

–

ns

ms

T_{PROGRAM_HOT}Flash Block Erase + Flash Block Write Time

T_{PROGRAM_COLD}Flash Block Erase + Flash Block Write Time

–

100

200

–

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AC I²C Specifications

Table 28 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T_A 85 °C, and 3.0 V to 3.6 V and –40 °C  T_A 85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at

25 °C and are for design guidance only.

Table 28. AC Characteristics of the I²C SDA and SCL Pins for Vdd 3.0 V

Standard Mode

Fast Mode

Symbol

F_SCLI2C

Description

SCL Clock Frequency

Units

Notes

Min

0

Max

100

–

Min

0

Max

400

–

kHz

T_HDSTAI2C

Hold Time (repeated) START Condition.

After this period, the first clock pulse is

generated.

4.0

0.6

s

T_LOWI2C

T_HIGHI2C

T_SUSTAI2C

LOW Period of the SCL Clock

HIGH Period of the SCL Clock

4.7

4.0

4.7

–

1.3

0.6

–

s

Setup Time for a Repeated START

Condition

T_HDDATI2C

T_SUDATI2C

T_SUSTOI2C

T_BUFI2C

Data Hold Time

0

–

0

100^[17]

0.6

–

s

ns

s

Data Setup Time

250

4.0

4.7

Setup Time for STOP Condition

Bus Free Time Between a STOP and

START Condition

1.3

T_SPI2C

Pulse Width of spikes are suppressed by the

Input Filter

–

0

50

ns

Figure 7. Definition for Timing for Fast/Standard Mode on the I²C Bus

I2C_SDA

T_SUDATI2C

T_HDSTAI2C

T_SPI2C

T_SUSTAI2C

T_BUFI2C

T_HDDATI2C

I2C_SCL

T_HIGHI2CT_LOWI2C

T_SUSTOI2C

P

S

Sr

Repeated START Condition

STOP Condition

START Condition

Note

17. A Fast-Mode I2C-bus device may be used in a Standard-Mode I2C-bus system, but the requirement T

 250 ns must then be met. This is automatically the

SUDATI2C

case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit

to the SDA line t + T = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

rmax

SUDATI2C

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CY8C22545

Packaging Information

Figure 8. 28-pin SOIC

51-85026 *F

Figure 9. 44-pin TQFP

51-85064 *E

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CY8C22545

Thermal Impedances

Table 29. Thermal Impedances per Package

[19]

Package

28-pin SOIC

44-pin TQFP

Typical _JA

68 °C/W

61 °C/W

Solder Reflow Specifications

Table 30 shows the solder reflow temperature limits that must not be exceeded.

Table 30. Solder Reflow Specifications

Maximum Peak Temperature

Package

Maximum Time above T_C– 5 °C

(T_C)

28-pin SOIC

44-pin TQFP

260 °C

30 seconds

Ordering Information

The following table lists the key package features and ordering codes of this PSoC device family.

Table 31. PSoC Device Family Key Features and Ordering Information

Package

Ordering Code

28-pin SOIC

CY8C21345-24SXI

CY8C21345-24SXIT

CY8C22345-24SXI

CY8C22345-24SXIT

CY8C22545-24AXI

8

512B

1K

4

8

6

24 24^[18]

38 38^[18]

0

Y

–40 °C to +85 °C

–40 °C to +85 C

28-pin SOIC (Tape and Reel)

28-pin SOIC

8

16

28-pin SOIC (Tape and Reel)

44-pin TQFP

1K

44-pin TQFP (Tape and Reel) CY8C22545-24AXIT

1K

Ordering Code Definitions

CY 8 C 2x xxx-SPxx

Package Type:

Thermal Rating:

PX = PDIP Pb-free

SX = SOIC Pb-free

PVX = SSOP Pb-free

LFX/LTX = QFN Pb-free

AX = TQFP Pb-free

C = Commercial

I = Industrial

E = Extended

CPU Speed: 24 MHz

Part Number

Family Code (21, 22)

Technology Code: C = CMOS

Marketing Code: 8 = PSoC

Company ID: CY = Cypress

Note

18. Ten direct inputs.

19. T = T + POWER x 

JA

J

A

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CY8C21345

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CY8C22545

Acronyms

Table 32 lists the acronyms that are used in this document.

Table 32. Acronyms Used in this Datasheet

Acronym

AC

Description

alternating current

Acronym

MAC

Description

multiply-accumulate

ADC

API

analog-to-digital converter

application programming interface

complementary metal oxide semiconductor

central processing unit

MCU

MIPS

PCB

microcontroller unit

million instructions per second

printed circuit board

CMOS

CPU

CRC

CSD

CT

PGA

PLL

programmable gain amplifier

phase-locked loop

cyclic redundancy check

CapSense sigma delta

POR

PPOR

PRS

PSoC^®

PWM

QFN

RTC

power on reset

continuous time

precision power on reset

pseudo-random sequence

Programmable System-on-Chip

pulse width modulator

quad flat no leads

DAC

DC

digital-to-analog converter

direct current

DNL

differential nonlinearity

ECO

EEPROM

external crystal oscillator

electrically erasable programmable read-only

memory

real time clock

FSK

GPIO

I/O

frequency-shift keying

general-purpose I/O

input/output

SAR

successive approximation

switched capacitor

SC

SLIMO

SOIC

SPI™

SRAM

SROM

SSOP

TQFP

UART

USB

slow IMO

ICE

in-circuit emulator

small-outline integrated circuit

serial peripheral interface

static random access memory

supervisory read only memory

shrink small-outline package

thin quad flat pack

IDE

integrated development environment

current DAC

IDAC

ILO

internal low speed oscillator

internal main oscillator

integral nonlinearity

IMO

INL

IrDA

ISSP

LPC

LSB

LVD

infrared data association

in-system serial programming

low power comparator

least-significant bit

universal asynchronous receiver / transmitter

universal serial bus

WDT

watchdog timer

XRES

external reset

low voltage detect

Reference Documents

CY8C22x45 and CY8C21345 PSoC® Programmable System-on-Chip™ Technical Reference Manual (TRM) (001-48461)

Design Aids – Reading and Writing PSoC^®Flash – AN2015 (001-40459)

Understanding Datasheet Jitter Specifications for Cypress Timing Products

Document Number: 001-43084 Rev. *Q

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Document Conventions

Units of Measure

Table 33 lists the units of measures.

Table 33. Units of Measure

Symbol

kB

Unit of Measure

Symbol

mV

nA

ns

Unit of Measure

1024 bytes

degree Celsius

kilohertz

millivolts

C

nanoampere

nanosecond

ohm

kHz

k

kilohm

W

LSB

MHz

µA

least significant bit

megahertz

microampere

microsecond

microvolt

%

percent

pF

picofarad

picosecond

ps

µs

sps

pA

V

samples per second

pikoampere

volts

µV

mA

mm

ms

milliampere

millimeter

µW

W

microwatts

watt

millisecond

Numeric Conventions

Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).

Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended

lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.

Glossary

active high

1. A logic signal having its asserted state as the logic 1 state.

2. A logic signal having the logic 1 state as the higher voltage of the two states.

analog blocks

The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.

These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.

analog-to-digital A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts

(ADC) a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation.

API (Application A series of software routines that comprise an interface between a computer application and lower level services

Programming

Interface)

and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that

create software applications.

asynchronous

A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.

bandgap

reference

A stable voltage reference design that matches the positive temperature coefficient of VT with the negative

temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.

bandwidth

1. The frequency range of a message or information processing system measured in hertz.

2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is

sometimes represented more specifically as, for example, full width at half maximum.

Document Number: 001-43084 Rev. *Q

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CY8C22545

Glossary (continued)

bias

1. A systematic deviation of a value from a reference value.

2. The amount by which the average of a set of values departs from a reference value.

3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to

operate the device.

block

buffer

1. A functional unit that performs a single function, such as an oscillator.

2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or

an analog PSoC block.

1. A storage area for data that is used to compensate for a speed difference, when transferring data from one

device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which

data is written.

2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received

from an external device.

3. An amplifier used to lower the output impedance of a system.

bus

1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing

patterns.

2. A set of signals performing a common function and carrying similar data. Typically represented using vector

notation; for example, address[7:0].

3. One or more conductors that serve as a common connection for a group of related devices.

clock

The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to

synchronize different logic blocks.

comparator

compiler

An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy

predetermined amplitude requirements.

A program that translates a high level language, such as C, into machine language.

configuration

space

In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’.

crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less

sensitive to ambient temperature than other circuit components.

cyclicredundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift

check (CRC)

register. Similar calculations may be used for a variety of other purposes such as data compression.

data bus

A bi-directional set of signals used by a computer to convey information from a memory location to the central

processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.

debugger

A hardware and software system that allows the user to analyze the operation of the system under development.

A debugger usually allows the developer to step through the firmware one step at a time, set break points, and

analyze memory.

dead band

A period of time when neither of two or more signals are in their active state or in transition.

digital blocks

The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,

pseudo-random number generator, or SPI.

digital-to-analog A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC)

(DAC) converter performs the reverse operation.

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Glossary (continued)

duty cycle

emulator

The relationship of a clock period high time to its low time, expressed as a percent.

Duplicates (provides an emulation of) the functions of one system with a different system, so that the second

system appears to behave like the first system.

external reset

(XRES)

An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop

and return to a pre-defined state.

flash

An electrically programmable and erasable, non-volatile technology that provides users with the programmability

and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power

is off.

Flash block

The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash

space that may be protected. A Flash block holds 64 bytes.

frequency

gain

The number of cycles or events per unit of time, for a periodic function.

The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually

expressed in dB.

I²C

A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated

Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in

the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building

control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high

with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode.

ICE

The in-circuit emulatorthat allowsusers to test the project ina hardware environment, while viewingthe debugging

device activity in a software environment (PSoC Designer).

input/output (I/O) A device that introduces data into or extracts data from a system.

interrupt

A suspension of a process, such as the execution of a computer program, caused by an event external to that

process, and performed in such a way that the process can be resumed.

interrupt service A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many

routine (ISR)

interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends

with the RETI instruction, returning the device to the point in the program where it left normal program execution.

jitter

1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on

serial data streams.

2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between

successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.

low-voltage

detect (LVD)

A circuit that senses Vdd and provides an interrupt to the system when Vdd falls below a selected threshold.

M8C

An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by

interfacing to the Flash, SRAM, and register space.

master device

A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in

width, the master device is the one that controls the timing for data exchanges between the cascaded devices

and an external interface. The controlled device is called the slave device.

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Glossary (continued)

microcontroller

An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a

microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the

realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This

in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for

general-purpose computation as is a microprocessor.

mixed-signal

modulator

noise

The reference to a circuit containing both analog and digital techniques and components.

A device that imposes a signal on a carrier.

1. A disturbance that affects a signal and that may distort the information carried by the signal.

2. The random variations of one or more characteristics of any entity such as voltage, current, or data.

oscillator

parity

A circuit that may be crystal controlled and is used to generate a clock frequency.

A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the

digits of the binary data either always even (even parity) or always odd (odd parity).

phase-locked

loop (PLL)

An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference

signal.

pinouts

The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their

physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between

schematic and PCB design (both being computer generated files) and may also involve pin names.

port

A group of pins, usually eight.

power on reset

(POR)

A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware

reset.

PSoC^®

Cypress Semiconductor’s PSoC^®is a registered trademark and Programmable System-on-Chip™ is a trademark

of Cypress.

PSoCDesigner™ The software for Cypress’ Programmable System-on-Chip technology.

pulse width

An output in the form of duty cycle which varies as a function of the applied measurand

modulator (PWM)

RAM

An acronym for random access memory. A data-storage device from which data can be read out and new data

can be written in.

register

reset

A storage device with a specific capacity, such as a bit or byte.

A means of bringing a system back to a know state. See hardware reset and software reset.

ROM

An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot

be written in.

serial

1. Pertaining to a process in which all events occur one after the other.

2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or

channel.

settling time

The time it takes for an output signal or value to stabilize after the input has changed from one value to another.

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Glossary (continued)

shift register

slave device

A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.

A device that allows another device to control the timing for data exchanges between two devices. Or when

devices are cascaded in width, the slave device is the one that allows another device to control the timing of data

exchanges between the cascaded devices and an external interface. The controlling device is called the master

device.

SRAM

SROM

An acronym for static random access memory. A memory device allowing users to store and retrieve data at a

high rate of speed. The term static is used because, after a value has been loaded into an SRAM cell, it remains

unchanged until it is explicitly altered or until power is removed from the device.

An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate

circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code,

operating from Flash.

stop bit

A signal following a character or block that prepares the receiving device to receive the next character or block.

synchronous

1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.

2. A system whose operation is synchronized by a clock signal.

tri-state

A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any

value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,

allowing another output to drive the same net.

UART

A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.

user modules

Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower

level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming

Interface) for the peripheral function.

user space

The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal

program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during

the initialization phase of the program.

V_DD

A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V.

A name for a power net meaning "voltage source." The most negative power supply signal.

V_SS

watchdog timer

A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.

Document Number: 001-43084 Rev. *Q

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CY8C22545

®

Appendix: Silicon Errata for the PSoC CY8C21x45, CY8C22x45 Product Family

This section describes the errata for the CY8C21x45, CY8C22x45 family of PSoC devices. Details include errata trigger conditions,

scope of impact, available workarounds, and silicon revision applicability.

Contact your local Cypress Sales Representative if you have questions.

Part Numbers Affected

Part Number

CY8C21345

CY8C21645

CY8C22045

CY8C22345

CY8C22545

CY8C22645

Device Characteristics

All Variants

CY8C21x45, CY8C22x45 Qualification Status

Product Status: In Production

Errata Summary

The following table defines the errata applicable for this PSoC family device.

Items

Part Number

Silicon Revision

Fix Status

1. Free Running Nonstop Reading

All CY8C21x45, CY8C22x45

All

Silicon fix not planned. Use

workaround.

cause 7 LSB Pseudo Code Variation devices affected

in SAR10ADC

2. Internal Main Oscillator (IMO)

Tolerance Deviation at Temperature devices affected

Extremes

All CY8C21x45, CY8C22x45

All

Silicon fix not planned. Use

workaround.

1. Free Running Nonstop Reading cause 7 LSB Pseudo Code Variation in SAR10ADC

■ Problem Definition

In free running mode, there can be a variation of up to 7 LSB in the digital output of SAR10 ADC.

■ Parameters Affected

Code Variation. This is not a specified parameter.

It is defined as the number of unique output codes generated by the ADC for a given constant input voltage, in addition to the correct

code. For example, for an input voltage of 2.000 V, the expected code is 190hex and the ADC generates three codes: 191hex, 190hex,

and 192hex. The code variation is 2 LSB.

■ Trigger Condition(S)

SAR10 ADC is configured in the free running mode.

■ Scope of Impact

Inaccurate output is possible.

■ Workaround

This issue can be averted by using one or both of the following workarounds. Consult a Cypress representative for additional

assistance.

❐ Use the averaging technique. That is, take multiple samples of the input, and use a digital averaging filter.

❐ Disable the free running mode before reading data out, and enable the free running mode after completing the read operation.

■ Fix Status

No silicon fix is planned.

Document Number: 001-43084 Rev. *Q

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2. Internal Main Oscillator (IMO) Tolerance Deviation at Temperature Extremes

■ Problem Definition

Asynchronous Digital Communications Interfaces may fail framing beyond 0 to 70 °C. This problem does not affect end-product usage

between 0 and 70 °C.

■ Parameters Affected

The IMO frequency tolerance. The worst case deviation when operated below 0 °C and above +70 °C and within the upper and lower

datasheet temperature range is ±5%.

■ Trigger Condiiton(S)

The asynchronous Rx/Tx clock source IMO frequency tolerance may deviate beyond the datasheet limit of ±2.5% when operated

beyond the temperature range of 0 to +70 °C.

■ Scope of Impact

This problem may affect UART, IrDA, and FSK implementations.

■ Workaround

Implement a quartz crystal stabilized clock source on at least one end of the asynchronous digital communications interface.

■ Fix Status

The cause of this problem and its solution has been identified. No silicon fix is planned to correct the deficiency in silicon.

Document Number: 001-43084 Rev. *Q

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CY8C22545

Document History Page

Document Title: CY8C21345, CY8C22345, CY8C22545, PSoC^®Programmable System-on-Chip

Document Number: 001-43084

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

2251907

PMP /

AESA

See ECN New data sheet.

*A

*B

2506377 EIJ / AESA

See ECN Changed data sheet status to “Preliminary”. Changed part numbers to

CY8C22x45. Updated data sheet template.

Added 56-Pin OCD information. Added: “You must put filters on intended ADC

input channels for anti-aliasing. This ensures that any out-of-band content is

not folded into the Input Signal Band." To Section Analog System on page 4.

Corrected Minimum Electro Static Discharge Voltage in Table 7 on page 14.

2558750

PMP /

AESA

08/28/2008 Updated Features on page 1, PSoC Core on page 3, Analog System on page 4.

Changed DBB to DBC, and DCB to DCC in Register Tables Table 5 on page

11 and Table 6 on page 12.

Removed INL at 8 bit reference in Table 14 on page 18.

Changed IDD3 value Table 16 on page 19 Typ:3.3 mA, Max 6 mA

Added “3.0 V < Vdd < 3.6 V and -40C < T_A< 85C, IMO can guarantee 5%

accuracy only” to Table 19 on page 21.

Updated data sheet template.

*C

2606793

NUQ /

AESA

11/19/2008 Updated data sheet status to “Final”. Updated block diagram on page 1.

Removed CY8C22045 56-Pin OCD information. Added part numbers

CY8C21345, CY8C22345, and CY8C22545. For more details, see CDT

31271.

*D

*E

2615697

2631733

PMP /

AESA

12/03/2008 Confirmed CY8C22345 and CY8C21345 have same pinout on page 8.

Confirmed that IMO has 5% accuracy in Table 19 on page 21.

PMP /

PYRS

01/07/2009 Updated Table 16. SAR10 ADC DC Specifications and Table 29 AC

Programming Specifications. Title changed to “CY8C21345, CY8C22345,

CY8C22545 PSoC® Programmable System-on-Chip™”

*F

*G

*H

*I

2648800

2658078

2667311

2748976

2786560

JHU /

AESA

01/28/2009 Updated INL, DNL information in Table 14 on page 18, Development Tools on

page 6, and T_DSCLKparameter in Table 27 on page 25.

HMI /

AESA

02/11/2009 Updated section Features on page 1.

JHU /

AESA

03/16/2009 Added parameter “F_32KU” and added Min% and Max % to parameter “F_IMO6

in Table 19 on page 21, according to updated SLIMO spec.

”

JZHU /

PYRS

08/06/2009 Updated F_32K1max rating in Table 19 on page 21.

*J

JZHU

10/23/2009 Added DC_ILO, T_ERASEALL, T_{PROGRAM_HOT}, T_{PROGRAM_COLD}, SR_POWERUP,

I_OH, and I_OLparameters.

Added Tape and Reel parts in Ordering Information table

*K

*L

2901653

NJF

03/30/2010 Updated PSoC Designer Software Subsystems.

Added T_BAKETEMPand T_BAKETIMEparameters in Absolute Maximum Ratings

Modified Note 6 on page 17.

Added F_OUT48Mparameter in 5 V and 3.3 V AC Chip-Level Specifications.

Removed AC Analog Mux Bus Specifications.

Updated Ordering Code Definitions.

Updated links in Sales, Solutions, and Legal Information.

3114978

NJF

12/19/10

Added DC I²C Specifications.

Added Tjit_IMO specification, removed existing jitter specifications.

Updated DC Programming Specifications.

Updated AC Digital Block Specifications.

Updated I²C Timing Diagram.

Added Solder Reflow Peak Temperature table.

Updated Units of Measure, Acronyms, Glossary, and References sections.

Document Number: 001-43084 Rev. *Q

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CY8C21345

CY8C22345

CY8C22545

Document History Page (continued)

Document Title: CY8C21345, CY8C22345, CY8C22545, PSoC^®Programmable System-on-Chip

Document Number: 001-43084

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

*M

3231771

BOBH /

ECU

04/18/11

Updated analog inputs column in Table 31 on page 28 and included reference

to Note 18.

Updated the following sections: Getting Started, Development Tools, and

Designing with PSoC Designer as all the System level designs have been

de-emphasized.

Updated Table 30, “Solder Reflow Specifications,” on page 28.

Updated package diagrams:

51-85026 to *F

51-85064 to *E

*N

3578757

PMAD

04/11/2012 Removed reference to AN2012 as the document is in obsolete status.

Updated template.

No technical updates. Completing sunset review.

*O

*P

3598230

3915358

LURE /

XZNG

04/24/2012 Changed the PWM description string from “8- to 32-bit” to “8- and 16-bit”.

SAMP

02/27/2013 Updated Electrical Specifications (Updated DC Electrical Characteristics

(Updated DC GPIO Specifications (Updated Table 10 (Updated Notes for V_OH

and V_OLparameters)))).

*Q

3959550

SAMP

04/09/2013 Added Appendix: Silicon Errata for the PSoC® CY8C21x45, CY8C22x45

Product Family.

Document Number: 001-43084 Rev. *Q

Page 38 of 39

CY8C21345

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CY8C22545

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

Automotive

cypress.com/go/automotive

cypress.com/go/clocks

cypress.com/go/interface

cypress.com/go/powerpsoc

cypress.com/go/plc

PSoC Solutions

Clocks & Buffers

Interface

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 5

Lighting & Power Control

Memory

cypress.com/go/memory

cypress.com/go/psoc

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/go/touch

cypress.com/go/USB

cypress.com/go/wireless

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-43084 Rev. *Q

Revised April 9, 2013

Page 39 of 39

PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation.

2

Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided

2

that the system conforms to the I C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.

All products and company names mentioned in this document may be the trademarks of their respective holders.


型号：	CY8C22045
厂家：	CYPRESS
描述：	PSoCÂ® Programmable System-on-Chip PSoCÂ®可编程系统级芯片
文件：	总39页 (文件大小：531K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C22045 [CYPRESS]

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