CY8C24423A-24LTXIT [CYPRESS]

PSoC Programmable System-on-Chip; 的PSoC可编程系统级芯片
CY8C24423A-24LTXIT
型号: CY8C24423A-24LTXIT
厂家: CYPRESS    CYPRESS
描述:

PSoC Programmable System-on-Chip
的PSoC可编程系统级芯片

多功能外围设备 微控制器和处理器 时钟
文件: 总55页 (文件大小:1570K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CY8C24123A  
CY8C24223A, CY8C24423A  
PSoC® Programmable System-on-Chip™  
New CY8C24x23A PSoC Device  
Derived From the CY8C24x23 Device  
Low Power and Low Voltage (2.4V)  
Features  
Powerful Harvard Architecture Processor  
M8C Processor Speeds to 24 MHz  
8x8 Multiply, 32-Bit Accumulate  
Low Power at High Speed  
2.4 to 5.25V Operating Voltage  
Operating Voltages Down to 1.0V Using On-Chip Switch  
Mode Pump (SMP)  
Additional System Resources  
I2CSlave, Master, and MultiMaster to 400 kHz  
Watchdog and Sleep Timers  
User-Configurable Low Voltage Detection  
Integrated Supervisory Circuit  
On-Chip Precision Voltage Reference  
Industrial Temperature Range: -40°C to +85°C  
Advanced Peripherals (PSoC® Blocks)  
Six Rail-to-Rail Analog PSoC Blocks Provide:  
• Up to 14-Bit ADCs  
Complete Development Tools  
Free Development Software (PSoC Designer™)  
Full-Featured, In-Circuit Emulator, and Programmer  
Full Speed Emulation  
Complex Breakpoint Structure  
128K Trace Memory  
• Up to 9-Bit DACs  
• Programmable Gain Amplifiers  
• Programmable Filters and Comparators  
Four Digital PSoC Blocks Provide:  
• 8 to 32-Bit Timers, Counters, and PWMs  
• CRC and PRS Modules  
Logic Block Diagram  
Analog  
Port 2 Port 1 Port 0  
Drivers  
• Full-Duplex UART  
PSoC CORE  
• Multiple SPI Masters or Slaves  
• Connectable to All GPIO Pins  
Complex Peripherals by Combining Blocks  
System Bus  
Precision, Programmable Clocking  
Global Digital Interconnect  
Global Analog Interconnect  
Internal ±2.5% 24/48 MHz Oscillator  
SRAM  
256 Bytes  
SROM  
Flash 4K  
High accuracy 24 MHz with optional 32 kHz Crystal and PLL  
Optional External Oscillator, up to 24 MHz  
Internal Oscillator for Watchdog and Sleep  
Sleep and  
Watchdog  
CPU Core (M8C)  
Interrupt  
Controller  
Flexible On-Chip Memory  
Multiple Clock Sources  
(Includes IMO, ILO, PLL, and ECO)  
4K Flash Program Storage 50,000 Erase/Write Cycles  
256 Bytes SRAM Data Storage  
In-System Serial Programming (ISSP)  
Partial Flash Updates  
Flexible Protection Modes  
EEPROM Emulation in Flash  
DIGITAL SYSTEM  
ANALOG SYSTEM  
Analog  
Ref  
Digital  
Block  
Array  
Analog  
Block  
Array  
Analog  
Input  
Muxing  
Programmable Pin Configurations  
25 mA Sink on all GPIO  
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive  
Modes on All GPIO  
Up to Ten Analog Inputs on GPIO  
Two 30 mA Analog Outputs on GPIO  
Configurable Interrupt on All GPIO  
Internal  
Voltage  
Ref.  
Switch  
Mode  
Pump  
Digital  
Clocks Accum.  
Multiply  
POR and LVD  
System Resets  
I2C  
Decimator  
SYSTEM RESOURCES  
Cypress Semiconductor Corporation  
Document Number: 38-12028 Rev. *J  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 14, 2009  
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Digital System  
PSoC Functional Overview  
The Digital System consists of 4 digital PSoC blocks. Each block  
is an 8-bit resource that may be used alone or combined with  
other blocks to form 8, 16, 24, and 32-bit peripherals, which are  
called user module references.  
The PSoC family consists of many Mixed-Signal Array with  
On-Chip Controller devices. These devices are designed to  
replace multiple traditional MCU-based system components with  
a low cost single-chip programmable device. PSoC devices  
include configurable blocks of analog and digital logic, and  
programmable interconnects. This architecture enables the user  
to create customized peripheral configurations that match the  
requirements of each individual application. Additionally, a fast  
CPU, Flash program memory, SRAM data memory, and  
configurable IO are included in a range of convenient pinouts and  
packages.  
Figure 1. Digital System Block Diagram  
Port 1  
Port 2  
Port 0  
To System Bus  
Digital Clocks  
From Core  
To Analog  
System  
The PSoC architecture, shown in Figure 1, consists of four main  
areas: PSoC Core, Digital System, Analog System, and System  
Resources. Configurable global busing allows combining all the  
device resources into a complete custom system. The PSoC  
CY8C24x23A family can have up to three IO ports that connect  
to the global digital and analog interconnects, providing access  
to 4 digital blocks and 6 analog blocks.  
DIGITAL SYSTEM  
Digital PSoC Block Array  
Row 0  
8
4
8
8
8
DBB00  
DBB01  
DCB02 DCB03  
4
PSoC Core  
The PSoC Core is a powerful engine that supports a rich feature  
set. The core includes a CPU, memory, clocks, and configurable  
GPIO (General Purpose IO).  
GIE[7:0]  
GIO[7:0]  
GOE[7:0]  
GOO[7:0]  
Global Digital  
Interconnect  
The M8C CPU core is a powerful processor with speeds up to  
24 MHz, providing a four MIPS 8-bit Harvard architecture  
microprocessor. The CPU uses an interrupt controller with  
11 vectors, to simplify programming of real time embedded  
events. Program execution is timed and protected using the  
included Sleep and Watchdog Timers (WDT).  
Digital peripheral configurations are:  
PWMs (8 to 32 bit)  
Memory encompasses 4 KB of Flash for program storage, 256  
bytes of SRAM for data storage, and up to 2 KB of EEPROM  
emulated using the Flash. Program Flash uses four protection  
levels on blocks of 64 bytes, allowing customized software IP  
protection.  
PWMs with Dead band (8 to 24 bit)  
Counters (8 to 32 bit)  
Timers (8 to 32 bit)  
The PSoC device incorporates flexible internal clock generators,  
including a 24 MHz IMO (internal main oscillator) accurate to  
2.5% over temperature and voltage. The 24 MHz IMO can also  
be doubled to 48 MHz for use by the digital system. A low power  
32 kHz ILO (internal low speed oscillator) is provided for the  
Sleep timer and WDT. If crystal accuracy is required, the ECO  
(32.768 kHz external crystal oscillator) is available for use as a  
Real Time Clock (RTC) and can optionally generate a  
crystal-accurate 24 MHz system clock using a PLL. The clocks,  
together with programmable clock dividers (as a System  
Resource), provide the flexibility to integrate almost any timing  
requirement into the PSoC device.  
UART 8 bit with selectable parity  
SPI master and slave  
I2C slave and multi-master (one is available as a System  
Resource)  
Cyclical Redundancy Checker/Generator (8 to 32 bit)  
IrDA  
Pseudo Random Sequence Generators (8 to 32 bit)  
The digital blocks may be connected to any GPIO through a  
series of global buses that can route any signal to any pin. The  
buses also allow for signal multiplexing and performing logic  
operations. This configurability frees your designs from the  
constraints of a fixed peripheral controller.  
PSoC GPIOs provide connection to the CPU, digital, and analog  
resources of the device. Each pin’s drive mode may be selected  
from eight options, allowing great flexibility in external  
interfacing. Every pin can generate a system interrupt on high  
level, low level, and change from last read.  
Digital blocks are provided in rows of four, where the number of  
blocks varies by PSoC device family. This gives a choice of  
system resources for your application. Family resources are  
shown in Table 1 on page 4.  
Document Number: 38-12028 Rev. *J  
Page 2 of 55  
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Figure 2. Analog System Block Diagram  
Analog System  
The Analog System consists of six configurable blocks, each  
consisting of an opamp circuit that allows the creation of complex  
analog signal flows. Analog peripherals are very flexible and can  
be customized to support specific application requirements.  
Some of the more common PSoC analog functions (most  
available as user modules) are:  
P0[7]  
P0[6]  
P0[4]  
P0[5]  
P0[3]  
P0[1]  
P0[2]  
P0[0]  
Analog-to-digital converters (up to two, with 6 to 14-bit  
resolution, selectable as Incremental, Delta Sigma, and SAR)  
P2[6]  
P2[4]  
P2[3]  
P2[1]  
Filters (two and four pole band-pass, low-pass, and notch)  
Amplifiers (up to two, with selectable gain to 48x)  
Instrumentation amplifiers (one with selectable gain to 93x)  
Comparators (up to two, with 16 selectable thresholds)  
DACs (up to two, with 6 to 9-bit resolution)  
P2[2]  
P2[0]  
Array Input Configuration  
Multiplying DACs (up to two, with 6 to 9-bit resolution)  
High current output drivers (two with 30 mA drive as a PSoC  
ACI0[1:0]  
ACI1[1:0]  
Core resource)  
1.3V reference (as a System Resource)  
DTMF Dialer  
Block Array  
ACB00  
ASC10  
ASD20  
ACB01  
Modulators  
ASD11  
ASC21  
Correlators  
Peak Detectors  
Many other topologies possible  
Analog blocks are arranged in a column of three, which includes  
one CT (Continuous Time) and two SC (Switched Capacitor)  
blocks, as shown in Figure 2.  
Analog Reference  
Interface to  
Digital System  
Reference  
Generators  
RefHi  
RefLo  
AGND  
AGNDIn  
RefIn  
Bandgap  
M8C Interface (Address Bus, Data Bus, Etc.)  
Additional System Resources  
System Resources, some of which are listed in the previous  
sections, provide additional capability useful to complete  
systems. Additional resources include a multiplier, decimator,  
switch mode pump, low voltage detection, and power on reset.  
Statements describing the merits of each system resource  
follow:  
Digital clock dividers provide three customizable clock  
frequencies for use in applications. The clocks can be routed  
to both the digital and analog systems. Additional clocks may  
be generated using digital PSoC blocks as clock dividers.  
A multiply accumulate (MAC) provides a fast 8-bit multiplier  
with 32-bit accumulate, to assist in both general math and  
digital filters.  
The decimator provides a custom hardware filter for digital  
signal processing applications including the creation of Delta  
Sigma ADCs.  
TheI2Cmoduleprovides100and400kHzcommunicationover  
two wires. Slave, master, and multi-master are supported.  
Document Number: 38-12028 Rev. *J  
Page 3 of 55  
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Low Voltage Detection (LVD) interrupts can signal the appli-  
cation of falling voltagelevels, while the advanced POR (Power  
On Reset) circuit eliminates the need for a system supervisor.  
Getting Started  
The quickest way to understand PSoC silicon is to read this data  
sheet and then use the PSoC Designer Integrated Development  
Environment (IDE). This data sheet is an overview of the PSoC  
integrated circuit and presents specific pin, register, and  
electrical specifications.  
An internal 1.3V reference provides an absolute reference for  
the analog system, including ADCs and DACs.  
An integrated switch mode pump (SMP) generates normal  
operating voltages from a single 1.2V battery cell, providing a  
low cost boost converter.  
For in depth information, along with detailed programming infor-  
mation, see the PSoC® Programmable System-on-Chip  
Technical Reference Manual for CY8C28xxx PSoC devices.  
PSoC Device Characteristics  
For up-to-date ordering, packaging, and electrical specification  
information, see the latest PSoC device data sheets on the web  
at www.cypress.com/psoc.  
Depending on your PSoC device characteristics, the digital and  
analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or  
4 analog blocks. Table 1 lists the resources available for specific  
PSoC device groups. The PSoC device covered by this data  
sheet is highlighted in this table.  
Application Notes  
Application notes are an excellent introduction to the wide variety  
of possible PSoC designs. They are located here:  
www.cypress.com/psoc. Select Application Notes under the  
Documentation tab.  
Table 1. PSoC Device Characteristics  
PSoC Part  
Number  
Development Kits  
PSoC Development Kits are available online from Cypress at  
www.cypress.com/shop and through a growing number of  
regional and global distributors, which include Arrow, Avnet,  
Digi-Key, Farnell, Future Electronics, and Newark.  
CY8C29x66  
CY8C27x43  
up to  
64  
4
2
16 12  
4
4
4
4
12 2K  
32K  
16K  
up to  
44  
8
12  
12 256  
Bytes  
CY8C24x94  
CY8C24x23  
49  
1
1
4
4
48  
12  
2
2
2
2
6
6
1K  
16K  
4K  
Training  
up to  
24  
256  
Bytes  
Free PSoC technical training (on demand, webinars, and  
workshops) is available online at www.cypress.com/training. The  
training covers a wide variety of topics and skill levels to assist  
you in your designs.  
CY8C24x23A up to 1  
24  
4
4
4
0
12  
28  
8
2
0
0
0
2
2
2
0
6
256  
Bytes  
4K  
8K  
4K  
8K  
CY8C21x34  
CY8C21x23  
CY8C20x34  
up to  
28  
1
1
0
4[1] 512  
Bytes  
4[1] 256  
Bytes  
3[2] 512  
Bytes  
Cypros Consultants  
16  
Certified PSoC Consultants offer everything from technical  
assistance to completed PSoC designs. To contact or become a  
PSoC Consultant go to www.cypress.com/cypros.  
up to  
28  
28  
Solutions Library  
Visit our growing library of solution focused designs at  
www.cypress.com/solutions. Here you can find various appli-  
cation designs that include firmware and hardware design files  
that enable you to complete your designs quickly.  
Technical Support  
For assistance with technical issues, search KnowledgeBase  
articles and forums at www.cypress.com/support. If you cannot  
find an answer to your question, call technical support at  
1-800-541-4736.  
Notes  
1. Limited analog functionality.  
2. Two analog blocks and one CapSense.  
Document Number: 38-12028 Rev. *J  
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Code Generation Tools  
Development Tools  
PSoC Designer supports multiple third party C compilers and  
assemblers. The code generation tools work seamlessly within  
the PSoC Designer interface and have been tested with a full  
range of debugging tools. The choice is yours.  
PSoC Designer is a Microsoft® Windows-based, integrated  
development  
environment  
for  
the  
Programmable  
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs  
on Windows XP or Windows Vista.  
This system provides design database management by project,  
an integrated debugger with In-Circuit Emulator, in-system  
programming support, and built-in support for third-party  
assemblers and C compilers.  
Assemblers. The assemblers allow assembly code to merge  
seamlessly with C code. Link libraries automatically use absolute  
addressing or are compiled in relative mode, and linked with  
other software modules to get absolute addressing.  
PSoC Designer also supports C language compilers developed  
specifically for the devices in the PSoC family.  
C Language Compilers. C language compilers are available  
that support the PSoC family of devices. The products allow you  
to create complete C programs for the PSoC family devices.  
PSoC Designer Software Subsystems  
The optimizing C compilers provide all the features of C tailored  
to the PSoC architecture. They come complete with embedded  
libraries providing port and bus operations, standard keypad and  
display support, and extended math functionality.  
System-Level View  
A drag-and-drop visual embedded system design environment  
based on PSoC Express. In the system level view you create a  
model of your system inputs, outputs, and communication inter-  
faces. You define when and how an output device changes state  
based upon any or all other system devices. Based upon the  
design, PSoC Designer automatically selects one or more PSoC  
Mixed-Signal Controllers that match your system requirements.  
Debugger  
The PSoC Designer Debugger subsystem provides hardware  
in-circuit emulation, allowing you to test the program in a physical  
system while providing an internal view of the PSoC device.  
Debugger commands allow the designer to read and program  
and read and write data memory, read and write IO registers,  
read and write CPU registers, set and clear breakpoints, and  
provide program run, halt, and step control. The debugger also  
allows the designer to create a trace buffer of registers and  
memory locations of interest.  
PSoC Designer generates all embedded code, then compiles  
and links it into a programming file for a specific PSoC device.  
Chip-Level View  
The chip-level view is a more traditional Integrated Development  
Environment (IDE) based on PSoC Designer 4.4. Choose a base  
device to work with and then select different onboard analog and  
digital components called user modules that use the PSoC  
blocks. Examples of user modules are ADCs, DACs, Amplifiers,  
and Filters. Configure the user modules for your chosen  
application and connect them to each other and to the proper  
pins. Then generate your project. This prepopulates your project  
with APIs and libraries that you can use to program your  
application.  
Online Help System  
The online help system displays online, context-sensitive help  
for the user. Designed for procedural and quick reference, each  
functional subsystem has its own context-sensitive help. This  
system also provides tutorials and links to FAQs and an Online  
Support Forum to aid the designer in getting started.  
In-Circuit Emulator  
The device editor also supports easy development of multiple  
configurations and dynamic reconfiguration. Dynamic  
configuration allows for changing configurations at run time.  
A low cost, high functionality In-Circuit Emulator (ICE) is  
available for development support. This hardware has the  
capability to program single devices.  
Hybrid Designs  
The emulator consists of a base unit that connects to the PC by  
way of a USB port. The base unit is universal and operates with  
all PSoC devices. Emulation pods for each device family are  
available separately. The emulation pod takes the place of the  
PSoC device in the target board and performs full speed (24  
MHz) operation.  
You can begin in the system-level view, allow it to choose and  
configure your user modules, routing, and generate code, then  
switch to the chip-level view to gain complete control over  
on-chip resources. All views of the project share a common code  
editor, builder, and common debug, emulation, and programming  
tools.  
Document Number: 38-12028 Rev. *J  
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property, and other information you may need to successfully  
implement your design.  
Designing with PSoC Designer  
The development process for the PSoC device differs from that  
of a traditional fixed function microprocessor. The configurable  
analog and digital hardware blocks give the PSoC architecture a  
unique flexibility that pays dividends in managing specification  
change during development and by lowering inventory costs.  
These configurable resources, called PSoC Blocks, have the  
ability to implement a wide variety of user-selectable functions.  
Organize and Connect  
You can build signal chains at the chip level by interconnecting  
user modules to each other and the IO pins, or connect system  
level inputs, outputs, and communication interfaces to each  
other with valuator functions.  
In the system-level view, selecting a potentiometer driver to  
control a variable speed fan driver and setting up the valuators  
to control the fan speed based on input from the pot selects,  
places, routes, and configures a programmable gain amplifier  
(PGA) to buffer the input from the potentiometer, an analog to  
digital converter (ADC) to convert the potentiometer’s output to  
a digital signal, and a PWM to control the fan.  
The PSoC development process can be summarized in the  
following four steps:  
1. Select components  
2. Configure components  
3. Organize and Connect  
4. Generate, Verify, and Debug  
In the chip-level view, perform the selection, configuration, and  
routing so that you have complete control over the use of all  
on-chip resources.  
Select Components  
Both the system-level and chip-level views provide a library of  
prebuilt, pretested hardware peripheral components. In the  
system-level view, these components are called “drivers” and  
correspond to inputs (a thermistor, for example), outputs (a  
brushless DC fan, for example), communication interfaces  
(I C-bus, for example), and the logic to control how they interact  
with one another (called valuators).  
Generate, Verify, and Debug  
When you are ready to test the hardware configuration or move  
on to developing code for the project, perform the “Generate  
Application” step. This causes PSoC Designer to generate  
source code that automatically configures the device to your  
specification and provides the software for the system.  
2
In the chip-level view, the components are called “user modules”.  
User modules make selecting and implementing peripheral  
devices simple, and come in analog, digital, and mixed signal  
varieties.  
Both system-level and chip-level designs generate software  
based on your design. The chip-level design provides application  
programming interfaces (APIs) with high level functions to  
control and respond to hardware events at run-time and interrupt  
service routines that you can adapt as needed. The system-level  
design also generates a C main() program that completely  
controls the chosen application and contains placeholders for  
custom code at strategic positions allowing you to further refine  
the software without disrupting the generated code.  
Configure Components  
Each of the components you select establishes the basic register  
settings that implement the selected function. They also provide  
parameters and properties that allow you to tailor their precise  
configuration to your particular application. For example, a Pulse  
Width Modulator (PWM) User Module configures one or more  
digital PSoC blocks, one for each 8 bits of resolution. The user  
module parameters permit you to establish the pulse width and  
duty cycle. Configure the parameters and properties to  
correspond to your chosen application. Enter values directly or  
by selecting values from drop-down menus.  
A complete code development environment allows you to  
develop and customize your applications in C, assembly  
language, or both.  
The last step in the development process takes place inside  
PSoC Designer’s Debugger subsystem. The Debugger  
downloads the HEX image to the ICE where it runs at full speed.  
Debugger capabilities rival those of systems costing many times  
more. In addition to traditional single-step, run-to-breakpoint and  
watch-variable features, the Debugger provides a large trace  
buffer and allows you define complex breakpoint events that  
include monitoring address and data bus values, memory  
locations and external signals.  
Both the system-level drivers and chip-level user modules are  
documented in data sheets that are viewed directly in PSoC  
Designer. These data sheets explain the internal operation of the  
component and provide performance specifications. Each data  
sheet describes the use of each user module parameter or driver  
Document Number: 38-12028 Rev. *J  
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Units of Measure  
Document Conventions  
A unit of measure table is located in the section  
Electrical Specifications on page 17. Table 8 on page 14 lists all  
the abbreviations used to measure the PSoC devices.  
Acronyms Used  
The following table lists the acronyms that are used in this  
document.  
Numeric Naming  
Table 2. Acronyms Used  
Hexadecimal numbers are represented with all letters in  
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or  
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’  
prefix, the C coding convention. Binary numbers have an  
appended lowercase ‘b’ (for example, 01010100b’ or  
‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.  
Acronym  
AC  
Description  
alternating current  
ADC  
API  
analog-to-digital converter  
application programming interface  
central processing unit  
continuous time  
CPU  
CT  
DAC  
DC  
digital-to-analog converter  
direct current  
ECO  
EEPROM  
external crystal oscillator  
electrically erasable programmable read-only  
memory  
FSR  
GPIO  
GUI  
full scale range  
general purpose IO  
graphical user interface  
human body model  
in-circuit emulator  
HBM  
ICE  
ILO  
internal low speed oscillator  
internal main oscillator  
input/output  
IMO  
IO  
IPOR  
LSb  
imprecise power on reset  
least-significant bit  
low voltage detect  
LVD  
MSb  
PC  
most-significant bit  
program counter  
PLL  
phase-locked loop  
POR  
PPOR  
PSoC®  
PWM  
SC  
power on reset  
precision power on reset  
Programmable System-on-Chip™  
pulse width modulator  
switched capacitor  
slow IMO  
SLIMO  
SMP  
SRAM  
switch mode pump  
static random access memory  
Document Number: 38-12028 Rev. *J  
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Pinouts  
This section describes, lists, and illustrates the CY8C24x23A PSoC device pins and pinout configurations. Every port pin (labeled  
with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.  
8-Pin Part Pinoutt  
Table 3. Pin Definitions - 8-Pin PDIP and SOIC  
Type  
Figure 3. CY8C24123A 8-Pin PSoC Device  
Pin  
No.  
Pin  
Name  
Description  
Digital Analog  
A, IO,P0[5]  
A,IO, P0[3]  
I2CSCL,XTALin,P1[1]  
Vss  
1
2
3
4
8
7
6
5
Vdd  
P0[4], A,I  
P0[2], A,I  
1
I/O  
I/O  
I/O  
I/O  
P0[5] Analog Column Mux Input and  
Column Output  
PDIP  
SOIC  
2
3
I/O  
P0[3] Analog Column Mux Input and  
Column Output  
P1[0],XTALout,I2CSDA  
P1[1] Crystal Input (XTALin), I2C Serial  
Clock (SCL), ISSP-SCLK*  
4
5
Power  
I/O  
Vss  
Ground Connection  
P1[0] CrystalOutput(XTALout), I2CSerial  
Data (SDA), ISSP-SDATA*  
6
7
8
I/O  
I
I
P0[2] Analog Column Mux Input  
P0[4] Analog Column Mux Input  
I/O  
Power  
Vdd  
Supply Voltage  
LEGEND: A = Analog, I = Input, and O = Output.  
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details.  
Document Number: 38-12028 Rev. *J  
Page 8 of 55  
[+] Feedback  
CY8C24123A  
CY8C24223A, CY8C24423A  
20-Pin Part Pinout  
Table 4. Pin Definitions - 20-Pin PDIP, SSOP, and SOIC  
Type  
Figure 4. CY8C24223A 20-Pin PSoC Device  
Pin  
No.  
Pin  
Description  
Name  
Digital Analog  
A, I,P0[7]  
A,IO, P0[5]  
A,IO, P0[3]  
A,I, P0[1]  
Vdd  
1
2
3
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1
I/O  
I/O  
I
P0[7] Analog Column Mux Input  
P0[6], A,I  
2
I/O  
P0[5] Analog Column Mux Input and Column  
Output  
P0[4], A,I  
P0[2], A,I  
4
PDIP  
SSOP  
SOIC  
SMP  
P0[0], A,I  
5
3
I/O  
I/O  
I
P0[3] Analog Column Mux Input and Column  
Output  
I2CSCL,P1[7]  
I2C SDA,P1[5]  
P1[3]  
XRES  
P1[6]  
6
7
8
9
4
5
I/O  
P0[1] Analog Column Mux Input  
P1[4],EXTCLK  
P1[2]  
P1[0],XTALout,I2CSDA  
Power  
SMP Switch Mode Pump (SMP) Connection to  
External Components required  
I2CSCL,XTALin,P1[1]  
Vss  
10  
6
7
8
9
I/O  
I/O  
I/O  
I/O  
P1[7] I2C Serial Clock (SCL)  
P1[5] I2C Serial Data (SDA)  
P1[3]  
P1[1] Crystal Input (XTALin), I2C Serial Clock  
(SCL), ISSP-SCLK*  
10 Power  
11 I/O  
Vss  
Ground Connection.  
P1[0] Crystal Output (XTALout), I2C Serial Data  
(SDA), ISSP-SDATA*  
12 I/O  
13 I/O  
14 I/O  
15 Input  
P1[2]  
P1[4] Optional External Clock Input (EXTCLK)  
P1[6]  
XRES Active High External Reset with Internal  
Pull Down  
16 I/O  
17 I/O  
18 I/O  
19 I/O  
20 Power  
I
I
I
I
P0[0] Analog Column Mux Input  
P0[2] Analog Column Mux Input  
P0[4] Analog Column Mux Input  
P0[6] Analog Column Mux Input  
Vdd  
Supply Voltage  
LEGEND: A = Analog, I = Input, and O = Output.  
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details.  
Document Number: 38-12028 Rev. *J  
Page 9 of 55  
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CY8C24123A  
CY8C24223A, CY8C24423A  
28-Pin Part Pinout  
Table 5. Pin Definitions - 28-Pin PDIP, SSOP, and SOIC  
Type  
Figure 5. CY8C24423A 28-Pin PSoC Device  
Pin  
No.  
Pin  
Name  
Description  
Digital Analog  
A, I,P0[7]  
A,IO, P0[5]  
A,IO, P0[3]  
A,I, P0[1]  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
Vdd  
P0[6], A, I  
P0[4], A, I  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
1
I/O  
I/O  
I
P0[7] Analog Column Mux Input  
2
I/O  
P0[5] Analog Column Mux Input and column  
output  
P0[2], A, I  
P0[0], A, I  
P2[6],Ex ternalVRef  
P2[4],Ex ternalAGND  
P2[2], A, I  
3
I/O  
I/O  
I
P0[3] Analog Column Mux Input and Column  
Output  
P2[7]  
P2[5]  
PDIP  
SSOP  
SOIC  
A,I, P2[3]  
A, I,P2[1]  
4
5
6
7
8
9
I/O  
P0[1] Analog Column Mux Input  
I/O  
P2[7]  
SMP  
P2[0], A, I  
XRES  
P1[6]  
I/O  
P2[5]  
I2CSCL,P1[7]  
I2CSDA,P1[5]  
P1[3]  
I/O  
I
I
P2[3] Direct Switched Capacitor Block Input  
P2[1] Direct Switched Capacitor Block Input  
P1[4],EXTCLK  
P1[2]  
P1[0],XTALout,I2CSDA  
I/O  
I2CSCL,XTALin,P1[1]  
Vss  
Power  
SMP Switch Mode Pump (SMP) Connection to  
External Components required  
10  
11  
12  
13  
I/O  
I/O  
I/O  
I/O  
P1[7] I2C Serial Clock (SCL)  
P1[5] I2C Serial Data (SDA)  
P1[3]  
P1[1] Crystal Input (XTALin), I2C Serial Clock  
(SCL), ISSP-SCLK*  
14  
15  
Power  
I/O  
Vss  
Ground connection.  
P1[0] Crystal Output (XTALout), I2C Serial Data  
(SDA), ISSP-SDATA*  
16  
17  
18  
19  
I/O  
P1[2]  
I/O  
P1[4] Optional External Clock Input (EXTCLK)  
P1[6]  
I/O  
Input  
XRES Active High External Reset with Internal  
Pull Down  
20  
21  
22  
23  
24  
25  
26  
27  
28  
I/O  
I
I
P2[0] Direct Switched Capacitor Block Input  
P2[2] Direct Switched Capacitor Block Input  
P2[4] External Analog Ground (AGND)  
P2[6] External Voltage Reference (VRef)  
P0[0] Analog Column Mux Input  
I/O  
I/O  
I/O  
I/O  
I
I
I
I
I/O  
P0[2] Analog Column Mux Input  
I/O  
P0[4] Analog Column Mux Input  
I/O  
P0[6] Analog Column Mux Input  
Power  
Vdd  
Supply Voltage  
LEGEND: A = Analog, I = Input, and O = Output.  
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Pro-  
grammable Sytem-on-Chip Technical Reference Manual for details.  
Document Number: 38-12028 Rev. *J  
Page 10 of 55  
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CY8C24123A  
CY8C24223A, CY8C24423A  
32-Pin Part Pinout  
Table 6. Pin Definitions - 32-Pin QFN**  
Type  
Figure 6. CY8C24423A 32-Pin PSoC Device  
Pin  
No.  
Pin  
Name  
Description  
Digital Analog  
1
2
3
4
5
6
I/O  
P2[7]  
P2[5]  
I/O  
I/O  
I
I
P2[3] Direct Switched Capacitor Block Input  
P2[1] Direct Switched Capacitor Block Input  
P2[7]  
P2[5]  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
P0[2], A,I  
P0[0], A,I  
I/O  
A, I,P2[3]  
A, I,P2[1]  
Vss  
P2[6],ExternalVRef  
P2[4],ExternalAGND  
P2[2], A,I  
P2[0], A,I  
XRES  
Power  
Power  
Vss  
Ground Connection  
QFN  
(Top View)  
SMP Switch Mode Pump (SMP) Connection  
to External Components required  
SMP  
I2CSCL,P1[7]  
I2CSDA,P1[5]  
7
8
9
I/O  
I/O  
P1[7] I2C Serial Clock (SCL).  
P1[5] I2C Serial Data (SDA).  
P1[6]  
NC  
No Connection  
10  
11  
I/O  
I/O  
P1[3]  
P1[1] Crystal Input (XTALin), I2C Serial Clock  
(SCL), ISSP-SCLK*  
12  
13  
Power  
I/O  
Vss  
Ground Connection  
P1[0] Crystal Output (XTALout), I2C Serial  
Data (SDA), ISSP-SDATA*  
14  
15  
I/O  
I/O  
P1[2]  
Figure 9. CY8C24423A 32-Pin Sawn PSoC Device  
P1[4] Optional External Clock Input  
(EXTCLK)  
16  
17  
18  
NC  
No Connection  
I/O  
P1[6]  
Input  
XRES Active High External Reset with Internal  
Pull Down  
P2[7]  
P2[5]  
1
2
3
4
5
6
7
8
P0[2], A, I  
24  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
I
P2[0] Direct Switched Capacitor Block Input  
P2[2] Direct Switched Capacitor Block Input  
P2[4] External Analog Ground (AGND)  
P2[6] External Voltage Reference (VRef)  
P0[0] Analog Column Mux Input  
23 P0[0], A, I  
A, I, P2[3]  
A, I, P2[1]  
Vss  
22 P2[6], ExternalVRef  
P2[4], ExternalA GND  
21  
20 P2[2], A, I  
QFN  
(Top View)  
SMP  
P2[0], A, I  
19  
12 CS CL, P1[7]  
12 CS DA, P1[5]  
18 XRES  
17 P1[6]  
I
I
P0[2] Analog Column Mux Input  
NC  
No Connection  
I/O  
I
I
P0[4] Analog Column Mux Input  
P0[6] Analog Column Mux Input  
I/O  
Power  
I/O  
Vdd  
Supply Voltage  
I
P0[7] Analog Column Mux Input  
I/O  
IO  
P0[5] Analog Column Mux Input and Column  
Output  
31  
I/O  
IO  
P0[3] Analog Column Mux Input and Column  
Output  
32  
I/O  
I
P0[1] Analog Column Mux Input  
LEGEND: A = Analog, I = Input, and O = Output.  
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details.  
** The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it must  
be electrically floated and not connected to any other signal.  
Document Number: 38-12028 Rev. *J  
Page 11 of 55  
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CY8C24123A  
CY8C24223A, CY8C24423A  
56-Pin Part Pinout  
The 56-pin SSOP part is for the CY8C24000A On-Chip Debug (OCD) PSoC device.  
Note This part is only used for in-circuit debugging. It is NOT available for production.  
Table 7. Pin Definitions - 56-Pin SSOP  
Type  
Pin  
No.  
Pin  
Description  
No Connection  
Name  
Digital Analog  
1
2
3
NC  
Figure 10. CY8C24000A 56-Pin PSoC Device  
I/O  
I/O  
I
I
P0[7] Analog Column Mux Input  
NC  
AI, P0[7]  
AIO, P0[5]  
AIO, P0[3]  
AI, P0[1]  
P2[7]  
56  
55  
54  
53  
1
2
3
4
5
6
Vdd  
P0[5] Analog Column Mux Input and  
Column Output  
P0[6], AI  
P0[4], AIO  
P0[2], AIO  
P0[0], AI  
4
I/O  
I
I
P0[3] Analog Column Mux Input and  
Column Output  
52  
51  
P2[6], External VRef  
P2[4], External AGND  
P2[2], AI  
P2[0], AI  
P4[6]  
P2[5]  
AI, P2[3]  
AI, P2[1]  
P4[7]  
7
8
9
50  
49  
48  
5
6
7
8
I/O  
I/O  
I/O  
I/O  
P0[1] Analog Column Mux Input  
P2[7]  
P2[5]  
10  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
P4[5]  
P4[3]  
P4[4]  
11  
12  
13  
P4[2]  
P4[0]  
I
I
P2[3] Direct Switched Capacitor Block  
Input  
P4[1]  
OCDE  
OCDO  
SMP  
14  
CCLK  
HCLK  
XRES  
P3[6]  
SSOP  
15  
16  
9
I/O  
P2[1] Direct sWitched Capacitor Block  
Input  
P3[7]  
17  
P3[5]  
P3[3]  
P3[4]  
P3[2]  
P3[0]  
P5[2]  
18  
19  
20  
10  
11  
12  
13  
14  
I/O  
P4[7]  
P4[5]  
P4[3]  
P4[1]  
P3[1]  
P5[3]  
I/O  
21  
22  
23  
P5[1]  
P5[0]  
P1[6]  
I/O  
I
I
I2C SCL, P1[7]  
I2C SDA, P1[5]  
NC  
P1[4], EXTCLK  
24  
25  
33  
32  
I/O  
P1[2]  
P1[3]  
SCLK, I2C SCL, XTALIn, P1[1]  
Vss  
26  
27  
28  
31  
30  
P1[0], XTALOut, I2C SDA, SDATA  
NC  
NC  
OCD  
OCD OCD Even Data IO.  
E
29  
15  
16  
OCD  
OCD OCD Odd Data Output  
O
Power  
SMP Switch Mode Pump (SMP)  
Connection to required External  
Components  
Not for Production  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
P3[7]  
P3[5]  
P3[3]  
P3[1]  
P5[3]  
P5[1]  
P1[7] I2C Serial Clock (SCL)  
P1[5] I2C Serial Data (SDA)  
NC  
No Connection  
I/O  
I/O  
P1[3]  
P1[1] Crystal Input (XTALin), I2C Serial  
Clock (SCL), ISSP-SCLK*  
28  
29  
30  
31  
Power  
Vdd  
NC  
NC  
Supply Voltage  
No Connection  
No Connection  
I/O  
P1[0] Crystal Output (XTALout), I2C  
Serial Data (SDA), ISSP-SDATA*  
32  
33  
I/O  
I/O  
P1[2]  
P1[4] Optional External Clock Input  
(EXTCLK)  
Document Number: 38-12028 Rev. *J  
Page 12 of 55  
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CY8C24123A  
CY8C24223A, CY8C24423A  
Table 7. Pin Definitions - 56-Pin SSOP (continued)  
Type  
Pin  
No.  
Pin  
Name  
Description  
Digital Analog  
34  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
Input  
P1[6]  
P5[0]  
P5[2]  
P3[0]  
P3[2]  
P3[4]  
P3[6]  
35  
36  
37  
38  
39  
40  
41  
XRES Active high external reset with  
internal pull down.  
42  
43  
44  
45  
46  
47  
48  
OCD  
OCD  
I/O  
HCLK OCD high-speed clock output.  
CCLK OCD CPU clock output.  
P4[0]  
P4[2]  
P4[4]  
P4[6]  
I/O  
I/O  
I/O  
I/O  
I
I
P2[0] Direct switched capacitor block  
input.  
49  
I/O  
P2[2] Direct switched capacitor block  
input.  
50  
51  
I/O  
I/O  
P2[4] External Analog Ground (AGND).  
P2[6] External Voltage Reference  
(VRef).  
52  
53  
I/O  
I/O  
I
I
P0[0] Analog column mux input.  
P0[2] Analog column mux input and  
column output.  
54  
I/O  
I
I
P0[4] Analog column mux input and  
column output.  
55  
56  
I/O  
P0[6] Analog column mux input.  
Power  
Vdd  
Supply voltage.  
LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.  
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details.  
Document Number: 38-12028 Rev. *J  
Page 13 of 55  
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CY8C24123A  
CY8C24223A, CY8C24423A  
Register Mapping Tables  
Register Reference  
The PSoC device has a total register address space of 512  
bytes. The register space is referred to as IO space and is  
divided into two banks. The XOI bit in the Flag register (CPU_F)  
determines which bank the user is currently in. When the XOI bit  
is set the user is in Bank 1.  
This section lists the registers of the CY8C24x23A PSoC device.  
For detailed register information, refer the PSoC Programmable  
Sytem-on-Chip Reference Manual.  
Register Conventions  
Note In the following register mapping tables, blank fields are  
reserved and must not be accessed.  
Abbreviations Used  
The register conventions specific to this section are listed in the  
following table.  
Table 8. Abbreviations  
Convention  
Description  
Read register or bit(s)  
R
W
L
Write register or bit(s)  
Logical register or bit(s)  
Clearable register or bit(s)  
Access is bit specific  
C
#
Document Number: 38-12028 Rev. *J  
Page 14 of 55  
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CY8C24123A  
CY8C24223A, CY8C24423A  
Table 9. Register Map Bank 0 Table: User Space  
Name  
PRT0DR  
Addr (0,Hex) Access  
Name  
Addr (0,Hex) Access  
40  
Name  
ASC10CR0 80  
Addr (0,Hex)  
Access  
RW  
Name  
Addr (0,Hex) Access  
C0  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
0A  
0B  
0C  
0D  
0E  
0F  
10  
11  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
PRT0IE  
41  
42  
43  
44  
45  
46  
47  
48  
49  
4A  
4B  
4C  
4D  
4E  
4F  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
5A  
5B  
5C  
5D  
5E  
5F  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
6A  
6B  
6C  
6D  
6E  
6F  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
7A  
7B  
7C  
7D  
7E  
7F  
ASC10CR1 81  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
C9  
CA  
CB  
CC  
CD  
CE  
CF  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
DA  
DB  
DC  
DD  
DE  
DF  
E0  
E1  
E2  
E3  
E4  
E5  
E6  
E7  
E8  
E9  
EA  
EB  
EC  
ED  
EE  
EF  
F0  
PRT0GS  
PRT0DM2  
PRT1DR  
PRT1IE  
ASC10CR2 82  
ASC10CR3 83  
ASD11CR0 84  
ASD11CR1 85  
PRT1GS  
PRT1DM2  
PRT2DR  
PRT2IE  
ASD11CR2 86  
ASD11CR3 87  
88  
89  
PRT2GS  
PRT2DM2  
8A  
8B  
8C  
8D  
8E  
8F  
ASD20CR0 90  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
ASD20CR1 91  
12  
13  
14  
15  
16  
17  
18  
19  
1A  
1B  
1C  
1D  
1E  
1F  
20  
21  
22  
23  
24  
25  
26  
27  
ASD20CR2 92  
ASD20CR3 93  
ASC21CR0 94  
ASC21CR1 95  
ASC21CR2 96  
I2C_CFG  
I2C_SCR  
I2C_DR  
RW  
#
ASC21CR3 97  
98  
RW  
#
99  
I2C_MSCR  
INT_CLR0  
INT_CLR1  
9A  
9B  
9C  
9D  
9E  
9F  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
AA  
AB  
AC  
AD  
AE  
AF  
RW  
RW  
INT_CLR3  
INT_MSK3  
RW  
RW  
DBB00DR0  
DBB00DR1  
DBB00DR2  
DBB00CR0  
DBB01DR0  
DBB01DR1  
DBB01DR2  
DBB01CR0  
#
AMX_IN  
RW  
INT_MSK0  
INT_MSK1  
INT_VC  
RW  
RW  
RC  
W
W
RW  
#
ARF_CR  
CMP_CR0  
ASY_CR  
CMP_CR1  
RW  
#
RES_WDT  
DEC_DH  
DEC_DL  
DEC_CR0  
DEC_CR1  
MUL_X  
#
RC  
RC  
RW  
RW  
W
W
RW  
#
#
RW  
DCB02DR0 28  
#
DCB02DR1 29  
W
RW  
#
MUL_Y  
W
DCB02DR2 2A  
MUL_DH  
MUL_DL  
ACC_DR1  
ACC_DR0  
ACC_DR3  
ACC_DR2  
R
DCB02CR0 2B  
R
DCB03DR0 2C  
#
RW  
RW  
RW  
RW  
DCB03DR1 2D  
W
RW  
#
DCB03DR2 2E  
DCB03CR0 2F  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
3A  
3B  
3C  
3D  
3E  
3F  
ACB00CR3  
ACB00CR0  
ACB00CR1  
ACB00CR2  
ACB01CR3  
ACB01CR0  
ACB01CR1  
ACB01CR2  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RDI0RI  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
BA  
BB  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RDI0SYN  
RDI0IS  
F1  
F2  
RDI0LT0  
RDI0LT1  
RDI0RO0  
RDI0RO1  
F3  
F4  
F5  
F6  
CPU_F  
F7  
RL  
F8  
F9  
FA  
FB  
FC  
FD  
FE  
BC  
BD  
BE  
BF  
CPU_SCR1  
#
#
CPU_SCR0 FF  
Blank fields are Reserved and must not be accessed.  
# Access is bit specific.  
Document Number: 38-12028 Rev. *J  
Page 15 of 55  
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CY8C24223A, CY8C24423A  
Table 10. Register Map Bank 1 Table: Configuration Space  
Name  
Addr (1,Hex) Access  
Name  
Addr (1,Hex) Access  
Name  
Addr (1,Hex) Access  
Name  
Addr (1,Hex) Access  
PRT0DM0  
00  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
40  
ASC10CR0  
80  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
C0  
PRT0DM1  
PRT0IC0  
PRT0IC1  
PRT1DM0  
PRT1DM1  
PRT1IC0  
PRT1IC1  
PRT2DM0  
PRT2DM1  
PRT2IC0  
PRT2IC1  
01  
02  
03  
04  
05  
06  
07  
08  
09  
0A  
0B  
0C  
0D  
0E  
0F  
10  
11  
41  
42  
43  
44  
45  
46  
47  
48  
49  
4A  
4B  
4C  
4D  
4E  
4F  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
5A  
5B  
5C  
5D  
5E  
5F  
ASC10CR1  
ASC10CR2  
ASC10CR3  
ASD11CR0  
ASD11CR1  
ASD11CR2  
ASD11CR3  
81  
82  
83  
84  
85  
86  
87  
88  
89  
8A  
8B  
8C  
8D  
8E  
8F  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
9A  
9B  
9C  
9D  
9E  
9F  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
AA  
AB  
AC  
AD  
AE  
AF  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
BA  
BB  
BC  
BD  
BE  
BF  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
C9  
CA  
CB  
CC  
CD  
CE  
CF  
ASD20CR0  
ASD20CR1  
ASD20CR2  
ASD20CR3  
ASC21CR0  
ASC21CR1  
ASC21CR2  
ASC21CR3  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
GDI_O_IN  
GDI_E_IN  
GDI_O_OU  
GDI_E_OU  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
DA  
DB  
DC  
DD  
DE  
DF  
E0  
E1  
E2  
E3  
E4  
E5  
E6  
E7  
E8  
E9  
EA  
EB  
EC  
ED  
EE  
EF  
F0  
F1  
F2  
F3  
F4  
F5  
F6  
F7  
F8  
F9  
FA  
FB  
FC  
FD  
FE  
FF  
RW  
RW  
RW  
RW  
12  
13  
14  
15  
16  
17  
18  
19  
1A  
1B  
1C  
1D  
1E  
1F  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
2A  
2B  
2C  
2D  
2E  
2F  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
3A  
3B  
3C  
3D  
3E  
3F  
OSC_GO_EN  
OSC_CR4  
OSC_CR3  
OSC_CR0  
OSC_CR1  
OSC_CR2  
VLT_CR  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
R
DBB00FN  
DBB00IN  
DBB00OU  
RW  
RW  
RW  
CLK_CR0  
CLK_CR1  
ABF_CR0  
AMD_CR0  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
6A  
6B  
6C  
6D  
6E  
6F  
RW  
RW  
RW  
RW  
DBB01FN  
DBB01IN  
DBB01OU  
RW  
RW  
RW  
VLT_CMP  
AMD_CR1  
ALT_CR0  
RW  
RW  
DCB02FN  
DCB02IN  
DCB02OU  
RW  
RW  
RW  
IMO_TR  
ILO_TR  
BDG_TR  
ECO_TR  
W
W
RW  
W
DCB03FN  
DCB03IN  
DCB03OU  
RW  
RW  
RW  
ACB00CR3 70  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RDI0RI  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
ACB00CR0 71  
RDI0SYN  
RDI0IS  
ACB00CR1 72  
ACB00CR2 73  
RDI0LT0  
RDI0LT1  
RDI0RO0  
RDI0RO1  
ACB01CR3 74  
ACB01CR0 75  
ACB01CR1 76  
ACB01CR2 77  
CPU_F  
RL  
78  
79  
7A  
7B  
7C  
7D  
7E  
7F  
CPU_SCR1  
CPU_SCR0  
#
#
Blank fields are Reserved and must not be accessed.  
# Access is bit specific.  
Document Number: 38-12028 Rev. *J  
Page 16 of 55  
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CY8C24223A, CY8C24423A  
Electrical Specifications  
This section presents the DC and AC electrical specifications of the CY8C24x23A PSoC device. For the latest electrical specifications,  
check if you have the most recent data sheet by visiting the web at http://www.cypress.com/psoc.  
Specifications are valid for -40°C T 85°C and T 100°C, except where noted.  
A
J
Refer to Table 31 on page 31 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.  
Figure 11. Voltage versus CPU Frequency  
Figure 12. IMO Frequency Trim Options  
5.25  
4.75  
5.25  
4.75  
SLIMO  
Mode=1  
SLIMO  
Mode=0  
3.60  
3.00  
2.40  
SLIMO  
Mode=1  
SLIMO  
Mode=0  
3.00  
2.40  
SLIMO SLIMO  
Mode=1 Mode=1  
93 kHz  
12 MHz  
24 MHz  
3 MHz  
CPUFrequency  
93 kHz  
6 MHz  
12 MHz  
24 MHz  
IMOFrequency  
The following table lists the units of measure that are used in this section.  
Table 11. Units of Measure  
Symbol  
Unit of Measure  
degree Celsius  
Symbol  
Unit of Measure  
°C  
μW  
mA  
ms  
mV  
nA  
ns  
microwatts  
dB  
fF  
decibels  
milli-ampere  
milli-second  
milli-volts  
femto farad  
hertz  
Hz  
KB  
Kbit  
kHz  
kΩ  
MHz  
MΩ  
μA  
μF  
1024 bytes  
1024 bits  
nanoampere  
nanosecond  
nanovolts  
kilohertz  
nV  
W
kilohm  
ohm  
megahertz  
megaohm  
pA  
pF  
pp  
ppm  
ps  
picoampere  
picofarad  
microampere  
microfarad  
microhenry  
microsecond  
microvolts  
peak-to-peak  
parts per million  
picosecond  
μH  
μs  
μV  
sps  
s
samples per second  
sigma: one standard deviation  
volts  
μVrms  
microvolts root-mean-square  
V
Document Number: 38-12028 Rev. *J  
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Absolute Maximum Ratings  
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.  
Table 12. Absolute Maximum Ratings  
Symbol  
Description  
Storage Temperature  
Min  
Typ  
Max  
Units  
Notes  
T
-55  
25  
+100  
°C Higher storage temperatures  
reduce data retention time.  
Recommended storage  
STG  
temperature is +25°C ± 25°C.  
Extended duration storage  
temperatures above 65°C  
degrades reliability.  
T
Ambient Temperature with Power Applied  
Supply Voltage on Vdd Relative to Vss  
DC Input Voltage  
-40  
-0.5  
+85  
°C  
V
A
Vdd  
+6.0  
V
Vss - 0.5  
Vdd +  
0.5  
V
IO  
V
DC Voltage Applied to Tri-state  
Vss - 0.5  
Vdd +  
0.5  
V
IOZ  
I
Maximum Current into any Port Pin  
Electro Static Discharge Voltage  
Latch-up Current  
-25  
2000  
+50  
mA  
MIO  
ESD  
LU  
V
Human Body Model ESD.  
200  
mA  
Operating Temperature  
Table 13. Operating Temperature  
Symbol  
Description  
Min  
-40  
-40  
Typ  
Max  
+85  
Units  
Notes  
T
Ambient Temperature  
Junction Temperature  
°C  
A
T
+100  
°C The temperature rise from ambient  
to junction is package specific. See  
Table 50 on page 50. The user must  
limit the power consumption to  
J
comply with this requirement.  
Document Number: 38-12028 Rev. *J  
Page 18 of 55  
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DC Electrical Characteristics  
DC Chip-Level Specifications  
Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  
T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters apply to  
A
A
A
5V, 3.3V, and 2.7V at 25°C and are for design guidance only.  
Table 14. DC Chip-Level Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
Vdd  
Supply Voltage  
Supply Current  
2.4  
5.25  
V
See DC POR and LVD specifications,  
Table 29 on page 29.  
I
I
I
5
3.3  
2
8
6.0  
4
mA Conditions are Vdd = 5.0V, T = 25°C,  
DD  
A
CPU = 3 MHz, SYSCLK doubler  
disabled, VC1 = 1.5 MHz,  
VC2 = 93.75 kHz, VC3 = 93.75 kHz,  
analog power = off.  
SLIMO mode = 0. IMO = 24 MHz.  
Supply Current  
Supply Current  
mA Conditions are Vdd = 3.3V, T = 25 °C,  
DD3  
DD27  
A
CPU = 3 MHz, SYSCLK doubler  
disabled, VC1 = 1.5 MHz,  
VC2 = 93.75 kHz, VC3 = 93.75 kHz,  
analog power = off. SLIMO mode = 0.  
IMO = 24 MHz.  
mA Conditions are Vdd = 2.7V, T = 25°C,  
A
CPU = 0.75 MHz, SYSCLK doubler  
disabled, VC1 = 0.375 MHz,  
VC2 = 23.44 kHz, VC3 = 0.09 kHz,  
analog power = off. SLIMO mode = 1.  
IMO = 6 MHz.  
I
I
I
Sleep (Mode) Current with POR, LVD, Sleep  
Timer, and WDT.  
3
4
4
6.5  
25  
μA Conditions are with internal slow  
speed oscillator, Vdd = 3.3V, -40°C ≤  
SB  
[3]  
T 55°C, analog power = off.  
A
Sleep (Mode) Current with POR, LVD, Sleep  
μA Conditions are with internal slow  
SBH  
SBXTL  
[3]  
Timer, and WDT at high temperature.  
speedoscillator, Vdd=3.3V, 5C<T  
A
85°C, analog power = off.  
Sleep (Mode) Current with POR, LVD, Sleep  
7.5  
μA Conditions are with properly loaded,  
1 μW max, 32.768 kHz crystal.  
[3]  
Timer, WDT, and external crystal.  
Vdd = 3.3V, -40°C T 55°C, analog  
A
power = off.  
I
Sleep (Mode) Current with POR, LVD, Sleep  
Timer, WDT, and external crystal at high  
temperature.  
5
26  
μA Conditions are with properly loaded,  
1μW max, 32.768 kHz crystal.  
SBXTLH  
[3]  
Vdd = 3.3 V, 55°C < T 85°C, analog  
A
power = off.  
V
V
Reference Voltage (Bandgap)  
Reference Voltage (Bandgap)  
1.28  
1.16  
1.30  
1.30  
1.33  
1.33  
V
V
Trimmed for appropriate Vdd.  
Vdd > 3.0V  
REF  
Trimmed for appropriate Vdd.  
Vdd = 2.4V to 3.0V  
REF27  
Note  
3. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar  
functions enabled.  
Document Number: 38-12028 Rev. *J  
Page 19 of 55  
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DC General Purpose IO Specifications  
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters  
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.  
Table 15. 5V and 3.3V DC GPIO Specifications  
Symbol  
Description  
Min  
Typ  
5.6  
5.6  
Max  
Units  
kΩ  
kΩ  
Notes  
R
Pull up Resistor  
4
4
8
8
PU  
R
Pull down Resistor  
High Output Level  
PD  
V
Vdd - 1.0  
V
IOH = 10 mA, Vdd = 4.75 to 5.25V  
(maximum 40 mA on even port pins  
(for example, P0[2], P1[4]),  
OH  
maximum 40 mA on odd port pins  
(for example, P0[3], P1[5])). 80 mA  
maximum combined IOH budget.  
V
Low Output Level  
0.75  
V
IOL = 25 mA, Vdd = 4.75 to 5.25V  
(maximum 100 mA on even port  
pins (for example, P0[2], P1[4]),  
maximum 100 mA on odd port pins  
(for example, P0[3], P1[5])). 150  
mA maximum combined IOL  
budget.  
OL  
V
V
V
I
Input Low Level  
2.1  
0.8  
V
V
Vdd = 3.0 to 5.25  
Vdd = 3.0 to 5.25  
IL  
IH  
H
Input High Level  
Input Hysterisis  
60  
1
mV  
Input Leakage (Absolute Value)  
Capacitive Load on Pins as Input  
nA Gross tested to 1 μA  
pF Package and pin dependent.  
Temp = 25°C  
IL  
C
3.5  
10  
IN  
C
Capacitive Load on Pins as Output  
3.5  
10  
pF Package and pin dependent.  
Temp = 25°C  
OUT  
Table 16. 2.7V DC GPIO Specifications  
Symbol  
Description  
Min  
Typ  
5.6  
5.6  
Max  
Units  
Notes  
R
Pull up Resistor  
4
4
8
8
kΩ  
kΩ  
V
PU  
R
Pull down Resistor  
High Output Level  
PD  
V
Vdd - 0.4  
IOH = 2 mA (6.25 Typ), Vdd = 2.4  
to 3.0V (16 mA maximum, 50 mA  
Typ combined IOH budget).  
OH  
V
Low Output Level  
0.75  
V
IOL = 11.25 mA, Vdd = 2.4 to 3.0V  
(90 mA maximum combined IOL  
budget).  
OL  
V
V
V
I
Input Low Level  
2.0  
0.75  
V
V
Vdd = 2.4 to 3.0  
Vdd = 2.4 to 3.0  
IL  
IH  
H
Input High Level  
Input Hysteresis  
90  
1
mV  
Input Leakage (Absolute Value)  
Capacitive Load on Pins as Input  
nA Gross tested to 1 μA  
pF Package and pin dependent.  
IL  
C
3.5  
10  
IN  
o
Temp = 25 C  
C
Capacitive Load on Pins as Output  
3.5  
10  
pF Package and pin dependent.  
OUT  
o
Temp = 25 C  
Document Number: 38-12028 Rev. *J  
Page 20 of 55  
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CY8C24123A  
CY8C24223A, CY8C24423A  
DC Operational Amplifier Specifications  
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters  
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.  
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC  
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at  
25°C and are for design guidance only.  
Table 17. 5V DC Operational Amplifier Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
V
Input Offset Voltage (absolute value)  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
OSOA  
1.6  
1.3  
1.2  
10  
8
7.5  
mV  
mV  
mV  
TCV  
Average Input Offset Voltage Drift  
7.0  
20  
35.0  
μV/°C  
OSOA  
I
Input Leakage Current (Port 0 Analog Pins)  
Input Capacitance (Port 0 Analog Pins)  
pA Gross tested to 1 μA  
pF Package and pin dependent.  
Temp = 25°C  
EBOA  
C
4.5  
9.5  
INOA  
V
Common Mode Voltage Range  
Common Mode Voltage Range (high power or  
high opamp bias)  
0.0  
0.5  
Vdd  
Vdd - 0.5  
V
The common-mode input voltage  
range is measured through an  
analog output buffer. The  
specification includes the  
limitations imposed by the  
characteristics of the analog  
output buffer.  
CMOA  
G
Open Loop Gain  
dB Specification is applicable at high  
power. For all other bias modes  
(except high power, high opamp  
bias), minimum is 60 dB.  
OLOA  
OHIGHOA  
OLOWOA  
SOA  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
60  
60  
80  
V
V
High Output Voltage Swing (internal signals)  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
Vdd - 0.2  
Vdd - 0.2  
Vdd - 0.5  
V
V
V
Low Output Voltage Swing (internal signals)  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = High  
0.2  
0.2  
0.5  
V
V
V
Power = High, Opamp Bias = High  
I
Supply Current (including associated AGND  
buffer)  
Power = Low, Opamp Bias = High  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = High  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
Power = High, Opamp Bias = High  
150  
300  
600  
1200  
2400  
4600  
200  
400  
800  
1600  
3200  
6400  
μA  
μA  
μA  
μA  
μA  
μA  
PSRR  
Supply Voltage Rejection Ratio  
64  
80  
dB Vss VIN (Vdd - 2.25) or  
(Vdd - 1.25V) VIN Vdd  
OA  
Document Number: 38-12028 Rev. *J  
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CY8C24123A  
CY8C24223A, CY8C24423A  
Table 18. 3.3V DC Operational Amplifier Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
V
Input Offset Voltage (absolute value)  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = High  
High Power is 5 Volts Only  
OSOA  
1.65  
1.32  
10  
8
mV  
mV  
TCV  
Average Input Offset Voltage Drift  
7.0  
20  
35.0  
μV/°C  
OSOA  
I
Input Leakage Current (Port 0 Analog Pins)  
Input Capacitance (Port 0 Analog Pins)  
pA Gross tested to 1 μA  
EBOA  
C
4.5  
9.5  
pF Package and pin dependent.  
Temp = 25°C  
INOA  
V
Common Mode Voltage Range  
0.2  
Vdd - 0.2  
V
The common-mode input voltage  
range is measured through an  
analog output buffer. The  
specification includes the  
limitations imposed by the  
characteristics of the analog  
output buffer.  
CMOA  
G
Open Loop Gain  
dB Specification is applicable at high  
power. For all other bias modes  
(except high power, high opamp  
bias), minimum is 60 dB.  
OLOA  
OHIGHOA  
OLOWOA  
SOA  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = Low  
Power = High, Opamp Bias = Low  
60  
60  
80  
V
V
High Output Voltage Swing (internal signals)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = Low  
Power = High is 5V only  
Vdd - 0.2  
Vdd - 0.2  
Vdd - 0.2  
V
V
V
Low Output Voltage Swing (internal signals)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = Low  
0.2  
0.2  
0.2  
V
V
V
Power = High, Opamp Bias = Low  
I
Supply Current (including associated AGND  
buffer)  
Power = Low, Opamp Bias = Low  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = Low  
Power = High, Opamp Bias = High  
150  
300  
600  
1200  
2400  
4600  
200  
400  
800  
1600  
3200  
6400  
μA  
μA  
μA  
μA  
μA  
μA  
PSRR  
Supply Voltage Rejection Ratio  
64  
80  
dB Vss VIN (Vdd - 2.25) or  
(Vdd - 1.25V) VIN Vdd  
OA  
Document Number: 38-12028 Rev. *J  
Page 22 of 55  
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Table 19. 2.7V DC Operational Amplifier Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
V
Input Offset Voltage (absolute value)  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = High  
High Power is 5 Volts Only  
OSOA  
1.65  
1.32  
10  
8
mV  
mV  
TCV  
Average Input Offset Voltage Drift  
7.0  
20  
35.0  
μV/°C  
OSOA  
I
Input Leakage Current (Port 0 Analog Pins)  
Input Capacitance (Port 0 Analog Pins)  
pA Gross tested to 1 μA  
EBOA  
C
4.5  
9.5  
pF Package and pin dependent.  
Temp = 25°C  
INOA  
V
Common Mode Voltage Range  
0.2  
Vdd - 0.2  
V
The common-mode input voltage  
range is measured through an  
analog output buffer. The  
specification includes the  
limitations imposed by the  
characteristics of the analog output  
buffer.  
CMOA  
G
Open Loop Gain  
dB Specification is applicable at high  
power. For all other bias modes  
(except high power, high opamp  
bias), minimum is 60 dB.  
OLOA  
OHIGHOA  
OLOWOA  
SOA  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = Low  
Power = High  
60  
60  
80  
V
V
High Output Voltage Swing (internal signals)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = Low  
Power = High is 5V only  
Vdd - 0.2  
Vdd - 0.2  
Vdd - 0.2  
V
V
V
Low Output Voltage Swing (internal signals)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = Low  
0.2  
0.2  
0.2  
V
V
V
Power = High, Opamp Bias = Low  
I
Supply Current (including associated AGND  
buffer)  
Power = Low, Opamp Bias = Low  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = Low  
Power = High, Opamp Bias = High  
150  
300  
600  
1200  
2400  
4600  
200  
400  
800  
1600  
3200  
6400  
μA  
μA  
μA  
μA  
μA  
μA  
PSRR  
Supply Voltage Rejection Ratio  
64  
80  
dB Vss VIN (Vdd - 2.25) or  
(Vdd - 1.25V) VIN Vdd  
OA  
DC Low Power Comparator Specifications  
Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  
T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters apply to  
A
A
A
5V at 25°C and are for design guidance only.  
Table 20. DC Low Power Comparator Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
V
Low power comparator (LPC) reference  
voltage range  
0.2  
Vdd - 1  
V
REFLPC  
I
LPC supply current  
LPC voltage offset  
10  
40  
30  
μA  
mV  
SLPC  
V
2.5  
OSLPC  
Document Number: 38-12028 Rev. *J  
Page 23 of 55  
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DC Analog Output Buffer Specifications  
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters  
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.  
Table 21. 5V DC Analog Output Buffer Specifications  
Symbol  
Description  
Min  
Typ  
3
Max  
12  
Units  
mV  
Notes  
V
Input Offset Voltage (Absolute Value)  
Average Input Offset Voltage Drift  
Common-Mode Input Voltage Range  
OSOB  
TCV  
+6  
μV/°C  
V
OSOB  
CMOB  
V
0.5  
Vdd - 1.0  
R
Output Resistance  
Power = Low  
Power = High  
OUTOB  
1
1
W
W
V
V
High Output Voltage Swing (Load = 32 ohms  
to Vdd/2)  
Power = Low  
Power = High  
OHIGHOB  
OLOWOB  
SOB  
0.5 x Vdd + 1.1  
0.5 x Vdd + 1.1  
V
V
Low Output Voltage Swing (Load = 32 ohms  
to Vdd/2)  
Power = Low  
Power = High  
.5 x Vdd - 1.3  
0.5 x Vdd - 1.3  
V
V
I
Supply Current Including Bias Cell (No Load)  
Power = Low  
Power = High  
1.1  
2.6  
5.1  
8.8  
mA  
mA  
PSRR  
Supply Voltage Rejection Ratio  
52  
64  
dB  
V
> (Vdd - 1.25).  
OB  
OUT  
Table 22. 3.3V DC Analog Output Buffer Specifications  
Symbol  
Description  
Min  
Typ  
3
Max  
12  
Units  
mV  
Notes  
V
Input Offset Voltage (Absolute Value)  
Average Input Offset Voltage Drift  
Common-Mode Input Voltage Range  
OSOB  
TCV  
+6  
-
μV/°C  
V
OSOB  
V
0.5  
Vdd - 1.0  
CMOB  
R
Output Resistance  
Power = Low  
Power = High  
OUTOB  
1
1
W
W
V
High Output Voltage Swing (Load = 1k ohms  
to Vdd/2)  
Power = Low  
Power = High  
OHIGHOB  
OLOWOB  
SOB  
0.5 x Vdd + 1.0  
0.5 x Vdd + 1.0  
V
V
V
Low Output Voltage Swing (Load = 1k ohms  
to Vdd/2)  
Power = Low  
Power = High  
0.5 x Vdd - 1.0  
0.5 x Vdd - 1.0  
V
V
I
Supply Current Including Bias Cell (No Load)  
Power = Low  
0.8  
2.0  
2.0  
4.3  
mA  
mA  
Power = High  
PSRR  
Supply Voltage Rejection Ratio  
52  
64  
dB  
V
> (Vdd - 1.25)  
OB  
OUT  
Document Number: 38-12028 Rev. *J  
Page 24 of 55  
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Table 23. 2.7V DC Analog Output Buffer Specifications  
Symbol  
Description  
Min  
Typ  
3
Max  
12  
Units  
mV  
Notes  
V
Input Offset Voltage (Absolute Value)  
Average Input Offset Voltage Drift  
Common-Mode Input Voltage Range  
OSOB  
TCV  
+6  
-
μV/°C  
V
OSOB  
CMOB  
V
0.5  
Vdd - 1.0  
R
Output Resistance  
Power = Low  
Power = High  
OUTOB  
1
1
W
W
V
V
High Output Voltage Swing (Load = 1k ohms  
to Vdd/2)  
Power = Low  
Power = High  
OHIGHOB  
OLOWOB  
SOB  
V
V
0.5 x Vdd + 0.2  
0.5 x Vdd + 0.2  
Low Output Voltage Swing (Load = 1k ohms  
to Vdd/2)  
Power = Low  
Power = High  
V
V
0.5 x Vdd - 0.7  
0.5 x Vdd - 0.7  
I
Supply Current Including Bias Cell (No Load)  
Power = Low  
Power = High  
0.8  
2.0  
2.0  
4.3  
mA  
mA  
PSRR  
Supply Voltage Rejection Ratio  
52  
64  
dB  
V
> (Vdd - 1.25).  
OB  
OUT  
DC Switch Mode Pump Specifications  
Table 24 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  
T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters apply to  
A
A
A
5V, 3.3V, and 2.7V at 25°C and are for design guidance only.  
Table 24. DC Switch Mode Pump (SMP) Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
a
V
V
V
5V  
3V  
2V  
5V Output Voltage from Pump  
4.75  
5.0  
5.25  
V
Configuration listed in footnote.  
PUMP  
PUMP  
PUMP  
PUMP  
Average, neglecting ripple. SMP  
trip voltage is set to 5.0V.  
a
3.3V Output Voltage from Pump  
2.6V Output Voltage from Pump  
Available Output Current  
3.00  
2.45  
3.25  
2.55  
3.60  
2.80  
V
V
Configuration listed in footnote.  
Average, neglecting ripple. SMP  
trip voltage is set to 3.25V.  
a
Configuration listed in footnote.  
Average, neglecting ripple. SMP  
trip voltage is set to 2.55V.  
a
I
Configuration listed in footnote.  
V
V
V
= 1.8V, V  
= 1.5V, V  
= 1.3V, V  
= 5.0V  
= 3.25V  
= 2.55V  
5
8
8
mA  
mA  
mA  
SMP trip voltage is set to 5.0V.  
SMP trip voltage is set to 3.25V.  
SMP trip voltage is set to 2.55V.  
BAT  
BAT  
BAT  
PUMP  
PUMP  
PUMP  
a
V
V
V
V
5V  
Input Voltage Range from Battery  
Input Voltage Range from Battery  
Input Voltage Range from Battery  
1.8  
1.0  
1.0  
1.2  
5.0  
3.3  
3.0  
V
V
V
V
Configuration listed in footnote.  
SMP trip voltage is set to 5.0V.  
BAT  
BAT  
BAT  
a
3V  
2V  
Configuration listed in footnote.  
SMP trip voltage is set to 3.25V.  
a
Configuration listed in footnote.  
SMP trip voltage is set to 2.55V.  
a
Minimum Input Voltage from Battery to  
Start Pump  
Configuration listed in footnote.  
BATSTART  
0°C T 100. 1.25V at  
A
T = -40°C  
A
Document Number: 38-12028 Rev. *J  
Page 25 of 55  
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Table 24. DC Switch Mode Pump (SMP) Specifications (continued)  
Symbol  
Description  
Line Regulation (over V  
Min  
Typ  
Max  
Units  
Notes  
[4]  
ΔV  
ΔV  
ΔV  
range)  
5
%V  
Configuration listed in footnote.  
PUMP_Line  
BAT  
O
V
is the “Vdd Value for PUMP  
O
Trip” specified by the VM[2:0]  
setting in the DC POR and LVD  
Specification, Table 29 on page 29.  
[4]  
Load Regulation  
5
%V  
Configuration listed in footnote.  
PUMP_Load  
O
V
is the “Vdd Value for PUMP  
O
Trip” specified by the VM[2:0]  
setting in the DC POR and LVD  
Specification, Table 29 on page 29.  
[4]  
Output Voltage Ripple (depends on  
capacitor/load)  
100  
50  
mVpp Configuration listed in footnote.  
Load is 5 mA.  
PUMP_Ripple  
[4]  
E
Efficiency  
35  
%
Configuration listed in footnote.  
3
Load is 5 mA. SMP trip voltage is  
set to 3.25V.  
E
Efficiency  
2
F
Switching Frequency  
Switching Duty Cycle  
1.3  
50  
MHz  
%
PUMP  
DC  
PUMP  
Figure 13. Basic Switch Mode Pump Circuit  
D1  
Vdd  
VPUMP  
L1  
SMP  
+
VBAT  
Battery  
PSoC  
C1  
Vss  
Note  
4.  
L
= 2 mH inductor, C = 10 mF capacitor, D = Schottky diode. See Figure 13.  
1 1  
1
Document Number: 38-12028 Rev. *J  
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DC Analog Reference Specifications  
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters  
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.  
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to  
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control  
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.  
Reference control power is high.  
Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling  
of the digital signal may appear on the AGND.  
Table 25. 5V DC Analog Reference Specifications  
Symbol  
Description  
Bandgap Voltage Reference  
AGND = Vdd/2  
Min  
1.28  
Typ  
1.30  
Max  
1.33  
Units  
BG  
V
V
V
V
V
V
V
Vdd/2 - 0.04  
2 x BG - 0.048  
P2[4] - 0.011  
BG - 0.009  
1.6 x BG - 0.022  
-0.034  
Vdd/2 - 0.01  
2 x BG - 0.030  
P2[4]  
Vdd/2 + 0.007  
2 x BG + 0.024  
P2[4] + 0.011  
BG + 0.016  
1.6 x BG + 0.018  
0.034  
AGND = 2 x BandGap  
AGND = P2[4] (P2[4] = Vdd/2)  
AGND = BandGap  
BG + 0.008  
1.6 x BG - 0.010  
0.000  
AGND = 1.6 x BandGap  
AGND Block to Block Variation  
(AGND = Vdd/2)  
RefHi = Vdd/2 + BandGap  
RefHi = 3 x BandGap  
Vdd/2 + BG - 0.10  
3 x BG - 0.06  
Vdd/2 + BG  
3 x BG  
Vdd/2 + BG + 0.10  
3 x BG + 0.06  
V
V
V
V
V
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) 2 x BG + P2[6] - 0.113 2 x BG + P2[6] - 0.018 2 x BG + P2[6] + 0.077  
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)  
P2[4] + BG - 0.130  
P2[4] + BG - 0.016  
P2[4] + BG + 0.098  
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2  
P2[6] = 1.3V)  
P2[4] + P2[6] - 0.133 P2[4] + P2[6] - 0.016 P2[4] + P2[6]+ 0.100  
RefHi = 3.2 x BandGap  
RefLo = Vdd/2 – BandGap  
RefLo = BandGap  
3.2 x BG - 0.112  
Vdd/2 - BG - 0.04  
BG - 0.06  
3.2 x BG  
Vdd/2 - BG + 0.024  
BG  
3.2 x BG + 0.076  
Vdd/2 - BG + 0.04  
BG + 0.06  
V
V
V
V
V
V
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2 x BG - P2[6] - 0.084 2 x BG - P2[6] + 0.025 2 x BG - P2[6] + 0.134  
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)  
P2[4] - BG - 0.056  
P2[4] - BG + 0.026  
P2[4] - BG + 0.107  
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2,  
P2[6] = 1.3V)  
P2[4] - P2[6] - 0.057 P2[4] - P2[6] + 0.026 P2[4] - P2[6] + 0.110  
Table 26. 3.3V DC Analog Reference Specifications  
Symbol  
Description  
Bandgap Voltage Reference  
AGND = Vdd/2  
Min  
1.28  
Typ  
1.30  
Max  
1.33  
Units  
BG  
V
V
Vdd/2 - 0.03  
Vdd/2 - 0.01  
Vdd/2 + 0.005  
AGND = 2 x BandGap  
AGND = P2[4] (P2[4] = Vdd/2)  
AGND = BandGap  
Not Allowed  
P2[4] - 0.008  
BG - 0.009  
P2[4] + 0.001  
BG + 0.005  
1.6 x BG - 0.010  
0.000  
P2[4] + 0.009  
BG + 0.015  
1.6 x BG + 0.018  
0.034  
V
V
AGND = 1.6 x BandGap  
1.6 x BG - 0.027  
-0.034  
V
AGND Column to Column Variation  
(AGND = Vdd/2)  
mV  
RefHi = Vdd/2 + BandGap  
Not Allowed  
Not Allowed  
Not Allowed  
Not Allowed  
RefHi = 3 x BandGap  
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)  
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)  
Document Number: 38-12028 Rev. *J  
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Table 26. 3.3V DC Analog Reference Specifications (continued)  
Symbol  
Description  
Min  
Typ  
Max  
Units  
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,  
P2[6] = 0.5V)  
P2[4] + P2[6] - 0.075 P2[4] + P2[6] - 0.009 P2[4] + P2[6] + 0.057  
V
RefHi = 3.2 x BandGap  
Not Allowed  
RefLo = Vdd/2 - BandGap  
Not Allowed  
RefLo = BandGap  
Not Allowed  
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)  
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)  
Not Allowed  
Not Allowed  
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2,  
P2[6] = 0.5V)  
P2[4] - P2[6] - 0.048 P2[4]- P2[6] + 0.022 P2[4] - P2[6] + 0.092  
V
Table 27. 2.7V DC Analog Reference Specifications  
Symbol  
Description  
Bandgap Voltage Reference  
AGND = Vdd/2  
Min  
1.16  
Typ  
1.30  
Max  
1.33  
Units  
BG  
V
V
Vdd/2 - 0.03  
Vdd/2 - 0.01  
Vdd/2 + 0.01  
AGND = 2 x BandGap  
AGND = P2[4] (P2[4] = Vdd/2)  
AGND = BandGap  
Not Allowed  
P2[4] - 0.01  
BG - 0.01  
P2[4]  
P2[4] + 0.01  
BG + 0.015  
V
V
BG  
AGND = 1.6 x BandGap  
Not Allowed  
0.000  
AGND Column to Column Variation  
(AGND = Vdd/2)  
-0.034  
0.034  
mV  
RefHi = Vdd/2 + BandGap  
Not Allowed  
Not Allowed  
Not Allowed  
Not Allowed  
RefHi = 3 x BandGap  
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)  
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)  
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,  
P2[6] = 0.5V)  
P2[4] + P2[6] - 0.08 P2[4] + P2[6] - 0.01 P2[4] + P2[6] + 0.06  
V
RefHi = 3.2 x BandGap  
Not Allowed  
Not Allowed  
Not Allowed  
Not Allowed  
Not Allowed  
RefLo = Vdd/2 - BandGap  
RefLo = BandGap  
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)  
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)  
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2,  
P2[6] = 0.5V)  
P2[4] - P2[6] - 0.05  
P2[4]- P2[6] + 0.01  
P2[4] - P2[6] + 0.09  
V
Document Number: 38-12028 Rev. *J  
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DC Analog PSoC Block Specifications  
Table 29 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  
T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters apply to  
A
A
A
5V, 3.3V, and 2.7V at 25°C and are for design guidance only.  
Table 28. DC Analog PSoC Block Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
kΩ  
fF  
Notes  
R
Resistor Unit Value (Continuous Time)  
Capacitor Unit Value (Switched Capacitor)  
12.2  
80  
CT  
SC  
C
DC POR, SMP, and LVD Specifications  
Table 30 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  
T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters apply to  
A
A
A
5V, 3.3V, and 2.7V at 25°C and are for design guidance only.  
Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Programmable Sytem-on-Chip  
Technical Reference Manual for more information on the VLT_CR register.  
Table 29. DC POR and LVD Specifications  
Symbol  
Description  
Vdd Value for PPOR Trip  
PORLEV[1:0] = 00b  
PORLEV[1:0] = 01b  
PORLEV[1:0] = 10b  
Min  
Typ  
Max  
Units  
Notes  
Vdd must be greater than  
or equal to 2.5V during  
startup, reset from the  
XRES pin, or reset from  
Watchdog.  
V
2.36  
2.82  
4.55  
2.40  
2.95  
4.70  
V
V
V
PPOR0  
PPOR1  
PPOR2  
V
V
Vdd Value for LVD Trip  
VM[2:0] = 000b  
VM[2:0] = 001b  
VM[2:0] = 010b  
VM[2:0] = 011b  
VM[2:0] = 100b  
VM[2:0] = 101b  
VM[2:0] = 110b  
VM[2:0] = 111b  
0
[5]  
0
V
V
V
V
V
V
V
V
2.40  
2.85  
2.95  
3.06  
4.37  
4.50  
4.62  
4.71  
2.45  
2.92  
2.51  
2.99  
V
LVD0  
LVD1  
LVD2  
LVD3  
LVD4  
LVD5  
LVD6  
LVD7  
0
[6]  
0
V
0
3.02  
3.13  
4.48  
4.64  
4.73  
4.81  
3.09  
3.20  
4.55  
4.75  
4.83  
4.95  
V
0
V
0
V
V
V
V
Vdd Value for SMP Trip  
VM[2:0] = 000b  
VM[2:0] = 001b  
VM[2:0] = 010b  
VM[2:0] = 011b  
VM[2:0] = 100b  
VM[2:0] = 101b  
VM[2:0] = 110b  
VM[2:0] = 111b  
0
0
[7]  
V
V
V
V
V
V
V
V
2.50  
2.96  
3.03  
3.18  
4.54  
4.62  
4.71  
4.89  
2.55  
3.02  
3.10  
2.62  
3.09  
3.16  
V
PUMP0  
PUMP1  
PUMP2  
PUMP3  
PUMP4  
PUMP5  
PUMP6  
PUMP7  
0
V
0
V
0
[8]  
0
3.25  
4.64  
4.73  
4.82  
5.00  
3.32  
4.74  
4.83  
4.92  
5.12  
V
0
V
V
V
V
Notes  
5. Always greater than 50 mV above V  
6. Always greater than 50 mV above V  
(PORLEV=00) for falling supply.  
(PORLEV=01) for falling supply.  
PPOR  
7. Always greater than 50 mV aboPvPeOVR  
8. Always greater than 50 mV above V  
.
LVD0  
.
LVD3  
Document Number: 38-12028 Rev. *J  
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DC Programming Specifications  
Table 31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  
T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters apply to  
A
A
A
5V, 3.3V, and 2.7V at 25°C and are for design guidance only.  
Table 30. DC Programming Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
Vdd  
Supply Voltage for Flash Write Operations  
2.70  
V
IWRIT  
E
I
Supply Current During Programming or Verify  
Input Low Voltage During Programming or Verify  
Input High Voltage During Programming or Verify  
5
25  
0.8  
mA  
V
DDP  
V
V
ILP  
2.1  
V
IHP  
I
Input Current when Applying Vilp to P1[0] or P1[1]  
During Programming or Verify  
0.2  
mA  
Drivinginternalpulldown  
resistor.  
ILP  
I
InputCurrentwhenApplyingVihptoP1[0]orP1[1]  
During Programming or Verify  
1.5  
mA  
Drivinginternalpulldown  
resistor.  
IHP  
V
V
Output Low Voltage During Programming or Verify  
Vss + 0.75  
Vdd  
V
V
OLV  
Output High Voltage During Programming or  
Verify  
Vdd - 1.0  
OHV  
Flash  
Flash Endurance (per block)  
50,000  
Erase/write cycles per  
block  
ENP  
B
[9]  
Flash  
Flash Endurance (total)  
1,800,000  
10  
Erase/write cycles  
ENT  
DR  
Flash  
Flash Data Retention  
Years  
Note  
9. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2  
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block  
ever sees more than 50,000 cycles).  
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.  
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.  
Document Number: 38-12028 Rev. *J  
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AC Electrical Characteristics  
AC Chip-Level Specifications  
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters  
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.  
Table 31. 5V and 3.3V AC Chip-Level Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
[10,11,12]  
F
F
Internal Main Oscillator Frequency for  
24 MHz  
23.4  
24  
24.6  
MHz Trimmed for 5V or 3.3V operation  
usingfactorytrimvalues. SeeFigure  
12 on page 17. SLIMO mode = 0.  
IMO24  
[10,11,12]  
Internal Main Oscillator Frequency for  
6 MHz  
5.75  
6
6.35  
MHz Trimmed for 5V or 3.3V operation  
usingfactorytrimvalues. SeeFigure  
12 on page 17. SLIMO mode = 1.  
IMO6  
[10,11]  
F
F
F
CPU Frequency (5V Nominal)  
CPU Frequency (3.3V Nominal)  
Digital PSoC Block Frequency  
0.93  
0.93  
0
24  
12  
48  
24.6  
MHz  
MHz  
CPU1  
CPU2  
48M  
[11,12]  
12.3  
[10,11,13]  
49.2  
MHz Refer to the AC Digital Block  
Specifications.  
[11,13]  
F
F
Digital PSoC Block Frequency  
0
24  
32  
24.6  
MHz  
kHz  
24M  
Internal Low Speed Oscillator  
Frequency  
15  
64  
32K1  
F
F
External Crystal Oscillator  
32.768  
23.986  
kHz Accuracy is capacitor and crystal  
dependent. 50% duty cycle.  
32K2  
PLL  
PLL Frequency  
MHz Is a multiple (x732) of crystal  
frequency.  
Jitter24M2 24 MHz Period Jitter (PLL)  
600  
10  
ps  
ms  
ms  
T
T
PLL Lock Time  
0.5  
0.5  
PLLSLEW  
PLL Lock Time for Low Gain Setting  
50  
PLLSLEWSL  
OW  
T
T
External Crystal Oscillator Startup to 1%  
1700  
2800  
2620  
3800  
ms  
OS  
External Crystal Oscillator Startup to  
100 ppm  
ms The crystal oscillator frequency is  
within 100 ppm of its final value by  
OSACC  
the end of the T  
period. Correct  
osacc  
operation assumes a properly  
loaded 1 uW maximum drive level  
32.768 kHz crystal. 3.0V Vdd ≤  
5.5V, -40 oC TA 85 oC.  
Jitter32k  
32 kHz Period Jitter  
10  
40  
100  
ns  
μs  
%
T
External Reset Pulse Width  
24 MHz Duty Cycle  
60  
XRST  
DC24M  
50  
Step24M  
Fout48M  
24 MHz Trim Step Size  
48 MHz Output Frequency  
50  
kHz  
[10,12]  
46.8  
48.0  
300  
49.2  
MHz Trimmed. Using factory trim values.  
ps  
Jitter24M1P 24 MHz Period Jitter (IMO)  
Peak-to-Peak  
Jitter24M1R 24 MHz Period Jitter (IMO) Root Mean  
Squared  
0
600  
12.3  
ps  
MHz  
μs  
F
Maximum frequency of signal on row  
input or row output.  
MAX  
T
Supply Ramp Time  
RAMP  
Notes  
10. 4.75V < Vdd < 5.25V.  
11. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.  
12. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation  
at 3.3V.  
13. See the individual user module data sheets for information on maximum frequencies for user modules.  
Document Number: 38-12028 Rev. *J  
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Table 32. 2.7V AC Chip-Level Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
[14,15,16]  
F
F
Internal Main Oscillator Frequency for  
12 MHz  
11.5  
12  
12.7  
MHz Trimmed for 2.7V operation using  
factory trim values. See Figure 12 on  
page 17. SLIMO mode = 1.  
IMO12  
[14,15,16]  
Internal Main Oscillator Frequency for 6  
MHz  
5.75  
6
6.35  
12.7  
MHz Trimmed for 2.7V operation using  
factory trim values. See Figure 12 on  
page 17. SLIMO mode = 1.  
IMO6  
0
0
0
[14,15]  
0
F
F
CPU Frequency (2.7V Nominal)  
0.93  
0
3
3.15  
MHz  
CPU1  
[14,15,16]  
0
Digital PSoC Block Frequency (2.7V  
Nominal)  
12  
MHz Refer to the AC Digital Block  
BLK27  
Specifications.  
F
Internal Low Speed Oscillator  
Frequency  
8
32  
96  
kHz  
32K1  
Jitter32k  
32 kHz Period Jitter  
10  
40  
150  
ns  
μs  
%
T
External Reset Pulse Width  
12 MHz Duty Cycle  
XRST  
DC12M  
50  
60  
Jitter12M1P  
12 MHz Period Jitter (IMO)  
Peak-to-Peak  
340  
ps  
Jitter12M1R  
12 MHz Period Jitter (IMO) Root Mean  
Squared  
0
600  
ps  
MHz  
μs  
F
T
Maximum frequency of signal on row  
input or row output.  
12.7  
MAX  
Supply Ramp Time  
RAMP  
Notes  
14. 2.4V < Vdd < 3.0V.  
15. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.  
16. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum frequency for User Modules.  
Document Number: 38-12028 Rev. *J  
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Figure 14. PLL Lock Timing Diagram  
PLL  
Enable  
T
24 MHz  
PLLSLEW  
FPLL  
PLL  
Gain  
0
Figure 15. PLL Lock for Low Gain Setting Timing Diagram  
PLL  
Enable  
T
24 MHz  
PLLSLEWLOW  
FPLL  
PLL  
Gain  
1
Figure 16. External Crystal Oscillator Startup Timing Diagram  
32K  
Select  
32 kHz  
T
OS  
F32K2  
Figure 17. 24 MHz Period Jitter (IMO) Timing Diagram  
Jitter24M1  
F24M  
Figure 18. 32 kHz Period Jitter (ECO) Timing Diagram  
Jitter32k  
F32K2  
Document Number: 38-12028 Rev. *J  
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AC General Purpose IO Specifications  
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters  
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.  
Table 33. 5V and 3.3V AC GPIO Specifications  
Symbol  
Description  
Min  
0
Typ  
Max  
12  
18  
18  
Units  
Notes  
F
GPIO Operating Frequency  
MHz Normal Strong Mode  
GPIO  
TRiseF  
Rise Time, Normal Strong Mode, Cload = 50 pF  
Fall Time, Normal Strong Mode, Cload = 50 pF  
Rise Time, Slow Strong Mode, Cload = 50 pF  
Fall Time, Slow Strong Mode, Cload = 50 pF  
3
ns  
ns  
ns  
ns  
Vdd = 4.5 to 5.25V, 10% - 90%  
TFallF  
TRiseS  
TFallS  
2
Vdd = 4.5 to 5.25V, 10% - 90%  
Vdd = 3 to 5.25V, 10% - 90%  
Vdd = 3 to 5.25V, 10% - 90%  
10  
10  
27  
22  
Table 34. 2.7V AC GPIO Specifications  
Symbol  
Description  
Min  
0
Typ  
Max  
3
Units  
Notes  
F
GPIO Operating Frequency  
MHz Normal Strong Mode  
GPIO  
TRiseF  
Rise Time, Normal Strong Mode, Cload = 50 pF  
Fall Time, Normal Strong Mode, Cload = 50 pF  
Rise Time, Slow Strong Mode, Cload = 50 pF  
Fall Time, Slow Strong Mode, Cload = 50 pF  
6
50  
ns  
ns  
ns  
ns  
Vdd = 2.4 to 3.0V, 10% - 90%  
TFallF  
TRiseS  
TFallS  
6
50  
Vdd = 2.4 to 3.0V, 10% - 90%  
Vdd = 2.4 to 3.0V, 10% - 90%  
Vdd = 2.4 to 3.0V, 10% - 90%  
18  
18  
40  
40  
120  
120  
Figure 19. GPIO Timing Diagram  
90%  
GPIO  
Pin  
Output  
Voltage  
10%  
TRiseF  
TRiseS  
TFallF  
TFallS  
Document Number: 38-12028 Rev. *J  
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AC Operational Amplifier Specifications  
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters  
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.  
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.  
Power = High and Opamp Bias = High is not supported at 3.3V and 2.7V.  
Table 35. 5V AC Operational Amplifier Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
T
T
Rising Settling Time from 80% of ΔV to 0.1% of ΔV  
(10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
ROA  
3.9  
0.72  
0.62  
μs  
μs  
μs  
Falling Settling Time from 20% of ΔV to 0.1% of ΔV  
(10 pF load, Unity Gain)  
SOA  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
5.9  
0.92  
0.72  
μs  
μs  
μs  
SR  
SR  
Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
ROA  
0.15  
1.7  
6.5  
V/μs  
V/μs  
V/μs  
Falling Slew Rate (20% to 80%) (10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
FOA  
0.01  
0.5  
4.0  
V/μs  
V/μs  
V/μs  
Power = High, Opamp Bias = High  
BW  
Gain Bandwidth Product  
OA  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
0.75  
3.1  
5.4  
MHz  
MHz  
MHz  
E
Noise at 1 kHz (Power = Medium, Opamp Bias = High)  
100  
nV/rt-Hz  
NOA  
Table 36. 3.3V AC Operational Amplifier Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
T
T
Rising Settling Time from 80% of ΔV to 0.1% of ΔV  
(10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
ROA  
3.92  
0.72  
μs  
μs  
Power = Medium, Opamp Bias = High  
Falling Settling Time from 20% of ΔV to 0.1% of ΔV  
(10 pF load, Unity Gain)  
SOA  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
5.41  
0.72  
μs  
μs  
SR  
SR  
Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
ROA  
0.31  
2.7  
V/μs  
V/μs  
Falling Slew Rate (20% to 80%) (10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
FOA  
0.24  
1.8  
V/μs  
V/μs  
BW  
Gain Bandwidth Product  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
OA  
0.67  
2.8  
MHz  
MHz  
E
Noise at 1 kHz (Power = Medium, Opamp Bias = High)  
100  
nV/rt-Hz  
NOA  
Document Number: 38-12028 Rev. *J  
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Table 37. 2.7V AC Operational Amplifier Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
T
T
Rising Settling Time from 80% of ΔV to 0.1% of ΔV  
(10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
ROA  
3.92  
0.72  
μs  
μs  
Power = Medium, Opamp Bias = High  
Falling Settling Time from 20% of ΔV to 0.1% of ΔV  
(10 pF load, Unity Gain)  
SOA  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
5.41  
0.72  
μs  
μs  
SR  
SR  
Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
ROA  
0.31  
2.7  
V/μs  
V/μs  
Falling Slew Rate (20% to 80%) (10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
FOA  
0.24  
1.8  
V/μs  
V/μs  
BW  
Gain Bandwidth Product  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
OA  
0.67  
2.8  
MHz  
MHz  
E
Noise at 1 kHz (Power = Medium, Opamp Bias = High)  
100  
nV/rt-Hz  
NOA  
Document Number: 38-12028 Rev. *J  
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When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up  
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.  
Figure 20. Typical AGND Noise with P2[4] Bypass  
dBV/rtHz  
10000  
0
0.01  
0.1  
1.0  
10  
1000  
100  
0.001  
0.01  
0.1 Freq (kHz)  
1
10  
100  
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high  
frequencies, increased power level reduces the noise spectrum level.  
Figure 21. Typical Opamp Noise  
nV/rtHz  
10000  
PH_BH  
PH_BL  
PM_BL  
PL_BL  
1000  
100  
10  
0.001  
0.01  
0.1  
1
10  
100  
Freq (kHz)  
Document Number: 38-12028 Rev. *J  
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AC Low Power Comparator Specifications  
Table 38 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  
T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters apply to  
A
A
A
5V at 25°C and are for design guidance only.  
Table 38. AC Low Power Comparator Specifications  
Symbol  
Description  
LPC response time  
Min  
Typ  
Max  
Units  
Notes  
T
50  
μs  
50 mV overdrive comparator  
reference set within V  
RLPC  
REFLPC  
AC Digital Block Specifications  
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters  
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.  
Table 39. 5V and 3.3V AC Digital Block Specifications  
Function  
Timer  
Description  
Capture Pulse Width  
Min  
Typ  
Max  
Units  
Notes  
[17]  
50  
ns  
Maximum Frequency, No Capture  
Maximum Frequency, With Capture  
Enable Pulse Width  
49.2  
24.6  
MHz 4.75V < Vdd < 5.25V  
MHz  
[17]  
Counter  
50  
ns  
Maximum Frequency, No Enable Input  
Maximum Frequency, Enable Input  
Kill Pulse Width:  
49.2  
24.6  
MHz 4.75V < Vdd < 5.25V  
MHz  
Dead Band  
Asynchronous Restart Mode  
Synchronous Restart Mode  
Disable Mode  
20  
ns  
[17]  
50  
50  
ns  
[17]  
ns  
Maximum Frequency  
49.2  
49.2  
MHz 4.75V < Vdd < 5.25V  
MHz 4.75V < Vdd < 5.25V  
CRCPRS  
(PRS Mode)  
Maximum Input Clock Frequency  
CRCPRS  
(CRC Mode)  
Maximum Input Clock Frequency  
Maximum Input Clock Frequency  
Maximum Input Clock Frequency  
24.6  
8.2  
MHz  
SPIM  
MHz Maximum data rate at 4.1 MHz  
due to 2 x over clocking.  
SPIS  
4.1  
ns  
ns  
[17]  
Width of SS_ Negated Between Transmissions 50  
Transmitter  
Receiver  
Maximum Input Clock Frequency  
24.6  
MHz Maximum data rate at 3.08  
MHz due to 8 x over clocking.  
Maximum Input Clock Frequency with Vdd ≥  
49.2  
24.6  
49.2  
MHz Maximum data rate at 6.15  
MHz due to 8 x over clocking.  
4.75V, 2 Stop Bits  
Maximum Input Clock Frequency  
MHz Maximum data rate at 3.08  
MHz due to 8 x over clocking.  
Maximum Input Clock Frequency with Vdd ≥  
4.75V, 2 Stop Bits  
MHz Maximum data rate at 6.15  
MHz due to 8 x over clocking.  
Note  
17. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).  
Document Number: 38-12028 Rev. *J  
Page 38 of 55  
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Table 40. 2.7V AC Digital Block Specifications  
Function  
Description  
Min  
Typ  
Max  
Units  
Notes  
All  
Maximum Block Clocking Frequency  
12.7  
MHz 2.4V < Vdd < 3.0V  
Functions  
[18]  
0
0
Timer  
Capture Pulse Width  
100  
ns  
Maximum Frequency, With or Without Capture  
12.7  
MHz  
ns  
[18]  
0
0
Counter Enable Pulse Width  
Maximum Frequency, No Enable Input  
100  
12.7  
12.7  
MHz  
MHz  
Maximum Frequency, Enable Input  
Kill Pulse Width:  
Dead  
Band  
Asynchronous Restart Mode  
Synchronous Restart Mode  
20  
ns  
ns  
[18]  
0
0
100  
100  
0
[18]  
0
0
Disable Mode  
ns  
Maximum Frequency  
12.7  
12.7  
MHz  
MHz  
CRCPRS Maximum Input Clock Frequency  
(PRS  
Mode)  
CRCPRS Maximum Input Clock Frequency  
12.7  
MHz  
(CRC  
Mode)  
SPIM  
Maximum Input Clock Frequency  
Maximum Input Clock Frequency  
6.35  
4.23  
MHz Maximum data rate at 3.17 MHz  
due to 2 x over clocking.  
SPIS  
ns  
ns  
[18]  
0
0
Width of SS_ Negated Between Transmissions 100  
Trans-  
mitter  
Maximum Input Clock Frequency  
12.7  
12.7  
MHz Maximum data rate at 1.59 MHz  
due to 8 x over clocking.  
Receiver Maximum Input Clock Frequency  
MHz Maximum data rate at 1.59 MHz  
due to 8 x over clocking.  
Note  
18. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).  
Document Number: 38-12028 Rev. *J  
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CY8C24223A, CY8C24423A  
AC Analog Output Buffer Specifications  
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters  
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.  
Table 41. 5V AC Analog Output Buffer Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
T
Rising Settling Time to 0.1%, 1V Step, 100 pF Load  
Power = Low  
Power = High  
ROB  
2.5  
2.5  
μs  
μs  
T
Falling Settling Time to 0.1%, 1V Step, 100 pF Load  
Power = Low  
Power = High  
SOB  
2.2  
2.2  
μs  
μs  
SR  
SR  
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load  
Power = Low  
Power = High  
ROB  
0.65  
0.65  
V/μs  
V/μs  
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load  
Power = Low  
Power = High  
FOB  
0.65  
0.65  
V/μs  
V/μs  
BW  
BW  
Small Signal Bandwidth, 20mV , 3dB BW, 100 pF Load  
Power = Low  
Power = High  
OB  
pp  
0.8  
0.8  
MHz  
MHz  
Large Signal Bandwidth, 1V , 3dB BW, 100 pF Load  
OB  
pp  
Power = Low  
Power = High  
300  
300  
kHz  
kHz  
Table 42. 3.3V AC Analog Output Buffer Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
T
Rising Settling Time to 0.1%, 1V Step, 100 pF Load  
Power = Low  
Power = High  
ROB  
3.8  
3.8  
μs  
μs  
T
Falling Settling Time to 0.1%, 1V Step, 100 pF Load  
Power = Low  
Power = High  
SOB  
2.6  
2.6  
μs  
μs  
SR  
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load  
Power = Low  
Power = High  
ROB  
FOB  
0.5  
0.5  
V/μs  
V/μs  
SR  
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load  
Power = Low  
Power = High  
0.5  
0.5  
V/μs  
V/μs  
BW  
BW  
Small Signal Bandwidth, 20mV , 3dB BW, 100 pF Load  
Power = Low  
Power = High  
OB  
OB  
pp  
0.7  
0.7  
MHz  
MHz  
Large Signal Bandwidth, 1V , 3dB BW, 100 pF Load  
pp  
Power = Low  
Power = High  
200  
200  
kHz  
kHz  
Document Number: 38-12028 Rev. *J  
Page 40 of 55  
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Table 43. 2.7V AC Analog Output Buffer Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
T
Rising Settling Time to 0.1%, 1V Step, 100 pF Load  
Power = Low  
Power = High  
ROB  
4
4
μs  
μs  
T
Falling Settling Time to 0.1%, 1V Step, 100 pF Load  
Power = Low  
Power = High  
SOB  
3
3
μs  
μs  
SR  
SR  
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load  
Power = Low  
Power = High  
ROB  
0.4  
0.4  
V/μs  
V/μs  
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load  
Power = Low  
Power = High  
FOB  
0.4  
0.4  
V/μs  
V/μs  
BW  
Small Signal Bandwidth, 20mV , 3dB BW, 100 pF Load  
Power = Low  
Power = High  
OB  
OB  
pp  
0.6  
0.6  
MHz  
MHz  
BW  
Large Signal Bandwidth, 1V , 3dB BW, 100 pF Load  
pp  
Power = Low  
Power = High  
180  
180  
kHz  
kHz  
AC External Clock Specifications  
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters  
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.  
Table 44. 5V AC External Clock Specifications  
Symbol  
Description  
Min  
0.093  
20.6  
20.6  
150  
Typ  
Max  
24.6  
5300  
Units  
MHz  
ns  
F
Frequency  
OSCEXT  
High Period  
Low Period  
ns  
Power Up IMO to Switch  
μs  
Table 45. 3.3V AC External Clock Specifications  
Symbol  
Description  
Min  
0.093  
0.186  
41.7  
41.7  
150  
Typ  
Max  
12.3  
24.6  
5300  
Units  
MHz  
MHz  
ns  
[19]  
F
Frequency with CPU Clock divide by 1  
OSCEXT  
OSCEXT  
[20]  
F
Frequency with CPU Clock divide by 2 or greater  
High Period with CPU Clock divide by 1  
Low Period with CPU Clock divide by 1  
Power Up IMO to Switch  
ns  
μs  
Notes  
19. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle  
requirements.  
20. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the  
fifty percent duty cycle requirement is met  
Document Number: 38-12028 Rev. *J  
Page 41 of 55  
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Table 46. 2.7V AC External Clock Specifications  
Symbol  
Description  
Min  
0.093  
0.186  
41.7  
41.7  
150  
Typ  
Max  
12.3  
12.3  
5300  
Units  
MHz  
MHz  
ns  
[21]  
F
Frequency with CPU Clock divide by 1  
OSCEXT  
OSCEXT  
[22]  
F
Frequency with CPU Clock divide by 2 or greater  
High Period with CPU Clock divide by 1  
Low Period with CPU Clock divide by 1  
Power Up IMO to Switch  
ns  
μs  
AC Programming Specifications  
Table 47 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  
T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters apply to  
A
A
A
5V, 3.3V, and 2.7V at 25°C and are for design guidance only.  
Table 47. AC Programming Specifications  
Symbol  
Description  
Min  
1
1
40  
40  
0
Typ  
Max  
20  
20  
8
45  
50  
70  
Units  
ns  
ns  
ns  
ns  
MHz  
ms  
ms  
ns  
ns  
ns  
Notes  
T
T
T
T
F
T
T
T
T
T
Rise Time of SCLK  
Fall Time of SCLK  
RSCLK  
FSCLK  
SSCLK  
HSCLK  
SCLK  
Data Setup Time to Falling Edge of SCLK  
Data Hold Time from Falling Edge of SCLK  
Frequency of SCLK  
Flash Erase Time (Block)  
20  
20  
ERASEB  
WRITE  
DSCLK  
DSCLK3  
DSCLK2  
Flash Block Write Time  
Data Out Delay from Falling Edge of SCLK  
Data Out Delay from Falling Edge of SCLK  
Data Out Delay from Falling Edge of SCLK  
Vdd > 3.6  
3.0 Vdd 3.6  
2.4 Vdd 3.0  
AC I2C Specifications  
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, 3.0V to 3.6V and -40°C T 85°C, or 2.4V to 3.0V and -40°C T 85°C, respectively. Typical parameters  
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.  
Table 48. AC Characteristics of the I2C SDA and SCL Pins for Vdd > 3.0V  
Standard Mode  
Fast Mode  
Symbol  
Description  
Units  
Min  
0
Max  
100  
Min  
Max  
400  
F
T
SCL Clock Frequency  
0
kHz  
SCLI2C  
Hold Time (repeated) START Condition. After this period, the  
first clock pulse is generated.  
4.0  
0.6  
μs  
HDSTAI2C  
T
T
T
T
T
LOW Period of the SCL Clock  
HIGH Period of the SCL Clock  
Setup Time for a Repeated START Condition  
Data Hold Time  
4.7  
4.0  
4.7  
0
1.3  
0.6  
0.6  
0
μs  
μs  
μs  
μs  
ns  
LOWI2C  
HIGHI2C  
SUSTAI2C  
HDDATI2C  
SUDATI2C  
[23]  
Data Setup Time  
250  
100  
Notes  
21. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle  
requirements.  
22. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the  
fifty percent duty cycle requirement is met.  
23. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t  
Š 250 ns must then be met. This is automatically the  
SU;DAT  
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data  
bit to the SDA line t + t = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.  
rmax  
SU;DAT  
Document Number: 38-12028 Rev. *J  
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Table 48. AC Characteristics of the I2C SDA and SCL Pins for Vdd > 3.0V (continued)  
Standard Mode  
Fast Mode  
Symbol  
Description  
Setup Time for STOP Condition  
Units  
Min  
4.0  
4.7  
Max  
Min  
Max  
T
T
T
0.6  
1.3  
0
μs  
μs  
ns  
SUSTOI2C  
BUFI2C  
SPI2C  
Bus Free Time Between a STOP and START Condition  
Pulse Width of spikes are suppressed by the input filter.  
50  
Table 49. AC Characteristics of the I2C SDA and SCL Pins for Vdd < 3.0V (Fast Mode Not Supported)  
Standard Mode  
Fast Mode  
Symbol  
Description  
Units  
Min  
0
Max  
100  
Min  
Max  
F
T
SCL Clock Frequency  
kHz  
SCLI2C  
Hold Time (repeated) START Condition. After this period, the  
first clock pulse is generated.  
4.0  
μs  
HDSTAI2C  
T
T
T
T
T
T
T
T
LOW Period of the SCL Clock  
4.7  
4.0  
4.7  
0
μs  
μs  
μs  
μs  
ns  
μs  
μs  
ns  
LOWI2C  
HIGH Period of the SCL Clock  
HIGHI2C  
SUSTAI2C  
HDDATI2C  
SUDATI2C  
SUSTOI2C  
BUFI2C  
Setup Time for a Repeated START Condition  
Data Hold Time  
Data Setup Time  
250  
4.0  
4.7  
Setup Time for STOP Condition  
Bus Free Time Between a STOP and START Condition  
Pulse Width of spikes are suppressed by the input filter  
SPI2C  
Figure 22. Definition for Timing for Fast/Standard Mode on the I2C Bus  
SDA  
SCL  
TSPI2C  
T
LOWI2C  
TSUDATI2C  
THDSTAI2C  
TBUFI2C  
TSUSTOI2C  
TSUSTAI2C  
THDDATI2C  
THDSTAI2C  
THIGHI2C  
S
Sr  
P
S
Document Number: 38-12028 Rev. *J  
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CY8C24223A, CY8C24423A  
Packaging Information  
This section illustrates the packaging specifications for the CY8C24x23A PSoC device, along with the thermal impedances for each  
package and the typical package capacitance on crystal pins.  
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of  
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at  
http://www.cypress.com/design/MR10161.  
Packaging Dimensions  
Figure 23. 8-Pin (300-Mil) PDIP  
0.380  
0.390  
PIN 1 ID  
4
1
DIMENSIONS IN INCHES MIN.  
MAX.  
0.240  
0.260  
5
8
0.300  
0.325  
0.100 BSC.  
SEATING  
PLANE  
0.115  
0.145  
0.180 MAX.  
0.008  
0.015  
0.015 MIN.  
0.125  
0.140  
0°-10°  
0.055  
0.070  
0.430 MAX.  
0.014  
0.022  
51-85075 *A  
Document Number: 38-12028 Rev. *J  
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Figure 24. 8-Pin (150-Mil) SOIC  
PIN 1 ID  
1
4
1. DIMENSIONS IN INCHES[MM] MIN.  
2. PIN 1 ID IS OPTIONAL,  
MAX.  
ROUND ON SINGLE LEADFRAME  
0.150[3.810]  
0.157[3.987]  
RECTANGULAR ON MATRIX LEADFRAME  
3. REFERENCE JEDEC MS-012  
4. PACKAGE WEIGHT 0.07gms  
0.230[5.842]  
0.244[6.197]  
PART #  
S08.15 STANDARD PKG.  
SZ08.15 LEAD FREE PKG.  
5
8
0.189[4.800]  
0.196[4.978]  
0.010[0.254]  
0.016[0.406]  
X 45°  
SEATING PLANE  
0.061[1.549]  
0.068[1.727]  
0.004[0.102]  
0.050[1.270]  
BSC  
0.0075[0.190]  
0.0098[0.249]  
0.004[0.102]  
0.0098[0.249]  
0°~8°  
0.016[0.406]  
0.035[0.889]  
0.0138[0.350]  
0.0192[0.487]  
51-85066 *C  
Figure 25. 20-Pin (300-Mil) Molded DIP  
51-85011 *A  
Document Number: 38-12028 Rev. *J  
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Figure 26. 20-Pin (210-Mil) SSOP  
51-85077 *C  
Figure 27. 20-Pin (300-Mil) Molded SOIC  
51-85024 *C  
Document Number: 38-12028 Rev. *J  
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Figure 28. 28-Pin (300-Mil) Molded DIP  
51-85014 *D  
Figure 29. 28-Pin (210-Mil) SSOP  
51-85079 *C  
Document Number: 38-12028 Rev. *J  
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Figure 30. 28-Pin (300-Mil) Molded SOIC  
51-85026 *D  
Figure 31. 32-Pin (5x5 mm) QFN  
51-85188 *C  
Document Number: 38-12028 Rev. *J  
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Figure 32. 32-Pin Sawn QFN Package  
SOLDERABLE  
EXPOSED  
PAD  
NOTES:  
1. HATCH AREA IS SOLDERABLE EXPOSED PAD  
2. BASED ON REF JEDEC # MO-220  
3. PACKAGE W EIGHT: 0.058g  
001-30999 *A  
4. DIMENSIONS ARE IN MILLIMETERS  
Important Note For information on the preferred dimensions for mounting QFN packages, see the following application note at  
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.  
Figure 33. 56-Pin (300-Mil) SSOP  
51-85062 *C  
Document Number: 38-12028 Rev. *J  
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Thermal Impedances  
Capacitance on Crystal Pins  
Table 50. Thermal Impedances per Package  
Table 51. Typical Package Capacitance on Crystal Pins  
Package Package Capacitance  
2.8 pF  
[24]  
Package  
Typical θJA  
8 PDIP  
123°C/W  
185°C/W  
109°C/W  
117 °C/W  
81°C/W  
8 PDIP  
8 SOIC  
8 SOIC  
2.0 pF  
3.0 pF  
2.6 pF  
2.5 pF  
3.5 pF  
2.8 pF  
2.7 pF  
2.0 pF  
20 PDIP  
20 SSOP  
20 SOIC  
28 PDIP  
28 SSOP  
28 SOIC  
32 QFN  
20 PDIP  
20 SSOP  
20 SOIC  
28 PDIP  
28 SSOP  
28 SOIC  
32 QFN  
69 °C/W  
101°C/W  
74 °C/W  
22°C/W  
Solder Reflow Peak Temperature  
The following table lists the minimum solder reflow peak temperatures to achieve good solderability.  
Table 52. Solder Reflow Peak Temperature  
Package  
Minimum Peak Temperature[25] Maximum Peak Temperature  
8 PDIP  
240°C  
240°C  
240°C  
240°C  
220°C  
240°C  
240°C  
220°C  
240°C  
260°C  
260°C  
260°C  
260°C  
260°C  
260°C  
260°C  
260°C  
260°C  
8 SOIC  
20 PDIP  
20 SSOP  
20 SOIC  
28 PDIP  
28 SSOP  
28 SOIC  
32 QFN  
Notes  
24. T = T + POWER x θJA  
J
A
o
o
25. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 C with Sn-Pb or 245 ± 5 C with Sn-Ag-Cu paste.  
Refer to the solder manufacturer specifications.  
Document Number: 38-12028 Rev. *J  
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iMAGEcraft C Compiler (Registration Required)  
Development Tool Selection  
ISSP Cable  
This section presents the development tools available for all  
current PSoC device families including the CY8C24x23A family.  
USB 2.0 Cable and Blue Cat-5 Cable  
2 CY8C29466-24PXI 28-PDIP Chip Samples  
Software  
CY3210-ExpressDK PSoC Express Development Kit  
PSoC Designer™  
The CY3210-ExpressDK is for advanced prototyping and  
development with PSoC Express (may be used with ICE-Cube  
In-Circuit Emulator). It provides access to I C buses, voltage  
reference, switches, upgradeable modules and more. The kit  
includes:  
At the core of the PSoC development software suite is PSoC  
Designer. Used by thousands of PSoC developers, this robust  
software has been facilitating PSoC designs for half a decade.  
PSoC Designer is available free of charge at  
http://www.cypress.com under DESIGN RESOURCES >>  
Software and Drivers.  
2
PSoC Express Software CD  
Express Development Board  
4 Fan Modules  
PSoC Programmer  
Flexible enough to be used on the bench in development, yet  
suitable for factory programming, PSoC Programmer works  
either as a standalone programming application or it can operate  
directly from PSoC Designer or PSoC Express. PSoC  
Programmer software is compatible with both PSoC ICE-Cube  
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is  
available free ofcharge at http://www.cypress.com/psocpro-  
grammer.  
2 Proto Modules  
MiniProg In-System Serial Programmer  
MiniEval PCB Evaluation Board  
Jumper Wire Kit  
USB 2.0 Cable  
C Compilers  
Serial Cable (DB9)  
PSoC Designer comes with a free HI-TECH C Lite C compiler.  
The HI-TECH C Lite compiler is free, supports all PSoC devices,  
integrates fully with PSoC Designer and PSoC Express, and  
runs on Windows versions up to 32-bit Vista. Compilers with  
additional features are available at additional cost from their  
manufactures.  
110 ~ 240V Power Supply, Euro-Plug Adapter  
2 CY8C24423A-24PXI 28-PDIP Chip Samples  
2 CY8C27443-24PXI 28-PDIP Chip Samples  
2 CY8C29466-24PXI 28-PDIP Chip Samples  
HI-TECH C PRO for the PSoC is available from  
http://www.htsoft.com.  
Evaluation Tools  
ImageCraft Cypress Edition Compiler is available from  
http://www.imagecraft.com.  
All evaluation tools can be purchased from the Cypress Online  
Store.  
Development Kits  
CY3210-MiniProg1  
All development kits can be purchased from the Cypress Online  
Store.  
The CY3210-MiniProg1 kit allows a user to program PSoC  
devices through the MiniProg1 programming unit. The MiniProg  
is a small, compact prototyping programmer that connects to the  
PC through a provided USB 2.0 cable. The kit includes:  
CY3215-DK Basic Development Kit  
The CY3215-DK is for prototyping and development with PSoC  
Designer. This kit supports in-circuit emulation and the software  
interface allows users to run, halt, and single step the processor  
and view the content of specific memory locations. Advance  
emulation features also supported through PSoC Designer. The  
kit includes:  
MiniProg Programming Unit  
MiniEval Socket Programming and Evaluation Board  
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample  
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample  
PSoC Designer Software CD  
PSoC Designer Software CD  
ICE-Cube In-Circuit Emulator  
ICE Flex-Pod for CY8C29x66 Family  
Cat-5 Adapter  
Getting Started Guide  
USB 2.0 Cable  
Mini-Eval Programming Board  
110 ~ 240V Power Supply, Euro-Plug Adapter  
Document Number: 38-12028 Rev. *J  
Page 51 of 55  
[+] Feedback  
CY8C24123A  
CY8C24223A, CY8C24423A  
CY3210-PSoCEval1  
Device Programmers  
The CY3210-PSoCEval1 kit features an evaluation board and  
the MiniProg1 programming unit. The evaluation board includes  
an LCD module, potentiometer, LEDs, and plenty of bread-  
boarding space to meet all of your evaluation needs. The kit  
includes:  
All device programmers can be purchased from the Cypress  
Online Store.  
CY3216 Modular Programmer  
The CY3216 Modular Programmer kit features a modular  
programmer and the MiniProg1 programming unit. The modular  
programmer includes three programming module cards and  
supports multiple Cypress products. The kit includes:  
Evaluation Board with LCD Module  
MiniProg Programming Unit  
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)  
PSoC Designer Software CD  
Getting Started Guide  
Modular Programmer Base  
3 Programming Module Cards  
MiniProg Programming Unit  
PSoC Designer Software CD  
Getting Started Guide  
USB 2.0 Cable  
CY3214-PSoCEvalUSB  
The CY3214-PSoCEvalUSB evaluation kit features  
a
USB 2.0 Cable  
development board for the CY8C24794-24LFXI PSoC device.  
Special features of the board include both USB and capacitive  
sensing development and debugging support. This evaluation  
board also includes an LCD module, potentiometer, LEDs, an  
enunciator and plenty of bread boarding space to meet all of your  
evaluation needs. The kit includes:  
CY3207ISSP In-System Serial Programmer (ISSP)  
The CY3207ISSP is a production programmer. It includes  
protection circuitry and an industrial case that is more robust than  
the MiniProg in a production-programming environment.  
Note CY3207ISSP needs special software and is not compatible  
with PSoC Programmer. The kit includes:  
PSoCEvalUSB Board  
LCD Module  
CY3207 Programmer Unit  
PSoC ISSP Software CD  
MIniProg Programming Unit  
Mini USB Cable  
110 ~ 240V Power Supply, Euro-Plug Adapter  
USB 2.0 Cable  
PSoC Designer and Example Projects CD  
Getting Started Guide  
Wire Pack  
Accessories (Emulation and Programming)  
Table 53. Emulation and Programming Accessories  
Part #  
All non-QFN  
Pin Package  
Flex-Pod Kit[26]  
Foot Kit[27]  
Adapter[28]  
All non QFN  
CY3250-24X23A  
CY3250-8DIP-FK,  
CY3250-8SOIC-FK,  
CY3250-20DIP-FK,  
CY3250-20SOIC-FK,  
CY3250-20SSOP-FK,  
CY3250-28DIP-FK,  
CY3250-28SOIC-FK,  
CY3250-28SSOP-FK  
Adapters can be found at  
http://www.emulation.com.  
CY8C24423A-24LFXI  
32 QFN  
CY3250-24X23AQFN  
CY3250-32QFN-FK  
Third Party Tools  
Build a PSoC Emulator into Your Board  
Several tools have been specially designed by the following  
3rd-party vendors to accompany PSoC devices during devel-  
opment and production. Specific details for each of these tools  
can be found at http://www.cypress.com under DESIGN  
RESOURCES >> Evaluation Boards.  
For details on how to emulate your circuit before going to volume  
production using an on-chip debug (OCD) non-production PSoC  
device, see application note AN2323 “Debugging - Build a PSoC  
Emulator into Your Board”.  
Notes  
26. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.  
27. Foot kit includes surface mount feet that can be soldered to the target PCB.  
28. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at  
http://www.emulation.com.  
Document Number: 38-12028 Rev. *J  
Page 52 of 55  
[+] Feedback  
CY8C24123A  
CY8C24223A, CY8C24423A  
Ordering Information  
The following table lists the CY8C24x23A PSoC device’s key package features and ordering codes.  
Table 54. CY8C24x23A PSoC Device Key Features and Ordering Information  
8 Pin (300 Mil) DIP  
8 Pin (150 Mil) SOIC  
CY8C24123A-24PXI  
CY8C24123A-24SXI  
4K  
4K  
256 No  
256 No  
-40C to +85C  
-40C to +85C  
4
4
6
6
6
6
4
4
2
2
No  
No  
8 Pin (150 Mil) SOIC  
(Tape and Reel)  
CY8C24123A-24SXIT  
4K  
256 No  
-40C to +85C  
4
6
6
4
2
No  
20 Pin (300 Mil) DIP  
CY8C24223A-24PXI  
CY8C24223A-24PVXI  
4K  
4K  
256 Yes -40C to +85C  
256 Yes -40C to +85C  
4
4
6
6
16  
16  
8
8
2
2
Yes  
Yes  
20 Pin (210 Mil) SSOP  
20 Pin (210 Mil) SSOP  
(Tape and Reel)  
CY8C24223A-24PVXIT 4K  
256 Yes -40C to +85C  
256 Yes -40C to +85C  
256 Yes -40C to +85C  
4
4
4
6
6
6
16  
16  
16  
8
8
8
2
2
2
Yes  
Yes  
Yes  
20 Pin (300 Mil) SOIC  
CY8C24223A-24SXI  
CY8C24223A-24SXIT  
4K  
4K  
20 Pin (300 Mil) SOIC  
(Tape and Reel)  
28 Pin (300 Mil) DIP  
CY8C24423A-24PXI  
CY8C24423A-24PVXI  
4K  
4K  
256 Yes -40C to +85C  
256 Yes -40C to +85C  
4
4
6
6
24  
24  
10  
10  
2
2
Yes  
Yes  
28 Pin (210 Mil) SSOP  
28 Pin (210 Mil) SSOP  
(Tape and Reel)  
CY8C24423A-24PVXIT 4K  
256 Yes -40C to +85C  
256 Yes -40C to +85C  
256 Yes -40C to +85C  
256 Yes -40C to +85C  
256 Yes -40C to +85C  
4
4
4
4
4
6
6
6
6
6
24  
24  
24  
24  
24  
10  
10  
10  
10  
10  
2
2
2
2
2
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
28 Pin (300 Mil) SOIC  
CY8C24423A-24SXI  
CY8C24423A-24SXIT  
CY8C24423A-24LFXI  
CY8C24423A-24LTXI  
4K  
4K  
4K  
4K  
28 Pin (300 Mil) SOIC  
(Tape and Reel)  
32 Pin (5x5 mm) QFN  
32 Pin (5x5 mm 1.00 MAX)  
SAWN QFN  
32 Pin (5x5 mm 1.00 MAX)  
SAWN QFN (Tape and Reel)  
CY8C24423A-24LTXIT  
4K  
4K  
256 Yes -40C to +85C  
256 Yes -40C to +85C  
4
4
6
6
24  
24  
10  
10  
2
2
[29]  
56 Pin OCD SSOP  
CY8C24000A-24PVXI  
Yes  
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).  
Ordering Code Definitions  
CY 8 C 24 xxx-SPxx  
Package Type:  
Thermal Rating:  
C = Commercial  
I = Industrial  
PX = PDIP Pb-Free  
SX = SOIC Pb-Free  
PVX = SSOP Pb-Free  
LFX/LKX = QFN Pb-Free  
AX = TQFP Pb-Free  
E = Extended  
Speed: 24 MHz  
Part Number  
Family Code  
Technology Code: C = CMOS  
Marketing Code: 8 = Cypress PSoC  
Company ID: CY = Cypress  
Note  
29. This part may be used for in-circuit debugging. It is NOT available for production  
Document Number: 38-12028 Rev. *J  
Page 53 of 55  
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CY8C24123A  
CY8C24223A, CY8C24423A  
Document History Page  
Document Title: CY8C24123A, CY8C24223A, CY8C24423A PSoC® Programmable System-on-Chip™  
Document Number: 38-12028  
Orig. of  
Change  
Submission  
Date  
Rev.  
**  
ECN  
Description of Change  
236409  
247589  
SFV  
See ECN  
See ECN  
New silicon and new document – Preliminary Data Sheet.  
*A  
SFV  
Changed the title to read “Final” data sheet. Updated Electrical Specifications  
chapter.  
*B  
*C  
261711  
279731  
HMT  
HMT  
See ECN  
See ECN  
Input all SFV memo changes. Updated Electrical Specifications chapter.  
Update Electrical Specifications chapter, including 2.7 VIL DC GPIO spec. Add  
Solder Reflow Peak Temperature table. Clean up pinouts and fine tune wording and  
format throughout.  
*D  
*E  
*F  
352614  
424036  
521439  
HMT  
HMT  
HMT  
See ECN  
See ECN  
See ECN  
Add new color and CY logo. Add URL to preferred dimensions for mounting MLF  
packages. Update Transmitter and Receiver AC Digital Block Electrical Specifica-  
tions. Re-add ISSP pinout identifier. Delete Electrical Specification sentence re:  
devices running at greater than 12 MHz. Update Solder Reflow Peak Temperature  
table. Fix CY.com URLs. Update CY copyright.  
Fix SMP 8-pin SOIC error in Feature and Order table. Update 32-pin QFN E-Pad  
dimensions and rev. *A. Add ISSP note to pinout tables. Update typical and recom-  
mended Storage Temperature per industrial specs. Add OCD non-production pinout  
and package diagram. Update CY branding and QFN convention. Update package  
diagram revisions.  
Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add new Dev.  
Tool section. Add CY8C20x34 to PSoC Device Characteristics table.  
*G  
*H  
2256806 UVS/PYRS See ECN  
2425586 DSO/AESA See ECN  
Added Sawn pin information.  
Corrected Ordering Information to include CY8C24423A-24LTXI and  
CY8C24423A-24LTXIT  
®
*I  
2619935 OGNE/AESA 12/11/2008  
Changed title to “CY8C24123A, CY8C24223A, CY8C24423A PSoC  
Programmable System-on-Chip™”  
Updated package diagram 001-30999 to *A.  
Added note on digital signaling in DC Analog Reference Specifications on page 27.  
Added Die Sales information note to Ordering Information on page 53.  
*J  
2692871 DPT/PYRS  
04/16/2009 Updated Max package thickness for 32-pin QFN package  
Formatted Notes  
Updated “Getting Started” on page 4  
Updated “Development Tools” on page 5 and “Designing with PSoC Designer” on  
page 6  
Document Number: 38-12028 Rev. *J  
Page 54 of 55  
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CY8C24123A  
CY8C24223A, CY8C24423A  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
psoc.cypress.com  
clocks.cypress.com  
wireless.cypress.com  
memory.cypress.com  
image.cypress.com  
psoc.cypress.com/solutions  
psoc.cypress.com/low-power  
psoc.cypress.com/precision-analog  
psoc.cypress.com/lcd-drive  
psoc.cypress.com/can  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
psoc.cypress.com/usb  
© Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 38-12028 Rev. *J  
Revised April 14, 2009  
Page 55 of 55  
PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced  
herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights  
to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document  
may be the trademarks of their respective holders.  
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