CY8C24894-24LFXA [CYPRESS]
Automotive PSoC Programmable System-on-Chip Low power at high speed; 汽车的PSoC可编程系统级芯片的低功耗高速
| 型号： | CY8C24894-24LFXA |
| 厂家： | 
CYPRESS |
| 描述： | Automotive PSoC Programmable System-on-Chip Low power at high speed |
| 文件： | 总46页 (文件大小：1206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C24894
Automotive PSoC®
Programmable System-on-Chip™
❐ Internal low-speed, low-power oscillator for watchdog and
sleep functionality
Features
❐ Optional external oscillator, up to 24 MHz
■ Automotive Electronics Council (AEC) qualified
■ Additional system resources
■ Powerful Harvard-architecture processor
❐ M8C processor speeds up to 24 MHz
❐ Two 8 × 8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ Operating voltage: 3.0 V to 5.25 V
❐ Automotive temperature range: –40 °C to +85 °C
❐ I2C™ slave, master, or multimaster operation up to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable LVD
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
■ Complete development tools
■ Advanced peripherals (PSoC® blocks)
❐ Six rail-to-rail analog PSoC blocks provide:
• Up to 14-bit analog-to-digital converters (ADCs)
• Up to 9-bit digital-to-analog converters (DACs)
• Programmable gain amplifiers (PGAs)
• Programmable filters and comparators
❐ Free development software (PSoC Designer™)
❐ Full-featured in-circuit emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
❐ Four digital PSoC blocks provide:
• 8- to 32-bit timers, counters, and pulse-width modulators
(PWMs)
Logic Block Diagram
Analog
Drivers
• Cyclic redundancy check (CRC) and pseudo-random
sequence (PRS) modules
Port5 Port4 Port3 Port2 Port1 Port0
Port7
• Full- or half-duplex UART
• SPI master or slave
• Connectable to all general purpose I/O (GPIO) pins
❐ Complex peripherals by combining blocks
• Capacitive sensing application capability
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
SRAM
1K
SROM
Flash16K
■ Flexible on-chip memory
❐ 16 KB flash program storage, 1000 erase/write cycles
❐ 1 KB SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
Sleep and
Watchdog
CPU Core(M8C)
Interrupt
Controller
Clock Sources
(Includes IMO and ILO)
❐ Flexible protection modes
❐ EEPROM emulation in flash
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
■ Programmable pin configurations
❐ 25 mA sink, 10 mA drive on all GPIOs
❐ Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
Digital
Block
Array
Analog
Block
Array
❐ Up to 47 analog inputs on GPIOs
❐ Two 30 mA analog outputs on GPIOs
❐ Configurable interrupt on all GPIOs
Analog
Input
Muxing
Internal
Voltage
Re.f
Digital
Clocks MACs
2
Decimator
Type2
POR and LVD
System Resets
I2C
■ Precision, programmable clocking
❐ Internal ±4% 24/48 MHz oscillator
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-53754 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 2, 2011
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CY8C24894
Contents
PSoC Functional Overview ..............................................3
The PSoC Core ...........................................................3
The Digital System ......................................................3
The Analog System .....................................................4
Additional System Resources .....................................5
PSoC Device Characteristics ......................................5
Getting Started ..................................................................6
Application Notes ........................................................6
Development Kits ........................................................6
Training .......................................................................6
CYPros Consultants ....................................................6
Solutions Library ..........................................................6
Technical Support .......................................................6
Development Tools ..........................................................6
PSoC Designer Software Subsystems ........................6
Designing with PSoC Designer .......................................7
Select User Modules ...................................................7
Configure User Modules ..............................................7
Organize and Connect ................................................7
Generate, Verify, and Debug .......................................7
Pinouts ..............................................................................8
56-Pin Part Pinout (with XRES pin) ............................8
Registers ...........................................................................9
Register Conventions ..................................................9
Register Mapping Tables ............................................9
Register Map Bank 0 Table: User Space .................10
Register Map Bank 1 Table: Configuration Space ...11
Electrical Specifications ................................................12
Absolute Maximum Ratings .......................................13
Operating Temperature .............................................13
DC Electrical Characteristics .....................................14
AC Electrical Characteristics .....................................26
Packaging Information ...................................................34
Thermal Impedances .................................................34
Solder Reflow Specifications .....................................34
Tape and Reel Information ........................................35
Development Tool Selection .........................................36
Software ....................................................................36
Development Kits ......................................................36
Evaluation Tools ........................................................36
Device Programmers .................................................37
Accessories (Emulation and Programming) ..............37
Ordering Information ......................................................38
Ordering Code Definitions .........................................38
Reference Information ...................................................39
Acronyms ..................................................................39
Reference Documents ...............................................39
Document Conventions .............................................40
Glossary ....................................................................40
Document History Page .................................................45
Sales, Solutions, and Legal Information ......................46
Worldwide Sales and Design Support .......................46
Products ....................................................................46
PSoC Solutions .........................................................46
Document Number: 001-53754 Rev. *D
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CY8C24894
The Digital System
PSoC Functional Overview
The digital system is composed of four digital PSoC blocks. Each
block is an 8-bit resource used alone or combined with other
blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are
called user modules.
The PSoC family consists of many Programmable
System-on-Chip with on-chip controller devices. All PSoC family
devices are designed to replace traditional microcontroller units
(MCUs), system ICs, and the numerous discrete components
that surround them. Configurable analog, digital, and inter-
connect circuitry enable a high level of integration in a host of
industrial, consumer, and communication applications.
Figure 1. Digital System Block Diagram
Port 7
Port 5
Port 3
Port 1
Port 4
Port 2
Port 0
This architecture allows the user to create customized peripheral
configurations that match the requirements of each individual
application. Additionally, a fast CPU, Flash program memory,
SRAM data memory, and configurable I/O are included in a
range of convenient pinouts and packages.
To System Bus
Digital Clocks
From Core
To Analog
System
The PSoC architecture, as illustrated in the Logic Block Diagram
on page 1, is comprised of four main areas: PSoc Core, digital
system, analog system, and system resources. Configurable
global busing allows all the device resources to be combined into
a complete custom system. The PSoC CY8C24x94 devices can
have up to seven I/O ports that connect to the global digital and
analog interconnects, providing access to four digital blocks and
six analog blocks.
DIGITAL SYSTEM
Digital PSoC Block Array
Row 0
8
4
8
8
8
DBB00
DBB01
DCB02 DCB03
4
The PSoC Core
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIOs.
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four-MIPS 8-bit Harvard architecture micro-
processor. The CPU uses an interrupt controller with up to 20
vectors, to simplify programming of real-time embedded events.
Program execution is timed and protected using the included
sleep timer and watchdog timer (WDT).
Digital peripheral configurations include those listed below.
■ PWMs (8- to 32-bit)
■ PWMs with Dead band (8- to 24-bit)
■ Counters (8- to 32-bit)
Memory encompasses 16 KB of flash for program storage, 1 KB
of SRAM for data storage, and up to 2 KB of emulated EEPROM
using the flash. Program flash has four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
■ Timers (8- to 32-bit)
■ Full- or half-duplex 8-bit UART with selectable parity
■ SPI master and slave
The PSoC device incorporates flexible internal clock generators,
including a 24-MHz internal main oscillator (IMO) accurate to
±4% over temperature and voltage. The 24-MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32-kHz internal low-speed oscillator (ILO) is provided for the
sleep timer and WDT. The clocks, together with programmable
clock dividers (as system resources), provide the flexibility to
integrate almost any timing requirement into the PSoC device.
■ I2C master, slave, or multimaster (implemented in a dedicated
I2C block)
■ Cyclic redundancy checker/generator (16-bit)
■ Infrared Data Association (IrDA)
■ PRS generators (8- to 32-bit)
PSoC GPIOs provide connection to the CPU, digital resources,
and analog resources of the device. Each pin’s drive mode may
be selected from eight options, allowing great flexibility in
external interfacing. Every pin is also capable of generating a
system interrupt.
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow signal multiplexing and performing logic opera-
tions. This configurability frees your designs from the constraints
of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in Table 1 on page 5.
Document Number: 001-53754 Rev. *D
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CY8C24894
Figure 2. Analog System Block Diagram
The Analog System
A ll IO
(E x c e p t P o rt 7 )
The analog system is composed of six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are listed below.
P 0 [7 ]
P 0 [5 ]
P 0 [6 ]
P 0 [4 ]
P 0 [3 ]
P 0 [1 ]
P 0 [2 ]
P 0 [0 ]
■ ADCs (up to two, with 6- to 14-bit resolution, selectable as
incremental,delta-sigma, orsuccessiveapproximationregister
(SAR))
P 2 [6 ]
P 2 [4 ]
P 2 [3 ]
P 2 [1 ]
■ Filters (Two- and Four-pole band pass, low pass, and notch)
■ Amplifiers (up to two, with selectable gain to 48x)
■ Instrumentation amplifiers (one with selectable gain to 93x)
■ Comparators (up to two, with 16 selectable thresholds)
■ DACs (up to two, with 6- to 9-bit resolution)
■ Multiplying DACs (up to two, with 6- to 9-bit resolution)
■ High current output drivers (two with 30 mA drive)
■ 1.3-V reference (as a system resource)
■ DTMF Dialer
P 2 [2 ]
P 2 [0 ]
A C I0 [1 :0 ]
A rra y In p u t
A C I1 [1 :0 ]
C o n fig u ra tio n
B lo c k
A rray
A C B 0 0
A S C 1 0
A S D 2 0
A C B 0 1
■ Modulators
A S D 1 1
A S C 2 1
■ Correlators
■ Peak Detectors
A n a lo g R e fe re n c e
■ Many other topologies possible
In te rfa c e to
D ig ita l S y s te m
R e fe re n c e
G e n e ra to rs
Analog blocks are arranged in a column of three, which includes
one continuous time (CT) and two switched capacitor (SC)
blocks, as shown in Figure 2.
R e fH i
R e fL o
A G N D
A G N D In
R e fIn
B a n d g a p
M 8 C In te rfa c e (A d d re s s B u s , D a ta B u s , E tc .)
The Analog Multiplexer System
The analog mux bus can connect to every GPIO pin in ports 0-5.
Pins are connected to the bus individually or in any combination.
The bus also connects to the analog system for analysis with
comparators and ADCs. It can be split into two sections for simul-
taneous dual-channel processing. An additional 8:1 analog input
multiplexer provides a second path to bring Port 0 pins to the
analog array.
Switch control logic enables selected pins to precharge continu-
ously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■ Track pad, finger sensing.
■ Chip-wide mux that allows analog input from up to 47 I/O pins.
■ Crosspoint connection between any I/O pin combination.
Document Number: 001-53754 Rev. *D
Page 4 of 46
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CY8C24894
Additional System Resources
System resources provide additional capability useful for
complete systems. Additional resources include a multiplier,
decimator, LVD, and power-on reset (POR). Brief statements
describing the merits of each resource follow.
■ The decimator provides a custom hardware filter for digital
signal processing applications including creation of Delta-
Sigma ADCs.
■ The I2C module provides 0 to 400 kHz communication over two
wires. Slave, master, and multi-master modes are all
supported.
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks are
generated using digital PSoC blocks as clock dividers.
■ LVD interrupts can signal the application of falling voltage
levels, while the advanced POR circuit eliminates the need for
a system supervisor.
■ Two multiply accumulates (MACs) provide fast 8-bit multipliers
with 32-bit accumulate, to assist in both general math and
digital filters.
■ An internal 1.3-V voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
■ Versatile analog multiplexer system.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have varying numbers of digital and analog
blocks. The following table lists the resources available for specific PSoC device groups. The device covered by this datasheet is
shown in the highlighted row of the table.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Analog
Analog
SRAM
Size
Flash
Size
Outputs Columns Blocks
[1]
CY8C29x66
CY8C28xxx
up to 64
up to 44
4
16
up to 12
up to 44
4
4
12
2 K
1 K
32 K
16 K
up to 3
up to 12
up to 4
up to 6
up to
12 + 4
[2]
CY8C27x43
up to 44
up to 56
up to 24
up to 26
up to 38
up to 24
up to 28
up to 16
up to 28
up to 36
2
1
1
1
2
1
1
1
0
0
8
4
4
4
8
4
4
4
0
0
up to 12
up to 48
up to 12
up to 12
up to 38
up to 24
up to 28
4
2
2
2
0
0
0
0
0
0
4
2
2
2
4
4
2
2
0
0
12
6
256
1 K
16 K
16 K
4 K
[1]
CY8C24x94
[1]
CY8C24x23A
6
256
CY8C23x33
4
256
8 K
[1]
[2]
CY8C22x45
CY8C21x45
CY8C21x34
6
1 K
16 K
8 K
[1]
[1]
[2]
6
512
[2]
4
512
8 K
[2]
CY8C21x23
up to
8
4
256
4 K
[1]
[2,3]
CY8C20x34
CY8C20xx6
up to 28
up to 36
3
512
8 K
[2,3]
3
up to 2 K
up to 32 K
Notes
1. Automotive qualified devices available in this group.
2. Limited analog functionality.
®
3. Two analog blocks and one CapSense block.
Document Number: 001-53754 Rev. *D
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CY8C24894
■ Free C compiler with no size restrictions or time limits
Getting Started
■ Built-in debugger
■ In-circuit emulation
For in depth information, along with detailed programming
details, see the PSoC® Technical Reference Manual.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web.
■ Built-in support for communication interfaces:
❐ Hardware and software I2C slaves and masters
❐ Full-speed USB 2.0
❐ Up to four full-duplex universal asynchronous receiver/trans-
mitters (UARTs), SPI master and slave, and wireless
Application Notes
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), amplifiers, and filters.
Configure the user modules for your chosen application and
connect them to each other and to the proper pins. Then
generate your project. This prepopulates your project with APIs
and libraries that you can use to program your application.
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
CYPros Consultants
Certified PSoC consultants offer everything from technical assis-
tance to completed PSoC designs. To contact or become a PSoC
consultant go to the CYPros Consultants web site.
The tool also supports easy development of multiple configura-
tions and dynamic reconfiguration. Dynamic reconfiguration
makes it possible to change configurations at run time. In
essence, this allows you to use more than 100 percent of PSoC's
resources for a given application.
Solutions Library
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Technical Support
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Development Tools
PSoC Designer™ is the revolutionary Integrated Design
Environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also allows you to create a trace buffer of registers and memory
locations of interest.
■ Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■ Extensive user module catalog
■ Integrated source-code editor (C and assembly)
Document Number: 001-53754 Rev. *D
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Online Help System
configuration to your particular application. For example, a pulse
width modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to corre-
spond to your chosen application. Enter values directly or by
selecting values from drop-down menus. All the user modules
are documented in datasheets that may be viewed directly in
PSoC Designer or on the Cypress website. These user module
datasheets explain the internal operation of the user module and
provide performance specifications. Each datasheet describes
the use of each user module parameter, and other information
you may need to successfully implement your design.
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an Online Support
Forum to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality In-Circuit Emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24-MHz) operation.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
Designing with PSoC Designer
Generate, Verify, and Debug
The development process for the PSoC® device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process is summarized in four steps:
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run time and interrupt service routines that
you can adapt as needed.
1. Select User Modules.
2. Configure user modules.
3. Organize and connect.
4. Generate, verify, and debug.
A complete code development environment allows you to
develop and customize your applications in either C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging capabil-
ities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint and watch-variable
features, the debug interface provides a large trace buffer and
allows you to define complex breakpoint events that include
monitoring address and data bus values, memory locations and
external signals.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules.” User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
Document Number: 001-53754 Rev. *D
Page 7 of 46
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CY8C24894
Pinouts
The automotive CY8C24x94 PSoC device is available in a variety of packages which are listed and illustrated in the following tables.
Every port pin (labeled with a “P”) is capable of digital I/O. However, VSS, VDD, and XRES are not capable of digital I/O.
56-Pin Part Pinout (with XRES pin)
Table 2. 56-Pin Part Pinout (QFN)
Type
Pin
No.
Figure 3. CY8C24894 56-Pin PSoC Device
Name
Description
Digital Analog
1
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I, M
I, M
M
M
M
P2[3] Direct switched capacitor block input
P2[1] Direct switched capacitor block input
3
4
5
P4[7]
P4[5]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
6
7
8
M
M
M
9
M
M
M
AI, M, P2[3]
1
2
3
4
5
6
7
8
9
42 P2[2], AI, M
AI, M, P2[1]
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
M, P3[7]
M, P3[5]
41 P2[0], AI, M
40 P4[6], M
39 P4[4], M
38 P4[2], M
37 P4[0], M
36 XRES
35 P3[4], M
34 P3[2], M
33 P3[0], M
32 P5[6], M
31 P5[4], M
30 P5[2], M
29 P5[0], M
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
M
M
M
QFN
(Top View)
2
M
M
M
P1[7] I C serial clock (SCL)
P1[5] I C serial data (SDA)
2
M, P3[3]
P1[3]
M, P3[1] 10
M, P5[7] 11
M, P5[5] 12
M, P5[3] 13
M, P5[1] 14
2
[4]
M
P1[1] I C SCL, ISSP SCLK
Power
V
Ground connection
SS
DNC
DNC
Do not connect anything to this pin
Do not connect anything to this pin
Supply voltage
Power
V
DD
I/O
I/O
I/O
I/O
I/O
I/O
P7[7]
P7[0]
2
[4]
M
M
M
M
P1[0] I C SDA, ISSP SDATA
P1[2]
P1[4] Optional external clock (EXTCLK) input
P1[6]
29
30
31
32
33
34
35
36
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
M
M
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
Type
Digital Analog
Name
Description
Pin
No.
45
46
47
48
49
I/O
I/O
I/O
I/O
I, M
I, M
I, M
I, M
P0[0] Analog column mux input
P0[2] Analog column mux input
P0[4] Analog column mux input
P0[6] Analog column mux input
Input
XRES Active high external reset with internal
pull-down
Power
V
Supply voltage
DD
37
38
39
40
41
42
43
44
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
P4[0]
50
51
52
53
54
55
56
Power
I, M
V
Ground connection
SS
P4[2]
I/O
I/O
I/O
I/O
I/O
I/O
P0[7] Analog column mux input
P4[4]
I/O, M P0[5] Analog column mux input and column output
I/O, M P0[3] Analog column mux input and column output
P4[6]
I, M
I, M
M
P2[0] Direct switched capacitor block input
P2[2] Direct switched capacitor block input
P2[4] External analog ground (AGND) input
I, M
M
P0[1] Analog column mux input
P2[7]
P2[5]
M
M
P2[6] External voltage reference (VREF) input EP
Power
V
Exposed pad is not connected internally. Connect
to circuit ground for best performance
SS
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Note
4. These are the ISSP pins, which are not high Z when coming out of reset state. See the PSoC Technical Reference Manual for details.
Document Number: 001-53754 Rev. *D
Page 8 of 46
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CY8C24894
Registers
This section lists the registers of the automotive CY8C24x94 PSoC device family. For detailed register information, refer to the PSoC
Technical Reference Manual.
Register Conventions
Register Mapping Tables
The register conventions specific to this section are listed in the
following table.
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks. The XIO bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XIO bit
is set the user is in Bank 1.
Convention
Description
Read register or bit(s)
R
W
L
Note In the following register mapping tables, blank fields are
Reserved and should not be accessed.
Write register or bit(s)
Logical register or bit(s)
Clearable register or bit(s)
Access is bit specific
C
#
Document Number: 001-53754 Rev. *D
Page 9 of 46
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CY8C24894
Register Map Bank 0 Table: User Space
Name
Addr (0,Hex) Access
Name
Addr (0,Hex) Access
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr (0,Hex) Access
Name
Addr (0,Hex) Access
PRT0DR
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RW
RW
RW
RW
RW
RW
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
RW
RW
RW
RW
RW
RW
CUR_PP
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
STK_PP
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
IDX_PP
RW
RW
RW
RW
#
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
PRT5GS
PRT5DM2
RW
#
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
PRT7DR
RW
RW
RW
RW
#
PRT7IE
PRT7GS
PRT7DM2
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
AMX_IN
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RW
RW
W
AMUXCFG
RW
#
ARF_CR
CMP_CR0
ASY_CR
CMP_CR1
RW
#
RES_WDT
DEC_DH
#
RC
RC
RW
RW
W
W
#
DEC_DL
RW
#
RW
DEC_CR0
DEC_CR1
MUL0_X
#
MUL1_X
W
W
MUL1_Y
W
MUL0_Y
W
RW
#
MUL1_DH
MUL1_DL
ACC1_DR1
ACC1_DR0
ACC1_DR3
ACC1_DR2
RDI0RI
R
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
R
R
R
#
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
RW
#
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
CPU_F
RL
DAC_D
RW
#
CPU_SCR1
CPU_SCR0
#
Blank fields are Reserved and should not be accessed.
# Access is bit specific.
Document Number: 001-53754 Rev. *D
Page 10 of 46
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CY8C24894
Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
PRT5DM1
PRT5IC0
PRT5IC1
Addr (1,Hex) Access
Name
Addr (1,Hex) Access
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr (1,Hex) Access
Name
Addr (1,Hex) Access
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RW
RW
RW
RW
RW
RW
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
RW
RW
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
RW
RW
RW
RW
RW
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
RW
RW
RW
RW
PRT7DM0
PRT7DM1
PRT7IC0
PRT7IC1
DBB00FN
DBB00IN
DBB00OU
RW
RW
RW
RW
RW
RW
RW
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
RW
RW
RW
RW
RW
RW
RW
R
CLK_CR0
CLK_CR1
ABF_CR0
AMD_CR0
CMP_GO_EN
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RW
RW
RW
RW
RW
DBB01FN
DBB01IN
DBB01OU
RW
RW
RW
VLT_CMP
AMD_CR1
ALT_CR0
RW
RW
DCB02FN
DCB02IN
DCB02OU
RW
RW
RW
IMO_TR
W
W
ILO_TR
BDG_TR
ECO_TR
MUX_CR4
MUX_CR5
RW
W
DCB03FN
DCB03IN
DCB03OU
RW
RW
RW
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RW
RW
RW
RW
RW
RW
RW
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
CPU_F
RL
DAC_CR
RW
#
CPU_SCR1
CPU_SCR0
#
Blank fields are Reserved and should not be accessed.
# Access is bit specific.
Document Number: 001-53754 Rev. *D
Page 11 of 46
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CY8C24894
Electrical Specifications
This section presents the DC and AC electrical specifications of the automotive CY8C24x94 PSoC device family. For the most up to
date electrical specifications, confirm that you have the most recent datasheet by visiting http://www.cypress.com.
Specifications are valid for –40 °C ≤ T ≤ 85 °C and T ≤ 100 °C, except where noted.
A
J
Figure 4. Voltage versus CPU Frequency
5.25
4.75
3.0
0
93 kHz
12 MHz
24 MHz
CPU Frequency
(nominal setting)
Document Number: 001-53754 Rev. *D
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CY8C24894
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 3. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage temperature
Min
Typ
Max
Units
Notes
–55
25
+100
°C
Higher storage temperatures
reduce data retention time.
Recommended storage
temperature is +25 °C ± 25 °C.
Time spent in storage at a
temperature greater than 65 °C
counts toward the FlashDR
electrical specification in Table 16
on page 25.
TBAKETEMP Bake temperature
tBAKETIME Bake time
–
125
–
See
package
label
°C
See
package
label
72
Hours
TA
Ambient temperature with power applied
–40
–0.5
–
–
–
–
–
–
+85
+6.0
°C
V
VDD
VIO
Supply voltage on VDD relative to VSS
DC input voltage
VSS – 0.5
VSS – 0.5
–25
VDD + 0.5
VDD + 0.5
+50
V
VIO2
IMIO
IMAIO
DC voltage applied to tri-state
Maximum current into any port pin
V
mA
mA
Maximum current into any port pin
configured as analog driver
–50
+50
ESD
LU
Electro static discharge voltage
Latch-up current
2000
–
–
–
–
V
Human Body Model ESD.
200
mA
Operating Temperature
Table 4. Operating Temperature
Symbol
Description
Min
–40
–40
Typ
–
Max
+85
Units
°C
°C
Notes
TA
TJ
Ambient temperature
Junction temperature
–
+100
The temperature rise from ambient
to junction is package specific. See
Table 28 on page 34. The user must
limit the power consumption to
comply with this requirement.
Document Number: 001-53754 Rev. *D
Page 13 of 46
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CY8C24894
DC Electrical Characteristics
DC Chip Level Specifications
Table 5 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C
≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for
design guidance only.
Table 5. DC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VDD
Supply voltage
3.0
–
5.25
V
See DC POR and LVD specifications,
Table 15 on page 24.
IDD5
Supply current, IMO = 24 MHz, VDD = 5 V
Supply current, IMO = 24 MHz, VDD = 3.3 V
–
–
14
8
27
14
mA
mA
Conditions are VDD = 5.0 V, TA = 25 °C,
CPU = 3 MHz, 48 MHz disabled, VC1 =
1.5MHz, VC2=93.75kHz, VC3=93.75
kHz, Analog power = off.
Conditions are VDD = 3.3 V, TA = 25 °C,
CPU = 3 MHz, 48 MHz disabled, VC1 =
1.5MHz, VC2=93.75kHz, VC3=0.367
kHz, Analog power = off.
IDD3
ISB
Sleep(mode)currentwithPOR,LVD, sleep
timer, and WDT.[5]
–
–
3
4
6.5
25
μA
μA
Conditions are with ILO active, VDD
3.3 V, –40 °C ≤ TA ≤ 55 °C, Analog
power = off.
=
ISBH
Sleep(mode)currentwithPOR,LVD, sleep
timer, and WDT at high temperature.[5]
Conditions are with ILO active, VDD
=
3.3 V, 55 °C < TA ≤ 85 °C, Analog power
= off.
DC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 6. DC GPIO Specifications
Symbol
RPU
RPD
Description
Pull-up resistor
Pull-down resistor
Min
4
4
Typ
5.6
5.6
Max
8
8
Units
kΩ
kΩ
Notes
Also applies to the internal pull-down
resistor on the XRES pin
VOH
High output level
VDD – 1.0
–
–
V
IOH = 10 mA, VDD = 4.75 V to 5.25 V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])). 80 mA
maximum combined IOH budget.
VOL
Low output level
–
–
0.75
V
IOL = 25 mA, VDD = 4.75 V to 5.25 V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])). 200
mA maximum combined IOL budget.
IOH
IOL
High level source current
Low level sink current
10
25
–
–
–
–
mA
mA
VOH ≥ VDD – 1.0 V, see the limitations
of the total current in the note for VOH
.
VOL ≤ 0.75 V, see the limitations of the
total current in the note for VOL
.
VIL
VIH
VH
IIL
Input low level
Input high level
Input hysterisis
Input leakage (absolute value)
Capacitive load on pins as input
–
2.1
–
–
–
–
–
60
1
0.8
–
–
–
10
V
V
mV
nA
pF
VDD = 3.0 V to 5.25 V.
VDD = 3.0 V to 5.25 V.
Gross tested to 1 μA.
Package and pin dependent.
TA = 25 °C.
CIN
3.5
COUT
Capacitive load on pins as output
–
3.5
10
pF
Package and pin dependent.
TA = 25 °C.
Note
5. Standby current includes all functions (POR, LVD, WDT, sleep timer) needed for reliable system operation. This should be compared with devices that have similar
functions enabled.
Document Number: 001-53754 Rev. *D
Page 14 of 46
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CY8C24894
DC Operational Amplifier Specifications
Table 7 and Table 8 on page 16 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges:
4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V
and 3.3 V at 25 °C and are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time (CT) PSoC blocks and the Analog Switched Capacitor
(SC) PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.
Table 7. 5-V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VOSOA
Input offset voltage (absolute value)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
–
–
–
–
–
–
1.6
1.3
1.2
10
8
7.5
mV
mV
mV
TCVOSOA Average input offset voltage Drift
7.0
20
35.0
–
μV/°C
pA
IEBOA
CINOA
Input leakage current (Port 0 Analog Pins)
Input capacitance (Port 0 Analog Pins)
Gross tested to 1 μA.
Package and pin dependent. TA =
25 °C.
4.5
9.5
pF
VCMOA
Common Mode Voltage Range
All cases, except highest
Power = high, Opamp bias = high
The common-mode input voltage
range is measured through an
analog output buffer. The specifi-
cation includes the limitations
imposed by the characteristics of
the analog output buffer.
0.0
0.5
–
–
VDD
VDD – 0.5
V
V
GOLOA
Open loop gain
Specification is applicable at high
power. For all other bias modes
(except high power, high Opamp
bias), minimum is 60 dB.
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
60
60
80
–
–
–
–
–
–
dB
dB
dB
VOHIGHOA High output voltage swing (internal
signals)
VDD – 0.2
–
–
–
–
–
–
V
V
V
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
VDD – 0.2
DD – 0.5
V
VOLOWOA Low output voltage swing (internal
signals)
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
ISOA
Supply current (including associated
AGND buffer)
Power = low, Opamp bias = low
Power = low, Opamp bias = high
Power = medium, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = low
Power = high, Opamp bias = high
–
–
–
–
–
–
400
500
800
1200
2400
4600
800
900
1000
1600
3200
6400
μA
μA
μA
μA
μA
μA
PSRROA Supply voltage rejection ratio
65
80
–
dB
VSS ≤ VIN ≤ (VDD – 2.25 V) or (VDD
– 1.25 V) ≤ VIN ≤ VDD
.
Document Number: 001-53754 Rev. *D
Page 15 of 46
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CY8C24894
Table 8. 3.3-V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VOSOA
Input offset voltage (absolute value)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
Power = high, Opamp bias =
–
–
–
1.65
1.32
–
10
8
–
mV high setting is not allowed for
mV 3.3 V VDD operation
mV
TCVOSOA Average input offset voltage drift
–
–
–
7.0
20
35.0
–
µV/°C
IEBOA
CINOA
Input leakage current (Port 0 analog pins)
Input capacitance (Port 0 analog pins)
pA
pF
Gross tested to 1 µA.
4.5
9.5
Package and pin dependent.
TA = 25 °C.
VCMOA
Common mode voltage range
0.2
–
VDD – 0.2
V
The common-mode input
voltage range is measured
through an analog output
buffer. The specification
includes the limitations
imposed by the characteristics
of the analog output buffer.
GOLOA
Open loop gain
Specification is applicable at
low Opamp bias. For high
Opampbiasmode(excepthigh
power, high Opamp bias),
minimum is 60 dB.
Power = low, Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
60
60
80
–
–
–
–
–
–
dB
dB
dB
VOHIGHOA High output voltage swing (internal signals)
Power = low, Opamp bias = low
VDD – 0.2
VDD – 0.2
VDD – 0.2
–
–
–
–
–
–
V
V
V
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
VOLOWOA Low output voltage swing (internal signals)
Power = low, Opamp bias = low
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
ISOA
Supply current
Power = high, Opamp bias =
high setting is not allowed for
3.3 V VDD operation
(including associated AGND buffer)
Power = low, Opamp bias = low
Power = low, Opamp bias = high
Power = medium, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = low
Power = high, Opamp bias = high
–
–
–
–
–
–
400
500
800
1200
2400
–
800
900
1000
1600
3200
–
µA
µA
µA
µA
µA
µA
PSRROA Supply voltage rejection ratio
65
80
–
dB
VSS ≤ VIN ≤ (VDD – 2.25) or
(VDD – 1.25 V) ≤ VIN ≤ VDD
DC Low Power Comparator Specifications
Table 9 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C
≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V at 25 °C and are for design
guidance only.
Table 9. DC Low Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VREFLPC
Low power comparator (LPC) reference
voltage range
0.2
–
VDD – 1.0
V
ISLPC
LPC supply current
LPC voltage offset
–
–
10
55
55
μA
mV
VOSLPC
2.5
Document Number: 001-53754 Rev. *D
Page 16 of 46
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CY8C24894
DC Analog Output Buffer Specifications
Table 10 and Table 11 on page 18 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges:
4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V
and 3.3 V at 25 °C and are for design guidance only.
Table 10. 5-V DC Analog Output Buffer Specifications
Symbol
Description
Min
–
Typ
3
Max
Units
mV
Notes
VOSOB
Input offset voltage (absolute value)
12
–
TCVOSOB Average input offset voltage drift
VCMOB
–
+6
–
µV/°C
V
Common mode input voltage range
0.5
VDD – 1.0
ROUTOB
Output resistance
Power = low
–
–
0.6
0.6
–
–
Ω
Ω
Power = high
VOHIGHOB High output voltage swing
(load = 32 Ω to VDD/2)
Power = low
0.5 × VDD + 1.1
0.5 × VDD + 1.1
–
–
–
–
V
V
Power = high
VOLOWOB Low output voltage swing
(load = 32 Ω to VDD/2)
Power = low
–
–
–
–
0.5 × VDD – 1.3
0.5 × VDD – 1.3
V
V
Power = high
ISOB
Supply current including opamp
bias cell (no load)
Power = low
–
–
1.1
2.6
5.1
8.8
mA
mA
Power = high
PSRROB
CL
Supply voltage rejection ratio
53
64
–
dB
(0.5 × VDD – 1.3) ≤ VOUT ≤
(VDD – 2.3).
This specification applies to
the external circuit that is being
driven by the analog output
buffer.
Load capacitance
–
–
200
pF
Document Number: 001-53754 Rev. *D
Page 17 of 46
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CY8C24894
Table 11. 3.3-V DC Analog Output Buffer Specifications
Symbol
Description
Min
–
Typ
3
Max
Units
mV
Notes
VOSOB
Input offset voltage (absolute value)
12
–
TCVOSOB Average input offset voltage drift
VCMOB
–
+6
–
µV/°C
V
Common mode input voltage range
0.5
VDD – 1.0
ROUTOB
Output resistance
Power = low
–
–
1
1
–
–
Ω
Ω
Power = high
VOHIGHOB High output voltage swing
(load = 1 KΩ to VDD/2)
Power = low
0.5 × VDD + 1.0
0.5 × VDD + 1.0
–
–
–
–
V
V
Power = high
VOLOWOB Low output voltage swing
(load = 1 KΩ to VDD/2)
Power = low
–
–
–
–
0.5 × VDD – 1.0
0.5 × VDD – 1.0
V
V
Power = high
ISOB
Supply current including opamp
bias cell (no load)
Power = low
–
–
0.8
2.0
2.0
4.3
mA
mA
Power = high
PSRROB
CL
Supply voltage rejection ratio
Load capacitance
34
64
–
dB
(0.5 × VDD – 1.0) ≤ VOUT ≤ (0.5
× VDD + 0.9).
Thisspecificationappliestothe
external circuit that is being
driven by the analog output
buffer.
–
–
200
pF
Document Number: 001-53754 Rev. *D
Page 18 of 46
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CY8C24894
DC Analog Reference Specifications
Table 12 and Table 13 on page 22 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges:
4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V
and 3.3 V at 25 °C. These are for design guidance only.
The guaranteed specifications are measured through the analog CT PSoC blocks. The power levels for AGND refer to the power of
the analog CT PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for
AGND include the offset error of the AGND buffer local to the analog CT PSoC block. Reference control power is high.
Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the analog reference. Some coupling of
the digital signal may appear on the AGND.
Table 12. 5-V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
Reference Power
Symbol Reference
Description
Min
Typ
Max
Units
Settings
0b000
RefPower = high
Opamp bias = high
V
Ref High
AGND
V
V
V
V
V
V
V
V
V
V
V
V
/2 + Bandgap
/2
V
V
V
V
V
V
V
V
V
V
V
V
/2 + 1.229
/2 – 0.038
/2 – 1.356
/2 + 1.220
/2 – 0.036
/2 – 1.357
/2 + 1.221
/2 – 0.036
/2 – 1.357
/2 + 1.219
/2 – 0.037
/2 – 1.359
V
/2 + 1.290
V
V
V
V
V
V
V
V
V
V
V
V
/2 + 1.346
/2 + 0.040
/2 – 1.218
/2 + 1.348
/2 + 0.036
/2 – 1.225
/2 + 1.351
/2 + 0.036
/2 – 1.228
/2 + 1.353
/2 + 0.036
/2 – 1.229
V
V
V
V
V
V
V
V
V
V
V
V
V
REFHI
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
V
V
/2
AGND
DD
V
Ref Low
Ref High
AGND
/2 – Bandgap
/2 + Bandgap
/2
V
V
/2 – 1.295
/2 + 1.292
REFLO
V
REFHI
DD
DD
RefPower = high
Opamp bias = low
V
V
/2
AGND
DD
V
Ref Low
Ref High
AGND
/2 – Bandgap
/2 + Bandgap
/2
V
V
/2 – 1.297
/2 + 1.293
REFLO
REFHI
AGND
REFLO
REFHI
AGND
REFLO
DD
DD
RefPower = medium V
Opamp bias = high
V
V
/2
DD
V
Ref Low
Ref High
AGND
/2 – Bandgap
/2 + Bandgap
/2
V
V
V
V
/2 – 1.298
/2 + 1.293
/2 – 0.001
/2 – 1.299
DD
DD
DD
DD
RefPower = medium V
Opamp bias = low
V
V
Ref Low
Ref High
/2 – Bandgap
0b001
RefPower = high
Opamp bias = high
V
P2[4]+P2[6] (P2[4] =
/2, P2[6] = 1.3 V)
P2[4] + P2[6] – P2[4]+P2[6]– P2[4]+P2[6]+
REFHI
V
0.092
0.011
0.064
DD
V
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
AGND
V
Ref Low
P2[4]–P2[6] (P2[4] =
P2[4] – P2[6] – P2[4]–P2[6]+ P2[4]–P2[6]+
0.031 0.007 0.056
P2[4] + P2[6] – P2[4]+P2[6]– P2[4]+P2[6]+
V
REFLO
V
/2, P2[6] = 1.3 V)
DD
RefPower = high
Opamp bias = low
V
Ref High
P2[4]+P2[6] (P2[4] =
/2, P2[6] = 1.3 V)
V
REFHI
V
0.078
0.008
0.063
DD
V
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
AGND
V
Ref Low
P2[4]–P2[6] (P2[4] =
P2[4] – P2[6] – P2[4]–P2[6]+ P2[4]–P2[6]+
0.031 0.004 0.043
P2[4] + P2[6] – P2[4]+P2[6]– P2[4]+P2[6]+
V
REFLO
V
/2, P2[6] = 1.3 V)
DD
RefPower = medium V
Opamp bias = high
Ref High
P2[4]+P2[6] (P2[4] =
/2, P2[6] = 1.3 V)
V
REFHI
V
0.073
0.006
0.062
DD
V
V
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
AGND
Ref Low
P2[4]–P2[6] (P2[4] =
P2[4] – P2[6] – P2[4]–P2[6]+ P2[4]–P2[6]+
0.032 0.003 0.038
P2[4] + P2[6] – P2[4]+P2[6]– P2[4]+P2[6]+
V
REFLO
V
/2, P2[6] = 1.3 V)
DD
RefPower = medium V
Opamp bias = low
Ref High
P2[4]+P2[6] (P2[4] =
/2, P2[6] = 1.3 V)
V
REFHI
V
0.073
0.006
0.062
DD
V
V
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
AGND
Ref Low
P2[4]–P2[6] (P2[4] =
P2[4] – P2[6] – P2[4]–P2[6]+ P2[4]–P2[6]+
0.034 0.002 0.037
V
REFLO
V
/2, P2[6] = 1.3 V)
DD
Document Number: 001-53754 Rev. *D
Page 19 of 46
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CY8C24894
Table 12. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
Reference Power
Symbol Reference
Description
Min
Typ
Max
Units
Settings
0b010
0b011
0b100
RefPower = high
Opamp bias = high
V
Ref High
AGND
V
V
V
V
V
V
V
V
V
V
V
V
V
– 0.037
V
– 0.007
V
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
REFHI
DD
DD
SS
DD
DD
SS
DD
DD
SS
DD
DD
SS
DD
DD
V
/2
V
/2 – 0.036
V
/2 – 0.001
V
/2 + 0.036
AGND
DD
DD
DD
DD
DD
DD
V
Ref Low
Ref High
AGND
V
V
V
+ 0.005
– 0.006
V
+ 0.029
REFLO
REFHI
SS
SS
DD
SS
RefPower = high
Opamp bias = low
V
V
– 0.034
V
DD
DD
V
/2
/2
/2
V
/2 – 0.036
V /2 – 0.001
DD
V
/2 + 0.035
+ 0.024
AGND
DD
V
Ref Low
Ref High
AGND
V
V
V
+ 0.004
– 0.005
V
REFLO
REFHI
AGND
REFLO
REFHI
AGND
REFLO
SS
SS
DD
SS
RefPower = medium V
Opamp bias = high
V
– 0.032
V
DD
DD
V
V
/2 – 0.036
V
/2 – 0.001
V
/2 + 0.035
+ 0.022
DD
DD
V
Ref Low
Ref High
AGND
V
V
V
+ 0.003
– 0.005
V
SS
SS
SS
RefPower = medium V
Opamp bias = low
V
– 0.031
V
DD
DD
DD
V
V
/2 – 0.037
V
/2 – 0.001
V
/2 + 0.035
+ 0.020
DD
DD
V
Ref Low
Ref High
AGND
V
V
+ 0.003
V
SS
SS
SS
RefPower = high
Opamp bias = high
V
3 × Bandgap
2 × Bandgap
Bandgap
3.760
2.522
1.252
3.766
2.523
1.252
3.769
2.523
1.251
3.769
2.523
1.251
3.884
2.593
1.299
3.887
2.594
1.297
3.888
2.594
1.296
3.889
2.595
1.296
4.006
2.669
1.342
4.010
2.670
1.342
4.013
2.671
1.343
4.015
2.671
1.344
REFHI
V
AGND
V
Ref Low
Ref High
AGND
REFLO
REFHI
RefPower = high
Opamp bias = low
V
3 × Bandgap
2 × Bandgap
Bandgap
V
AGND
V
Ref Low
Ref High
AGND
REFLO
REFHI
AGND
REFLO
REFHI
AGND
REFLO
RefPower = medium V
Opamp bias = high
3 × Bandgap
2 × Bandgap
Bandgap
V
V
Ref Low
Ref High
AGND
RefPower = medium V
Opamp bias = low
3 × Bandgap
2 × Bandgap
Bandgap
V
V
Ref Low
Ref High
RefPower = high
Opamp bias = high
V
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.483 – P2[6] 2.582 – P2[6] 2.674 – P2[6]
REFHI
V
AGND
2 × Bandgap
2.522 2.593 2.669
V
V
AGND
V
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.524 – P2[6] 2.600 – P2[6] 2.676 – P2[6]
2.490 – P2[6] 2.586 – P2[6] 2.679 – P2[6]
REFLO
RefPower = high
Opamp bias = low
V
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
V
REFHI
V
AGND
2 × Bandgap
2.523
2.594
2.669
V
V
AGND
V
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.523 – P2[6] 2.598 – P2[6] 2.675 – P2[6]
REFLO
RefPower = medium V
Opamp bias = high
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.493 – P2[6] 2.588 – P2[6] 2.682 – P2[6]
V
REFHI
V
V
AGND
2 × Bandgap
2.523
2.594
2.670
V
V
AGND
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.523 – P2[6] 2.597 – P2[6] 2.675 – P2[6]
REFLO
RefPower = medium V
Opamp bias = low
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.494 – P2[6] 2.589 – P2[6] 2.685 – P2[6]
V
REFHI
V
V
AGND
2 × Bandgap
2.523
2.595
2.671
V
V
AGND
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.522 – P2[6] 2.596 – P2[6] 2.676 – P2[6]
REFLO
Document Number: 001-53754 Rev. *D
Page 20 of 46
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CY8C24894
Table 12. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
Reference Power
Symbol Reference
Description
Min
P2[4] + 1.218 P2[4] + 1.291 P2[4] + 1.354
P2[4] P2[4] P2[4]
Typ
Max
Units
Settings
0b101
RefPower = high
V
Ref High
P2[4] + Bandgap
V
REFHI
Opamp bias = high
(P2[4] = V /2)
DD
V
AGND
P2[4]
–
AGND
V
Ref Low
P2[4] – Bandgap
P2[4] – 1.335 P2[4] – 1.294 P2[4] – 1.237
V
REFLO
(P2[4] = V /2)
DD
RefPower = high
Opamp bias = low
V
Ref High
P2[4] + Bandgap
P2[4] + 1.221 P2[4] + 1.293 P2[4] + 1.358
V
REFHI
(P2[4] = V /2)
DD
V
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
AGND
V
Ref Low
P2[4] – Bandgap
P2[4] – 1.337 P2[4] – 1.297 P2[4] – 1.243
V
REFLO
(P2[4] = V /2)
DD
RefPower = medium V
Opamp bias = high
Ref High
P2[4] + Bandgap
P2[4] + 1.222 P2[4] + 1.294 P2[4] + 1.360
V
REFHI
(P2[4] = V /2)
DD
V
V
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
AGND
Ref Low
P2[4] – Bandgap
P2[4] – 1.338 P2[4] – 1.298 P2[4] – 1.245
V
REFLO
(P2[4] = V /2)
DD
RefPower = medium V
Opamp bias = low
Ref High
P2[4] + Bandgap
P2[4] + 1.221 P2[4] + 1.294 P2[4] + 1.362
V
REFHI
(P2[4] = V /2)
DD
V
V
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
AGND
Ref Low
P2[4] – Bandgap
P2[4] – 1.340 P2[4] – 1.298 P2[4] – 1.245
V
REFLO
(P2[4] = V /2)
DD
0b110
RefPower = high
Opamp bias = high
V
Ref High
AGND
2 × Bandgap
Bandgap
2.513
1.264
2.593
1.302
2.672
1.340
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
REFHI
V
AGND
V
Ref Low
Ref High
AGND
V
V
V
V
V
V
V
V
V
V
+ 0.008
V
V
V
V
V
V
V
V
+ 0.038
REFLO
REFHI
SS
SS
SS
SS
RefPower = high
Opamp bias = low
V
2 × Bandgap
Bandgap
2.514
1.264
2.593
1.301
2.674
1.340
V
AGND
V
Ref Low
Ref High
AGND
V
V
+ 0.005
+ 0.028
SS
REFLO
REFHI
AGND
REFLO
REFHI
AGND
REFLO
SS
SS
SS
RefPower = medium V
Opamp bias = high
2 × Bandgap
Bandgap
2.514
1.264
2.593
1.301
2.676
1.340
V
V
Ref Low
Ref High
AGND
V
V
+ 0.004
+ 0.024
SS
SS
SS
SS
RefPower = medium V
Opamp bias = low
2 × Bandgap
Bandgap
2.514
1.264
2.593
1.300
2.677
1.340
V
V
Ref Low
Ref High
AGND
V
V
+ 0.003
+ 0.021
SS
SS
SS
SS
0b111
RefPower = high
Opamp bias = high
V
3.2 × Bandgap
1.6 × Bandgap
4.028
2.028
4.144
2.076
4.242
2.125
REFHI
V
AGND
V
Ref Low
Ref High
AGND
V
V
+ 0.008
+ 0.034
SS
REFLO
REFHI
SS
SS
SS
RefPower = high
Opamp bias = low
V
3.2 × Bandgap
1.6 × Bandgap
4.032
2.029
4.142
2.076
4.245
2.126
V
AGND
V
Ref Low
Ref High
AGND
V
V
+ 0.005
+ 0.025
SS
REFLO
REFHI
AGND
REFLO
REFHI
AGND
REFLO
SS
SS
SS
RefPower = medium V
Opamp bias = high
3.2 × Bandgap
1.6 × Bandgap
4.034
2.029
4.143
2.076
4.247
2.126
V
V
Ref Low
Ref High
AGND
V
V
+ 0.004
+ 0.021
SS
SS
SS
SS
RefPower = medium V
Opamp bias = low
3.2 × Bandgap
1.6 × Bandgap
4.036
2.029
4.144
2.076
4.249
2.126
V
V
Ref Low
V
V
+ 0.003
+ 0.019
SS
SS
SS
SS
Document Number: 001-53754 Rev. *D
Page 21 of 46
[+] Feedback
CY8C24894
Table 13. 3.3-V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
Reference Power
Symbol Reference
Description
Min
Typ
Max
Units
Settings
0b000
RefPower = high
Opamp bias = high
V
Ref High
AGND
V
V
V
V
V
V
V
V
V
V
V
V
/2 + Bandgap
/2
V
V
V
V
V
V
V
V
V
V
V
V
/2 + 1.200
/2 – 0.030
/2 – 1.346
/2 + 1.196
/2 – 0.029
/2 – 1.349
/2 + 1.204
/2 – 0.030
/2 – 1.351
/2 + 1.189
/2 – 0.032
/2 – 1.353
V
/2 + 1.290
V
V
V
V
V
V
V
V
V
V
V
V
/2 + 1.365
/2 + 0.034
/2 – 1.208
/2 + 1.374
/2 + 0.031
/2 – 1.227
/2 + 1.369
/2 + 0.030
/2 – 1.229
/2 + 1.384
/2 + 0.029
/2 – 1.230
V
V
V
V
V
V
V
V
V
V
V
V
V
REFHI
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
V
V
/2
DD
AGND
V
Ref Low
Ref High
AGND
/2 – Bandgap
/2 + Bandgap
/2
V
V
/2 – 1.292
/2 + 1.292
REFLO
V
REFHI
DD
DD
RefPower = high
Opamp bias = low
V
V
/2
DD
AGND
V
Ref Low
Ref High
AGND
/2 – Bandgap
/2 + Bandgap
/2
V
V
/2 – 1.295
/2 + 1.293
REFLO
REFHI
AGND
REFLO
REFHI
AGND
REFLO
DD
DD
RefPower = medium V
Opamp bias = high
V
V
/2
DD
V
Ref Low
Ref High
AGND
/2 – Bandgap
/2 + Bandgap
/2
V
V
/2 – 1.297
/2 + 1.294
DD
DD
RefPower = medium V
Opamp bias = low
V
V
/2
DD
V
Ref Low
Ref High
/2 – Bandgap
V
/2 – 1.297
DD
0b001
RefPower = high
V
P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4]+P2[6]– P2[4]+P2[6]+
REFHI
Opamp bias = high
V
/2, P2[6] = 0.5 V)
0.105
0.008
0.095
DD
V
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
AGND
V
Ref Low
P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4]–P2[6]+ P2[4]–P2[6]+
/2, P2[6] = 0.5 V) 0.035 0.006 0.053
P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4]+P2[6]– P2[4]+P2[6]+
V
REFLO
V
DD
RefPower = high
Opamp bias = low
V
Ref High
V
REFHI
V
/2, P2[6] = 0.5 V)
0.094
0.005
0.073
DD
V
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
AGND
V
Ref Low
P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4]–P2[6]+ P2[4]–P2[6]+
/2, P2[6] = 0.5 V) 0.033 0.002 0.042
P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4]+P2[6]– P2[4]+P2[6]+
V
REFLO
V
DD
RefPower = medium V
Opamp bias = high
Ref High
V
REFHI
V
/2, P2[6] = 0.5 V)
0.094
0.003
0.075
DD
V
V
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
AGND
Ref Low
P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] P2[4]–P2[6]+
/2, P2[6] = 0.5 V) 0.035 0.038
P2[4]+P2[6] (P2[4] = P2[4] + P2[6] – P2[4]+P2[6]– P2[4]+P2[6]+
V
REFLO
V
DD
RefPower = medium V
Opamp bias = low
Ref High
V
REFHI
V
/2, P2[6] = 0.5 V)
0.095
0.003
0.080
DD
V
V
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
AGND
Ref Low
P2[4]–P2[6] (P2[4] = P2[4] – P2[6] – P2[4] – P2[6] P2[4]–P2[6]+
V
REFLO
V
V
V
V
V
V
V
V
V
V
V
V
V
/2, P2[6] = 0.5 V)
0.038
0.038
DD
DD
DD
SS
DD
DD
SS
DD
DD
SS
DD
DD
SS
0b010
RefPower = high
Opamp bias = high
V
Ref High
AGND
V
– 0.119
V
– 0.005
V
DD
V
V
V
V
V
V
V
V
V
V
V
V
REFHI
DD
DD
V
/2
V
/2 – 0.028
V
/2
V
/2 + 0.029
AGND
DD
DD
DD
DD
DD
DD
V
Ref Low
Ref High
AGND
V
V
V
+ 0.004
– 0.004
V
+ 0.022
SS
REFLO
REFHI
SS
SS
DD
RefPower = high
Opamp bias = low
V
V
– 0.131
V
DD
DD
V
/2
/2
/2
V
/2 – 0.028
V /2
DD
V
/2 + 0.028
+ 0.021
AGND
DD
V
Ref Low
Ref High
AGND
V
V
V
+ 0.003
– 0.003
V
REFLO
REFHI
AGND
REFLO
REFHI
AGND
REFLO
SS
SS
DD
SS
RefPower = medium V
Opamp bias = high
V
– 0.111
V
DD
DD
V
V
/2 – 0.029
V
/2
DD
V
/2 + 0.028
+ 0.017
DD
V
Ref Low
Ref High
AGND
V
V
V
+ 0.002
– 0.003
V
SS
SS
DD
SS
RefPower = medium V
Opamp bias = low
V
– 0.128
V
DD
DD
V
V
/2 – 0.029
V
/2
DD
V
/2 + 0.029
+ 0.019
DD
V
Ref Low
V
V
+ 0.002
V
SS
SS
SS
Document Number: 001-53754 Rev. *D
Page 22 of 46
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CY8C24894
Table 13. 3.3-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
Reference Power
Symbol Reference
Description
Min
–
Typ
–
Max
–
Units
Settings
0b011
0b100
0b101
All power settings.
Not allowed for 3.3 V.
–
–
–
–
–
–
V
All power settings.
Not allowed for 3.3 V.
–
–
–
–
–
RefPower = high
V
Ref High
P2[4] + Bandgap
P2[4] + 1.214 P2[4] + 1.291 P2[4] + 1.359
P2[4] P2[4] P2[4]
REFHI
Opamp bias = high
(P2[4] = V /2)
DD
V
AGND
P2[4]
–
AGND
V
Ref Low
P2[4] – Bandgap
P2[4] – 1.335 P2[4] – 1.292 P2[4] – 1.200
V
REFLO
(P2[4] = V /2)
DD
RefPower = high
Opamp bias = low
V
Ref High
P2[4] + Bandgap
P2[4] + 1.219 P2[4] + 1.293 P2[4] + 1.357
V
REFHI
(P2[4] = V /2)
DD
V
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
AGND
V
Ref Low
P2[4] – Bandgap
P2[4] – 1.335 P2[4] – 1.295 P2[4] – 1.243
V
REFLO
(P2[4] = V /2)
DD
RefPower = medium V
Opamp bias = high
Ref High
P2[4] + Bandgap
P2[4] + 1.222 P2[4] + 1.294 P2[4] + 1.356
V
REFHI
(P2[4] = V /2)
DD
V
V
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
AGND
Ref Low
P2[4] – Bandgap
P2[4] – 1.337 P2[4] – 1.296 P2[4] – 1.244
V
REFLO
(P2[4] = V /2)
DD
RefPower = medium V
Opamp bias = low
Ref High
P2[4] + Bandgap
P2[4] + 1.224 P2[4] + 1.295 P2[4] + 1.355
V
REFHI
(P2[4] = V /2)
DD
V
V
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
AGND
Ref Low
P2[4] – Bandgap
P2[4] – 1.339 P2[4] – 1.297 P2[4] – 1.244
V
REFLO
(P2[4] = V /2)
DD
0b110
RefPower = high
Opamp bias = high
V
Ref High
AGND
2 × Bandgap
Bandgap
2.510
1.276
2.595
1.301
2.655
1.332
V
V
V
V
V
V
V
V
V
V
V
V
–
REFHI
V
AGND
V
Ref Low
Ref High
AGND
V
V
V
V
V
V
+ 0.006
V
V
V
V
+ 0.031
SS
REFLO
REFHI
SS
SS
SS
RefPower = high
Opamp bias = low
V
2 × Bandgap
Bandgap
2.513
1.275
2.594
1.301
2.656
1.331
V
AGND
V
Ref Low
Ref High
AGND
V
V
+ 0.004
+ 0.021
SS
REFLO
REFHI
AGND
REFLO
REFHI
AGND
REFLO
SS
SS
SS
RefPower = medium V
Opamp bias = high
2 × Bandgap
Bandgap
2.516
1.275
2.595
1.301
2.657
1.331
V
V
Ref Low
Ref High
AGND
V
V
+ 0.003
+ 0.017
SS
SS
SS
SS
RefPower = medium V
Opamp bias = low
2 × Bandgap
Bandgap
2.520
1.275
2.595
1.300
2.658
1.331
V
V
Ref Low
–
V
–
V
+ 0.002
–
+ 0.015
–
SS
SS
SS
SS
0b111
All power settings.
–
–
Not allowed for 3.3 V.
Document Number: 001-53754 Rev. *D
Page 23 of 46
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CY8C24894
DC Analog PSoC Block Specifications
Table 14 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40
°C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are
for design guidance only.
Table 14. DC Analog PSoC Block Specifications
Symbol
RCT
Description
Min
–
Typ
12.2
80
Max
–
Units
kΩ
fF
Notes
Resistor unit value (continuous time)
Capacitor unit value (switched capacitor)
CSC
–
–
DC POR and LVD Specifications
Table 15 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40
°C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and are
for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Technical Reference Manual
for more information on the VLT_CR register.
Table 15. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VDD Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
VDD must be greater than or equal
to 2.5 V during startup, reset from
the XRES pin, or reset from
watchdog.
VPPOR0
VPPOR1
VPPOR2
–
–
–
2.82
4.39
4.55
–
–
–
V
V
V
PORLEV[1:0] = 10b
PPOR Hysteresis
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VPH0
VPH1
VPH2
–
–
–
92
0
0
–
–
–
mV
mV
mV
VDD Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
2.86
2.96
3.07
3.92
4.39
4.55
4.63
4.72
2.92
3.02
3.13
4.00
4.48
4.64
4.73
4.81
3.02[6]
3.12
3.24
V
V
V
V
V
V
V
V
4.12
4.62
4.78[7]
4.87
4.96
Notes
6. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
7. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
Document Number: 001-53754 Rev. *D
Page 24 of 46
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CY8C24894
DC Programming Specifications
Table 16 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40
°C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are
for design guidance only.
Table 16. DC Programming Specifications
Symbol
VDDP
Description
Min
Typ
Max
Units
Notes
VDD for programming and erase
4.5
5.0
5.5
V
This specification applies to
the functional requirements of
external programmer tools
VDDLV
Low VDD for verify
High VDD for verify
3.0
5.1
3.0
3.1
5.2
–
3.2
5.3
V
V
V
This specification applies to
the functional requirements of
external programmer tools
VDDHV
This specification applies to
the functional requirements of
external programmer tools
VDDIWRITE Supply voltage for flash write operation
5.25
This specification applies to
this device when it is
executing internal flash writes
IDDP
VILP
VIHP
IILP
Supply current during programming or verify
Input low voltage during programming or verify
Input high voltage during programming or verify
–
–
15
–
30
0.8
–
mA
V
2.1
–
–
V
Input current when applying VILP to P1[0] or
P1[1] during programming or verify
–
0.2
mA
Driving internal pull-down
resistor.
IIHP
Input current when applying VIHP to P1[0] or
P1[1] during programming or verify
–
–
–
–
–
1.5
0.75
VDD
mA
V
Driving internal pull-down
resistor.
VOLV
VOHV
Output low voltage during programming or
verify
Output high voltage during programming or
verify
VDD – 1.0
V
FlashENPB Flash endurance (per block)[8, 9]
FlashENT Flash endurance (total)[9, 10]
1,000
256,000
10
–
–
–
–
–
–
–
–
Erase/write cycles per block.
Erase/write cycles.
FlashDR
Flash data retention[9]
Years
Notes
8. The erase/write cycle limit per block (Flash
) is only guaranteed if the device operates within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to
ENPB
5.25 V.
9. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the temperature
argument before writing. Refer to the Flash APIs Application Note AN2015 for more information.
10. The maximum total number of allowed erase/write cycles is the minimum Flash
value multiplied by the number of flash blocks in the device.
ENPB
Document Number: 001-53754 Rev. *D
Page 25 of 46
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CY8C24894
AC Electrical Characteristics
AC Chip-Level Specifications
Table 17 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40
°C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are
for design guidance only.
Table 17. AC Chip-Level Specifications
Symbol
Description
Min
23.04[11]
Typ
Max
24.96[11]
Units
Notes
FIMO245V
IMO frequency for 24 MHz (5 V
nominal)
24
MHz Trimmed for 5 V operation using
factory trim values.
FIMO243V
IMO frequency for 24 MHz (3.3 V
nominal)
22.08[11]
24
25.92[11]
MHz Trimmedfor3.3Voperationusing
factory trim values.
FCPU1
FCPU2
FBLK5
CPU frequency (5 V nominal)
CPU frequency (3.3 V nominal)
0.090[11]
0.086[11]
0
24
12
48
24.96[11]
12.96[11]
49.92[11,12]
MHz SLIMO mode = 0.
MHz SLIMO mode = 0.
Digital PSoC block frequency (5 V
nominal)
MHz Refer to the AC Digital Block
Specifications.
FBLK3
F32K1
F32KU
Digital PSoC block frequency (3.3 V
nominal)
0
15
5
24
32
–
25.92[11,12]
MHz Refer to the AC Digital Block
Specifications.
ILO frequency
64
kHz This specification applies when
the ILO has been trimmed.
ILO untrimmed frequency
100
kHz After a reset and before the M8C
processor starts to execute, the
ILO is not trimmed.
tXRST
External reset pulse width
24 MHz duty cycle
10
–
–
60
µs
DC24M
DCILO
40
50
50
50
48
–
%
ILO duty cycle
20
80
%
Step24M
Fout48M
FMAX
24 MHz trim step size
48 MHz output frequency
–
46.08[11]
–
–
kHz
49.92[11]
12.96[11]
MHz 4.75 V ≤ VDD ≤ 5.25 V
MHz
Maximum frequency of signal on row
input or row output.
SRPOWERUP Power supply slew rate
–
–
–
250
100
V/ms VDD slew rate during power-up.
tPOWERUP
Time between end of POR state and
16
ms
Power-up from 0 V.
CPU code execution
[13]
t
24 MHz IMO cycle-to-cycle jitter (RMS)
–
–
200
900
1200
6000
ps
ps
JIT_IMO
24 MHz IMO long term N cycle-to-cycle
jitter (RMS)
N = 32
24 MHz IMO period jitter (RMS)
–
200
900
ps
Notes
11. Accuracy derived from IMO with appropriate trim for V range.
DD
12. See the individual user module datasheets for information on maximum frequencies for user modules.
13. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 001-53754 Rev. *D
Page 26 of 46
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CY8C24894
AC GPIO Specifications
Table 18 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40
°C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are
for design guidance only.
Table 18. AC GPIO Specifications
Symbol
FGPIO
tRISEF
tFALLF
tRISES
tFALLS
Description
Min
0
Typ
–
Max
Units
Notes
GPIO operating frequency
12.96[14] MHz Normal Strong Mode
Rise time, normal strong mode, Cload = 50 pF
Fall time, normal strong mode, Cload = 50 pF
Rise time, slow strong mode, Cload = 50 pF
Fall time, slow strong mode, Cload = 50 pF
3
–
18
18
–
ns
ns
ns
ns
VDD = 4.5 to 5.25 V, 10% to 90%
VDD = 4.5 to 5.25 V, 10% to 90%
VDD = 3 to 5.25 V, 10% to 90%
VDD = 3 to 5.25 V, 10% to 90%
2
–
10
10
27
22
–
Figure 5. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
t
t
FALLF
RISEF
t
FALLS
t
T
RISES
Note
14. Specification derived from the accuracy of the Internal Main Oscillator (IMO) with appropriate trim for V range.
DD
Document Number: 001-53754 Rev. *D
Page 27 of 46
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CY8C24894
AC Operational Amplifier Specifications
Table 19 and Table 20 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V
at 25 °C and are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = high and Opamp bias = high is not supported at 3.3 V.
Table 19. 5-V AC Operational Amplifier Specifications
Symbol
tROA
Description
Min
Typ
Max
Units
Rising settling time from 80% of ΔV to 0.1% of ΔV
(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
–
–
–
–
–
–
3.9
0.72
0.62
µs
µs
µs
tSOA
Falling settling time from 20% of ΔV to 0.1% of ΔV
(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
–
–
–
–
–
–
5.9
0.92
0.72
µs
µs
µs
SRROA
SRFOA
BWOA
ENOA
Rising slew rate (20% to 80%) (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
0.15
1.7
6.5
–
–
–
–
–
–
V/µs
V/µs
V/µs
Falling slew rate (20% to 80%) (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
0.01
0.5
4.0
–
–
–
–
–
–
V/µs
V/µs
V/µs
Gain bandwidth product
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
0.75
3.1
5.4
–
–
–
–
–
–
MHz
MHz
MHz
Noise at 1 kHz (Power = medium, Opamp bias = high)
–
100
–
nV/rt-Hz
Table 20. 3.3-V AC Operational Amplifier Specifications
Symbol
tROA
Description
Min
Typ
Max
Units
Rising settling time from 80% of ΔV to 0.1% of ΔV
(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
–
–
–
–
3.92
0.72
µs
µs
tSOA
Falling settling time from 20% of ΔV to 0.1% of ΔV
(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
–
–
–
–
5.41
0.72
µs
µs
SRROA
SRFOA
BWOA
ENOA
Rising slew rate (20% to 80%) (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
0.31
2.7
–
–
–
–
V/µs
V/µs
Falling slew rate (20% to 80%) (10 pF load, Unity Gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
0.24
1.8
–
–
–
–
V/µs
V/µs
Gain bandwidth product
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
0.67
2.8
–
–
–
–
MHz
MHz
Noise at 1 kHz (Power = medium, Opamp bias = high)
–
100
–
nV/rt-Hz
Document Number: 001-53754 Rev. *D
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CY8C24894
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 kΩ resistance and the external capacitor.
Figure 6. Typical AGND Noise with P2[4] Bypass
nV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 7. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
0.01
0.1
1
10
100
Freq (kHz)
Document Number: 001-53754 Rev. *D
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CY8C24894
AC Low Power Comparator Specifications
Table 21 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40
°C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V at 25 °C and are for design
guidance only.
Table 21. AC Low Power Comparator Specifications
Symbol
tRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
μs
Notes
≥ 50 mV overdrive comparator
reference set within VREFLPC
.
AC Digital Block Specifications
Table 22 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40
°C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are
for design guidance only.
Table 22. AC Digital Block Specifications
Function
All
functions
Description
Block input clock frequency
VDD ≥ 4.75 V
Min
Typ
Max
Units
Notes
–
–
–
–
49.92[15] MHz
25.92[15] MHz
V
DD < 4.75 V
Timer
Input clock frequency
No capture, VDD ≥ 4.75 V
No capture, VDD < 4.75 V
With capture
–
–
–
–
–
–
–
49.92[15] MHz
25.92[15] MHz
25.92[15] MHz
Capture pulse width
50[16]
–
ns
Counter Input clock frequency
No enable input, VDD ≥ 4.75 V
–
–
–
–
–
–
–
49.92[15] MHz
25.92[15] MHz
25.92[15] MHz
No enable input, VDD < 4.75 V
With enable input
Enable input pulse width
Kill pulse width
Asynchronous restart mode
Synchronous restart mode
Disable mode
50[16]
–
ns
Dead
Band
20
–
–
–
–
–
–
ns
ns
ns
50[16]
50[16]
Input clock frequency
VDD ≥ 4.75 V
–
–
–
–
49.92[15] MHz
25.92[15] MHz
V
DD < 4.75 V
CRCPRS Input clock frequency
49.92[15] MHz
25.92[15] MHz
25.92[15] MHz
(PRS
VDD ≥ 4.75 V
–
–
–
–
–
–
Mode)
V
DD < 4.75 V
CRCPRS Input clock frequency
(CRC
Mode)
SPIM
Input clock frequency
–
–
8.64[15]
MHz The SPI serial clock (SCLK)
frequency is equal to the input
clock frequency divided by 2.
MHz The input clock is the SPI SCLK in
SPIS mode.
SPIS
Input clock (SCLK) frequency
–
–
–
4.32[15]
–
Width of SS_Negated between transmissions
Input Clock Frequency
VDD ≥ 4.75 V, 2 stop bits
50[16]
ns
Trans-
mitter
The baud rate is equal to the input
clock frequency divided by 8.
–
–
–
–
–
–
49.92[15] MHz
25.92[15] MHz
25.92[15] MHz
VDD ≥ 4.75 V, 1 stop bit
V
DD < 4.75 V
Notes
15. Accuracy derived from IMO with appropriate trim for V range.
DD
16. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-53754 Rev. *D
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CY8C24894
Table 22. AC Digital Block Specifications (continued)
Function Description
Min
Typ
Max
Units
Notes
Receiver Input clock frequency
VDD ≥ 4.75 V, 2 stop bits
VDD ≥ 4.75 V, 1 stop bit
The baud rate is equal to the input
clock frequency divided by 8.
–
–
–
–
–
–
49.92[15] MHz
25.92[15] MHz
25.92[15] MHz
V
DD < 4.75 V
AC External Clock Specifications
Table 23 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C
≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for
design guidance only.
Table 23. AC External Clock Specifications
Symbol
Description
Min
0
Typ
–
Max
Units
MHz
ns
Notes
FOSCEXT Frequency
24.24
–
–
–
High period
Low period
20.5
20.5
150
–
–
–
–
–
ns
Power-up IMO to switch
–
μs
AC Analog Output Buffer Specifications
Table 24 and Table 25 on page 32 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges:
4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V
and 3.3 V at 25 °C and are for design guidance only.
Table 24. 5-V AC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
tROB
Rising settling time to 0.1%, 1 V step, 100pF load
Power = low
Power = high
–
–
–
–
2.5
2.5
μs
μs
tSOB
Falling settling time to 0.1%, 1 V step, 100pF load
Power = low
Power = high
–
–
–
–
2.2
2.2
μs
μs
SRROB
SRFOB
Rising slew rate (20% to 80%), 1 V step, 100 pF load
Power = low
Power = high
0.65
0.65
–
–
–
–
V/μs
V/μs
Falling slew rate (80% to 20%), 1 V step, 100 pF load
Power = low
Power = high
0.65
0.65
–
–
–
–
V/μs
V/μs
BWOBSS Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load
Power = low
Power = high
0.8
0.8
–
–
–
–
MHz
MHz
BWOBLS Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load
Power = low
Power = high
300
300
–
–
–
–
kHz
kHz
Document Number: 001-53754 Rev. *D
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CY8C24894
Table 25. 3.3-V AC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
tROB
Rising settling time to 0.1%, 1 V step, 100 pF load
Power = low
Power = high
–
–
–
–
3.8
3.8
μs
μs
tSOB
Falling settling time to 0.1%, 1 V step, 100 pF load
Power = low
Power = high
–
–
–
–
2.6
2.6
μs
μs
SRROB
SRFOB
Rising slew rate (20% to 80%), 1 V step, 100 pF load
Power = low
Power = high
0.5
0.5
–
–
–
–
V/μs
V/μs
Falling slew rate (80% to 20%), 1 V step, 100 pF load
Power = low
Power = high
0.5
0.5
–
–
–
–
V/μs
V/μs
BWOBSS Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load
Power = low
Power = high
0.7
0.7
–
–
–
–
MHz
MHz
BWOBLS Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load
Power = low
Power = high
200
200
–
–
–
–
kHz
kHz
AC Programming Specifications
Table 26 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40
°C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are
for design guidance only.
Table 26. AC Programming Specifications
Symbol
tRSCLK
tFSCLK
tSSCLK
tHSCLK
FSCLK
Description
Min
1
Typ
–
Max
20
Units
ns
Notes
Rise time of SCLK
Fall time of SCLK
1
–
20
ns
Data setup time to falling edge of SCLK
Data hold time from falling edge of SCLK
Frequency of SCLK
40
40
0
–
–
ns
–
–
ns
–
8
MHz
ms
ms
ns
tERASEB
tWRITE
tDSCLK
tDSCLK3
tPRGH
Flash erase time (block)
–
10
40
–
40[17]
160[17]
45
Flash block write time
–
Data out delay from falling edge of SCLK
Data out delay from falling edge of SCLK
Total flash block program time (tERASEB + tWRITE), hot
Total flash block program time (tERASEB + tWRITE), cold
–
VDD > 3.6 V
–
–
50
ns
3.0 V ≤ VDD ≤ 3.6 V
TJ ≥ 0 °C
–
–
100[17]
200[17]
ms
ms
tPRGC
–
–
TJ < 0 °C
Note
17. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the temperature
argument before writing. Refer to the Flash APIs Application Note AN2015 for more information.
Document Number: 001-53754 Rev. *D
Page 32 of 46
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CY8C24894
AC I2C Specifications
Table 27 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40
°C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are
for design guidance only.
Table 27. AC Characteristics of the I2C SDA and SCL Pins for VDD
Standard Mode
Fast Mode
Symbol
Description
SCL clock frequency
Units
Notes
Min
0
Max
100[18]
–
Min
0
Max
400[18]
FSCLI2C
kHz
tHDSTAI2C Hold time (repeated) START condition. After
this period, the first clock pulse is generated.
4.0
0.6
–
μs
tLOWI2C
tHIGHI2C
LOW period of the SCL clock
HIGH period of the SCL clock
4.7
4.0
4.7
0
–
–
–
–
–
–
–
1.3
0.6
–
–
–
–
–
–
–
μs
μs
μs
μs
ns
μs
μs
tSUSTAI2C Setup time for a repeated START condition
tHDDATI2C Data hold time
0.6
0
tSUDATI2C Data setup time
250
4.0
4.7
100[19]
tSUSTOI2C Setup time for STOP condition
0.6
tBUFI2C
Bus free time between a stop and start
condition
1.3
tSPI2C
Pulse width of spikes are suppressed by the
input filter.
–
–
0
50
ns
Figure 8. Definition for Timing for Fast/Standard Mode on the I2C Bus
I2C_SDA
I2C_SCL
tSUDATI2C
tHDSTAI2C
tSPI2C
tSUSTAI2C
tBUFI2C
tHDDATI2C
tHIGHI2C tLOWI2C
tSUSTOI2C
P
S
S
Sr
Repeated START Condition
STOP Condition
START Condition
Notes
18. F
is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the F
SCLI2C
SCLI2C
specification adjusts accordingly.
19. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t
≥ 250 ns must then be met. This is automatically the
SUDATI2C
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to
the SDA line t
+ t
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
rmax
SUDATI2C
Document Number: 001-53754 Rev. *D
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CY8C24894
Packaging Information
This section illustrates the package specification for the CY8C24x94 PSoC devices, along with the thermal impedance for the package
and solder reflow peak temperatures.
Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation
tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com.
Figure 9. 56-Pin (8 × 8 mm) QFN (Punched)
SOLDERABLE
EXPOSED
PAD
001-12921 *B
Important Note
■ For information on the preferred dimensions for mounting QFN packages, see the following application note, Application Notes for
Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com.
■ Pinned vias for thermal conduction are not required for the low power PSoC device.
Thermal Impedances
Solder Reflow Specifications
Table 29 shows the solder reflow temperature limits that must not
be exceeded.
Table 28. Thermal Impedance per Package
[20]
Package
Typical θJA
19 °C/W
Typical θJC
1.7 °C/W
Table 29. Solder Reflow Specifications
56-pin QFN[21]
Maximum Peak
Temperature (TC)
Maximum Time
above TC – 5 °C
Package
56-pin QFN
260 °C
30 seconds
Notes
20. T = T + Power × θ
J
A
JA.
21. To achieve the thermal impedance specified for the QFN package, refer to the application notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF)
Packages available at http://www.amkor.com.
Document Number: 001-53754 Rev. *D
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CY8C24894
Tape and Reel Information
Figure 10. 56-Pin (8 × 8 mm) QFN (Punched) Carrier Tape Drawing
51-51165 *B
Table 30. Tape and Reel Specifications
Minimum
Trailing Empty
Pockets
Cover Tape
Package
Hub Size
(inches)
Minimum Leading
Empty Pockets
Standard Full Reel
Width (mm)
Quantity
56-Pin QFN
13.1
7
42
25
2000
Document Number: 001-53754 Rev. *D
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CY8C24894
Development Tool Selection
Software
The Universal CapSense Controller Kit is designed for easy
prototyping and debug of CapSense designs with pre-defined
control circuitry and plug-in hardware. The CY3280-24X94 kit
contains no plug-in hardware. Therefore, it is only usable if
plug-in hardware is purchased as part of the CY3280-BK1 kit or
other separate kits. The kit includes:
PSoC Designer
At the core of the PSoC development software suite is PSoC
Designer, used to generate PSoC firmware applications. PSoC
Designer is available free of charge at http://www.cypress.com
and includes a free C compiler.
■ CY3280-24X94 Universal CapSense Controller Board
■ CY3240-I2USB Bridge Board
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer or PSoC Express. PSoC
Programmer software is compatible with both PSoC ICE-Cube
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free of charge at http://www.cypress.com.
■ CY3210 PSoC MiniProg1 Programmer
■ CY3280-24X94 Quick Start
■ USB Retractable Cable (A to mini-B)
■ PSoC Express Installation CD
■ PSoC Designer and PSoC Programmer CD
■ CY3280-24X94 Universal CapSense Controller Kit CD
Development Kits
All development kits can be purchased from the Cypress Online
Store. The online store also has the most up to date information
on kit contents, descriptions, and availability.
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online
Store. The online store also has the most up to date information
on kit contents, descriptions, and availability.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface allows users to run, halt, and single step the processor
and view the contents of specific memory locations. Advanced
emulation features are also supported through PSoC Designer.
The kit includes:
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread-
boarding space to meet all of your evaluation needs. The kit
includes:
■ ICE-Cube Unit
■ Evaluation Board with LCD Module
■ MiniProg Programming Unit
■ 28-Pin PDIP Emulation Pod for CY8C29466-24PXI
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Samples (two)
■ PSoC Designer Software CD
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■ PSoC Designer Software CD
■ Getting Started Guide
■ ISSP Cable
■ MiniEval Socket Programming and Evaluation board
■ Backward Compatibility Cable (for connecting to legacy Pods)
■ Universal 110/220 Power Supply (12 V)
■ European Plug Adapter
■ USB 2.0 Cable
CY3210-24X94 Evaluation Pod (EvalPod)
PSoC EvalPods are pods that connect to the ICE In-Circuit
Emulator (CY3215-DK kit) to allow debugging capability. They
can also function as a standalone device without debugging
capability. The EvalPod has a 28-pin DIP footprint on the bottom
for easy connection to development kits or other hardware. The
top of the EvalPod has prototyping headers for easy connection
to the device's pins. CY3210-24X94 provides evaluation of the
CY8C24x94 PSoC device family.
■ USB 2.0 Cable
■ Getting Started Guide
■ Development Kit Registration form
CY3280-24X94 Universal CapSense Controller Board
The CY3280-24X94 Controller Board is an additional controller
board for the CY3280-BK1 Universal CapSense Controller Kit.
Document Number: 001-53754 Rev. *D
Page 36 of 46
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CY8C24894
CY3207ISSP In-System Serial Programmer (ISSP)
Device Programmers
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
All device programmers can be purchased from the Cypress
Online Store.
CY3210-MiniProg1
Note: CY3207ISSP needs special software and is not
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
compatible with PSoC Programmer. The kit includes:
■ CY3207 Programmer Unit
■ PSoC ISSP Software CD
■ MiniProg Programming Unit
■ 110 ~ 240 V Power Supply, Euro-Plug Adapter
■ USB 2.0 Cable
■ MiniEval Socket Programming and Evaluation Board
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■ PSoC Designer Software CD
■ Getting Started Guide
■ USB 2.0 Cable
Accessories (Emulation and Programming)
Table 31. Emulation and Programming Accessories
Part #
Pin Package
Flex-Pod Kit[22]
Foot Kit[23]
Adapter[24]
AS-56-28-01ML-6
CY8C24894-24LFXA
56-pin QFN
CY3250-24X94QFN
CY3250-56QFN-FK
Notes
22. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
23. Foot kit includes surface mount feet that are soldered to the target PCB.
24. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters are found at
http://www.emulation.com.
Document Number: 001-53754 Rev. *D
Page 37 of 46
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CY8C24894
Ordering Information
Table 32. CY8C24x94 PSoC Device’s Key Features and Ordering Information
56-pin (8 × 8 mm) QFN,
punched
CY8C24894-24LFXA
CY8C24894-24LFXAT
16 K 1 K
16 K 1 K
–40 °C to +85 °C
–40 °C to +85 °C
4
4
6
6
49
49
47
47
2
2
Yes
Yes
56-pin (8 × 8 mm) QFN,
punched (tape and reel)
Ordering Code Definitions
CY 8 C 24 xxx-SPxx
Package Type:
Thermal Rating:
PX = PDIP Pb-free
A = Automotive –40 °C to +85 °C
SX = SOIC Pb-free
PVX = SSOP Pb-free
LFX/LKX = QFN Pb-free
AX = TQFP Pb-free
BVX = VFBGA Pb-free
C = Commercial
E = Automotive Extended –40 °C to +125 °C
I = Industrial
CPU Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
Document Number: 001-53754 Rev. *D
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Reference Information
Acronyms
Table 33 lists the acronyms that are used in this document.
Table 33. Acronyms Used in this Datasheet
Acronym
AC
Description
Acronym
MIPS
PCB
Description
alternating current
million instructions per second
printed circuit board
ADC
AEC
analog-to-digital converter
Automotive Electronics Council
application programming interface
central processing unit
PDIP
PLL
plastic dual in-line package
phase-locked loop
API
CPU
CRC
CT
POR
power-on reset
cyclic redundancy check
continuous time
PPOR
PSoC®
PWM
QFN
precision POR
Programmable System-on-Chip
pulse-width modulator
quad flat no leads
DAC
DC
digital-to-analog converter
direct current or duty cycle
dual-tone multi-frequency
DTMF
EEPROM
RMS
root mean square
electrically erasable programmable read-only
memory
SAR
successive approximation register
EXTCLK
GPIO
I2C
external clock
SC
SCL / SCLK
SDA
switched capacitor
serial clock
general purpose I/O
inter-integrated circuit
in-circuit emulator
serial data
ICE
SLIMO
SMP
slow IMO
IDE
integrated development environment
internal low-speed oscillator
internal main oscillator
input/output
switch mode pump
small-outline integrated circuit
serial peripheral interface
static random-access memory
supervisory read-only memory
thin quad flat pack
ILO
SOIC
IMO
I/O
SPI
SRAM
SROM
TQFP
UART
IrDA
ISSP
LCD
Infrared Data Association
in-system serial programming
liquid crystal display
universal asynchronous receiver
transmitter
LED
LPC
LVD
MCU
light-emitting diode
low power comparator
low voltage detect
microcontroller unit
USB
WDT
XRES
universal serial bus
watchdog timer
external reset
Reference Documents
CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34,
CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical
Reference Manual (TRM) (001-14463)
Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459)
Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503)
Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com.
Document Number: 001-53754 Rev. *D
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Document Conventions
Units of Measure
The following table lists the units of measure that are used in this document.
Table 34. Units of Measure
Symbol
°C
Unit of Measure
Symbol
mVPP
nA
Unit of Measure
millivolts peak-to-peak
degree Celsius
decibel
dB
nanoampere
nanosecond
nanovolt
ohm
fF
femtofarad
1024 bytes
kilohertz
ns
KB
nV
kHz
kΩ
Ω
%
kilohm
percent
MHz
μA
μs
μV
mA
ms
megahertz
microampere
microsecond
microvolt
pA
picoampere
picofarad
picosecond
root hertz
volt
pF
ps
rt-Hz
V
milliampere
millisecond
millivolt
W
watt
mV
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, ‘01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are in decimal format.
Glossary
active high
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.
These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
analog-to-digital A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts
converter (ADC) a voltage to a digital number. The digital-to-analog converter (DAC) performs the reverse operation.
Application
programming
interface (API)
A series of software routines that comprise an interface between a computer application and lower level services
and functions (for example, user modules and libraries). APIs serve asbuilding blocks for programmers that create
software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with the negative
temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or
loss); it is sometimes represented more specifically as, for example, full width at half maximum.
Document Number: 001-53754 Rev. *D
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Glossary (continued)
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to
operate the device.
block
buffer
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or
an analog PSoC block.
1. A storage area for data that is used to compensate for a speed difference, when transferring data from one
device to another. Usually refers to an area reserved for I/O operations, into which data is read, or from which
data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received
from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing
patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented using vector
notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to
synchronize different logic blocks.
comparator
compiler
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy
predetermined amplitude requirements.
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to
‘1’.
crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric
crystal is less sensitive to ambient temperature than other circuit components.
cyclicredundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift
check (CRC)
register. Similar calculations may be used for a variety of other purposes such as data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location to the central
processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.
debugger
A hardware and software system that allows you to analyze the operation of the system under development. A
debugger usually allows the developer to step through the firmware one step at a time, set break points, and
analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,
pseudo-random number generator, or SPI.
digital-to-analog A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital
converter (DAC) converter (ADC) performs the reverse operation.
Document Number: 001-53754 Rev. *D
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Glossary (continued)
duty cycle
emulator
The relationship of a clock period high time to its low time, expressed as a percent.
Duplicates (provides an emulation of) the functions of one system with a different system, so that the second
system appears to behave like the first system.
external reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop
and return to a pre-defined state.
flash
An electrically programmable and erasable, non-volatile technology that provides you the programmability and
data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is
off.
flash block
The smallest amount of flash ROM space that may be programmed at one time and the smallest amount of flash
space that may be protected.
frequency
gain
The number of cycles or events per unit of time, for a periodic function.
The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually
expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). It is used to connect
low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery
control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses
only two bi-directional pins, clock and data, both running at the VDD suppy voltage and pulled high with resistors.
The bus operates up to100 kbits/second in standard mode and 400 kbits/second in fast mode.
ICE
The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging
device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event external to that
process, and performed in such a way that the process can be resumed.
interrupt service A block of code that normal code execution is diverted to when the CPU receives a hardware interrupt. Many
routine (ISR)
interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends
with the RETI instruction, returning the device to the point in the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls below a selected threshold.
(LVD)
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by
interfacing to the flash, SRAM, and register space.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in
width, the master device is the one that controls the timing for data exchanges between the cascaded devices
and an external interface. The controlled device is called the slave device.
Document Number: 001-53754 Rev. *D
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Glossary (continued)
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a
microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason for this is to permit the
realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This
in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for
general-purpose computation as is a microprocessor.
mixed-signal
modulator
noise
The reference to a circuit containing both analog and digital techniques and components.
A device that imposes a signal on a carrier.
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
parity
A circuit that may be crystal controlled and is used to generate a clock frequency.
A technique for testing transmitted data. Typically, a binary digit is added to the data to make the sum of all the
digits of the binary data either always even (even parity) or always odd (odd parity).
phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference
signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their
physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between
schematic and PCB design (both being computer generated files) and may also involve pin names.
port
A group of pins, usually eight.
power-on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware
reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark
of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied value.
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out and new data
can be written in.
register
reset
A storage device with a specific capacity, such as a bit or byte.
A means of bringing a system back to a known state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot
be written in.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
Document Number: 001-53754 Rev. *D
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Glossary (continued)
shift register
slave device
A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
A device that allows another device to control the timing for data exchanges between two devices. Or when
devices are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
SRAM
SROM
An acronym for static random access memory. A memory device where you can store and retrieve data at a high
rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged
until it is explicitly altered or until power is removed from the device.
An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform flash operations. The functions of the SROM may be accessed in normal user code,
operating from flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.
user modules
Pre-built, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level analog and digital PSoC blocks. User modules also provide high level API (Application Programming
Interface) for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
VDD
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V.
A name for a power net meaning "voltage source." The most negative power supply signal.
VSS
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
Document Number: 001-53754 Rev. *D
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Document History Page
Document Title: CY8C24894 Automotive PSoC® Programmable System-on-Chip™
Document Number: 001-53754
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
2715097
2782580
MASJ
BTK
06/08/09
10/09/09
New datasheet.
*A
Updated Features section. Updated text of PSoC Functional Overview section.
Updated Getting Started section. Made corrections and minor text edits to
Pinouts section. Changed the name of some sections to improve consistency.
Improved formatting of the register tables. Added clarifying comments to some
electrical specifications. Fixed all AC specifications to conform to a ±4% or ±8%
IMO accuracy. Made other miscellaneous minor text edits. Deleted some
non-applicable or redundant information. Improved and edited content in Devel-
opment Tool Selection section. Improved the bookmark structure. Changed
FlashENT, VCMOA, the DC POR and LVD specifications, and the DC Analog
Reference specifications according to MASJ directives. Added TXRST, DC24M,
and 3.3 V DC Operational Amplifier specifications.
*B
*C
2822792 BTK/AESA
12/07/09
03/30/10
Added TPRGH, TPRGC, IOL, IOH, F32KU, DCILO, and TPOWERUP electrical speci-
fications. Updated the footnotes of Table 16, “DC Programming Specifications,”
on page 25. Added maximum values and updated typical values for TERASEB
and TWRITE electrical specifications. Replaced TRAMP electrical specification
with SRPOWERUP electrical specification. Added “Contents” on page 2.
2888007
3272922
NJF
Updated Cypress website links.
Removed reference to PSoC Designer 4.4 in PSoC Designer Software
Subsystems
Updated The Analog System.
Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings.
Updated AC Chip-Level Specifications. Updated Packaging Information.
Removed Third Party Tools and Build a PSoC Emulator into your Board.
Updated links in Sales, Solutions, and Legal Information.
*D
BTK/NJF
06/02/11
Updated Figure 8 on page 33 to improve clarity.
Updated wording, formatting, and notes of the AC Digital Block Specifications
table to improve clarity.
Added VDDP, VDDLV, and VDDHV electrical specifications to give more infor-
mation for programming the device.
Updated Solder Reflow Specifications to give more clarity.
Updated the jitter specifications.
Updated PSoC Device Characteristics table.
Updated the F32KU electrical specification.
Updated note for RPD electrical specification.
Updated note for the TSTG electrical specification to add more clarity.
Added Tape and Reel Specifications section.
Added CL electrical specification.
Updated DC Analog Reference Specifications.
Changed “NC” pins on the device to “DNC” pins.
Corrected information about the exposed pad to clarify that it is not internally
connected.
Document Number: 001-53754 Rev. *D
Page 45 of 46
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-53754 Rev. *D
Revised June 2, 2011
Page 46 of 46
All products and company names mentioned in this document may be the trademarks of their respective holders.
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