CY8C24894-24LFXI_技术文档

PSoC® Mixed-Signal Array

Final Data Sheet

CY8C24094, CY8C24794,

CY8C24894, and CY8C24994

Features

■

CY8C24894 includes an XRES pin to support In-System Serial Programming (ISSP) and external reset control

■

Powerful Harvard Architecture Processor

■

Full-Speed USB (12 Mbps)

■

Precision, Programmable Clocking

❐

M8C Processor Speeds to 24 MHz

Two 8x8 Multiply, 32-Bit Accumulate

Low Power at High Speed

3.0 to 5.25V Operating Voltage

Industrial Temperature Range: -40°C to +85°C

USB Temperature Range: -10°C to +85°C

❐

Four Uni-Directional Endpoints

One Bi-Directional Control Endpoint

USB 2.0 Compliant

Dedicated 256 Byte Buffer

No External Crystal Required

❐

Internal ±4% 24/48 MHz Oscillator

Internal Oscillator for Watchdog and Sleep

.25% Accuracy for USB with no External

Components

■

Additional System Resources

2

Flexible On-Chip Memory

❐

I C™ Slave, Master, and Multi-Master to

400 kHz

■

Advanced Peripherals (PSoC Blocks)

❐

16K Flash Program Storage 50,000 Erase/

Write Cycles

❐

6 Rail-to-Rail Analog PSoC Blocks Provide:

❐

Watchdog and Sleep Timers

User-Configurable Low Voltage Detection

Integrated Supervisory Circuit

On-Chip Precision Voltage Reference

❐

1K SRAM Data Storage

In-System Serial Programming (ISSP)

Partial Flash Updates

Flexible Protection Modes

EEPROM Emulation in Flash

- Up to 14-Bit ADCs

- Up to 9-Bit DACs

- Programmable Gain Amplifiers

- Programmable Filters and Comparators

4 Digital PSoC Blocks Provide:

■

Complete Development Tools

❐

Free Development Software

(PSoC Designer™)

■

Programmable Pin Configurations

- 8- to 32-Bit Timers, Counters, and PWMs

- CRC and PRS Modules

- Full-Duplex UART

❐

25 mA Sink on all GPIO

❐

Full-Featured, In-Circuit Emulator and

Programmer

Pull up, Pull down, High Z, Strong, or Open

Drain Drive Modes on all GPIO

Up to 48 Analog Inputs on GPIO

Two 33 mA Analog Outputs on GPIO

Configurable Interrupt on all GPIO

❐

Full Speed Emulation

Complex Breakpoint Structure

128K Bytes Trace Memory

- Multiple SPI™ Masters or Slaves

- Connectable to all GPIO Pins

Complex Peripherals by Combining Blocks

❐

Capacitive Sensing Application Capability

Analog

Drivers

PSoC® Functional Overview

Port 5 Port 4 Port 3 Port 2 Port 1 Port 0

Port 7

The PSoC® family consists of many Mixed-Signal Array with

On-Chip Controller devices. All PSoC family devices are

designed to replace traditional MCUs, system ICs, and the

numerous discrete components that surround them. The PSoC

CY8C24x94 devices are unique members of the PSoC family

because it includes a full-featured, full-speed (12 Mbps) USB

port. Configurable analog, digital, and interconnect circuitry

enable a high level of integration in a host of industrial, con-

sumer, and communication applications.

Global Digital Interconnect

Global Analog Interconnect

PSoC CORE

SRAM

1K

SROM

Flash 16K

Sleep and

Watchdog

CPUCore(M8C)

Interrupt

Controller

This architecture allows the user to create customized periph-

eral configurations that match the requirements of each individ-

ual application. Additionally, a fast CPU, Flash program

memory, SRAM data memory, and configurable IO are included

in a range of convenient pinouts and packages.

ClockSources

(IncludesIMOandILO)

DIGITAL SYSTEM

ANALOG SYSTEM

Analog

Ref.

The PSoC architecture, as illustrated on the left, is comprised of

four main areas: PSoC Core, Digital System, Analog System,

and System Resources including a full-speed USB port. Config-

urable global busing allows all the device resources to be com-

bined into a complete custom system. The PSoC CY8C24x94

devices can have up to seven IO ports that connect to the glo-

bal digital and analog interconnects, providing access to 4 digi-

tal blocks and 6 analog blocks.

Digital

Block

Array

Analog

Block

Array

Internal

Voltage USB

Ref.

Analog

Input

Muxing

Digital

Clocks MACs Type 2

2

Decimator

POR and LVD

System Resets

I2C

SYSTEM RESOURCES

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PSoC® Overview

Digital peripheral configurations include those listed below.

The PSoC Core

■ Full-Speed USB (12 Mbps)

■ PWMs (8 to 32 bit)

The PSoC Core is a powerful engine that supports a rich fea-

ture set. The core includes a CPU, memory, clocks, and config-

urable GPIO (General Purpose IO).

■ PWMs with Dead band (8 to 24 bit)

■ Counters (8 to 32 bit)

The M8C CPU core is a powerful processor with speeds up to

24 MHz, providing a four MIPS 8-bit Harvard architecture micro-

processor. The CPU utilizes an interrupt controller with up to 20

vectors, to simplify programming of real time embedded events.

Program execution is timed and protected using the included

Sleep and Watch Dog Timers (WDT).

■ Timers (8 to 32 bit)

■ UART 8 bit with selectable parity

■ SPI master and slave

■ I2C slave and multi-master

■ Cyclical Redundancy Checker/Generator (8 to 32 bit)

■ IrDA

Memory encompasses 16K of Flash for program storage, 1K of

SRAM for data storage, and up to 2K of EEPROM emulated

using the Flash. Program Flash utilizes four protection levels on

blocks of 64 bytes, allowing customized software IP protection.

■ Pseudo Random Sequence Generators (8 to 32 bit)

The digital blocks can be connected to any GPIO through a

series of global buses that can route any signal to any pin. The

buses also allow for signal multiplexing and for performing logic

operations. This configurability frees your designs from the con-

straints of a fixed peripheral controller.

The PSoC device incorporates flexible internal clock genera-

tors, including a 24 MHz IMO (internal main oscillator) accurate

to 8% over temperature and voltage. The 24 MHz IMO can also

be doubled to 48 MHz for use by the digital system. A low

power 32 kHz ILO (internal low speed oscillator) is provided for

the Sleep timer and WDT. The clocks, together with program-

mable clock dividers (as a System Resource), provide the flexi-

bility to integrate almost any timing requirement into the PSoC

device. In USB systems, the IMO will self-tune to ± 0.25% accu-

racy for USB communication.

Digital blocks are provided in rows of four, where the number of

blocks varies by PSoC device family. This allows you the opti-

mum choice of system resources for your application. Family

resources are shown in the table titled PSoC Device Character-

istics.

PSoC GPIOs provide connection to the CPU, digital and analog

resources of the device. Each pin’s drive mode may be selected

from eight options, allowing great flexibility in external interfac-

ing. Every pin also has the capability to generate a system inter-

rupt on high level, low level, and change from last read.

The Analog System

The Analog System is composed of 6 configurable blocks, each

comprised of an opamp circuit allowing the creation of complex

analog signal flows. Analog peripherals are very flexible and

can be customized to support specific application requirements.

Some of the more common PSoC analog functions (most avail-

able as user modules) are listed below.

The Digital System

The Digital System is composed of 4 digital PSoC blocks. Each

block is an 8-bit resource that can be used alone or combined

with other blocks to form 8, 16, 24, and 32-bit peripherals, which

are called user module references.

■ Analog-to-digital converters (up to 2, with 6- to 14-bit resolu-

tion, selectable as Incremental, Delta Sigma, and SAR)

■ Filters (2 and 4 pole band-pass, low-pass, and notch)

■ Amplifiers (up to 2, with selectable gain to 48x)

■ Instrumentation amplifiers (1 with selectable gain to 93x)

■ Comparators (up to 2, with 16 selectable thresholds)

■ DACs (up to 2, with 6- to 9-bit resolution)

Digital System Block Diagram

Port 7

Port 5

Port 3

Port 1

Port 4

Port 2

Port 0

■ Multiplying DACs (up to 2, with 6- to 9-bit resolution)

To SystemBus

DigitalC locks

FromCore

ToAnalog

System

■ High current output drivers (two with 30 mA drive as a PSoC

Core Resource)

■ 1.3V reference (as a System Resource)

■ DTMF Dialer

DIGITAL SYSTEM

DigitalPSoCBlockArray

■ Modulators

Row0

8

4

8

■ Correlators

8

DBB00

DBB01

DCB02

DCB03

■ Peak Detectors

4

■ Many other topologies possible

GIE[7:0]

GIO[7:0]

GOE[7:0]

GOO[7:0]

GlobalDigital

Interconnect

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PSoC® Overview

Analog blocks are arranged in a column of three, which

includes one CT (Continuous Time) and two SC (Switched

Capacitor) blocks, as shown in the figure below.

The Analog Multiplexer System

The Analog Mux Bus can connect to every GPIO pin in ports 0-

5. Pins can be connected to the bus individually or in any com-

bination. The bus also connects to the analog system for analy-

sis with comparators and analog-to-digital converters. It can be

split into two sections for simultaneous dual-channel process-

ing. An additional 8:1 analog input multiplexer provides a sec-

ond path to bring Port 0 pins to the analog array.

Analog System Block Diagram

All IO

(Except Port 7)

P0[7]

P0[5]

P0[6]

P0[4]

Switch control logic enables selected pins to precharge continu-

ously under hardware control. This enables capacitive mea-

surement for applications such as touch sensing. Other

multiplexer applications include:

P0[3]

P0[1]

P0[2]

P0[0]

■ Track pad, finger sensing.

P2[6]

P2[4]

P2[3]

P2[1]

■ Chip-wide mux that allows analog input from up to 48 IO

pins.

P2[2]

P2[0]

■ Crosspoint connection between any IO pin combinations.

When designing capacitive sensing applications, refer to the lat-

est signal-to-noise signal level requirements Application Notes,

which can be found under http://www.cypress.com >> DESIGN

RESOURCES >> Application Notes. In general, and unless oth-

erwise noted in the relevant Application Notes, the minimum

signal-to-noise ratio (SNR) for CapSense applications is 5:1.

ACI0[1:0]

Array Input

ACI1[1:0]

Configuration

Additional System Resources

System Resources, provide additional capability useful to com-

plete systems. Additional resources include a multiplier, deci-

mator, low voltage detection, and power on reset. Brief

statements describing the merits of each resource follow.

Block

Array

ACB00

ASC10

ASD20

ACB01

ASD11

ASC21

■ Full-Speed USB (12 Mbps) with 5 configurable endpoints and

256 bytes of RAM. No external components required except

two series resistors. Wider than commercial temperature

USB operation (-10°C to +85°C).

AnalogReference

Interface to

Digital System

Reference

Generators

■ Digital clock dividers provide three customizable clock fre-

quencies for use in applications. The clocks can be routed to

both the digital and analog systems. Additional clocks can be

generated using digital PSoC blocks as clock dividers.

RefHi

RefLo

AGND

AGNDIn

RefIn

Bandgap

M8C Interface (Address Bus, Data Bus, Etc.)

■ Two multiply accumulates (MACs) provide fast 8-bit multipli-

ers with 32-bit accumulate, to assist in both general math as

well as digital filters.

■ Decimator provides a custom hardware filter for digital signal

processing apps. including creation of Delta Sigma ADCs.

■ The I2C module provides 100 and 400 kHz communication

over two wires. Slave, master, multi-master are supported.

■ Low Voltage Detection (LVD) interrupts signal the application

of falling voltage levels, while the advanced POR (Power On

Reset) circuit eliminates the need for a system supervisor.

■ An internal 1.3V reference provides an absolute reference for

the analog system, including ADCs and DACs.

■ Versatile analog multiplexer system.

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PSoC® Overview

PSoC Device Characteristics

Getting Started

Depending on your PSoC device characteristics, the digital and

analog systems can have 16, 8, or 4 digital blocks and 12, 6, or

4 analog blocks. The following table lists the resources

available for specific PSoC device groups. The device covered

by this data sheet is shown in the highlighted row of the table

The quickest path to understanding the PSoC silicon is by read-

ing this data sheet and using the PSoC Designer Integrated

Development Environment (IDE). This data sheet is an over-

view of the PSoC integrated circuit and presents specific pin,

register, and electrical specifications. For in-depth information,

along with detailed programming information, reference the

PSoC Mixed-Signal Array Technical Reference Manual.

PSoC Device Characteristics

For up-to-date Ordering, Packaging, and Electrical Specification

information, reference the latest PSoC device data sheets on

the web at http://www.cypress.com/psoc.

PSoC Part

Number

up to

64

CY8C29x66

4

16

12

4

12

2K

32K

To determine which PSoC device meets your requirements,

navigate through the PSoC Decision Tree in the Application

Note AN2209 at http://www.cypress.com and select Application

Notes under the Design Resources.

up to

44

256

Bytes

CY8C27x43

CY8C24x94

CY8C24x23A

2

1

8

4

12

48

12

4

2

4

2

12

6

16K

4K

56

1K

up to

24

256

Bytes

6

Development Kits

up to

28

512

Bytes

a

CY8C21x34

CY8C21x23

CY8C20x34

1

0

4

0

28

8

0

2

0

8K

4K

8K

4

Development Kits are available from the following distributors:

Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store

contains development kits, C compilers, and all accessories for

PSoC development. Go to the Cypress Online Store web site at

http://www.cypress.com, click the Online Store shopping cart

icon at the bottom of the web page, and click PSoC (Program-

mable System-on-Chip) to view a current list of available items.

256

Bytes

a

16

4

up to

28

512

Bytes

b

28

3

a. Limited analog functionality.

b. Two analog blocks and one CapSense.

Technical Training Modules

Free PSoC technical training modules are available for users

new to PSoC. Training modules cover designing, debugging,

advanced

analog

and

CapSense.

Go

to

http://

www.cypress.com/techtrain.

Consultants

Certified PSoC Consultants offer everything from technical

assistance to completed PSoC designs. To contact or become a

PSoC Consultant go to http://www.cypress.com, click on Design

Support located on the left side of the web page, and select

CYPros Consultants.

Technical Support

PSoC application engineers take pride in fast and accurate

response. They can be reached with a 4-hour guaranteed

response at http://www.cypress.com/support/login.cfm.

Application Notes

A long list of application notes will assist you in every aspect of

your design effort. To view the PSoC application notes, go to

the http://www.cypress.com web site and select Application

Notes under the Design Resources list located in the center of

the web page. Application notes are listed by date as default.

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PSoC® Overview

Development Tools

PSoC Designer is a Microsoft^®Windows-based, integrated

development environment for the Programmable System-on-

Chip (PSoC) devices. The PSoC Designer IDE and application

runs on Windows NT 4.0, Windows 2000, Windows Millennium

(Me), or Windows XP. (Reference the PSoC Designer Func-

tional Flow diagram below.)

PSoC Designer helps the customer to select an operating con-

figuration for the PSoC, write application code that uses the

PSoC, and debug the application. This system provides design

database management by project, an integrated debugger with

In-Circuit Emulator, in-system programming support, and the

CYASM macro assembler for the CPUs.

PSoC Designer also supports a high-level C language compiler

developed specifically for the devices in the family.

PSoC Designer Subsystems

Context

Sensitive

Help

Graphical Designer

PSoC

Designer

Interface

Importable

Design

Database

PSoC

Configuration

Sheet

Device

Database

PSoC

Designer

Core

Application

Database

Manufacturing

Information

File

Engine

Project

Database

User

Modules

Library

Emulation

Pod

In-Circuit

Emulator

Device

Programmer

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PSoC® Overview

PSoC Designer Software Subsystems

Device Editor

Debugger

The Device Editor subsystem allows the user to select different

onboard analog and digital components called user modules

using the PSoC blocks. Examples of user modules are ADCs,

DACs, Amplifiers, and Filters.

The PSoC Designer Debugger subsystem provides hardware

in-circuit emulation, allowing the designer to test the program in

a physical system while providing an internal view of the PSoC

device. Debugger commands allow the designer to read and

program and read and write data memory, read and write IO

registers, read and write CPU registers, set and clear break-

points, and provide program run, halt, and step control. The

debugger also allows the designer to create a trace buffer of

registers and memory locations of interest.

The device editor also supports easy development of multiple

configurations and dynamic reconfiguration. Dynamic configu-

ration allows for changing configurations at run time.

PSoC Designer sets up power-on initialization tables for

selected PSoC block configurations and creates source code

for an application framework. The framework contains software

to operate the selected components and, if the project uses

more than one operating configuration, contains routines to

switch between different sets of PSoC block configurations at

run time. PSoC Designer can print out a configuration sheet for

a given project configuration for use during application pro-

gramming in conjunction with the Device Data Sheet. Once the

framework is generated, the user can add application-specific

code to flesh out the framework. It’s also possible to change the

selected components and regenerate the framework.

Online Help System

The online help system displays online, context-sensitive help

for the user. Designed for procedural and quick reference, each

functional subsystem has its own context-sensitive help. This

system also provides tutorials and links to FAQs and an Online

Support Forum to aid the designer in getting started.

Hardware Tools

In-Circuit Emulator

Design Browser

A low cost, high functionality ICE (In-Circuit Emulator) is avail-

able for development support. This hardware has the capability

to program single devices.

The Design Browser allows users to select and import precon-

figured designs into the user’s project. Users can easily browse

a catalog of preconfigured designs to facilitate time-to-design.

Examples provided in the tools include a 300-baud modem, LIN

Bus master and slave, fan controller, and magnetic card reader.

The emulator consists of a base unit that connects to the PC by

way of a USB port. The base unit is universal and will operate

with all PSoC devices. Emulation pods for each device family

are available separately. The emulation pod takes the place of

the PSoC device in the target board and performs full speed (24

MHz) operation.

Application Editor

In the Application Editor you can edit your C language and

Assembly language source code. You can also assemble, com-

pile, link, and build.

Assembler. The macro assembler allows the assembly code

to be merged seamlessly with C code. The link libraries auto-

matically use absolute addressing or can be compiled in relative

mode, and linked with other software modules to get absolute

addressing.

C Language Compiler. A C language compiler is available

that supports the PSoC family of devices. Even if you have

never worked in the C language before, the product quickly

allows you to create complete C programs for the PSoC family

devices.

The embedded, optimizing C compiler provides all the features

of C tailored to the PSoC architecture. It comes complete with

embedded libraries providing port and bus operations, standard

keypad and display support, and extended math functionality.

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PSoC® Overview

User Module/Source Code Development Flows

Designing with User Modules

The development process for the PSoC device differs from that

of a traditional fixed function microprocessor. The configurable

analog and digital hardware blocks give the PSoC architecture

a unique flexibility that pays dividends in managing specification

change during development and by lowering inventory costs.

These configurable resources, called PSoC Blocks, have the

ability to implement a wide variety of user-selectable functions.

Each block has several registers that determine its function and

connectivity to other blocks, multiplexers, buses and to the IO

pins. Iterative development cycles permit you to adapt the hard-

ware as well as the software. This substantially lowers the risk

of having to select a different part to meet the final design

requirements.

Device Editor

Placement

and

Parameter

-ization

User

Module

Selection

Source

Code

Generator

Generate

Application

Application Editor

Source

Code

Editor

Project

Manager

Build

Manager

To speed the development process, the PSoC Designer Inte-

grated Development Environment (IDE) provides a library of

pre-built, pre-tested hardware peripheral functions, called “User

Modules.” User modules make selecting and implementing

peripheral devices simple, and come in analog, digital, and

mixed signal varieties. The standard User Module library con-

tains over 50 common peripherals such as ADCs, DACs Tim-

ers, Counters, UARTs, and other not-so common peripherals

such as DTMF Generators and Bi-Quad analog filter sections.

Build

All

Debugger

Each user module establishes the basic register settings that

implement the selected function. It also provides parameters

that allow you to tailor its precise configuration to your particular

application. For example, a Pulse Width Modulator User Mod-

ule configures one or more digital PSoC blocks, one for each 8

bits of resolution. The user module parameters permit you to

establish the pulse width and duty cycle. User modules also

provide tested software to cut your development time. The user

module application programming interface (API) provides high-

level functions to control and respond to hardware events at

run-time. The API also provides optional interrupt service rou-

tines that you can adapt as needed.

Event &

Breakpoint

Manager

Interface

to ICE

Storage

Inspector

The next step is to write your main program, and any sub-rou-

tines using PSoC Designer’s Application Editor subsystem.

The Application Editor includes a Project Manager that allows

you to open the project source code files (including all gener-

ated code files) from a hierarchal view. The source code editor

provides syntax coloring and advanced edit features for both C

and assembly language. File search capabilities include simple

string searches and recursive “grep-style” patterns. A single

mouse click invokes the Build Manager. It employs a profes-

sional-strength “makefile” system to automatically analyze all

file dependencies and run the compiler and assembler as nec-

essary. Project-level options control optimization strategies

used by the compiler and linker. Syntax errors are displayed in

a console window. Double clicking the error message takes you

directly to the offending line of source code. When all is correct,

the linker builds a HEX file image suitable for programming.

The API functions are documented in user module data sheets

that are viewed directly in the PSoC Designer IDE. These data

sheets explain the internal operation of the user module and

provide performance specifications. Each data sheet describes

the use of each user module parameter and documents the set-

ting of each register controlled by the user module.

The development process starts when you open a new project

and bring up the Device Editor, a graphical user interface (GUI)

for configuring the hardware. You pick the user modules you

need for your project and map them onto the PSoC blocks with

point-and-click simplicity. Next, you build signal chains by inter-

connecting user modules to each other and the IO pins. At this

stage, you also configure the clock source connections and

enter parameter values directly or by selecting values from

drop-down menus. When you are ready to test the hardware

configuration or move on to developing code for the project, you

perform the “Generate Application” step. This causes PSoC

Designer to generate source code that automatically configures

the device to your specification and provides the high-level user

module API functions.

The last step in the development process takes place inside the

PSoC Designer’s Debugger subsystem. The Debugger down-

loads the HEX image to the In-Circuit Emulator (ICE) where it

runs at full speed. Debugger capabilities rival those of systems

costing many times more. In addition to traditional single-step,

run-to-breakpoint and watch-variable features, the Debugger

provides a large trace buffer and allows you define complex

breakpoint events that include monitoring address and data bus

values, memory locations and external signals.

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PSoC® Overview

Document Conventions

Table of Contents

For an in depth discussion and more information on your PSoC

device, obtain the PSoC Mixed-Signal Array Technical Refer-

ence Manual. This document encompasses and is organized

into the following chapters and sections.

Acronyms Used

The following table lists the acronyms that are used in this doc-

ument.

Acronym

AC

Description

1.

Pin Information ........................................................................................ 9

alternating current

1.1

1.2

1.3

1.4

1.5

1.6

1.7

56-Pin Part Pinout ......................................................................... 9

56-Pin Part Pinout (with XRES) .................................................. 10

68-Pin Part Pinout ........................................................................ 11

68-Pin Part Pinout (On-Chip Debug) ........................................... 12

100-Ball VFBGA Part Pinout ........................................................ 13

100-Ball VFBGA Part Pinout (On-Chip Debug) ........................... 15

100-Pin Part Pinout (On-Chip Debug) .......................................... 17

ADC

API

analog-to-digital converter

application programming interface

central processing unit

continuous time

CPU

CT

DAC

DC

digital-to-analog converter

direct current

2.

3.

Register Reference ................................................................................ 19

2.1

Register Conventions ................................................................... 19

2.1.1 Abbreviations Used ....................................................... 19

Register Mapping Tables ............................................................. 19

ECO

EEPROM

FSR

GPIO

GUI

external crystal oscillator

electrically erasable programmable read-only memory

full scale range

2.2

Electrical Specifications ....................................................................... 22

3.1

3.2

3.3

Absolute Maximum Ratings ......................................................... 23

Operating Temperature ................................................................ 23

DC Electrical Characteristics ........................................................ 23

general purpose IO

graphical user interface

human body model

3.3.1

3.3.2

3.3.3

3.3.4

3.3.5

3.3.6

3.3.7

3.3.8

3.3.9

DC Chip-Level Specifications ........................................ 23

DC General Purpose IO Specifications ......................... 24

DC Full-Speed USB Specifications ............................... 24

DC Operational Amplifier Specifications ....................... 25

DC Low Power Comparator Specifications ................... 26

DC Analog Output Buffer Specifications ....................... 27

DC Analog Reference Specifications ............................ 28

DC Analog PSoC Block Specifications .......................... 29

DC POR and LVD Specifications .................................. 29

HBM

ICE

in-circuit emulator

ILO

internal low speed oscillator

internal main oscillator

input/output

IMO

IO

IPOR

LSb

imprecise power on reset

least-significant bit

3.3.10 DC Programming Specifications ................................... 30

AC Electrical Characteristics ........................................................ 31

3.4

3.4.1

3.4.2

3.4.3

3.4.4

3.4.5

3.4.6

3.4.7

3.4.8

3.4.9

AC Chip-Level Specifications ........................................ 31

AC General Purpose IO Specifications ......................... 32

AC Full-Speed USB Specifications ............................... 32

AC Operational Amplifier Specifications ........................ 33

AC Low Power Comparator Specifications ................... 35

AC Digital Block Specifications ..................................... 35

AC External Clock Specifications .................................. 35

AC Analog Output Buffer Specifications ........................ 36

AC Programming Specifications .................................... 37

LVD

low voltage detect

MSb

PC

most-significant bit

program counter

PLL

phase-locked loop

POR

PPOR

PSoC®

PWM

SC

power on reset

precision power on reset

Programmable System-on-Chip™

pulse width modulator

switched capacitor

3.4.10 AC I2C Specifications .................................................... 38

4.

5.

Packaging Information .......................................................................... 39

4.1

4.2

4.3

Packaging Dimensions ................................................................. 39

Thermal Impedance ..................................................................... 42

Solder Reflow Peak Temperature ................................................ 42

SRAM

static random access memory

Development Tool Selection ................................................................ 43

5.1

Software ....................................................................................... 43

5.1.1

5.1.2

5.1.3

5.1.4

PSoC Designer .............................................................. 43

PSoC Express ............................................................... 43

PSoC Programmer ........................................................ 43

CY3202-C iMAGEcraft C Compiler ............................... 43

Units of Measure

A units of measure table is located in the Electrical Specifica-

tions section. Table 3-1 on page 22 lists all the abbreviations

used to measure the PSoC devices.

5.2

5.3

Development Kits ......................................................................... 43

5.2.1

5.2.2

CY3215-DK Basic Development Kit .............................. 43

CY3210-ExpressDK Development Kit ........................... 44

Evaluation Tools ........................................................................... 44

5.3.1

5.3.2

5.3.3

CY3210-MiniProg1 ........................................................ 44

CY3210-PSoCEval1 ...................................................... 44

CY3214-PSoCEvalUSB ................................................ 44

Numeric Naming

5.4

Device Programmers ................................................................... 44

5.4.1

5.4.2

CY3216 Modular Programmer ...................................... 44

CY3207ISSP In-System Serial Programmer (ISSP) ..... 44

Hexidecimal numbers are represented with all letters in upper-

case with an appended lowercase ‘h’ (for example, ‘14h’ or

‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’

prefix, the C coding convention. Binary numbers have an

appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).

Numbers not indicated by an ‘h’ or ‘b’ are decimal.

5.5

5.6

5.7

Accessories (Emulation and Programming) ................................. 45

3rd-Party Tools ............................................................................. 45

Build a PSoC Emulator into Your Board ...................................... 45

6.

7.

Ordering Information ............................................................................ 46

6.1 Ordering Code Definitions ............................................................ 46

Sales and Company Information ......................................................... 47

7.1

7.2

Revision History ........................................................................... 47

Copyrights and Code Protection .................................................. 48

February 15, 2007

Document No. 38-12018 Rev. *J

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1. Pin Information

This chapter describes, lists, and illustrates the CY8C24x94 PSoC device family pins and pinout configuration.

The CY8C24x94 PSoC devices are available in the following packages, all of which are shown on the following pages. Every port pin

(labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO.

1.1

56-Pin Part Pinout

Table 1-1. 56-Pin Part Pinout (QFN**) See LEGEND details and footnotes in Table 1-2 on page 10.

Type

No.

CY8C24794 56-Pin PSoC Device

Name

Description

Digital Analog

1

2

IO

I, M

M

P2[3]

P2[1]

P4[7]

P4[5]

P4[3]

P4[1]

P3[7]

P3[5]

P3[3]

P3[1]

P5[7]

P5[5]

P5[3]

P5[1]

P1[7]

P1[5]

P1[3]

P1[1]

Vss

Direct switched capacitor block input.

3

4

5

6

7

8

M

A,I, M,P2[3]

A,I, M,P2[1]

M,P4[7]

1

2

P2[2],A, I,M

P2[0],A, I,M

P4[6],M

P4[4],M

P4[2],M

P4[0],M

P3[6],M

P3[4],M

P3[2],M

P3[0],M

P5[6],M

P5[4],M

P5[2],M

P5[0],M

42

41

3

4

5

6

40

9

M

M,P4[5]

M,P4[3]

M,P4[1]

39

38

37

36

35

34

33

32

31

30

29

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

M

M,P3[7]

7

8

9

10

11

12

13

14

QFN

(Top View)

M,P3[5]

M,P3[3]

M

I2C Serial Clock (SCL).

I2C Serial Data (SDA).

M,P3[1]

M,P5[7]

M,P5[5]

M,P5[3]

M,P5[1]

M

I2C Serial Clock (SCL), ISSP SCLK*.

Ground connection.

Power

USB

D+

D-

Vdd

Power

Supply voltage.

IO

P7[7]

P7[0]

P1[0]

P1[2]

P1[4]

P1[6]

P5[0]

P5[2]

P5[4]

P5[6]

P3[0]

P3[2]

P3[4]

P3[6]

P4[0]

P4[2]

P4[4]

P4[6]

P2[0]

P2[2]

P2[4]

M

I2C Serial Data (SDA), ISSP SDATA*.

Type

Digital Analog

No.

Name

Description

44

45

46

47

48

49

50

51

52

53

54

55

IO

M

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

External Voltage Reference (VREF) input.

Analog column mux input.

Analog column mux input VREF.

Analog column mux input.

Supply voltage.

I, M

Power

I, M

Vss

Ground connection.

IO

P0[7]

Analog column mux input,.

IO, M P0[5]

IO, M P0[3]

Analog column mux input and column output.

Analog column mux input.

I, M

M

Direct switched capacitor block input.

External Analog Ground (AGND) input. 56

I, M

M

P0[1]

P2[7]

P2[5]

February 15, 2007

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

1. Pin Information

1.2

56-Pin Part Pinout (with XRES)

Table 1-2. 56-Pin Part Pinout (QFN**)

Type

No.

CY8C24894 56-Pin PSoC Device

Name

Description

Digital Analog

1

2

IO

I, M

M

P2[3]

P2[1]

P4[7]

P4[5]

P4[3]

P4[1]

P3[7]

P3[5]

P3[3]

P3[1]

P5[7]

P5[5]

P5[3]

P5[1]

P1[7]

P1[5]

P1[3]

P1[1]

Vss

Direct switched capacitor block input.

3

4

5

6

7

8

M

A, I, M, P2[3]

A, I, M, P2[1]

1

2

P2[2], A, I, M

P2[0], A, I, M

42

41

40

39

38

37

9

M

M, P4[7]

M, P4[5]

M, P4[3]

M, P4[1]

M, P3[7]

3

4

5

6

P4[6], M

P4[4], M

P4[2], M

P4[0], M

XRES

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

M

7

8

QFN

(Top View)

36

35

34

33

M, P3[5]

M, P3[3]

M, P3[1]

P3[4], M

P3[2], M

P3[0], M

M

I2C Serial Clock (SCL).

I2C Serial Data (SDA).

9

10

M, P5[7]

M, P5[5]

M, P5[3]

M, P5[1]

11

12

13

14

P5[6], M

P5[4], M

P5[2], M

P5[0], M

32

31

30

29

M

I2C Serial Clock (SCL), ISSP SCLK*.

Ground connection.

Power

USB

D+

D-

Vdd

Power

Supply voltage.

IO

P7[7]

P7[0]

P1[0]

P1[2]

P1[4]

P1[6]

M

I2C Serial Data (SDA), ISSP SDATA*.

29

30

31

32

33

34

35

36

IO

M

P5[0]

P5[2]

P5[4]

P5[6]

P3[0]

P3[2]

P3[4]

Type

No.

Name

Description

Digital Analog

44

45

46

47

48

IO

M

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

External Voltage Reference (VREF) input.

Analog column mux input.

Analog column mux input VREF.

Analog column mux input.

Supply voltage.

I, M

Input

XRES Active high external reset with internal 49

pull down.

Power

37

38

39

40

41

42

43

IO

M

P4[0]

P4[2]

P4[4]

P4[6]

P2[0]

P2[2]

P2[4]

50

51

52

53

54

55

Power

I, M

Vss

Ground connection.

IO

P0[7]

Analog column mux input,.

IO, M P0[5]

IO, M P0[3]

Analog column mux input and column output.

Analog column mux input.

I, M

M

Direct switched capacitor block input.

I, M

M

P0[1]

P2[7]

P2[5]

External Analog Ground (AGND) input. 56

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

* These are the ISSP pins, which are not High Z at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details.

** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to

ground, it should be electrically floated and not connected to any other signal.

February 15, 2007

Document No. 38-12018 Rev. *J

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

1. Pin Information

1.3

68-Pin Part Pinout

The 68-pin QFN part table and drawing below is for the CY8C24994 PSoC device.

Table 1-3. 68-Pin Part Pinout (QFN**)

Type

No.

CY8C24994 68-Pin PSoC Device

Name

Description

Digital Analog

1

2

IO

M

P4[7]

P4[5]

P4[3]

P4[1]

NC

3

4

5

No connection.

6

NC

No connection.

M, P4[7]

M, P4[5]

M, P4[3]

P2[0], M, AI

P4[6], M

1

2

51

50

7

Power

Vss

Ground connection.

8

IO

M

P3[7]

P3[5]

P3[3]

P3[1]

P5[7]

P5[5]

P5[3]

P5[1]

P1[7]

P1[5]

P1[3]

P1[1]

Vss

3

4

P4[4], M

49

48

47

46

9

M, P4[1]

NC

P4[2], M

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

5

6

P4[0], M

XRES

NC

P3[6], M

P3[4], M

NC

Vs s

M, P3[7]

M, P3[5]

45

7

8

9

44

43

42

QFN

(Top View)

10

M, P3[3]

M, P3[1]

M, P5[7]

P3[2], M

P3[0], M

11

12

13

14

15

41

40

39

I2C Serial Clock (SCL).

I2C Serial Data (SDA).

M, P5[5]

P5[6], M

P5[4], M

M, P5[3]

M, P5[1]

I2C SCL, M, P1[7]

I2C SDA, M, P1[5]

38

37

36

35

P5[2], M

P5[0], M

16

17

I2C Serial Clock (SCL) ISSP SCLK*.

Ground connection.

P1[6], M

Power

USB

D+

USB

D-

Power

Vdd

Supply voltage.

IO

P7[7]

P7[6]

P7[5]

P7[4]

P7[3]

P7[2]

P7[1]

P7[0]

P1[0]

P1[2]

P1[4]

Type

No.

Name

Description

Digital Analog

50

IO

M

I,M

M

P4[6]

M

I2C Serial Data (SDA), ISSP SDATA*. 51

52

P2[0] Direct switched capacitor block input.

P2[2] Direct switched capacitor block input.

P2[4] External Analog Ground (AGND) input.

Optional External Clock Input (EXT-

CLK).

53

35

36

37

38

39

40

41

42

43

IO

M

P1[6]

P5[0]

P5[2]

P5[4]

P5[6]

P3[0]

P3[2]

P3[4]

P3[6]

54

55

56

57

58

59

60

61

62

IO

M

P2[6] External Voltage Reference (VREF) input.

P0[0] Analog column mux input.

I,M

P0[2] Analog column mux input and column output.

P0[4] Analog column mux input and column output.

P0[6] Analog column mux input.

Power

Vdd

Vss

Supply voltage.

Ground connection.

IO

I,M

P0[7] Analog column mux input, integration input #1

IO,M P0[5] Analog column mux input and column output, integra-

tion input #2.

44

45

46

NC

No connection.

63

64

IO

IO,M P0[3] Analog column mux input and column output.

I,M

M

P0[1] Analog column mux input.

P2[7]

Input

XRES Active high pin reset with internal pull 65

down.

47

48

49

IO

M

P4[0]

P4[2]

P4[4]

66

67

68

IO

M

P2[5]

I,M

P2[3] Direct switched capacitor block input.

P2[1] Direct switched capacitor block input.

LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input.

* These are the ISSP pins, which are not High Z at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details.

** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to

ground, it should be electrically floated and not connected to any other signal.

February 15, 2007

Document No. 38-12018 Rev. *J

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

1. Pin Information

1.4

68-Pin Part Pinout (On-Chip Debug)

The 68-pin QFN part table and drawing below is for the CY8C24094 On-Chip Debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production.

Table 1-4. 68-Pin Part Pinout (QFN**)

Type

No.

CY8C24094 68-Pin OCD PSoC Device

Name

Description

Digital Analog

1

2

IO

M

P4[7]

P4[5]

P4[3]

P4[1]

3

4

5

OCDE OCD even data IO.

OCDO OCD odd data output.

6

7

Power

Vss

Ground connection.

M, P4[7]

M, P4[5]

M, P4[3]

P2[0], M, AI

P4[6], M

P4[4], M

1

2

3

4

5

6

7

8

9

51

50

8

IO

M

P3[7]

P3[5]

P3[3]

P3[1]

P5[7]

P5[5]

P5[3]

P5[1]

P1[7]

P1[5]

P1[3]

P1[1]

Vss

9

49

48

47

M, P4[1]

OCDE

OCDO

P4[2], M

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

P4[0], M

XRES

CCLK

HCLK

P3[6], M

P3[4], M

P3[2], M

P3[0], M

46

45

44

43

42

41

40

39

38

37

36

35

Vss

M, P3[7]

M, P3[5]

QFN

(Top View)

10

M, P3[3]

M, P3[1]

M, P5[7]

M, P5[5]

11

12

13

14

15

16

17

I2C Serial Clock (SCL).

I2C Serial Data (SDA).

P5[6], M

P5[4], M

M, P5[3]

M, P5[1]

I2C SCL, M, P1[7]

I2C SDA, M, P1[5]

P5[2], M

P5[0], M

P1[6], M

I2C Serial Clock (SCL), ISSP SCLK*.

Ground connection.

Power

USB

D+

USB

D-

Power

Vdd

Supply voltage.

IO

P7[7]

P7[6]

P7[5]

P7[4]

P7[3]

P7[2]

P7[1]

P7[0]

P1[0]

P1[2]

P1[4]

Type

Digital Analog

No.

Name

Description

50

IO

M

I,M

M

P4[6]

M

I2C Serial Data (SDA), ISSP SDATA*. 51

52

P2[0] Direct switched capacitor block input.

P2[2] Direct switched capacitor block input.

P2[4] External Analog Ground (AGND) input.

Optional External Clock Input (EXT-

CLK).

53

35

36

37

38

39

40

41

42

43

IO

M

P1[6]

P5[0]

P5[2]

P5[4]

P5[6]

P3[0]

P3[2]

P3[4]

P3[6]

54

55

56

57

58

59

60

61

62

IO

M

P2[6] External Voltage Reference (VREF) input.

P0[0] Analog column mux input.

I,M

P0[2] Analog column mux input and column output.

P0[4] Analog column mux input and column output.

P0[6] Analog column mux input.

Power

Vdd

Vss

Supply voltage.

Ground connection.

IO

I,M

P0[7] Analog column mux input, integration input #1

IO,M P0[5] Analog column mux input and column output, integra-

tion input #2.

44

45

46

HCLK OCD high-speed clock output.

CCLK OCD CPU clock output.

63

64

IO

IO,M P0[3] Analog column mux input and column output.

I,M

M

P0[1] Analog column mux input.

P2[7]

Input

XRES Active high pin reset with internal pull 65

down.

47

48

49

IO

M

P4[0]

P4[2]

P4[4]

66

67

68

IO

M

P2[5]

I,M

P2[3] Direct switched capacitor block input.

P2[1] Direct switched capacitor block input.

LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, OCD = On-Chip Debugger.

* These are the ISSP pins, which are not High Z at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details.

** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to

ground, it should be electrically floated and not connected to any other signal.

February 15, 2007

Document No. 38-12018 Rev. *J

12

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

1. Pin Information

1.5

100-Ball VFBGA Part Pinout

The 100-ball VFBGA part is for the CY8C24994 PSoC device.

Table 1-5. 100-Ball Part Pinout (VFBGA)

No.

Name

Description

Name

Description

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

B1

B2

Power

Vss

NC

Vdd

NC

Vss

Ground connection.

F1

NC

No connection.

Ground connection.

No connection.

F2 IO

F3 IO

F4 IO

M

P5[7]

P3[5]

P5[1]

No connection.

F5

F6

Power Vss

Ground connection.

Power

Supply voltage.

No connection.

F7 IO

F8 IO

F9

M

P5[0]

P3[0]

No connection.

Power

Ground connection.

XRES Active high pin reset with internal pull down.

P7[1]

F10 IO

G1

NC

No connection.

G2 IO

G3 IO

G4 IO

G5 IO

G6 IO

G7 IO

G8 IO

G9 IO

G10 IO

H1

M

P5[5]

P3[3]

B3 IO

B4 IO

B5 IO

I,M P2[1] Direct switched capacitor block input.

I,M P0[1] Analog column mux input.

I,M P0[7] Analog column mux input.

P1[7] I2C Serial Clock (SCL).

P1[1] I2C Serial Clock (SCL), ISSP SCLK*.

B6

Power

Vdd

Supply voltage.

P1[0] I2C Serial Data (SDA), ISSP SDATA*.

B7 IO

B8 IO

I,M P0[2] Analog column mux input.

P1[6]

P3[4]

P5[6]

P7[2]

I,M P2[2] Direct switched capacitor block input.

B9

B10

C1

Power

Vss

Ground connection.

No connection.

Vss

NC

No connection.

C2 IO

C3 IO

C4 IO

M

P4[1]

P4[7]

P2[7]

H2 IO

H3 IO

H4 IO

M

P5[3]

P3[1]

P1[5] I2C Serial Data (SDA).

C5 IO IO,M P0[5] Analog column mux input and column output. H5 IO

P1[3]

P1[2]

P1[4]

P3[2]

P5[4]

P7[3]

C6 IO

C7 IO

C8 IO

C9 IO

C10

I,M P0[6] Analog column mux input.

I,M P0[0] Analog column mux input.

I,M P2[0] Direct switched capacitor block input.

H6 IO

H7 IO

H8 IO

H9 IO

H10 IO

M

P4[2]

NC

No connection.

D1

NC

J1

J2

J3

J4

Power Vss

Ground connection.

D2 IO

D3 IO

D4 IO

M

P3[7]

P4[5]

P2[5]

USB

D+

D-

D5 IO IO,M P0[3] Analog column mux input and column output. J5

Power Vdd

Supply voltage.

D6 IO

D7 IO

D8 IO

D9 IO

D10

I,M P0[4] Analog column mux input.

J6 IO

P7[7]

P7[0]

P5[2]

M

P2[6] External Voltage Reference (VREF) input.

J7 IO

J8 IO

P4[6]

P4[0]

M

J9

J10

K1

K2

K3

K4

K5

Power Vss

NC

Ground connection.

No connection.

NC

No connection.

E1

NC

E2

NC

E3 IO

E4 IO

M

P4[3]

I,M P2[3] Direct switched capacitor block input.

NC

No connection.

E5

E6

Power

Vss

Ground connection.

Power Vdd

Supply voltage.

K6 IO

K7 IO

K8 IO

P7[6]

P7[5]

P7[4]

E7 IO

E8 IO

E9 IO

E10

M

P2[4] External Analog Ground (AGND) input.

P4[4]

P3[6]

K9

Power Vss

Ground connection.

NC

No connection.

K10

LEGEND A = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection.

* This is the ISSP pin, which is not High Z at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details.

February 15, 2007

Document No. 38-12018 Rev. *J

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

CY8C24994

1. Pin Information

1

2

3

4

5

6

7

8

9

10

Vss

NC

Vss

NC

Vdd

NC

Vss

NC

A

B

C

D

E

F

Vss P2[1] P0[1] P0[7] Vdd P0[2] P2[2] Vss

P4[1] P4[7] P2[7] P0[5] P0[6] P0[0] P2[0] P4[2]

P3[7] P4[5] P2[5] P0[3] P0[4] P2[6] P4[6] P4[0]

NC P4[3] P2[3] Vss

P5[7] P3[5] P5[1] Vss

Vss P2[4] P4[4] P3[6]

Vss P5[0] P3[0] XRES P7[1]

P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2]

P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] P3[2] P5[4] P7[3]

G

H

J

Vss

D +

NC

D -

Vdd P7[7] P7[0] P5[2] Vss

Vdd P7[6] P7[5] P7[4] Vss

Vss

NC

K

BGA (Top View)

February 15, 2007

Document No. 38-12018 Rev. *J

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

1. Pin Information

1.6

100-Ball VFBGA Part Pinout (On-Chip Debug)

The 100-pin VFBGA part table and drawing below is for the CY8C24094 On-Chip Debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production.

Table 1-6. 100-Ball Part Pinout (VFBGA)

No.

Name

Description

Name

Description

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

B1

B2

Power

Vss

NC

Vdd

NC

Vss

Ground connection.

F1

OCDE OCD even data IO.

Ground connection.

No connection.

F2 IO

F3 IO

F4 IO

M

P5[7]

P3[5]

P5[1]

No connection.

F5

F6

Power Vss

Ground connection.

Power

Supply voltage.

No connection.

F7 IO

F8 IO

F9

M

P5[0]

P3[0]

No connection.

Power

Ground connection.

XRES Active high pin reset with internal pull down.

F10 IO

G1

P7[1]

OCDO OCD odd data output.

G2 IO

G3 IO

G4 IO

G5 IO

G6 IO

G7 IO

G8 IO

G9 IO

G10 IO

H1

M

P5[5]

B3 IO

B4 IO

B5 IO

I,M P2[1] Direct switched capacitor block input.

I,M P0[1] Analog column mux input.

I,M P0[7] Analog column mux input.

P3[3]

P1[7] I2C Serial Clock (SCL).

P1[1] I2C Serial Clock (SCL), ISSP SCLK*.

B6

Power

Vdd

Supply voltage.

P1[0] I2C Serial Data (SDA), ISSP SDATA*.

B7 IO

B8 IO

I,M P0[2] Analog column mux input.

P1[6]

P3[4]

P5[6]

P7[2]

I,M P2[2] Direct switched capacitor block input.

B9

B10

C1

Power

Vss

Ground connection.

No connection.

Vss

NC

No connection.

C2 IO

C3 IO

C4 IO

M

P4[1]

P4[7]

P2[7]

H2 IO

H3 IO

H4 IO

M

P5[3]

P3[1]

P1[5] I2C Serial Data (SDA).

C5 IO IO,M P0[5] Analog column mux input and column output. H5 IO

P1[3]

P1[2]

P1[4]

P3[2]

P5[4]

P7[3]

C6 IO

C7 IO

C8 IO

C9 IO

C10

I,M P0[6] Analog column mux input.

I,M P0[0] Analog column mux input.

I,M P2[0] Direct switched capacitor block input.

H6 IO

H7 IO

H8 IO

H9 IO

H10 IO

M

P4[2]

NC

No connection.

D1

NC

J1

J2

J3

J4

Power Vss

Ground connection.

D2 IO

D3 IO

D4 IO

M

P3[7]

P4[5]

P2[5]

USB

D+

D-

D5 IO IO,M P0[3] Analog column mux input and column output. J5

Power Vdd

Supply voltage.

D6 IO

D7 IO

D8 IO

D9 IO

D10

I,M P0[4] Analog column mux input.

J6 IO

P7[7]

P7[0]

P5[2]

M

P2[6] External Voltage Reference (VREF) input.

J7 IO

J8 IO

P4[6]

M

P4[0]

J9

J10

K1

K2

K3

K4

K5

Power Vss

NC

Ground connection.

No connection.

CCLK OCD CPU clock output.

E1

NC

No connection.

E2

NC

E3 IO

E4 IO

M

P4[3]

I,M P2[3] Direct switched capacitor block input.

NC

No connection.

E5

E6

Power

Vss

Ground connection.

Power Vdd

Supply voltage.

K6 IO

K7 IO

K8 IO

P7[6]

P7[5]

P7[4]

E7 IO

E8 IO

E9 IO

E10

M

P2[4] External Analog Ground (AGND) input.

P4[4]

P3[6]

K9

Power Vss

Ground connection.

HCLK OCD high-speed clock output.

K10

LEGEND A = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection, OCD = On-Chip Debugger.

* This is the ISSP pin, which is not High Z at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details.

February 15, 2007

Document No. 38-12018 Rev. *J

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

CY8C24094 OCD

1. Pin Information

1

2

3

4

5

6

7

8

9

10

Vss

NC

Vss

NC

Vdd

NC

Vss

NC

A

B

C

D

E

F

Vss P2[1] P0[1] P0[7] Vdd P0[2] P2[2] Vss

P4[1] P4[7] P2[7] P0[5] P0[6] P0[0] P2[0] P4[2]

P3[7] P4[5] P2[5] P0[3] P0[4] P2[6] P4[6] P4[0] CClk

NC P4[3] P2[3] Vss

Vss P2[4] P4[4] P3[6] HClk

Vss P5[0] P3[0] XRES P7[1]

ocde P5[7] P3[5] P5[1] Vss

ocdo P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2]

G

H

J

NC

Vss

P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] P3[2] P5[4] P7[3]

Vss

D +

NC

D -

Vdd P7[7] P7[0] P5[2] Vss

Vdd P7[6] P7[5] P7[4] Vss

Vss

NC

K

BGA (Top View)

Not for Production

February 15, 2007

Document No. 38-12018 Rev. *J

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

1. Pin Information

1.7

100-Pin Part Pinout (On-Chip Debug)

The 100-pin TQFP part is for the CY8C24094 On-Chip Debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production.

Table 1-7. 100-Pin Part Pinout (TQFP)

No.

Name

Description

Name

Description

1

NC

No connection.

51 IO

52 IO

53 IO

54 IO

55 IO

56 IO

57 IO

58 IO

59 IO

60

M

P1[6]

P5[0]

P5[2]

P5[4]

P5[6]

P3[0]

P3[2]

P3[4]

P3[6]

2

3

IO I, M P0[1] Analog column mux input.

4

IO

M

P2[7]

P2[5]

5

6

IO I, M P2[3] Direct switched capacitor block input.

IO I, M P2[1] Direct switched capacitor block input.

7

8

IO

M

P4[7]

9

P4[5]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

P4[3]

HCLK OCD high-speed clock output.

P4[1]

61

CCLK OCD CPU clock output.

OCDE OCD even data IO.

OCDO OCD odd data output.

62

Input

XRES Active high pin reset with internal pull down.

63 IO

64 IO

M

P4[0]

P4[2]

NC

Power Vss

No connection.

Ground connection.

65

Power

Vss

Ground connection.

IO

M

P3[7]

66 IO

67 IO

M

P4[4]

P4[6]

IO

P3[5]

P3[3]

P3[1]

P5[7]

P5[5]

P5[3]

P5[1]

68 IO I, M P2[0] Direct switched capacitor block input.

69 IO I, M P2[2] Direct switched capacitor block input.

70 IO

71

P2[4] External Analog Ground (AGND) input.

NC No connection.

P2[6] External Voltage Reference (VREF) input.

NC No connection.

P0[0] Analog column mux input.

72 IO

73

P1[7] I2C Serial Clock (SCL).

74 IO

75

I

NC

No connection.

NC

No connection.

76

77 IO I, M P0[2] Analog column mux input and column output.

78 NC No connection.

79 IO I, M P0[4] Analog column mux input and column output.

80 NC No connection.

IO

P1[5] I2C Serial Data (SDA)

P1[3]

P1[1] Crystal (XTALin), I2C Serial Clock (SCL),

ISSP SCLK*.

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

NC

Power Vss

No connection.

81 IO I, M P0[6] Analog column mux input.

Ground connection.

82

83

84

85

86

87

88

89

90

91

92

93

94

Power

Vdd

NC

Vss

NC

Supply voltage.

No connection.

Ground connection.

No connection.

USB

D+

D-

Power

Power Vdd

Supply voltage.

IO

P7[7]

P7[6]

P7[5]

P7[4]

P7[3]

P7[2]

P7[1]

P7[0]

NC

IO

No connection.

NC

95 IO I, M P0[7] Analog column mux input.

96 NC No connection.

97 IO IO, M P0[5] Analog column mux input and column output.

98 NC No connection.

NC

IO

P1[0] Crystal (XTALout), I2C Serial Data (SDA),

ISSP SDATA*.

49

50

IO

P1[2]

99 IO IO, M P0[3] Analog column mux input and column output.

100 NC No connection.

P1[4] Optional External Clock Input (EXTCLK).

LEGEND A = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input, OCD = On-Chip Debugger.

* These are the ISSP pins, which are not High Z at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details.

February 15, 2007

Document No. 38-12018 Rev. *J

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

CY8C24094 OCD

1. Pin Information

NC

1

2

3

4

75

74

P0[0],M, AI

NC

AI,M,P0[1]

M,P2[7]

M,P2[5]

AI,M,P2[3]

AI,M,P2[1]

M,P4[7]

M,P4[5]

M,P4[3]

M,P4[1]

OCDE

73

72

71

P2[6],M,External VREF

NC

P2[4],M,External AGND

5

6

70

69

7

8

9

P2[2],M, AI

P2[0],M, AI

P4[6],M

68

67

P4[4],M

10

11

12

13

14

15

16

17

18

19

20

21

22

66

65

64

63

62

61

60

59

Vss

P4[2],M

OCDO

TQFP

P4[0],M

XRES

NC

Vss

M,P3[7]

M,P3[5]

CCLK

HCLK

P3[6],M

P3[4],M

P3[2],M

P3[0],M

P5[6],M

M,P3[3]

58

57

56

55

M,P3[1]

M,P5[7]

M,P5[5]

P5[4],M

P5[2],M

P5[0],M

M,P5[3]

M,P5[1]

54

53

52

51

23

24

25

I2C SCL,P1[7]

NC

P1[6],M

Not for Production

February 15, 2007

Document No. 38-12018 Rev. *J

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2. Register Reference

This chapter lists the registers of the CY8C24x94 PSoC device family. For detailed register information, reference the

PSoC Mixed-Signal Array Technical Reference Manual.

2.1

Register Conventions

2.2

Register Mapping Tables

The PSoC device has a total register address space of 512

bytes. The register space is referred to as IO space and is

divided into two banks. The XOI bit in the Flag register (CPU_F)

determines which bank the user is currently in. When the XOI

bit is set the user is in Bank 1.

2.1.1

Abbreviations Used

The register conventions specific to this section are listed in the

following table.

Note In the following register mapping tables, blank fields are

Reserved and should not be accessed.

Convention

Description

Read register or bit(s)

R

W

L

Write register or bit(s)

Logical register or bit(s)

Clearable register or bit(s)

Access is bit specific

C

#

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Document No. 38-12018 Rev. *J

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

2. Register Reference

Register Map Bank 0 Table: User Space

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

PMA0_DR

PMA1_DR

PMA2_DR

PMA3_DR

PMA4_DR

PMA5_DR

PMA6_DR

PMA7_DR

USB_SOF0

USB_SOF1

USB_CR0

USBIO_CR0

USBIO_CR1

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

RW

R

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

PRT0DR

PRT0IE

PRT0GS

PRT0DM2

PRT1DR

PRT1IE

PRT1GS

PRT1DM2

PRT2DR

PRT2IE

PRT2GS

PRT2DM2

PRT3DR

PRT3IE

PRT3GS

PRT3DM2

PRT4DR

PRT4IE

PRT4GS

PRT4DM2

PRT5DR

PRT5IE

ASC10CR0

ASC10CR1

ASC10CR2

ASC10CR3

ASD11CR0

ASD11CR1

ASD11CR2

ASD11CR3

RW

R

RW

#

RW

EP1_CNT1

EP1_CNT

EP2_CNT1

EP2_CNT

EP3_CNT1

EP3_CNT

EP4_CNT1

EP4_CNT

EP0_CR

EP0_CNT

EP0_DR0

EP0_DR1

EP0_DR2

EP0_DR3

EP0_DR4

EP0_DR5

EP0_DR6

EP0_DR7

AMX_IN

#

RW

#

RW

#

RW

#

RW

#

RW

ASD20CR0

ASD20CR1

ASD20CR2

ASD20CR3

ASC21CR0

ASC21CR1

ASC21CR2

ASC21CR3

RW

CUR_PP

STK_PP

RW

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

IDX_PP

RW

#

MVR_PP

MVW_PP

I2C_CFG

I2C_SCR

I2C_DR

I2C_MSCR

INT_CLR0

INT_CLR1

INT_CLR2

INT_CLR3

INT_MSK3

INT_MSK2

INT_MSK0

INT_MSK1

INT_VC

PRT5GS

PRT5DM2

RW

#

RW

RC

W

RC

RW

W

R

RW

PRT7DR

PRT7IE

PRT7GS

RW

#

W

RW

#

W

RW

#

PRT7DM2

DBB00DR0

DBB00DR1

DBB00DR2

DBB00CR0

DBB01DR0

DBB01DR1

DBB01DR2

DBB01CR0

DCB02DR0

DCB02DR1

DCB02DR2

DCB02CR0

DCB03DR0

DCB03DR1

DCB03DR2

DCB03CR0

AMUXCFG

ARF_CR

CMP_CR0

ASY_CR

CMP_CR1

RW

#

RES_WDT

DEC_DH

DEC_DL

DEC_CR0

DEC_CR1

MUL0_X

RW

MUL1_X

MUL1_Y

W

R

W

RW

#

W

MUL0_Y

MUL1_DH

MUL1_DL

ACC1_DR1

ACC1_DR0

ACC1_DR3

ACC1_DR2

RDI0RI

RDI0SYN

RDI0IS

RDI0LT0

MUL0_DH

MUL0_DL

ACC0_DR1

ACC0_DR0

ACC0_DR3

ACC0_DR2

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

ACB00CR3

ACB00CR0

ACB00CR1

ACB00CR2

ACB01CR3

ACB01CR0

ACB01CR1

ACB01CR2

RW

#

RDI0LT1

RDI0RO0

RDI0RO1

CPU_F

RL

DAC_D

CPU_SCR1

CPU_SCR0

RW

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

February 15, 2007

Document No. 38-12018 Rev. *J

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

2. Register Reference

Register Map Bank 1 Table: Configuration Space

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

USBIO_CR2

USB_CR1

C0

C1

RW

#

PRT0DM0

PRT0DM1

PRT0IC0

PRT0IC1

PRT1DM0

PRT1DM1

PRT1IC0

PRT1IC1

PRT2DM0

PRT2DM1

PRT2IC0

PRT2IC1

PRT3DM0

PRT3DM1

PRT3IC0

PRT3IC1

PRT4DM0

PRT4DM1

PRT4IC0

PRT4IC1

PRT5DM0

PRT5DM1

PRT5IC0

PRT5IC1

RW

PMA0_WA

PMA1_WA

PMA2_WA

PMA3_WA

PMA4_WA

PMA5_WA

PMA6_WA

PMA7_WA

RW

ASC10CR0

ASC10CR1

ASC10CR2

ASC10CR3

ASD11CR0

ASD11CR1

ASD11CR2

ASD11CR3

RW

EP1_CR0

EP2_CR0

EP3_CR0

EP4_CR0

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

#

PMA0_RA

PMA1_RA

PMA2_RA

PMA3_RA

PMA4_RA

PMA5_RA

PMA6_RA

PMA7_RA

RW

GDI_O_IN

GDI_E_IN

GDI_O_OU

GDI_E_OU

RW

ASD20CR1

ASD20CR2

ASD20CR3

ASC21CR0

ASC21CR1

ASC21CR2

ASC21CR3

RW

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

MUX_CR0

MUX_CR1

MUX_CR2

MUX_CR3

RW

PRT7DM0

PRT7DM1

PRT7IC0

PRT7IC1

DBB00FN

DBB00IN

DBB00OU

RW

OSC_GO_EN

OSC_CR4

OSC_CR3

OSC_CR0

OSC_CR1

OSC_CR2

VLT_CR

RW

R

CLK_CR0

CLK_CR1

ABF_CR0

AMD_CR0

CMP_GO_EN

CMP_GO_EN1

AMD_CR1

ALT_CR0

RW

DBB01FN

DBB01IN

DBB01OU

RW

VLT_CMP

DCB02FN

DCB02IN

DCB02OU

RW

IMO_TR

ILO_TR

BDG_TR

ECO_TR

MUX_CR4

MUX_CR5

W

RW

W

RW

DCB03FN

DCB03IN

DCB03OU

RW

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

ACB00CR3

ACB00CR0

ACB00CR1

ACB00CR2

ACB01CR3

ACB01CR0

ACB01CR1

ACB01CR2

RW

RDI0RI

RDI0SYN

RDI0IS

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

RW

CPU_F

RL

DAC_CR

CPU_SCR1

CPU_SCR0

RW

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

February 15, 2007

Document No. 38-12018 Rev. *J

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3. Electrical Specifications

This chapter presents the DC and AC electrical specifications of the CY8C24x94 PSoC device family. For the most up to date elec-

trical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.

Specifications are valid for -40^oC ≤ T ≤ 85^oC and T ≤ 100^oC, except where noted. Specifications for devices running at greater

A

J

than 12 MHz are valid for -40^oC ≤ T ≤ 70^oC and T ≤ 82^oC.

A

J

Figure 3-1. Voltage versus CPU Frequency

5.25

4.75

3.00

93 kHz

12 MHz

24 MHz

CPUFrequency

The following table lists the units of measure that are used in this chapter.

Table 3-1: Units of Measure

Symbol

Unit of Measure

Symbol

Unit of Measure

o

degree Celsius

µW

microwatts

C

dB

fF

decibels

mA

ms

mV

nA

ns

milli-ampere

milli-second

milli-volts

femto farad

hertz

Hz

KB

1024 bytes

1024 bits

kilohertz

nanoampere

nanosecond

nanovolts

Kbit

kHz

kΩ

nV

Ω

kilohm

ohm

MHz

MΩ

µA

megahertz

megaohm

microampere

microfarad

microhenry

microsecond

microvolts

pA

pF

pp

ppm

ps

picoampere

picofarad

peak-to-peak

parts per million

picosecond

µF

µH

µs

sps

σ

samples per second

sigma: one standard deviation

volts

µV

µVrms

microvolts root-mean-square

V

February 15, 2007

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3. Electrical Specifications

3.1

Absolute Maximum Ratings

Table 3-2. Absolute Maximum Ratings

Symbol

Description

Min

-55

Typ

Max

+100

Units

Notes

o

T

Storage Temperature

25

–

Higher storage temperatures will reduce data

retention time. Recommended storage temper-

STG

C

o

ature is +25 C ± 25 C. Extended duration stor-

o

age temperatures above 65 C will degrade

reliability.

T

Ambient Temperature with Power Applied

-40

+85

A

C

Vdd

Supply Voltage on Vdd Relative to Vss

DC Input Voltage

-0.5

–

+6.0

V

Vss - 0.5

Vdd + 0.5

IO

DC Voltage Applied to Tri-state

Vss - 0.5

-25

–

Vdd + 0.5

+50

V

IO2

I

Maximum Current into any Port Pin

mA

MIO

MAIO

I

Maximum Current into any Port Pin Configured as Analog

Driver

-50

+50

ESD

LU

Electro Static Discharge Voltage

Latch-up Current

2000

–

V

Human Body Model ESD.

200

mA

3.2

Operating Temperature

Table 3-3. Operating Temperature

Symbol

Description

Min

Typ

Max

Units

Notes

o

T

Ambient Temperature

-40

–

+85

A

C

o

T

Ambient Temperature using USB

Junction Temperature

-10

-40

+85

AUSB

T

+100

The temperature rise from ambient to junction is

package specific. See “Thermal Impedance” on

page 42. The user must limit the power con-

sumption to comply with this requirement.

J

3.3

DC Electrical Characteristics

3.3.1

DC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-4. DC Chip-Level Specifications

Symbol

Description

Min

3.0

Typ

Max

5.25

Units

Notes

Vdd

Supply Voltage

–

V

See DC POR and LVD specifications, Table 3-

15 on page 29.

o

I

Supply Current, IMO = 24 MHz (5V)

–

14

27

mA

DD5

DD3

Conditions are Vdd = 5.0V, T = 25 C, CPU = 3

A

MHz, SYSCLK doubler disabled, VC1 = 1.5

MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, ana-

log power = off.

o

I

Supply Current, IMO = 24 MHz (3.3V)

–

8

14

Conditions are Vdd = 3.3V, T = 25 C, CPU = 3

A

MHz, SYSCLK doubler disabled, VC1 = 1.5

MHz, VC2 = 93.75 kHz, VC3 = 0.367 kHz, ana-

log power = off.

I

Sleep (Mode) Current with POR, LVD, Sleep Timer, and

–

3

4

6.5

25

µA

Conditions are with internal slow speed oscilla-

SB

a

o

WDT.

tor, Vdd = 3.3V, -40 C ≤ T ≤ 55 C, analog

A

power = off.

Sleep (Mode) Current with POR, LVD, Sleep Timer, and

Conditions are with internal slow speed oscilla-

SBH

a

o

WDT at high temperature.

tor, Vdd = 3.3V, 55 C < T ≤ 85 C, analog

A

power = off.

a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions

enabled.

February 15, 2007

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3. Electrical Specifications

3.3.2

DC General Purpose IO Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-5. DC GPIO Specifications

Symbol

Description

Min

Typ

5.6

Max

Units

kΩ

Notes

R

Pull-Up Resistor

Pull-Down Resistor

High Output Level

4

8

–

PU

PD

OH

R

5.6

–

kΩ

V

Vdd - 1.0

V

IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads,

4 on even port pins (for example, P0[2], P1[4]),

4 on odd port pins (for example, P0[3], P1[5])).

80 mA maximum combined IOH budget.

V

Low Output Level

–

0.75

0.8

V

IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads,

4 on even port pins (for example, P0[2], P1[4]),

4 on odd port pins (for example, P0[3], P1[5])).

200 mA maximum combined IOL budget.

OL

V

I

Input Low Level

Input High Level

Input Hysterisis

–

V

Vdd = 3.0 to 5.25.

IL

IH

H

2.1

–

V

60

1

–

mV

nA

pF

Input Leakage (Absolute Value)

Capacitive Load on Pins as Input

Capacitive Load on Pins as Output

–

Gross tested to 1 µA.

IL

o

C

–

3.5

10

IN

Package and pin dependent. Temp = 25 C.

o

–

OUT

Package and pin dependent. Temp = 25 C.

3.3.3

DC Full-Speed USB Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -10°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -10°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-6. DC Full-Speed (12 Mbps) USB Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

USB Interface

V

Differential Input Sensitivity

0.2

–

V

| (D+) - (D-) |

DI

Differential Input Common Mode Range

Single Ended Receiver Threshold

Transceiver Capacitance

0.8

–

2.5

2.0

20

CM

SE

C

I

pF

µA

Ω

V

IN

High-Z State Data Line Leakage

External USB Series Resistor

Static Output High, Driven

Static Output High, Idle

-10

23

2.8

2.7

–

10

0V < V < 3.3V.

IN

IO

R

V

25

In series with each USB pin.

EXT

3.6

0.3

44

15 kΩ ± 5% to Ground. Internal pull-up enabled.

UOH

UOHI

UOL

V

Z

V

Static Output Low

V

USB Driver Output Impedance

D+/D- Crossover Voltage

28

1.3

Ω

V

Including R

Resistor.

O

EXT

V

2.0

CRS

February 15, 2007

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

3. Electrical Specifications

3.3.4

DC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor

PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.

Table 3-7. 5V DC Operational Amplifier Specifications

Symbol

Description

Input Offset Voltage (absolute value)

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

Average Input Offset Voltage Drift

Min

Typ

Max

Units

Notes

V

OSOA

–

1.6

10

8

mV

1.3

1.2

7.0

mV

7.5

o

TCV

I

35.0

OSOA

µV/ C

Input Leakage Current (Port 0 Analog Pins)

Input Capacitance (Port 0 Analog Pins)

Common Mode Voltage Range

–

20

–

pA

Gross tested to 1 µA.

EBOA

o

C

4.5

9.5

pF

V

INOA

Package and pin dependent. Temp = 25 C.

V

0.0

0.5

–

Vdd

The common-mode input voltage range is mea-

sured through an analog output buffer. The

specification includes the limitations imposed

by the characteristics of the analog output

buffer.

CMOA

Common Mode Voltage Range (high power or high

opamp bias)

Vdd - 0.5

G

Open Loop Gain

–

dB

OLOA

OHIGHOA

OLOWOA

SOA

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

High Output Voltage Swing (internal signals)

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

Low Output Voltage Swing (internal signals)

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

Supply Current (including associated AGND buffer)

Power = Low, Opamp Bias = Low

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = Low

Power = High, Opamp Bias = High

Supply Voltage Rejection Ratio

60

80

V

Vdd - 0.2

Vdd - 0.5

–

V

–

0.2

0.5

V

I

–

400

500

800

1200

2400

4600

80

800

900

1000

1600

3200

6400

–

µA

dB

–

PSRR

65

Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN

≤ Vdd.

OA

February 15, 2007

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Table 3-8. 3.3V DC Operational Amplifier Specifications

3. Electrical Specifications

Symbol

Description

Input Offset Voltage (absolute value)

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = High

High Power is 5 Volts Only

Min

Typ

Max

Units

Notes

V

OSOA

–

1.65

10

8

mV

1.32

o

TCV

I

Average Input Offset Voltage Drift

–

7.0

20

4.5

–

35.0

OSOA

µV/ C

Input Leakage Current (Port 0 Analog Pins)

Input Capacitance (Port 0 Analog Pins)

Common Mode Voltage Range

–

pA

Gross tested to 1 µA.

EBOA

o

C

–

9.5

pF

V

INOA

Package and pin dependent. Temp = 25 C.

V

0.2

Vdd - 0.2

The common-mode input voltage range is

measured through an analog output buffer.

The specification includes the limitations

imposed by the characteristics of the analog

output buffer.

CMOA

G

Open Loop Gain

–

dB

OLOA

OHIGHOA

OLOWOA

SOA

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = Low

Power = High, Opamp Bias = Low

High Output Voltage Swing (internal signals)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = Low

Power = High is 5V only

60

80

V

Vdd - 0.2

–

V

Low Output Voltage Swing (internal signals)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = Low

Power = High, Opamp Bias = Low

Supply Current (including associated AGND buffer)

Power = Low, Opamp Bias = Low

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = Low

Power = High, Opamp Bias = High

Supply Voltage Rejection Ratio

–

0.2

V

I

–

400

500

800

1200

2400

4600

80

800

900

1000

1600

3200

6400

–

µA

dB

–

PSRR

65

Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤

VIN ≤ Vdd.

OA

3.3.5

DC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters

apply to 5V at 25°C and are for design guidance only.

Table 3-9. DC Low Power Comparator Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

V

I

Low power comparator (LPC) reference voltage range

0.2

–

Vdd - 1

V

REFLPC

LPC supply current

LPC voltage offset

10

40

30

µA

SLPC

V

–

2.5

mV

OSLPC

February 15, 2007

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3. Electrical Specifications

3.3.6

DC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-10. 5V DC Analog Output Buffer Specifications

Symbol

Description

Min

Typ

Max

Units

mV

Notes

V

Input Offset Voltage (Absolute Value)

–

3

12

–

OSOB

TCV

Average Input Offset Voltage Drift

Common-Mode Input Voltage Range

–

+6

–

µV/°C

OSOB

CMOB

V

0.5

Vdd - 1.0

V

R

Output Resistance

Power = Low

OUTOB

–

0.6

–

Ω

Power = High

V

High Output Voltage Swing (Load = 32 ohms to Vdd/2)

Power = Low

OHIGHOB

OLOWOB

SOB

0.5 x Vdd + 1.1

–

V

Power = High

V

Low Output Voltage Swing (Load = 32 ohms to Vdd/2)

Power = Low

Power = High

–

0.5 x Vdd - 1.3

V

I

Supply Current Including Bias Cell (No Load)

Power = Low

–

1.1

2.6

64

5.1

8.8

–

mA

dB

Power = High

–

PSRR

Supply Voltage Rejection Ratio

53

(0.5 x Vdd - 1.3) ≤ V

≤ (Vdd -

OUT

OB

2.3).

Table 3-11. 3.3V DC Analog Output Buffer Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

V

Input Offset Voltage (Absolute Value)

–

3

12

mV

µV/°C

V

OSOB

TCV

Average Input Offset Voltage Drift

Common-Mode Input Voltage Range

–

+6

-

–

OSOB

CMOB

V

0.5

Vdd - 1.0

R

Output Resistance

OUTOB

Power = Low

–

1

–

Ω

Power = High

V

High Output Voltage Swing (Load = 1K ohms to Vdd/2)

OHIGHOB

OLOWOB

SOB

Power = Low

Power = High

0.5 x Vdd + 1.0

–

V

Low Output Voltage Swing (Load = 1K ohms to Vdd/2)

Power = Low

Power = High

–

0.5 x Vdd - 1.0

V

I

Supply Current Including Bias Cell (No Load)

Power = Low

0.8

2.0

64

2.0

4.3

–

mA

dB

Power = High

–

PSRR

Supply Voltage Rejection Ratio

34

(0.5 x Vdd - 1.0) ≤ V

≤ (0.5 x

OB

OUT

Vdd + 0.9).

February 15, 2007

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

3. Electrical Specifications

3.3.7

DC Analog Reference Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to

the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control

register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.

Reference control power is high.

Table 3-12. 5V DC Analog Reference Specifications

Symbol

Description

Bandgap Voltage Reference

Min

Typ

Max

Units

BG

–

1.28

1.30

1.32

V

a

Vdd/2 - 0.04

2 x BG - 0.048

P2[4] - 0.011

BG - 0.009

Vdd/2 - 0.01

2 x BG - 0.030

P2[4]

Vdd/2 + 0.007

2 x BG + 0.024

P2[4] + 0.011

BG + 0.016

AGND = Vdd/2

AGND = 2 x BandGap

a

–

V

a

AGND = P2[4] (P2[4] = Vdd/2)

a

BG + 0.008

1.6 x BG - 0.010

0.000

AGND = BandGap

a

1.6 x BG - 0.022

-0.034

1.6 x BG + 0.018

0.034

AGND = 1.6 x BandGap

a

AGND Block to Block Variation (AGND = Vdd/2)

RefHi = Vdd/2 + BandGap

–

V

Vdd/2 + BG - 0.10

3 x BG - 0.06

Vdd/2 + BG

Vdd/2 + BG + 0.10

3 x BG + 0.06

RefHi = 3 x BandGap

3 x BG

RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)

RefHi = P2[4] + BandGap (P2[4] = Vdd/2)

2 x BG + P2[6] - 0.113

P2[4] + BG - 0.130

P2[4] + P2[6] - 0.133

3.2 x BG - 0.112

2 x BG + P2[6] - 0.018

P2[4] + BG - 0.016

P2[4] + P2[6] - 0.016

3.2 x BG

2 x BG + P2[6] + 0.077

P2[4] + BG + 0.098

P2[4] + P2[6]+ 0.100

3.2 x BG + 0.076

Vdd/2 - BG + 0.04

BG + 0.06

RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)

RefHi = 3.2 x BandGap

RefLo = Vdd/2 – BandGap

Vdd/2 - BG - 0.04

BG - 0.06

Vdd/2 - BG + 0.024

BG

RefLo = BandGap

RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)

RefLo = P2[4] – BandGap (P2[4] = Vdd/2)

RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)

2 x BG - P2[6] - 0.084

P2[4] - BG - 0.056

P2[4] - P2[6] - 0.057

2 x BG - P2[6] + 0.025

P2[4] - BG + 0.026

P2[4] - P2[6] + 0.026

2 x BG - P2[6] + 0.134

P2[4] - BG + 0.107

P2[4] - P2[6] + 0.110

a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.

Table 3-13. 3.3V DC Analog Reference Specifications

Symbol

BG

Description

Bandgap Voltage Reference

Min

Typ

Max

1.32

Units

1.28

1.30

V

a

–

Vdd/2 - 0.03

Vdd/2 - 0.01

Vdd/2 + 0.005

AGND = Vdd/2

AGND = 2 x BandGap

a

Not Allowed

P2[4] - 0.008

BG - 0.009

–

AGND = P2[4] (P2[4] = Vdd/2)

P2[4] + 0.001

BG + 0.005

P2[4] + 0.009

BG + 0.015

V

a

AGND = BandGap

a

–

1.6 x BG - 0.027

-0.034

1.6 x BG - 0.010

0.000

1.6 x BG + 0.018

0.034

V

AGND = 1.6 x BandGap

a

AGND Column to Column Variation (AGND = Vdd/2)

RefHi = Vdd/2 + BandGap

–

Not Allowed

RefHi = 3 x BandGap

Not Allowed

RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)

RefHi = P2[4] + BandGap (P2[4] = Vdd/2)

RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)

RefHi = 3.2 x BandGap

Not Allowed

P2[4] + P2[6] - 0.075

Not Allowed

P2[4] + P2[6] - 0.009

P2[4] + P2[6] + 0.057

V

RefLo = Vdd/2 - BandGap

Not Allowed

RefLo = BandGap

Not Allowed

RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)

RefLo = P2[4] – BandGap (P2[4] = Vdd/2)

RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)

Not Allowed

P2[4] - P2[6] - 0.048

P2[4]- P2[6] + 0.022

P2[4] - P2[6] + 0.092

a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.

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3. Electrical Specifications

3.3.8

DC Analog PSoC Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-14. DC Analog PSoC Block Specifications

Symbol

Description

Min

Typ

12.2

80

Max

Units

kΩ

fF

Notes

R

C

Resistor Unit Value (Continuous Time)

–

CT

SC

Capacitor Unit Value (Switched Capacitor)

3.3.9

DC POR and LVD Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V or 3.3V at 25°C and are

for design guidance only.

Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Mixed-Signal Array Technical

Reference Manual for more information on the VLT_CR register.

Table 3-15. DC POR and LVD Specifications

Symbol

Description

Vdd Value for PPOR Trip (positive ramp)

PORLEV[1:0] = 00b

Min

Typ

Max

Units

Notes

V

PPOR0R

PPOR1R

PPOR2R

2.91

V

PORLEV[1:0] = 01b

–

4.39

4.55

–

PORLEV[1:0] = 10b

Vdd Value for PPOR Trip (negative ramp)

PORLEV[1:0] = 00b

V

PPOR0

PPOR1

PPOR2

2.82

4.39

4.55

V

PORLEV[1:0] = 01b

PORLEV[1:0] = 10b

PPOR Hysteresis

PORLEV[1:0] = 00b

PORLEV[1:0] = 01b

PORLEV[1:0] = 10b

V

PH0

PH1

PH2

–

92

0

–

mV

0

Vdd Value for LVD Trip

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

V

a

2.86

2.96

3.07

3.92

4.39

4.55

4.63

4.72

2.92

3.02

3.13

4.00

4.48

4.64

4.73

4.81

LVD0

LVD1

LVD2

LVD3

LVD4

LVD5

LVD6

LVD7

V

2.98

3.08

3.20

4.08

4.57

V

b

4.74

4.82

4.91

a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.

b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.

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3. Electrical Specifications

3.3.10

DC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-16. DC Programming Specifications

Symbol

Description

Min

Typ

Max

Units

mA

Notes

I

Supply Current During Programming or Verify

–

15

–

30

0.8

–

DDP

V

Input Low Voltage During Programming or Verify

Input High Voltage During Programming or Verify

–

V

ILP

IHP

V

2.1

–

V

I

Input Current when Applying Vilp to P1[0] or P1[1] During

Programming or Verify

–

0.2

mA

Driving internal pull-down resistor.

ILP

Input Current when Applying Vihp to P1[0] or P1[1] During

Programming or Verify

–

1.5

mA

IHP

V

Output Low Voltage During Programming or Verify

Output High Voltage During Programming or Verify

–

Vss + 0.75

Vdd

V

OLV

Vdd - 1.0

OHV

Flash

Flash Endurance (per block)

50,000

1,800,000

10

–

Erase/write cycles per block.

Erase/write cycles.

ENPB

ENT

DR

a

–

Flash Endurance (total)

Flash Data Retention

Years

a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of

25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than

50,000 cycles).

For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to

the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

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3. Electrical Specifications

3.4

AC Electrical Characteristics

3.4.1

AC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-17. AC Chip-Level Specifications

Symbol

Description

Min

23.04

Typ

Max

Units

MHz

Notes

a,b

F

Internal Main Oscillator Frequency for 24 MHz (5V)

24

Trimmed for 5V operation using factory trim

values.

IMO245V

24.96

25.92

24.06

b,c

b

Internal Main Oscillator Frequency for 24 MHz (3.3V)

22.08

23.94

MHz

Trimmed for 3.3V operation using factory

trim values.

IMO243V

Internal Main Oscillator Frequency with USB (5V)

Frequency locking enabled and USB traffic present.

-10°C ≤ T ≤ 85°C

4.35 ≤ Vdd ≤ 5.15

IMOUSB5V

A

b

F

Internal Main Oscillator Frequency with USB (3.3V)

Frequency locking enabled and USB traffic present.

23.94

24

MHz

-0°C ≤ T ≤ 70°C

3.15 ≤ Vdd ≤ 3.45

IMOUSB3V

24.06

A

a,b

F

CPU Frequency (5V Nominal)

0.93

0

24

12

48

24

32

MHz

kHz

CPU1

CPU2

BLK5

BLK3

32K1

24.96

12.96

49.92

b,c

CPU Frequency (3.3V Nominal)

a,b,d

b, d

Digital PSoC Block Frequency (5V Nominal)

Digital PSoC Block Frequency (3.3V Nominal)

Internal Low Speed Oscillator Frequency

Refer to the AC Digital Block Specifications.

0

25.92

15

64

Jitter32k

Step24M

Fout48M

32 kHz Period Jitter

–

100

50

ns

24 MHz Trim Step Size

48 MHz Output Frequency

–

kHz

MHz

a,c

46.08

48.0

Trimmed. Utilizing factory trim values.

49.92

Jitter24M1

24 MHz Period Jitter (IMO) Peak-to-Peak

–

300

–

ps

F

T

Maximum frequency of signal on row input or row output.

12.96

–

MHz

MAX

Supply Ramp Time

0

–

µs

RAMP

a. 4.75V < Vdd < 5.25V.

b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.

c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.

d. See the individual user module data sheets for information on maximum frequencies for user modules.

Figure 3-2. 24 MHz Period Jitter (IMO) Timing Diagram

Jitter24M1

F_24M

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3. Electrical Specifications

3.4.2

AC General Purpose IO Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-18. AC GPIO Specifications

Symbol

Description

GPIO Operating Frequency

Min

Typ

Max

Units

MHz

Notes

Normal Strong Mode

F

0

–

12

GPIO

TRiseF

TFallF

TRiseS

TFallS

Rise Time, Normal Strong Mode, Cload = 50 pF

Fall Time, Normal Strong Mode, Cload = 50 pF

Rise Time, Slow Strong Mode, Cload = 50 pF

Fall Time, Slow Strong Mode, Cload = 50 pF

3

–

18

–

ns

Vdd = 4.5 to 5.25V, 10% - 90%

Vdd = 3 to 5.25V, 10% - 90%

2

–

10

27

22

–

Figure 3-3. GPIO Timing Diagram

90%

GPIO

Output

Voltage

10%

TRiseF

TRiseS

TFallF

TFallS

3.4.3

AC Full-Speed USB Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -10°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -10°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-19. AC Full-Speed (12 Mbps) USB Specifications

Symbol

Description

Min

Typ

Max

Units

ns

Notes

T

Transition Rise Time

Transition Fall Time

4

–

20

For 50 pF load.

RFS

T

4

20

ns

%

FSS

Rise/Fall Time Matching: (T /T )

90

111

RFMFS

DRATEFS

R

F

Full-Speed Data Rate

12 - 0.25% 12

12 + 0.25% Mbps

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3. Electrical Specifications

3.4.4

AC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.

Power = High and Opamp Bias = High is not supported at 3.3V.

Table 3-20. 5V AC Operational Amplifier Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

T

Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF

load, Unity Gain)

ROA

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

–

3.9

µs

–

0.72

0.62

µs

–

T

Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF

load, Unity Gain)

SOA

Power = Low, Opamp Bias = Low

–

5.9

µs

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

0.92

0.72

SR

Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)

Power = Low, Opamp Bias = Low

ROA

FOA

0.15

1.7

–

V/µs

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

6.5

Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)

Power = Low, Opamp Bias = Low

0.01

0.5

–

V/µs

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

4.0

BW

Gain Bandwidth Product

OA

Power = Low, Opamp Bias = Low

0.75

3.1

5.4

–

MHz

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

MHz

E

Noise at 1 kHz (Power = Medium, Opamp Bias = High)

100

nV/rt-Hz

NOA

Table 3-21. 3.3V AC Operational Amplifier Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

T

Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF

load, Unity Gain)

ROA

Power = Low, Opamp Bias = Low

–

3.92

0.72

µs

Power = Medium, Opamp Bias = High

T

Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF

load, Unity Gain)

SOA

Power = Low, Opamp Bias = Low

–

5.41

0.72

µs

Power = Medium, Opamp Bias = High

Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)

Power = Low, Opamp Bias = Low

SR

ROA

FOA

0.31

2.7

–

V/µs

Power = Medium, Opamp Bias = High

Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)

Power = Low, Opamp Bias = Low

0.24

1.8

–

V/µs

Power = Medium, Opamp Bias = High

Gain Bandwidth Product

BW

OA

Power = Low, Opamp Bias = Low

0.67

2.8

–

MHz

Power = Medium, Opamp Bias = High

Noise at 1 kHz (Power = Medium, Opamp Bias = High)

–

MHz

E

100

nV/rt-Hz

NOA

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3. Electrical Specifications

When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up

to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.

Figure 3-4. Typical AGND Noise with P2[4] Bypass

dBV/rtHz

10000

0

0.01

0.1

1.0

10

1000

100

0.001

0.01

0.1 Freq (kHz)

1

10

100

At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequen-

cies, increased power level reduces the noise spectrum level.

Figure 3-5. Typical Opamp Noise

nV/rtHz

10000

PH_BH

PH_BL

PM_BL

PL_BL

1000

100

10

0.001

0.01

0.1

1

10

100

Freq (kHz)

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3. Electrical Specifications

3.4.5

AC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters

apply to 5V at 25°C and are for design guidance only.

Table 3-22. AC Low Power Comparator Specifications

Symbol

Description

Min

Typ

Max

Units

µs

Notes

T

LPC response time

–

50

≥ 50 mV overdrive comparator reference set

RLPC

within V

.

REFLPC

3.4.6

AC Digital Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-23. AC Digital Block Specifications

Function

Timer

Description

Min

Typ

Max

Units

ns

Notes

a

Capture Pulse Width

–

50

–

Maximum Frequency, No Capture

Maximum Frequency, With Capture

Enable Pulse Width

–

49.92

25.92

–

MHz

ns

4.75V < Vdd < 5.25V.

–

a

Counter

50

–

Maximum Frequency, No Enable Input

Maximum Frequency, Enable Input

–

49.92

25.92

MHz

4.75V < Vdd < 5.25V.

–

Dead Band Kill Pulse Width:

Asynchronous Restart Mode

20

50

–

ns

a

Synchronous Restart Mode

Disable Mode

–

ns

50

–

Maximum Frequency

–

49.92

MHz

4.75V < Vdd < 5.25V.

CRCPRS

Maximum Input Clock Frequency

–

(PRS Mode)

CRCPRS

(CRC Mode)

Maximum Input Clock Frequency

–

24.6

8.2

MHz

SPIM

SPIS

Maximum data rate at 4.1 MHz due to 2 x over

clocking.

Maximum Input Clock Frequency

–

4.1

–

MHz

ns

a

Width of SS_ Negated Between Transmissions

50

–

Transmitter Maximum Input Clock Frequency

–

24.6

MHz

Maximum data rate at 3.08 MHz due to 8 x over

clocking.

Receiver Maximum Input Clock Frequency

–

24.6

MHz

Maximum data rate at 3.08 MHz due to 8 x over

clocking.

a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

3.4.7

AC External Clock Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-24. AC External Clock Specifications

Symbol

Description

Min

23.94

Typ

Max

24.06

Units

MHz

Notes

F

Frequency for USB Applications

24

OSCEXT

–

Duty Cycle

47

50

–

53

–

%

Power up to IMO Switch

150

µs

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3. Electrical Specifications

3.4.8

AC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-25. 5V AC Analog Output Buffer Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

T

Rising Settling Time to 0.1%, 1V Step, 100pF Load

ROB

Power = Low

–

2.5

µs

Power = High

2.5

µs

T

Falling Settling Time to 0.1%, 1V Step, 100pF Load

SOB

Power = Low

–

2.2

µs

Power = High

SR

Rising Slew Rate (20% to 80%), 1V Step, 100pF Load

ROB

FOB

Power = Low

0.65

–

V/µs

Power = High

Falling Slew Rate (80% to 20%), 1V Step, 100pF Load

Power = Low

Power = High

0.65

–

V/µs

BW

Small Signal Bandwidth, 20mV , 3dB BW, 100pF Load

pp

OBSS

OBLS

0.8

–

MHz

Power = Low

Power = High

Large Signal Bandwidth, 1V , 3dB BW, 100pF Load

pp

300

–

kHz

Power = Low

Power = High

Table 3-26. 3.3V AC Analog Output Buffer Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

T

Rising Settling Time to 0.1%, 1V Step, 100pF Load

ROB

Power = Low

–

3.8

µs

Power = High

T

Falling Settling Time to 0.1%, 1V Step, 100pF Load

SOB

Power = Low

–

2.6

µs

Power = High

SR

Rising Slew Rate (20% to 80%), 1V Step, 100pF Load

ROB

FOB

Power = Low

0.5

–

V/µs

Power = High

Falling Slew Rate (80% to 20%), 1V Step, 100pF Load

Power = Low

Power = High

0.5

–

V/µs

BW

Small Signal Bandwidth, 20mV , 3dB BW, 100pF Load

pp

OBSS

OBLS

0.7

–

MHz

Power = Low

Power = High

Large Signal Bandwidth, 1V , 3dB BW, 100pF Load

pp

200

–

kHz

Power = Low

Power = High

February 15, 2007

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

3. Electrical Specifications

3.4.9

AC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-27. AC Programming Specifications

Symbol

Description

Min

Typ

Max

Units

ns

Notes

T

Rise Time of SCLK

Fall Time of SCLK

1

–

20

–

RSCLK

FSCLK

SSCLK

HSCLK

SCLK

T

F

T

1

–

ns

Data Set up Time to Falling Edge of SCLK

Data Hold Time from Falling Edge of SCLK

Frequency of SCLK

40

0

–

ns

–

ns

–

8

MHz

ms

ns

Flash Erase Time (Block)

–

10

30

–

ERASEB

WRITE

DSCLK

DSCLK3

Flash Block Write Time

–

Data Out Delay from Falling Edge of SCLK

–

45

50

Vdd > 3.6

–

ns

3.0 ≤ Vdd ≤ 3.6

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3. Electrical Specifications

2

3.4.10

AC I C Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-28. AC Characteristics of the I²C SDA and SCL Pins for Vdd

Standard Mode

Min Max

100

Fast Mode

Min Max

Symbol

SCLI2C

Description

Units

kHz

Notes

F

T

SCL Clock Frequency

0

400

–

Hold Time (repeated) START Condition. After this period,

the first clock pulse is generated.

4.0

–

0.6

µs

HDSTAI2C

T

LOW Period of the SCL Clock

4.7

4.0

4.7

0

–

1.3

0.6

0

–

µs

ns

µs

ns

LOWI2C

HIGH Period of the SCL Clock

–

HIGHI2C

SUSTAI2C

HDDATI2C

SUDATI2C

SUSTOI2C

BUFI2C

Set-up Time for a Repeated START Condition

Data Hold Time

–

a

Data Set-up Time

250

4.0

4.7

–

100

0.6

Set-up Time for STOP Condition

Bus Free Time Between a STOP and START Condition

Pulse Width of spikes are suppressed by the input filter.

–

1.3

0

–

50

SPI2C

a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t_SU;DAT≥ 250 ns must then be met. This will automatically be the case if

the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line

t_rmax+ t_SU;DAT= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

Figure 3-6. Definition for Timing for Fast/Standard Mode on the I²C Bus

SDA

T_SPI2C

T

LOWI2C

T_SUDATI2C

T_HDSTAI2C

T_BUFI2C

SCL

T_SUSTOI2C

T_SUSTAI2C

T_HDDATI2C

T_HDSTAI2C

T_HIGHI2C

S

Sr

P

S

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4. Packaging Information

This chapter illustrates the package specification for the CY8C24x94 PSoC devices, along with the thermal impedance for the pack-

age and solder reflow peak temperatures.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of

the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at

http://www.cypress.com/design/MR10161.

4.1

Packaging Dimensions

Figure 4-1. 56-Lead (8x8 mm) QFN

001-12921 **

February 15, 2007

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

4. Packaging Information

Figure 4-2. 68-Lead (8x8 mm x 0.89 mm) QFN

51-85214 *C

Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at

http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.

Important Note Pinned vias for thermal conduction are not required for the low-power PSoC device.

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

Figure 4-3. 100-Ball (6x6 mm) VFBGA

4. Packaging Information

51-85209 *B

Figure 4-4. 100-Lead (14x14 x 1.4 mm) TQFP

51-85048 *C

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

4. Packaging Information

4.2

Thermal Impedance

Table 4-1. Thermal Impedance for the Package

Package

56 QFN**

68 QFN**

100 VFBGA

Typical θ_JA

*

o

12.93 C/W

o

13.05 C/W

o

65 C/W

* T = T + POWER x θ_JA

J

A

** To achieve the thermal impedance specified for the QFN package, the center

thermal pad should be soldered to the PCB ground plane.

4.3

Solder Reflow Peak Temperature

Following is the minimum solder reflow peak temperature to achieve good solderability.

Table 4-2. Solder Reflow Peak Temperature

Package

Minimum Peak Temperature*

Maximum Peak Temperature

o

56 QFN

240 C

260 C

o

68 QFN

240 C

260 C

o

100 VFBGA

240 C

260 C

o

*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 C

o

with Sn-Pb or 245 ± 5 C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.

February 15, 2007

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5. Development Tool Selection

This chapter presents the development tools available for all current PSoC device families including the CY8C24x94 family.

5.1

Software

5.2

Development Kits

All development kits can be purchased from the Cypress Online

Store.

5.1.1

PSoC Designer™

At the core of the PSoC development software suite is PSoC

Designer. Utilized by thousands of PSoC developers, this

robust software has been facilitating PSoC designs for half a

decade. PSoC Designer is available free of charge at http://

www.cypress.com under DESIGN RESOURCES >> Software

and Drivers.

5.2.1

CY3215-DK Basic Development Kit

The CY3215-DK is for prototyping and development with PSoC

Designer. This kit supports in-circuit emulation and the software

interface allows users to run, halt, and single step the processor

and view the content of specific memory locations. Advance

emulation features also supported through PSoC Designer. The

kit includes:

5.1.2

PSoC Express™

■ PSoC Designer Software CD

As the newest addition to the PSoC development software

suite, PSoC Express is the first visual embedded system design

tool that allows a user to create an entire PSoC project and

generate a schematic, BOM, and data sheet without writing a

single line of code. Users work directly with application objects

such as LEDs, switches, sensors, and fans. PSoC Express is

available free of charge at http://www.cypress.com/psocex-

press.

■ ICE-Cube In-Circuit Emulator

■ ICE Flex-Pod for CY8C29x66 Family

■ Cat-5 Adapter

■ Mini-Eval Programming Board

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ iMAGEcraft C Compiler (Registration Required)

■ ISSP Cable

5.1.3

PSoC Programmer

■ USB 2.0 Cable and Blue Cat-5 Cable

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

Flexible enough to be used on the bench in development, yet

suitable for factory programming, PSoC Programmer works

either as a standalone programming application or it can oper-

ate directly from PSoC Designer or PSoC Express. PSoC Pro-

grammer software is compatible with both PSoC ICE-Cube In-

Circuit Emulator and PSoC MiniProg. PSoC programmer is

available free ofcharge at http://www.cypress.com/psocpro-

grammer.

5.1.4

CY3202-C iMAGEcraft C Compiler

CY3202 is the optional upgrade to PSoC Designer that enables

the iMAGEcraft C compiler. It can be purchased from the

Cypress Online Store. At http://www.cypress.com, click the

Online Store shopping cart icon at the bottom of the web page,

and click PSoC (Programmable System-on-Chip) to view a cur-

rent list of available items..

February 15, 2007

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

5. Development Tool Selection

5.2.2

CY3210-ExpressDK PSoC Express

Development Kit

5.3.3

CY3214-PSoCEvalUSB

The CY3214-PSoCEvalUSB evaluation kit features a develop-

ment board for the CY8C24794-24LFXI PSoC device. Special

features of the board include both USB and capacitive sensing

development and debugging support. This evaluation board

also includes an LCD module, potentiometer, LEDs, an enunci-

ator and plenty of bread boarding space to meet all of your eval-

uation needs. The kit includes:

The CY3210-ExpressDK is for advanced prototyping and devel-

opment with PSoC Express (may be used with ICE-Cube In-Cir-

cuit Emulator). It provides access to I²C buses, voltage

reference, switches, upgradeable modules and more. The kit

includes:

■ PSoC Express Software CD

■ Express Development Board

■ 4 Fan Modules

■ PSoCEvalUSB Board

■ LCD Module

■ MIniProg Programming Unit

■ Mini USB Cable

■ 2 Proto Modules

■ MiniProg In-System Serial Programmer

■ MiniEval PCB Evaluation Board

■ Jumper Wire Kit

■ PSoC Designer and Example Projects CD

■ Getting Started Guide

■ Wire Pack

■ USB 2.0 Cable

■ Serial Cable (DB9)

5.4

Device Programmers

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ 2 CY8C24423A-24PXI 28-PDIP Chip Samples

■ 2 CY8C27443-24PXI 28-PDIP Chip Samples

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

All device programmers can be purchased from the Cypress

Online Store.

5.4.1

CY3216 Modular Programmer

5.3

Evaluation Tools

The CY3216 Modular Programmer kit features a modular pro-

grammer and the MiniProg1 programming unit. The modular

programmer includes three programming module cards and

supports multiple Cypress products. The kit includes:

All evaluation tools can be purchased from the Cypress Online

Store.

■ Modular Programmer Base

■ 3 Programming Module Cards

■ MiniProg Programming Unit

■ PSoC Designer Software CD

■ Getting Started Guide

5.3.1

CY3210-MiniProg1

The CY3210-MiniProg1 kit allows a user to program PSoC

devices via the MiniProg1 programming unit. The MiniProg is a

small, compact prototyping programmer that connects to the PC

via a provided USB 2.0 cable. The kit includes:

■ USB 2.0 Cable

■ MiniProg Programming Unit

■ MiniEval Socket Programming and Evaluation Board

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample

■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample

■ PSoC Designer Software CD

5.4.2

CY3207ISSP In-System Serial

Programmer (ISSP)

The CY3207ISSP is a production programmer. It includes pro-

tection circuitry and an industrial case that is more robust than

the MiniProg in a production-programming environment.

Note: CY3207ISSP needs special software and is not compati-

ble with PSoC Programmer. The kit includes:

■ Getting Started Guide

■ USB 2.0 Cable

5.3.2

CY3210-PSoCEval1

■ CY3207 Programmer Unit

■ PSoC ISSP Software CD

The CY3210-PSoCEval1 kit features an evaluation board and

the MiniProg1 programming unit. The evaluation board includes

an LCD module, potentiometer, LEDs, and plenty of bread-

boarding space to meet all of your evaluation needs. The kit

includes:

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ USB 2.0 Cable

■ Evaluation Board with LCD Module

■ MiniProg Programming Unit

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

February 15, 2007

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

5. Development Tool Selection

5.5

Accessories (Emulation and

Programming)

Table 5-1. Emulation and Programming Accessories

a

b

c

Part #

Package

Flex-Pod Kit

Foot Kit

Adapter

CY8C24794 56 QFN

-24LFXI

CY3250-

24X94QFN

CY3250-

56QFN-FK

AS-56-28

CY8C24894 56 QFN

-24LFXI

CY3250-

24X94QFN

CY3250-

56QFN-FK

AS-28-28-02SS-

6ENG-GANG

a. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two

flex-pods.

b. Foot kit includes surface mount feet that can be soldered to the target PCB.

c. Programming adapter converts non-DIP package to DIP footprint. Specific

details and ordering information for each of the adapters can be found at

http://www.emulation.com.

5.6

3rd-Party Tools

Several tools have been specially designed by the following

3rd-party vendors to accompany PSoC devices during develop-

ment and production. Specific details for each of these tools can

be found at http://www.cypress.com under DESIGN

RESOURCES >> Evaluation Boards.

5.7

Build a PSoC Emulator into

Your Board

For details on how to emulate your circuit before going to vol-

ume production using an on-chip debug (OCD) non-production

PSoC device, see Application Note “Debugging - Build a PSoC

Emulator into Your Board - AN2323” at http://www.cypress.com/

an2323.

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6. Ordering Information

The following table lists the CY8C24x94 PSoC device’s key package features and ordering codes.

Table 6-1. CY8C24x94 PSoC Device’s Key Features and Ordering Information

56 Pin (8x8 mm) QFN

CY8C24794-24LFXI

CY8C24794-24LFXIT

CY8C24894-24LFXI

CY8C24894-24LFXIT

16K

1K

-40C to +85C

4

6

50

49

48

47

2

No

56 Pin (8x8 mm) QFN

(Tape and Reel)

56 Pin (8x8 mm) QFN

Yes

56 Pin (8x8 mm) QFN

(Tape and Reel)

68 Pin OCD (8x8 mm) QFN^a

CY8C24094-24LFXI

CY8C24994-24LFXI

16K

1K

-40C to +85C

4

6

56

48

2

Yes

68 Pin (8x8 mm) QFN

(Tape and Reel)

CY8C24994-24LFXIT

16K

1K

-40C to +85C

4

6

56

48

2

Yes

100 Ball OCD (6x6 mm) VFBGA^a

100 Ball (6x6 mm) VFBGA

CY8C24094-24BVXI

CY8C24994-24BVXI

CY8C24094-24AXI

16K

1K

-40C to +85C

4

6

56

48

2

Yes

100 Pin OCD TQFP^a

a. This part may be used for in-circuit debugging. It is NOT available for production.

6.1

Ordering Code Definitions

CY 8 C 24 xxx-SPxx

Package Type:

Thermal Rating:

C = Commercial

I = Industrial

PX = PDIP Pb-Free

SX = SOIC Pb-Free

PVX = SSOP Pb-Free

E = Extended

LFX/LKX = QFN Pb-Free

AX = TQFP Pb-Free

BVX = VFBGA Pb-Free

Speed: 24 MHz

Part Number

Family Code

Technology Code: C = CMOS

Marketing Code: 8 = Cypress PSoC

Company ID: CY = Cypress

February 15, 2007

Document No. 38-12018 Rev. *J

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7. Sales and Company Information

To obtain information about Cypress Semiconductor or PSoC sales and technical support, reference the following information.

Cypress Semiconductor

198 Champion Court

San Jose, CA 95134

408.943.2600

Web Sites: Company Information – http://www.cypress.com

Sales – http://www.cypress.com/aboutus/sales_locations.cfm

Technical Support – http://www.cypress.com/support/login.cfm

7.1

Revision History

Table 6-1. CY8C24x94 Data Sheet Revision History

Document Title:

CY8C24094, CY8C24794, CY8C24894 and CY8C24994 PSoC® Mixed-Signal Array Final Data Sheet

Document Number: 38-12018

Revision ECN # Issue Date Origin of Change

Description of Change

New silicon and new document – Advance Data Sheet.

**

133189 01.27.2004 NWJ

*A

251672 See ECN

289742 See ECN

335236 See ECN

SFV

HMT

First Preliminary Data Sheet. Changed title to encompass only the CY8C24794 because the CY8C24494 and

CY8C24694 are not being offered by Cypress MicroSystems.

*B

*C

Add standard DS items from SFV memo. Add Analog Input Mux on pinouts. 2 MACs. Change 512 bytes of

SRAM to 1K. Add dimension key to package. Remove HAPI. Update diagrams, registers and specs.

Add CY logo. Update CY copyright. Update new CY.com URLs. Re-add ISSP programming pinout notation.

Add Reflow Temp. table. Update features (MAC, Oscillator, and voltage range), registers (INT_CLR2/MSK2,

second MAC), and specs. (Rext, IMO, analog output buffer...).

*D

*E

*F

*G

344318 See ECN

346774 See ECN

349566 See ECN

393164 See ECN

HMT

Add new color and logo. Expand analog arch. diagram. Fix IO #. Update Electrical Specifications.

Add USB temperature specifications. Make data sheet Final.

Remove USB logo. Add URL to preferred dimensions for mounting MLF packages.

Add new device, CY8C24894 56-pin MLF with XRES pin. Add Fimousb3v char. to specs. Upgrade to CY Per-

form logo and update corporate address and copyright.

*H

469243 See ECN

HMT

Add ISSP note to pinout tables. Update typical and recommended Storage Temperature per industrial specs.

Update Low Output Level maximum IOL budget. Add FLS_PR1 to Register Map Bank 1 for users to specify

which Flash bank should be used for SROM operations. Add two new devices for a 68-pin QFN and 100-ball

VFBGA under RPNs: CY8C24094 and CY8C24994. Add two packages for 68-pin QFN. Add OCD non-produc-

tion pinouts and package diagrams. Update CY branding and QFN convention. Add new Dev. Tool section.

Update copyright and trademarks.

*I

561158 See ECN

728238 See ECN

HMT

Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add CY8C20x34 to PSoC Device Character-

istics table. Add detailed dimensions to 56-pin QFN package diagram and update revision. Secure one package

diagram/manufacturing per QFN. Update emulation pod/feet kit part numbers. Fix pinout type-o per TestTrack.

*J

Add CapSense SNR requirement reference. Update figure standards. Update Technical Training paragraphs.

Add QFN package clarifications and dimensions. Update ECN-ed Amkor dimensioned QFN package diagram

revisions. Reword SNR reference. Add new 56-pin QFN spec.

Distribution: External/Public

Posting: None

February 15, 2007

47

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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet

7. Sales and Company Information

7.2

Copyrights and Code Protection

PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corpo-

rations.

The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other than circuitry

embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products

for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of

Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress

Semiconductor against all charges. Cypress Semiconductor products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety

applications, unless pursuant to an express written agreement with Cypress Semiconductor.

Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices.

Cypress Semiconductor products meet the specifications contained in their particular Cypress Semiconductor Data Sheets. Cypress Semiconductor believes that its fam-

ily of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semicon-

ductor, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor

nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreak-

able." Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at

Cypress Semiconductor are committed to continuously improving the code protection features of our products.

February 15, 2007

Document No. 38-12018 Rev. *J

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型号：	CY8C24894-24LFXI
厂家：	CYPRESS
描述：	PSoC㈢ Mixed-Signal Array 的PSoC ™混合信号阵列
文件：	总48页 (文件大小：648K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C24894-24LFXI [CYPRESS]

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