CY8C24894-24LTXI [CYPRESS]
PSoC Programmable System-on-Chip; 的PSoC可编程系统级芯片
| 型号： | CY8C24894-24LTXI |
| 厂家： | 
CYPRESS |
| 描述： | PSoC Programmable System-on-Chip |
| 文件： | 总47页 (文件大小：1479K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C24094, CY8C24794
CY8C24894, CY8C24994
PSoC® Programmable System-on-Chip™
■ Full Speed USB (12 Mbps)
❐ Four Uni-Directional Endpoints
❐ One Bi-Directional Control Endpoint
❐ USB 2.0 Compliant
1. Features
■ XRES Pin to Support In-System Serial Programming (ISSP)
and External Reset Control in CY8C24894
❐ Dedicated 256 Byte Buffer
❐ No External Crystal Required
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ Two 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 3V to 5.25V Operating Voltage
❐ Industrial Temperature Range: -40°C to +85°C
❐ USB Temperature Range: -10°C to +85°C
■ Flexible On-Chip Memory
❐ 16K Flash Program Storage 50,000 Erase and Write Cycles
❐ 1K SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
■ Advanced Peripherals (PSoC® Blocks)
❐ 6 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
• Up to 9-Bit DACs
❐ 25 mA Sink, 10 mA Drive on all GPI/O
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on all GPI/O
❐ Up to 48 Analog Inputs on GPI/O
❐ Two 33 mA Analog Outputs on GPI/O
❐ Configurable Interrupt on all GPI/O
■ Precision, Programmable Clocking
• Full-Duplex UART
❐ Internal ±4% 24 and 48 MHz Oscillator
❐ Internal Oscillator for Watchdog and Sleep
❐ 0.25% Accuracy for USB with no External Components
• Multiple SPI™ Masters or Slaves
• Connectable to all GPI/O Pins
❐ Complex Peripherals by Combining Blocks
❐ Capacitive Sensing Application Capability
■ Additional System Resources
❐ I2C Slave, Master, and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User Configurable Low Voltage Detection
A n a lo g
P o r t
5
P o r t
4
P o r t
3
P o r t
2
P o r t
1
P o r t 0
P o r t
7
D
r iv e r s
2. Logic Block Diagram
G lo b a l D ig ita l In t e r c o n n e c t
G lo b a l A n a lo g In te r c o n n e c t
P S o C C O R E
S R A M
1 K
S R O M
F la s h 1 6 K
S le e p a n d
a tc h d o g
C P U C o r e ( M 8 C )
W
In t e r r u p t
C o n tr o lle r
C lo c k S o u r c e s
( I n c lu d e s IM O a n d I L O )
D IG IT A L S Y S T E M
A N A L O G S Y S T E M
A n a lo g
R e f.
D i g it a l
B lo c k
A r r a y
A n a l o g
B lo c k
A r r a y
In te r n a l
V o lta g e
R e f.
A n a lo g
In p u t
D ig ita l
C lo c k s
2
D e c im a to r
T y p e
P O R a n d L V D
S y s te m R e s e t s
I 2 C
U S B
M
A C s
2
M
u x in g
S Y S T E M R E S O U R C E S
Cypress Semiconductor Corporation
Document Number: 38-12018 Rev. *O
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 11, 2009
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
2.2 The Digital System
2. PSoC Functional Overview
The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource used alone or combined with
other blocks to form 8, 16, 24, and 32-bit peripherals, which are
called user module references.
The PSoC family consists of many programmable
system-on-chips with On-Chip Controller devices. All PSoC
family devices are designed to replace traditional MCUs, system
ICs, and the numerous discrete components that surround them.
The PSoC CY8C24x94 devices are unique members of the
PSoC family because it includes a full featured, full speed (12
Mbps) USB port. Configurable analog, digital, and interconnect
circuitry enable a high level of integration in a host of industrial,
consumer, and communication applications.
Figure 2-1. Digital System Block Diagram
Port 7
Port 5
Port 3
Port 1
Port 4
Port 2
Port 0
This architecture enables the user to create customized
peripheral configurations that match the requirements of each
individual application. Additionally, a fast CPU, Flash program
memory, SRAM data memory, and configurable I/O are included
in a range of convenient pinouts and packages.
To System Bus
Digital Clocks
From Core
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources including a full speed USB port. Config-
urable global busing enables all the device resources to be
Row 0
8
4
8
8
8
DBB00
DBB01
DCB02
DCB03
4
combined into
a complete custom system. The PSoC
CY8C24x94 devices can have up to seven I/O ports that connect
to the global digital and analog interconnects, providing access
to 4 digital blocks and 6 analog blocks.
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
2.1 The PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPI/O (General Purpose I/O).
Digital peripheral configurations include the following:
■ Full Speed USB (12 Mbps)
The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four MIPS 8-bit Harvard architecture micropro-
cessor. The CPU uses an interrupt controller with up to 20
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
■ PWMs (8 to 32 bit)
■ PWMs with Dead band (8 to 24 bit)
■ Counters (8 to 32 bit)
Memory encompasses 16K of Flash for program storage, 1K of
SRAM for data storage, and up to 2K of EEPROM emulated
using the Flash. Program Flash uses four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
■ Timers (8 to 32 bit)
■ UART 8 bit with selectable parity
■ SPI master and slave
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to 8%
over temperature and voltage. The 24 MHz IMO can also be
doubled to 48 MHz for use by the digital system. A low power 32
kHz ILO (internal low speed oscillator) is provided for the Sleep
timer and WDT. The clocks, together with programmable clock
dividers (as a System Resource), provide the flexibility to
integrate almost any timing requirement into the PSoC device. In
USB systems, the IMO self tunes to ± 0.25% accuracy for USB
communication.
■ I2C slave and multi-master
■ Cyclical Redundancy Checker/Generator (8 to 32 bit)
■ IrDA
■ Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks are connected to any GPI/O through a series
of global buses that can route any signal to any pin. The buses
also enable signal multiplexing and performing logic operations.
This configurability frees the designs from the constraints of a
fixed peripheral controller.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external inter-
facing. Every pin is also capable of generating a system interrupt
on high level, low level, and change from last read.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This enables you the
optimum choice of system resources for your application. Family
resources are shown in Table 2-1 on page 4.
Document Number: 38-12018 Rev. *O
Page 2 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
Figure 2-2. Analog System Block Diagram
2.3 The Analog System
A ll IO
(E x c e p t P o rt 7 )
The Analog System is composed of 6 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are as follows.
P 0 [7 ]
P 0 [5 ]
P 0 [6 ]
P 0 [4 ]
P 0 [3 ]
P 0 [1 ]
P 0 [2 ]
P 0 [0 ]
■ Analog-to-digital converters (up to 2, with 6 to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
P 2 [6 ]
P 2 [4 ]
P 2 [3 ]
P 2 [1 ]
■ Filters (2 and 4 pole band-pass, low-pass, and notch)
■ Amplifiers (up to 2, with selectable gain to 48x)
■ Instrumentation amplifiers (1 with selectable gain to 93x)
■ Comparators (up to 2, with 16 selectable thresholds)
■ DACs (up to 2, with 6- to 9-bit resolution)
P 2 [2 ]
P 2 [0 ]
■ Multiplying DACs (up to 2, with 6- to 9-bit resolution)
A C I0 [1 :0 ]
A rra y In p u t
A C I1 [1 :0 ]
■ High current output drivers (two with 30 mA drive as a PSoC
Core Resource)
C o n fig u ra tio n
■ 1.3V reference (as a System Resource)
■ DTMF Dialer
B lo c k
A rray
A C B 0 0
A S C 1 0
A S D 2 0
A C B 0 1
■ Modulators
A S D 1 1
A S C 2 1
■ Correlators
■ Peak Detectors
A n a lo g R e fe re n c e
■ Many other topologies possible
In te rfa c e to
D ig ita l S y s te m
R e fe re n c e
G e n e ra to rs
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in Figure 2-2.
R e fH i
R e fL o
A G N D
A G N D In
R e fIn
B a n d g a p
M 8 C In te rfa c e (A d d re s s B u s , D a ta B u s , E tc .)
2.3.1 The Analog Multiplexer System
The Analog Mux Bus can connect to every GPI/O pin in ports 0-5.
Pins are connected to the bus individually or in any combination.
The bus also connects to the analog system for analysis with
comparators and analog-to-digital converters. It is split into two
sections for simultaneous dual-channel processing. An
additional 8:1 analog input multiplexer provides a second path to
bring Port 0 pins to the analog array.
Switch control logic enables selected pins to precharge continu-
ously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■ Track pad, finger sensing.
■ Chip-wide mux that enables analog input from up to 48 I/O pins.
■ Crosspoint connection between any I/O pin combinations.
When designing capacitive sensing applications, refer to the
latest signal-to-noise signal level requirements Application
Notes, which are found under http://www.cypress.com > Design
Resources > Application Notes. In general, and unless otherwise
noted in the relevant Application Notes, the minimum
signal-to-noise ratio (SNR) for CapSense applications is 5:1.
Document Number: 38-12018 Rev. *O
Page 3 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
2.4 Additional System Resources
3. Getting Started
System Resources, provide additional capability useful to
complete systems. Additional resources include a multiplier,
decimator, low voltage detection, and power on reset. Brief state-
ments describing the merits of each resource follow.
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
■ Full Speed USB (12 Mbps) with 5 configurable endpoints and
256 bytes of RAM. No external components required except
two series resistors. Wider than commercial temperature USB
operation (-10°C to +85°C).
For in depth information, along with detailed programming infor-
mation, see the PSoC® Programmable System-on-Chip
Technical Reference Manual for CY8C28xxx PSoC devices.
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks are
generated using digital PSoC blocks as clock dividers.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at www.cypress.com/psoc.
3.1 Application Notes
■ Two multiply accumulates (MACs) provide fast 8-bit multipliers
with 32-bit accumulate, to assist in both general math and
digital filters.
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
■ Decimator provides a custom hardware filter for digital signal
processing applications including creation of Delta Sigma
ADCs.
3.2 Development Kits
■ TheI2Cmoduleprovides100and400kHzcommunicationover
two wires. Slave, master, multi-master are supported.
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
■ Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
3.3 Training
■ An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
■ Versatile analog multiplexer system.
2.5 PSoC Device Characteristics
3.4 CyPros Consultants
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources available
for specific PSoC device groups. The device covered by this data
sheet is shown in the highlighted row of the table
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
3.5 Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various appli-
cation designs that include firmware and hardware design files
that enable you to complete your designs quickly.
Table 2-1. PSoC Device Characteristics
PSoC Part
Number
3.6 Technical Support
CY8C29x66
CY8C27x43
up to
64
4
2
16
8
12
12
4
4
4
4
12
12
2K
32K
16K
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
up to
44
256
Bytes
CY8C24x94
56
1
1
4
4
48
12
2
2
2
2
6
6
1K
16K
4K
CY8C24x23A
up to
24
256
Bytes
CY8C21x34
CY8C21x23
CY8C20x34
up to
28
1
1
0
4
4
0
28
8
0
0
0
2
2
0
4
4
3
512
8K
4K
8K
Bytes
16
256
Bytes
up to
28
28
512
Bytes
Document Number: 38-12018 Rev. *O
Page 4 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
4.1.4 Code Generation Tools
4. Development Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
4.1 PSoC Designer Software Subsystems
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
4.1.1 System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication inter-
faces. You define when and how an output device changes state
based upon any or all other system devices. Based upon the
design, PSoC Designer automatically selects one or more PSoC
Mixed-Signal Controllers that match your system requirements.
4.1.5 Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write I/O registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
4.1.2 Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.4. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
4.1.6 Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
4.2 In-Circuit Emulator
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration enables changing configurations at run time.
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
4.1.3 Hybrid Designs
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
Document Number: 38-12018 Rev. *O
Page 5 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
5.3 Organize and Connect
5. Designing with PSoC Designer
You can build signal chains at the chip level by interconnecting
user modules to each other and the I/O pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
The PSoC development process can be summarized in the
following four steps:
1. Select components
2. Configure components
3. Organize and Connect
4. Generate, Verify, and Debug
In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
5.4 Generate, Verify, and Debug
5.1 Select Components
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
(I2C-bus, for example), and the logic to control how they interact
with one another (called valuators).
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run-time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and mixed signal
varieties.
5.2 Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the ICE where it runs at full speed.
Debugger capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the Debugger provides a large trace
buffer and allows you define complex breakpoint events that
include monitoring address and data bus values, memory
locations and external signals.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Document Number: 38-12018 Rev. *O
Page 6 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
6.2 Units of Measure
6. Document Conventions
A units of measure table is located in the Electrical Specifications
section. Table 9-1 on page 20 lists all the abbreviations used to
measure the PSoC devices.
6.1 Acronyms Used
The following table lists the acronyms that are used in this
document.
6.3 Numeric Naming
Acronym
AC
Description
alternating current
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.
ADC
API
analog-to-digital converter
application programming interface
central processing unit
continuous time
CPU
CT
DAC
DC
digital-to-analog converter
direct current
ECO
external crystal oscillator
EEPROM electrically erasable programmable read-only
memory
FSR
GPI/O
GUI
full scale range
general purpose I/O
graphical user interface
human body model
in-circuit emulator
HBM
ICE
ILO
internal low speed oscillator
internal main oscillator
input/output
IMO
I/O
IPOR
LSb
imprecise power on reset
least-significant bit
LVD
low voltage detect
MSb
PC
most-significant bit
program counter
PLL
phase-locked loop
POR
PPOR
PSoC®
PWM
SC
power on reset
precision power on reset
Programmable System-on-Chip™
pulse width modulator
switched capacitor
SRAM
static random access memory
Document Number: 38-12018 Rev. *O
Page 7 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
7. Pin Information
This section describes, lists, and illustrates the CY8C24x94 PSoC device family pins and pinout configuration.
The CY8C24x94 PSoC devices are available in the following packages, all of which are shown on the following pages. Every port pin
(labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O.
Note CY8C24794 must use Power Cycle programming when using the MiniProg.
7.1 56-Pin Part Pinout
Table 7-1. 56-Pin Part Pinout (QFN[2]) See LEGEND details and footnotes in Table 7-2 on page 9.
Type
Digital Analog
Pin
No.
Figure 7-1. CY8C24794 56-Pin PSoC Device
Name
Description
1
2
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I, M
I, M
M
P2[3] Direct switched capacitor block input.
P2[1] Direct switched capacitor block input.
P4[7]
4
5
6
M
M
M
P4[5]
P4[3]
P4[1]
A,I, M,P2[3]
A,I, M,P2[1]
M,P4[7]
1
2
P2[2], A, I,M
P2[0], A, I,M
P4[6],M
P4[4],M
P4[2],M
P4[0],M
P3[6],M
P3[4],M
P3[2],M
P3[0],M
P5[6],M
P5[4],M
P5[2],M
P5[0],M
42
41
7
8
9
M
M
M
P3[7]
P3[5]
P3[3]
3
4
5
6
40
39
M,P4[5]
M,P4[3]
M,P4[1]
38
37
36
35
34
33
32
31
30
29
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
M
M
M
P3[1]
P5[7]
P5[5]
M,P3[7]
7
8
9
10
11
12
13
14
QFN
(Top View )
M,P3[5]
M,P3[3]
M
M
M
P5[3]
P5[1]
M,P3[1]
M,P5[7]
M,P5[5]
M,P5[3]
M,P5[1]
P1[7] I2C Serial Clock (SCL).
P1[5] I2C Serial Data (SDA).
P1[3]
M
M
M
[1]
P1[1] I2C Serial Clock (SCL), ISSP SCLK
.
Power
Vss Ground connection.
D+
D-
USB
USB
Power
Vdd Supply voltage.
P7[7]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P7[0]
[1]
M
M
M
M
M
P1[0] I2C Serial Data (SDA), ISSP SDATA
P1[2]
.
P1[4] Optional External Clock Input (EXTCLK).
P1[6]
P5[0]
Type
Pin
No.
Name
Description
30
31
32
33
34
35
36
37
38
39
40
41
42
43
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
M
M
M
M
M
M
P5[2]
Digital Analog
P5[4]
44
45
46
47
48
49
50
51
52
53
54
55
56
I/O
I/O
I/O
I/O
I/O
M
P2[6] External Voltage Reference (VREF) input.
P0[0] Analog column mux input.
P0[2] Analog column mux input.
P0[4] Analog column mux input VREF.
P0[6] Analog column mux input.
Vdd Supply voltage.
P5[6]
I, M
I, M
I, M
I, M
P3[0]
P3[2]
P3[4]
P3[6]
Power
Power
I, M
P4[0]
Vss Ground connectI/On.
P4[2]
I/O
I/O
I/O
I/O
I/O
I/O
P0[7] Analog column mux input,.
P4[4]
I/O, M P0[5] Analog column mux input and column output.
I/O, M P0[3] Analog column mux input and column output.
P4[6]
I, M
I, M
M
P2[0] Direct switched capacitor block input.
P2[2] Direct switched capacitor block input.
P2[4] External Analog Ground (AGND) input.
I, M
M
P0[1] Analog column mux input.
P2[7]
P2[5]
M
Document Number: 38-12018 Rev. *O
Page 8 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
7.2 56-Pin Part Pinout (with XRES)
Table 7-2. 56-Pin Part Pinout (QFN[2])
Type
Pin
Figure 7-2. CY8C24894 56-Pin PSoC Device
Name
Description
No.
Digital Analog
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I, M
I, M
M
P2[3] Direct switched capacitor block input.
2
3
4
P2[1] Direct switched capacitor block input.
P4[7]
P4[5]
M
5
6
7
M
M
M
P4[3]
P4[1]
P3[7]
A, I, M, P2[3]
1
2
P2[2], A, I, M
P2[0], A, I, M
42
41
40
39
38
37
A, I, M, P2[1]
8
9
M
M
M
P3[5]
P3[3]
P3[1]
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
M, P3[7]
3
4
5
6
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
M
M
M
P5[7]
P5[5]
P5[3]
7
8
QFN
(Top View)
36
35
34
33
M, P3[5]
M, P3[3]
M, P3[1]
P3[4], M
P3[2], M
P3[0], M
9
M
M
M
P5[1]
10
P1[7] I2C Serial Clock (SCL).
P1[5] I2C Serial Data (SDA).
P1[3]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
11
12
13
14
P5[6], M
P5[4], M
P5[2], M
P5[0], M
32
31
30
29
M
M
[1].
P1[1] I2C Serial Clock (SCL), ISSP SCLK
Power
Vss Ground connection.
USB
USB
D+
D-
Power
Vdd Supply voltage.
I/O
I/O
I/O
I/O
I/O
I/O
P7[7]
P7[0]
[1]
M
M
M
M
P1[0] I2C Serial Data (SDA), ISSP SDATA
P1[2]
.
P1[4] Optional External Clock Input (EXTCLK).
P1[6]
29
30
31
32
33
34
35
36
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
M
M
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
Type
Pin
No.
Name
Description
Digital Analog
44
45
46
47
48
49
I/O
I/O
I/O
I/O
I/O
M
P2[6] External Voltage Reference (VREF) input.
P0[0] Analog column mux input.
P0[2] Analog column mux input.
P0[4] Analog column mux input VREF.
P0[6] Analog column mux input.
Vdd Supply voltage.
I, M
I, M
I, M
I, M
Input
XRES Active high external reset with internal
pull down.
Power
37
38
39
40
41
42
43
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
P4[0]
50
51
52
53
54
55
56
Power
I, M
Vss Ground connection.
P4[2]
I/O
I/O
I/O
I/O
I/O
I/O
P0[7] Analog column mux input,.
P4[4]
I/O, M P0[5] Analog column mux input and column output.
I/O, M P0[3] Analog column mux input and column output.
P4[6]
I, M
I, M
M
P2[0] Direct switched capacitor block input.
P2[2] Direct switched capacitor block input.
P2[4] External Analog Ground (AGND) input.
I, M
M
P0[1] Analog column mux input.
P2[7]
P2[5]
M
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Notes
1. These are the ISSP pins, which are not High Z at POR. See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
2. The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
should be electrically floated and not connected to any other signal.
Document Number: 38-12018 Rev. *O
Page 9 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
7.3 68-Pin Part Pinout
The following 68-pin QFN part table and drawing is for the CY8C24994 PSoC device.
Table 7-3. 68-Pin Part Pinout (QFN[2])
Type
Figure 7-3. CY8C24994 68-Pin PSoC Device
Pin
No.
Name
Description
Digital Analog
1
I/O
I/O
I/O
I/O
M
M
M
M
P4[7]
P4[5]
P4[3]
P4[1]
NC
2
3
4
5
6
7
8
9
No connection.
No connection.
NC
Power
I/O
Vss
Ground connection.
M, P4[7]
M, P4[5]
M, P4[3]
P2[0], M, AI
51
1
2
M
M
M
M
M
M
M
M
M
M
M
M
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
50
P4[6], M
P4[4], M
P4[2], M
I/O
3
4
49
48
47
46
M, P4[1]
NC
10 I/O
11 I/O
5
6
P4[0], M
XRES
NC
NC
12 I/O
13 I/O
14 I/O
15 I/O
16 I/O
17 I/O
18 I/O
19 I/O
20 Power
21 USB
22 USB
23 Power
24 I/O
25 I/O
26 I/O
27 I/O
28 I/O
29 I/O
30 I/O
31 I/O
32 I/O
33 I/O
34 I/O
35 I/O
36 I/O
37 I/O
38 I/O
39 I/O
40 I/O
41 I/O
42 I/O
43 I/O
Vss
M, P3[7]
M, P3[5]
45
7
8
9
NC
P3[6], M
P3[4], M
44
43
42
QFN
(Top View)
10
M, P3[3]
M, P3[1]
M, P5[7]
P3[2], M
P3[0], M
11
12
13
14
15
41
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
40
39
M, P5[5]
P5[6], M
P5[4], M
M, P5[3]
M, P5[1]
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
38
37
36
35
P5[2], M
P5[0], M
[1]
I2C Serial Clock (SCL) ISSP SCLK
Ground connection.
.
16
17
P1[6], M
D+
D-
Vdd
Supply voltage.
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P1[0]
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
Type
Pin
No.
Name
Description
Digital Analog
50 I/O
51 I/O
52 I/O
M
P4[6]
[1]
M
M
M
M
M
M
M
M
M
M
M
M
I2C Serial Data (SDA), ISSP SDATA
.
I,M
I,M
M
P2[0] Direct switched capacitor block input.
P2[2] Direct switched capacitor block input.
P2[4] External Analog Ground (AGND) input.
P2[6] External Voltage Reference (VREF) input.
P0[0] Analog column mux input.
Optional External Clock Input (EXTCLK). 53 I/O
54 I/O
55 I/O
56 I/O
57 I/O
58 I/O
M
I,M
I,M
I,M
I,M
P0[2] Analog column mux input and column output.
P0[4] Analog column mux input and column output.
P0[6] Analog column mux input.
59 Power
Vdd
Vss
Supply voltage.
60 Power
61 I/O
Ground connection.
I,M
P0[7] Analog column mux input, integration input #1
62 I/O
I/O,M
P0[5] Analog column mux input and column output, integration
input #2.
44
NC
NC
No connection.
No connection.
63 I/O
64 I/O
65 I/O
I/O,M
I,M
P0[3] Analog column mux input and column output.
P0[1] Analog column mux input.
P2[7]
45
46 Input
XRES Active high pin reset with internal pull
down.
M
47 I/O
48 I/O
49 I/O
M
M
M
P4[0]
P4[2]
P4[4]
66 I/O
67 I/O
68 I/O
M
P2[5]
I,M
I,M
P2[3] Direct switched capacitor block input.
P2[1] Direct switched capacitor block input.
LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input.
Document Number: 38-12018 Rev. *O
Page 10 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
7.4 68-Pin Part Pinout (On-Chip Debug)
The following 68-pin QFN part table and drawing is for the CY8C24094 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Table 7-4. 68-Pin Part Pinout (QFN[2])
Type
Pin
No.
Figure 7-4. CY8C24094 68-Pin OCD PSoC Device
Name
Description
Digital Analog
1
I/O
I/O
I/O
I/O
M
M
M
M
P4[7]
P4[5]
P4[3]
P4[1]
2
3
4
5
6
7
8
9
OCDE OCD even data I/O.
OCDO OCD odd data output.
Power
I/O
Vss
Ground connection.
M, P4[7]
M, P4[5]
M, P4[3]
P2[0], M, AI
P4[6], M
1
2
3
4
5
6
7
8
9
51
50
M
M
M
M
M
M
M
M
M
M
M
M
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P4[4], M
P4[2], M
49
48
47
I/O
M, P4[1]
OCDE
OCDO
10 I/O
11 I/O
P4[0], M
XRES
CCLK
46
45
Vss
M, P3[7]
M, P3[5]
12 I/O
13 I/O
14 I/O
15 I/O
16 I/O
17 I/O
18 I/O
19 I/O
20 Power
21 USB
22 USB
23 Power
24 I/O
25 I/O
26 I/O
27 I/O
28 I/O
29 I/O
30 I/O
31 I/O
32 I/O
33 I/O
34 I/O
35 I/O
36 I/O
37 I/O
38 I/O
39 I/O
40 I/O
41 I/O
42 I/O
43 I/O
HCLK
P3[6], M
P3[4], M
44
43
42
QFN
(Top View)
10
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
P3[2], M
P3[0], M
11
12
13
14
15
16
17
41
40
39
38
37
36
35
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
P5[6], M
P5[4], M
M, P5[3]
M, P5[1]
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
P5[2], M
P5[0], M
P1[6], M
[1]
I2C Serial Clock (SCL), ISSP SCLK
Ground connection.
.
D+
D-
Vdd
Supply voltage.
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P1[0]
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
Type
Digital Analog
Pin
No.
Name
Description
50 I/O
51 I/O
52 I/O
M
P4[6]
[1]
M
M
M
M
M
M
M
M
M
M
M
M
I2C Serial Data (SDA), ISSP SDATA
.
I,M
I,M
M
P2[0] Direct switched capacitor block input.
P2[2] Direct switched capacitor block input.
Optional External Clock Input (EXTCLK). 53 I/O
P2[4] External Analog Ground (AGND) input.
P2[6] External Voltage Reference (VREF) input.
P0[0] Analog column mux input.
54 I/O
55 I/O
56 I/O
57 I/O
58 I/O
M
I,M
I,M
I,M
I,M
P0[2] Analog column mux input and column output.
P0[4] Analog column mux input and column output.
P0[6] Analog column mux input.
59 Power
Vdd
Vss
Supply voltage.
60 Power
61 I/O
Ground connection.
I,M
P0[7] Analog column mux input, integration input #1
62 I/O
I/O,M
P0[5] Analog column mux input and column output,
integration input #2.
44
HCLK OCD high speed clock output.
CCLK OCD CPU clock output.
63 I/O
64 I/O
65 I/O
I/O,M
I,M
P0[3] Analog column mux input and column output.
P0[1] Analog column mux input.
P2[7]
45
46 Input
XRES Active high pin reset with internal pull
down.
M
47 I/O
48 I/O
49 I/O
M
M
M
P4[0]
P4[2]
P4[4]
66 I/O
67 I/O
68 I/O
M
P2[5]
I,M
I,M
P2[3] Direct switched capacitor block input.
P2[1] Direct switched capacitor block input.
LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, OCD = On-Chip Debugger.
Document Number: 38-12018 Rev. *O
Page 11 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
7.5 100-Ball VFBGA Part Pinout
The 100-ball VFBGA part is for the CY8C24994 PSoC device.
Table 7-5. 100-Ball Part Pinout (VFBGA)
Pin
No.
Pin
No.
Name
Description
Name
Description
A1 Power
A2 Power
A3
Vss
Vss
NC
NC
NC
Vdd
NC
NC
Vss
Vss
Vss
Vss
Ground connection.
F1
NC
No connection.
Ground connection.
No connection.
F2 I/O
F3 I/O
F4 I/O
M
M
M
P5[7]
P3[5]
P5[1]
Vss
A4
No connection.
A5
No connection.
F5 Power
F6 Power
Ground connection.
Ground connection.
A6 Power
A7
Supply voltage.
Vss
No connection.
F7 I/O
F8 I/O
F9
M
P5[0]
P3[0]
A8
No connection.
M
A9 Power
A10 Power
B1 Power
B2 Power
B3 I/O I,M
B4 I/O I,M
B5 I/O I,M
B6 Power
B7 I/O I,M
B8 I/O I,M
B9 Power
B10 Power
C1
Ground connection.
Ground connection.
Ground connection.
Ground connection.
XRES Active high pin reset with internal pull down.
P7[1]
F10 I/O
G1
NC
No connection.
G2 I/O
G3 I/O
G4 I/O
G5 I/O
G6 I/O
G7 I/O
G8 I/O
G9 I/O
G10 I/O
H1
M
M
M
M
M
M
M
M
P5[5]
P3[3]
P2[1] Direct switched capacitor block input.
P0[1] Analog column mux input.
P1[7] I2C Serial Clock (SCL).
[1]
P0[7] Analog column mux input.
P1[1] I2C Serial Clock (SCL), ISSP SCLK .
[1]
Vdd
Supply voltage.
P1[0] I2C Serial Data (SDA), ISSP SDATA .
P0[2] Analog column mux input.
P1[6]
P3[4]
P5[6]
P7[2]
P2[2] Direct switched capacitor block input.
Vss
Ground connection.
Ground connection.
No connection.
Vss
NC
NC
No connection.
C2 I/O
C3 I/O
C4 I/O
M
M
M
P4[1]
P4[7]
P2[7]
H2 I/O
H3 I/O
H4 I/O
M
M
M
M
M
M
M
M
P5[3]
P3[1]
P1[5] I2C Serial Data (SDA).
C5 I/O I/O,M P0[5] Analog column mux input and column output. H5 I/O
P1[3]
P1[2]
C6 I/O I,M
C7 I/O I,M
C8 I/O I,M
P0[6] Analog column mux input.
P0[0] Analog column mux input.
P2[0] Direct switched capacitor block input.
P4[2]
H6 I/O
H7 I/O
H8 I/O
H9 I/O
H10 I/O
P1[4] Optional External Clock Input (EXTCLK).
P3[2]
P5[4]
P7[3]
C9 I/O
C10
M
NC
No connection.
No connection.
D1
NC
J1
J2
J3
J4
Power
Power
Vss
Vss
D+
Ground connection.
Ground connection.
D2 I/O
D3 I/O
D4 I/O
M
M
M
P3[7]
P4[5]
P2[5]
USB
USB
Power
I/O
D-
D5 I/O I/O,M P0[3] Analog column mux input and column output. J5
Vdd
P7[7]
P7[0]
P5[2]
Vss
Vss
Vss
Vss
NC
Supply voltage.
D6 I/O I,M
P0[4] Analog column mux input.
J6
J7
J8
J9
D7 I/O
D8 I/O
D9 I/O
D10
M
M
M
P2[6] External Voltage Reference (VREF) input.
I/O
P4[6]
P4[0]
I/O
M
Power
Ground connection.
Ground connection.
Ground connection.
Ground connection.
No connection.
NC
No connection.
No connection.
No connection.
J10 Power
K1 Power
K2 Power
K3
E1
NC
E2
NC
E3 I/O
M
P4[3]
E4 I/O I,M
E5 Power
E6 Power
P2[3] Direct switched capacitor block input.
K4
NC
No connection.
Vss
Vss
Ground connection.
Ground connection.
K5 Power
K6 I/O
K7 I/O
K8 I/O
K9 Power
K10 Power
Vdd
P7[6]
P7[5]
P7[4]
Vss
Vss
Supply voltage.
E7 I/O
E8 I/O
E9 I/O
E10
M
M
M
P2[4] External Analog Ground (AGND) input.
P4[4]
P3[6]
Ground connection.
Ground connection.
NC
No connection.
LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection.
Document Number: 38-12018 Rev. *O
Page 12 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
Figure 7-5. CY8C24094 OCD (Not for Production)
1
2
3
4
5
6
7
8
9
10
Vss
Vss
NC
NC
NC
NC
NC
NC
Vss
Vss
Vss
NC
NC
NC
Vdd
NC
NC
Vss
Vss
Vss
NC
NC
NC
A
B
C
D
E
F
Vss P2[1] P0[1] P0[7] Vdd P0[2] P2[2] Vss
P4[1] P4[7] P2[7] P0[5] P0[6] P0[0] P2[0] P4[2]
P3[7] P4[5] P2[5] P0[3] P0[4] P2[6] P4[6] P4[0]
NC P4[3] P2[3] Vss
P5[7] P3[5] P5[1] Vss
Vss P2[4] P4[4] P3[6]
Vss P5[0] P3[0] XRES P7[1]
P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2]
P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] P3[2] P5[4] P7[3]
G
H
J
Vss
Vss
D +
NC
D -
Vdd P7[7] P7[0] P5[2] Vss
Vdd P7[6] P7[5] P7[4] Vss
Vss
Vss
NC
K
BGA (Top View)
7.6 100-Ball VFBGA Part Pinout (On-Chip Debug)
The following 100-pin VFBGA part table and drawing is for the CY8C24094 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Table 7-6. 100-Ball Part Pinout (VFBGA)
Pin
No.
Pin
No.
Name
Description
Name
Description
A1 Power
A2 Power
A3
Vss
Vss
NC
NC
NC
Vdd
NC
NC
Vss
Vss
Vss
Vss
Ground connection.
F1
OCDE OCD even data I/O.
Ground connection.
No connection.
F2 I/O
F3 I/O
F4 I/O
M
M
M
P5[7]
P3[5]
P5[1]
A4
No connection.
A5
No connection.
F5 Power
F6 Power
Vss
Ground connection.
Ground connection.
A6 Power
A7
Supply voltage.
Vss
No connection.
F7 I/O
F8 I/O
F9
M
P5[0]
P3[0]
A8
No connection.
M
A9 Power
A10 Power
B1 Power
B2 Power
Ground connection.
Ground connection.
Ground connection.
Ground connection.
XRES Active high pin reset with internal pull down.
F10 I/O
G1
P7[1]
OCDO OCD odd data output.
G2 I/O
G3 I/O
G4 I/O
G5 I/O
G6 I/O
G7 I/O
G8 I/O
G9 I/O
G10 I/O
H1
M
M
M
M
M
M
M
M
P5[5]
P3[3]
B3 I/O I,M P2[1] Direct switched capacitor block input.
B4 I/O I,M P0[1] Analog column mux input.
B5 I/O I,M P0[7] Analog column mux input.
P1[7] I2C Serial Clock (SCL).
[1]
P1[1] I2C Serial Clock (SCL), ISSP SCLK
.
[1]
B6 Power
Vdd
Supply voltage.
P1[0] I2C Serial Data (SDA), ISSP SDATA .
B7 I/O I,M P0[2] Analog column mux input.
P1[6]
P3[4]
P5[6]
P7[2]
B8 I/O I,M P2[2] Direct switched capacitor block input.
B9 Power
B10 Power
C1
Vss
Ground connection.
Ground connection.
No connection.
Vss
NC
NC
No connection.
C2 I/O
C3 I/O
C4 I/O
M
P4[1]
P4[7]
P2[7]
H2 I/O
H3 I/O
H4 I/O
M
M
M
M
P5[3]
P3[1]
M
M
P1[5] I2C Serial Data (SDA).
P1[3]
C5 I/O I/O, P0[5] Analog column mux input and column output. H5 I/O
M
C6 I/O I,M P0[6] Analog column mux input.
C7 I/O I,M P0[0] Analog column mux input.
H6 I/O
H7 I/O
M
M
P1[2]
P1[4] Optional External Clock Input (EXTCLK).
Document Number: 38-12018 Rev. *O
Page 13 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
Table 7-6. 100-Ball Part Pinout (VFBGA) (continued)
C8 I/O I,M P2[0] Direct switched capacitor block input.
H8 I/O
H9 I/O
H10 I/O
M
M
P3[2]
P5[4]
P7[3]
Vss
Vss
D+
C9 I/O
C10
M
P4[2]
NC
No connection.
No connection.
D1
NC
J1
J2
J3
J4
Power
Power
Ground connection.
D2 I/O
D3 I/O
D4 I/O
M
M
M
P3[7]
P4[5]
P2[5]
Ground connection.
USB
USB
D-
D5 I/O I/O, P0[3] Analog column mux input and column output. J5
M
Power
Vdd
Supply voltage.
D6 I/O I,M P0[4] Analog column mux input.
J6
J7
J8
J9
I/O
I/O
P7[7]
P7[0]
P5[2]
Vss
D7 I/O
D8 I/O
D9 I/O
D10
M
M
M
P2[6] External Voltage Reference (VREF) input.
P4[6]
I/O
M
P4[0]
Power
Ground connection.
Ground connection.
Ground connection.
Ground connection.
No connection.
CCLK OCD CPU clock output.
J10 Power
K1 Power
K2 Power
K3
Vss
E1
NC
No connection.
No connection.
Vss
E2
NC
Vss
E3 I/O
M
P4[3]
NC
E4 I/O I,M P2[3] Direct switched capacitor block input.
K4
NC
No connection.
E5 Power
E6 Power
Vss
Vss
Ground connection.
Ground connection.
K5 Power
K6 I/O
K7 I/O
K8 I/O
K9 Power
K10 Power
Vdd
P7[6]
P7[5]
P7[4]
Vss
Supply voltage.
E7 I/O
E8 I/O
E9 I/O
E10
M
P2[4] External Analog Ground (AGND) input.
M
M
P4[4]
P3[6]
Ground connection.
Ground connection.
HCLK OCD high speed clock output.
Vss
LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection, OCD = On-Chip Debugger.
Figure 7-6. CY8C24094 OCD (Not for Production)
1
2
3
4
5
6
7
8
9
10
Vss
Vss
NC
NC
NC
Vss
NC
NC
NC
Vdd
NC
NC
Vss
Vss
Vss
NC
A
B
C
D
E
F
Vss P2[1] P0[1] P0[7] Vdd P0[2] P2[2] Vss
P4[1] P4[7] P2[7] P0[5] P0[6] P0[0] P2[0] P4[2]
P3[7] P4[5] P2[5] P0[3] P0[4] P2[6] P4[6] P4[0] CClk
NC P4[3] P2[3] Vss
Vss P2[4] P4[4] P3[6] HClk
Vss P5[0] P3[0] XRES P7[1]
ocde P5[7] P3[5] P5[1] Vss
ocdo P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2]
G
H
J
NC
Vss
Vss
P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] P3[2] P5[4] P7[3]
Vss
Vss
D +
NC
D -
Vdd P7[7] P7[0] P5[2] Vss
Vdd P7[6] P7[5] P7[4] Vss
Vss
Vss
NC
K
BGA (Top View)
Document Number: 38-12018 Rev. *O
Page 14 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
7.7 100-Pin Part Pinout (On-Chip Debug)
The 100-pin TQFP part is for the CY8C24094 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Table 7-7. 100-Pin Part Pinout (TQFP)
Pin
No.
Pin
No.
Name
Description
Name
Description
1
NC
NC
No connection.
No connection.
51 I/O
52 I/O
53 I/O
54 I/O
55 I/O
56 I/O
57 I/O
58 I/O
59 I/O
60
M
M
M
M
M
M
M
M
M
P1[6]
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
2
3
4
5
6
7
8
9
I/O I, M P0[1] Analog column mux input.
I/O
I/O
M
M
P2[7]
P2[5]
I/O I, M P2[3] Direct switched capacitor block input.
I/O I, M P2[1] Direct switched capacitor block input.
I/O
I/O
M
M
M
M
P4[7]
P4[5]
10 I/O
P4[3]
HCLK OCD high speed clock output.
11
12
13
14
I/O
P4[1]
61
CCLK OCD CPU clock output.
OCDE OCD even data I/O.
OCDO OCD odd data output.
62 Input
63 I/O
64 I/O
XRES Active high pin reset with internal pull down.
M
M
P4[0]
P4[2]
NC
No connection.
15 Power
Vss
Ground connection.
65 Power
Vss
Ground connection.
16 I/O
17 I/O
18 I/O
19 I/O
20 I/O
21 I/O
22 I/O
23 I/O
24 I/O
25
M
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
66 I/O
67 I/O
M
P4[4]
P4[6]
M
M
M
M
M
M
M
M
M
68 I/O I, M P2[0] Direct switched capacitor block input.
69 I/O I, M P2[2] Direct switched capacitor block input.
70 I/O
71
P2[4] External Analog Ground (AGND) input.
NC No connection.
P2[6] External Voltage Reference (VREF) input.
NC No connection.
P0[0] Analog column mux input.
72 I/O
73
P1[7] I2C Serial Clock (SCL).
74 I/O
75
I
NC
NC
NC
No connection.
No connection.
No connection.
NC
NC
No connection.
No connection.
26
76
27
77 I/O I, M P0[2] Analog column mux input and column output.
78 NC No connection.
79 I/O I, M P0[4] Analog column mux input and column output.
80 NC No connection.
28 I/O
29 I/O
30 I/O
P1[5] I2C Serial Data (SDA)
P1[3]
P1[1] Crystal (XTALin), I2C Serial Clock (SCL),
[1]
ISSP SCLK
.
31
NC
No connection.
81 I/O I, M P0[6] Analog column mux input.
32 Power
33 USB
34 USB
35 Power
36 I/O
37 I/O
38 I/O
39 I/O
40 I/O
41 I/O
42 I/O
43 I/O
44
Vss
Ground connection.
82 Power
Vdd
NC
Vss
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Supply voltage.
No connection.
Ground connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
D+
83
D-
84 Power
Vdd
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
NC
Supply voltage.
85
86
87
88
89
90
91
92
93
94
No connection.
No connection.
No connection.
No connection.
45
NC
95 I/O I, M P0[7] Analog column mux input.
96 NC No connection.
46
NC
47
NC
97 I/O I/O, P0[5] Analog column mux input and column output.
M
48 I/O
49 I/O
50 I/O
P1[0] Crystal (XTALout), I2C Serial Data (SDA),
98
NC
No connection.
[1]
ISSP SDATA
.
P1[2]
99 I/O I/O, P0[3] Analog column mux input and column output.
M
P1[4] Optional External Clock Input (EXTCLK).
100
NC
No connection.
Document Number: 38-12018 Rev. *O
Page 15 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
Table 7-7. 100-Pin Part Pinout (TQFP) (continued)
LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input, OCD = On-Chip Debugger.
Figure 7-7. CY8C24094 OCD (Not for Production)
NC
NC
NC
1
2
3
4
75
74
P0[0],M,AI
AI, M,P0[1]
M,P2[7]
M,P2[5]
AI, M,P2[3]
AI, M,P2[1]
M,P4[7]
M,P4[5]
M,P4[3]
M,P4[1]
OCDE
NC
73
72
71
P2[6],M,External VREF
NC
P2[4],M,External AGND
5
6
70
69
7
8
9
P2[2],M,AI
P2[0],M,AI
P4[6],M
68
67
P4[4],M
10
11
12
13
14
15
16
17
18
19
20
21
22
66
65
64
63
62
61
60
59
Vss
P4[2],M
OCDO
TQFP
P4[0],M
XRES
NC
Vss
M,P3[7]
M,P3[5]
CCLK
HCLK
P3[6],M
P3[4],M
P3[2],M
P3[0],M
P5[6],M
M,P3[3]
58
57
56
55
M,P3[1]
M,P5[7]
M,P5[5]
P5[4],M
P5[2],M
P5[0],M
M,P5[3]
M,P5[1]
54
53
52
51
23
24
25
I2C SCL,P1[7]
NC
P1[6],M
Document Number: 38-12018 Rev. *O
Page 16 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
8. Register Reference
This section lists the registers of the CY8C24x94 PSoC device family. For detailed register information, reference the
PSoC Programmable System-on-Chip Technical Reference Manual.
8.1 Register Conventions
8.2 Register Mapping Tables
The register conventions specific to this section are listed in the
following table.
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.
Convention
Description
Read register or bit(s)
R
W
L
Note In the following register mapping tables, blank fields are
Reserved and should not be accessed.
Write register or bit(s)
Logical register or bit(s)
Clearable register or bit(s)
Access is bit specific
C
#
Document Number: 38-12018 Rev. *O
Page 17 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
8.3 Register Map Bank 0 Table: User Space
Name
PRT0DR
Addr (0,Hex) Access
Name
Addr (0,Hex) Access
Name
ASC10CR0
Addr (0,Hex) Access
Name
Addr (0,Hex)
C0
Access
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
PMA0_DR
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RW
RW
RW
RW
RW
RW
RW
RW
R
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RW
RW
RW
RW
RW
RW
RW
RW
PRT0IE
PMA1_DR
PMA2_DR
PMA3_DR
PMA4_DR
PMA5_DR
PMA6_DR
PMA7_DR
USB_SOF0
USB_SOF1
USB_CR0
USBI/O_CR0
USBI/O_CR1
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
R
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
RW
#
RW
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
EP1_CNT1
EP1_CNT
EP2_CNT1
EP2_CNT
EP3_CNT1
EP3_CNT
EP4_CNT1
EP4_CNT
EP0_CR
#
RW
#
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
RW
RW
RW
RW
RW
RW
CUR_PP
RW
RW
#
STK_PP
RW
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
RW
#
IDX_PP
RW
RW
RW
RW
#
MVR_PP
RW
#
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
PRT5GS
PRT5DM2
EP0_CNT
EP0_DR0
EP0_DR1
EP0_DR2
EP0_DR3
EP0_DR4
EP0_DR5
EP0_DR6
EP0_DR7
AMX_IN
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
PRT7DR
RW
RW
RW
RW
#
PRT7IE
PRT7GS
PRT7DM2
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
W
AMUXCFG
RW
#
ARF_CR
CMP_CR0
ASY_CR
CMP_CR1
RW
#
RES_WDT
DEC_DH
#
RC
RC
RW
RW
W
W
#
DEC_DL
RW
#
RW
DEC_CR0
DEC_CR1
MUL0_X
#
MUL1_X
W
W
MUL1_Y
W
MUL0_Y
W
RW
#
MUL1_DH
MUL1_DL
ACC1_DR1
ACC1_DR0
ACC1_DR3
ACC1_DR2
RDI0RI
R
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
R
R
R
#
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
RW
#
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
CPU_F
RL
DAC_D
RW
#
CPU_SCR1
CPU_SCR0
#
Blank fields are Reserved and should not be accessed.
# Access is bit specific.
Document Number: 38-12018 Rev. *O
Page 18 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
8.4 Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
PRT5DM1
PRT5IC0
PRT5IC1
Addr (1,Hex) Access
Name
Addr (1,Hex) Access
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr (1,Hex) Access
Name
USBI/O_CR2
USB_CR1
Addr(1,Hex) Access
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
PMA0_WA
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RW
RW
RW
RW
RW
RW
RW
RW
80
RW
RW
RW
RW
RW
RW
RW
RW
C0
C1
RW
#
PMA1_WA
PMA2_WA
PMA3_WA
PMA4_WA
PMA5_WA
PMA6_WA
PMA7_WA
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
EP1_CR0
EP2_CR0
EP3_CR0
EP4_CR0
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
#
#
#
#
PMA0_RA
PMA1_RA
PMA2_RA
PMA3_RA
PMA4_RA
PMA5_RA
PMA6_RA
PMA7_RA
RW
RW
RW
RW
RW
RW
RW
RW
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
RW
RW
RW
RW
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
RW
RW
RW
RW
RW
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
RW
RW
RW
RW
PRT7DM0
PRT7DM1
PRT7IC0
PRT7IC1
DBB00FN
DBB00IN
DBB00OU
RW
RW
RW
RW
RW
RW
RW
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
RW
RW
RW
RW
RW
RW
RW
R
CLK_CR0
CLK_CR1
ABF_CR0
AMD_CR0
CMP_GO_EN
RW
RW
RW
RW
RW
DBB01FN
DBB01IN
DBB01OU
RW
RW
RW
VLT_CMP
AMD_CR1
ALT_CR0
RW
RW
DCB02FN
DCB02IN
DCB02OU
RW
RW
RW
IMO_TR
W
ILO_TR
W
BDG_TR
ECO_TR
MUX_CR4
MUX_CR5
RW
W
DCB03FN
DCB03IN
DCB03OU
RW
RW
RW
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RW
RW
RW
RW
RW
RW
RW
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
CPU_F
RL
DAC_CR
RW
#
CPU_SCR1
CPU_SCR0
#
Blank fields are Reserved and should not be accessed.
# Access is bit specific.
Document Number: 38-12018 Rev. *O
Page 19 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
9. Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C24x94 PSoC device family. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ T ≤ 85oC and T ≤ 100oC, except where noted. Specifications for devices running at greater than
A
J
12 MHz are valid for -40oC ≤ T ≤ 70oC and T ≤ 82oC.
A
J
Figure 9-1. Voltage versus CPU Frequency
5.25
4.75
3.00
93 kHz
12 MHz
24 MHz
CPU Frequency
The following table lists the units of measure that are used in this chapter.
Table 9-1. Units of Measure
Symbol
oC
Unit of Measure
degree Celsius
Symbol
μW
mA
ms
mV
nA
Unit of Measure
microwatts
dB
decibels
milli-ampere
milli-second
milli-volts
fF
femto farad
hertz
Hz
KB
1024 bytes
1024 bits
nanoampere
nanosecond
nanovolts
Kbit
kHz
kΩ
ns
kilohertz
nV
kilohm
W
ohm
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
megahertz
megaohm
pA
picoampere
picofarad
pF
microampere
microfarad
microhenry
microsecond
microvolts
pp
peak-to-peak
parts per million
picosecond
ppm
ps
sps
s
samples per second
sigma: one standard deviation
volts
microvolts root-mean-square
V
Document Number: 38-12018 Rev. *O
Page 20 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
9.1 Absolute Maximum Ratings
Table 9-2. Absolute Maximum Ratings
Symbol
Description
Storage Temperature
Min
Typ
Max
Units
oC
Notes
TSTG
-55
25
+100
Higher storage temperatures
reduces data retention time. Recom-
mended storage temperature is
+25oC ± 25oC. Extended duration
storage temperatures above 65oC
degrades reliability.
TA
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
-40
–
–
–
+85
oC
V
Vdd
VI/O
-0.5
+6.0
Vss -
0.5
Vdd +
0.5
V
VI/O2
DC Voltage Applied to Tri-state
Vss -
0.5
–
Vdd +
0.5
V
IMI/O
Maximum Current into any Port Pin
-25
-50
–
–
+50
+50
mA
mA
IMAI/O
Maximum Current into any Port Pin
Configured as Analog Driver
ESD
LU
Electro Static Discharge Voltage
Latch-up Current
2000
–
–
–
–
V
Human Body Model ESD.
200
mA
9.2 Operating Temperature
Table 9-3. Operating Temperature
Symbol
TA
Description
Min
-40
-10
-40
Typ
–
Max
+85
Units
oC
oC
oC
Notes
Ambient Temperature
TAUSB
TJ
Ambient Temperature using USB
Junction Temperature
–
+85
–
+100
Thetemperaturerisefromambientto
junction is package specific. See
Thermal Impedance on page 41. The
user must limit the power
consumption to comply with this
requirement.
Document Number: 38-12018 Rev. *O
Page 21 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
9.3 DC Electrical Characteristics
9.3.1 DC Chip Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9-4. DC Chip-Level Specifications
Symbol
Vdd
Description
Supply Voltage
Min
3.0
Typ
–
Max
5.25
Units
V
Notes
See DC POR and LVD specifications,
Table 9-14 on page 28.
IDD5
Supply Current, IMO = 24 MHz (5V)
Supply Current, IMO = 24 MHz (3.3V)
–
14
27
mA
Conditions are Vdd = 5.0V, TA = 25 oC,
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz, VC2 =93.75
kHz, VC3 = 93.75 kHz, analog power
= off.
Conditions are Vdd = 3.3V, TA = 25 oC,
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz, VC2 =93.75
kHz, VC3 = 0.367 kHz, analog power
= off.
IDD3
–
8
14
mA
ISB
Sleep (Mode) Current with POR, LVD,
Sleep Timer, and WDT.[3]
–
–
3
4
6.5
25
μA
μA
Conditions are with internal slow
speed oscillator, Vdd = 3.3V, -40 oC ≤
TA ≤ 55 oC, analog power = off.
Conditions are with internal slow
speed oscillator, Vdd = 3.3V, 55 oC <
TA ≤ 85 oC, analog power = off.
ISBH
Sleep (Mode) Current with POR, LVD,
Sleep Timer, and WDT at high temper-
ature.[3]
9.3.2 DC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9-5. DC GPI/O Specifications
Symbol
RPU
RPD
Description
Pull Up Resistor
Pull Down Resistor
High Output Level
Min
4
4
Typ
5.6
5.6
–
Max
Units
kΩ
kΩ
Notes
8
8
–
VOH
Vdd - 1.0
V
I/OH = 10 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])). 80
mA maximum combined I/OH budget.
VOL
Low Output Level
–
–
0.75
0.8
V
I/OL = 25 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])). 200
mA maximum combined I/OL budget.
Vdd = 3.0 to 5.25.
Vdd = 3.0 to 5.25.
VIL
VIH
VH
IIL
Input Low Level
Input High Level
Input Hysterisis
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
2.1
–
–
–
–
–
60
1
V
V
mV
nA
pF
–
–
10
Gross tested to 1 μA.
CIN
3.5
Package and pin dependent.
Temp = 25oC.
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent.
Temp = 25oC.
Note
3. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar
functions enabled.
Document Number: 38-12018 Rev. *O
Page 22 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
9.3.3 DC Full Speed USB Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -10°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -10°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9-6. DC Full Speed (12 Mbps) USB Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
| (D+) - (D-) |
USB Interface
VDI
Differential Input Sensitivity
0.2
0.8
0.8
–
–
–
–
–
–
–
–
–
V
V
VCM
VSE
CIN
Differential Input Common Mode Range
Single Ended Receiver Threshold
Transceiver Capacitance
2.5
2.0
20
10
25
3.6
V
pF
μA
W
V
II/O
High-Z State Data Line Leakage
External USB Series Resistor
Static Output High, Driven
-10
23
0V < VIN < 3.3V.
REXT
VUOH
In series with each USB pin.
2.8
15 kΩ ± 5% to Ground. Internal
pull up enabled.
VUOHI
VUOL
Static Output High, Idle
Static Output Low
2.7
–
–
–
3.6
0.3
V
V
15 kΩ ± 5% to Ground. Internal
pull up enabled.
15 kΩ ± 5% to Ground. Internal
pull up enabled.
ZO
USB Driver Output Impedance
D+/D- Crossover Voltage
28
–
–
44
W
V
Including REXT Resistor.
VCRS
1.3
2.0
9.3.4 DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.
Table 9-7. 5V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VOSOA
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
1.6
1.3
1.2
10
8
7.5
mV
mV
mV
TCVOSOA Average Input Offset Voltage Drift
7.0
20
35.0
–
μV/oC
pA
IEBOA
CINOA
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
Gross tested to 1 μA.
Package and pin dependent.
Temp = 25oC.
4.5
9.5
pF
VCMOA
Common Mode Voltage Range
Common Mode Voltage Range (high power
or high opamp bias)
0.0
0.5
–
–
Vdd
Vdd - 0.5
V
The common-mode input
voltage range is measured
through an analog output
buffer. The specification
includes the limitations
imposed by the characteristics
of the analog output buffer.
GOLOA
Open Loop Gain
–
–
dB
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
60
60
80
Document Number: 38-12018 Rev. *O
Page 23 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
Table 9-7. 5V DC Operational Amplifier Specifications (continued)
Symbol
Description
Min
Typ
Max
Units
Notes
VOHIGHO High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Vdd - 0.2
Vdd - 0.2
Vdd - 0.5
–
–
–
–
–
–
V
V
V
A
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
ISOA
Supply Current (including associated AGND
buffer)
–
–
–
–
–
–
400
500
800
1200
2400
4600
800
900
1000
1600
3200
6400
μA
μA
μA
μA
μA
μA
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
PSRROA Supply Voltage Rejection Ratio
65
80
–
dB
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd
- 1.25V) ≤ VIN ≤ Vdd.
9.3.5 DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 9-8. DC Low Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VREFLPC Low power comparator (LPC) reference
voltage range
0.2
–
Vdd - 1
V
ISLPC
LPC supply current
LPC voltage offset
–
–
10
40
30
μA
mV
VOSLPC
2.5
Document Number: 38-12018 Rev. *O
Page 24 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
9.3.6 DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9-9. 5V DC Analog Output Buffer Specifications
Symbol
Description
Min
–
Typ
3
Max
12
–
Units
mV
Notes
VOSOB
Input Offset Voltage (Absolute Value)
TCVOSO Average Input Offset Voltage Drift
–
+6
μV/°C
B
VCMOB
Common-Mode Input Voltage Range
0.5
–
Vdd - 1.0
V
ROUTOB Output Resistance
Power = Low
–
–
0.6
0.6
–
–
W
W
Power = High
VOHIGHO High Output Voltage Swing (Load = 32 ohms
to Vdd/2)
0.5 x Vdd +
1.1
0.5 x Vdd +
1.1
–
–
–
–
V
V
B
Power = Low
Power = High
VOLOWOB Low Output Voltage Swing (Load = 32 ohms
to Vdd/2)
Power = Low
–
–
–
–
0.5 x Vdd -
1.3
V
V
Power = High
0.5 x Vdd -
1.3
ISOB
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
–
–
1.1
2.6
5.1
8.8
mA
mA
PSRROB Supply Voltage Rejection Ratio
53
64
–
dB
(0.5 x Vdd - 1.3) ≤ VOUT ≤
(Vdd - 2.3).
Table 9-10. 3.3V DC Analog Output Buffer Specifications
Symbol
Description
Min
–
Typ
3
Max
12
Units
mV
Notes
VOSOB
Input Offset Voltage (Absolute Value)
TCVOSOB Average Input Offset Voltage Drift
VCMOB Common-Mode Input Voltage Range
–
+6
-
–
μV/°C
V
0.5
Vdd - 1.0
ROUTOB Output Resistance
Power = Low
–
–
1
1
–
–
W
W
Power = High
VOHIGHO High Output Voltage Swing (Load = 1K ohms
to Vdd/2)
0.5 x Vdd +
1.0
–
–
–
–
V
V
B
Power = Low
Power = High
0.5 x Vdd +
1.0
VOLOWOB Low Output Voltage Swing (Load = 1K ohms
to Vdd/2)
Power = Low
Power = High
–
–
–
–
0.5 x Vdd -
1.0
0.5 x Vdd -
1.0
V
V
ISOB
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
0.8
2.0
2.0
4.3
mA
mA
–
PSRROB Supply Voltage Rejection Ratio
34
64
–
dB
(0.5 xVdd -1.0)≤ VOUT ≤ (0.5
x Vdd + 0.9).
Document Number: 38-12018 Rev. *O
Page 25 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
9.3.7 DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 9-11. 5V DC Analog Reference Specifications
Symbol
Description
Bandgap Voltage Reference
AGND = Vdd/2[4, 5]
AGND = 2 x BandGap[4, 5]
AGND = P2[4] (P2[4] = Vdd/2)[4, 5]
AGND = BandGap[4, 5]
AGND = 1.6 x BandGap[4, 5]
AGND Block to Block Variation (AGND = Vdd/2)[4, 5]
RefHi = Vdd/2 + BandGap
Min
Typ
1.30
Max
Units
V
BG
–
1.28
1.32
Vdd/2 - 0.04
2 x BG - 0.048
P2[4] - 0.011
BG - 0.009
1.6 x BG - 0.022
-0.034
Vdd/2 - 0.01
2 x BG - 0.030
P2[4]
Vdd/2 + 0.007
2 x BG + 0.024
P2[4] + 0.011
BG + 0.016
1.6 x BG + 0.018
0.034
V
–
V
–
V
–
BG + 0.008
1.6 x BG - 0.010
0.000
V
–
V
–
V
–
Vdd/2 + BG - 0.10
3 x BG - 0.06
Vdd/2 + BG
3 x BG
Vdd/2 + BG + 0.10
3 x BG + 0.06
V
–
RefHi = 3 x BandGap
V
–
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
2 x BG + P2[6] -
0.113
2 x BG + P2[6] -
0.018
2 x BG + P2[6] +
0.077
V
–
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
P2[4] + BG - 0.130 P2[4] + BG - 0.016 P2[4] + BG + 0.098
V
V
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
P2[4] + P2[6] -
0.133
P2[4] + P2[6] -
0.016
P2[4] + P2[6]+
0.100
–
–
–
–
RefHi = 3.2 x BandGap
3.2 x BG - 0.112
3.2 x BG
3.2 x BG + 0.076
V
V
V
V
RefLo = Vdd/2 – BandGap
RefLo = BandGap
Vdd/2 - BG - 0.04 Vdd/2 - BG + 0.024 Vdd/2 - BG + 0.04
BG - 0.06
BG
BG + 0.06
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
2 x BG - P2[6] -
0.084
2 x BG - P2[6] +
0.025
2 x BG - P2[6] +
0.134
–
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107
V
V
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
P2[4] - P2[6] -
0.057
P2[4] - P2[6] +
0.026
P2[4] - P2[6] +
0.110
Table 9-12. 3.3V DC Analog Reference Specifications
Symbol
Description
Min
1.28
Typ
1.30
Max
1.32
Units
BG
–
Bandgap Voltage Reference
AGND = Vdd/2[4, 5]
AGND = 2 x BandGap[4, 5]
AGND = P2[4] (P2[4] = Vdd/2)
AGND = BandGap[4, 5]
V
V
Vdd/2 - 0.03
Vdd/2 - 0.01
Not Allowed
P2[4] + 0.001
BG + 0.005
1.6 x BG - 0.010
0.000
Vdd/2 + 0.005
–
–
P2[4] - 0.008
BG - 0.009
P2[4] + 0.009
BG + 0.015
1.6 x BG + 0.018
0.034
V
V
V
V
–
–
AGND = 1.6 x BandGap[4, 5]
1.6 x BG - 0.027
-0.034
–
AGND Column to Column Variation (AGND =
Vdd/2)[4, 5]
–
–
–
–
–
RefHi = Vdd/2 + BandGap
Not Allowed
Not Allowed
Not Allowed
Not Allowed
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
P2[4] + P2[6] -
0.075
P2[4] + P2[6] -
0.009
P2[4] + P2[6] +
0.057
V
Document Number: 38-12018 Rev. *O
Page 26 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
Table 9-12. 3.3V DC Analog Reference Specifications (continued)
Symbol
Description
RefHi = 3.2 x BandGap
Min
Typ
Max
Units
–
–
–
–
–
–
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
RefLo = Vdd/2 - BandGap
RefLo = BandGap
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] - 0.048
P2[4]- P2[6] +
0.022
P2[4] - P2[6] +
0.092
V
9.3.8 DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9-13. DC Analog PSoC Block Specifications
Symbol
RCT
Description
Min
–
Typ
12.2
80
Max
–
Units
kΩ
fF
Notes
Resistor Unit Value (Continuous Time)
Capacitor Unit Value (Switched Capacitor)
CSC
–
–
Note
4. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
5. Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling of the digital signal may appear on the
AGND.
Document Number: 38-12018 Rev. *O
Page 27 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
9.3.9 DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V or 3.3V at 25°C and are
for design guidance only.
Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Programmable
System-on-Chip Technical Reference Manual for more information on the VLT_CR register.
Table 9-14. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd Value for PPOR Trip (positive ramp)
VPPOR0R PORLEV[1:0] = 00b
VPPOR1R PORLEV[1:0] = 01b
VPPOR2R PORLEV[1:0] = 10b
2.91
4.39
4.55
V
V
V
–
–
Vdd Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VPPOR0
VPPOR1
VPPOR2
2.82
4.39
4.55
V
V
V
–
–
PPOR Hysteresis
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VPH0
VPH1
VPH2
–
–
–
92
0
0
–
–
–
mV
mV
mV
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
2.86
2.96
3.07
3.92
4.39
4.55
4.63
4.72
2.92
3.02
3.13
4.00
4.48
4.64
4.73
4.81
2.98[6]
3.08
3.20
V
V
V
V
V
V
V
V
V
4.08
4.57
4.74[7]
4.82
4.91
Notes
6. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
7. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
Document Number: 38-12018 Rev. *O
Page 28 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
9.3.10 DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9-15. DC Programming Specifications
Symbol
IDDP
Description
Min
–
Typ
15
–
Max
30
Units
mA
V
Notes
Supply Current During Programming or Verify
VILP
Input Low Voltage During Programming or
Verify
–
0.8
VIHP
IILP
Input High Voltage During Programming or
Verify
2.1
–
–
–
–
–
–
–
–
–
–
V
mA
mA
V
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
0.2
1.5
Driving internal pull down
resistor.
IIHP
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
–
Driving internal pull down
resistor.
VOLV
VOHV
Output Low Voltage During Programming or
Verify
–
Vss +
0.75
Output High Voltage During Programming or Vdd- 1.0
Verify
Vdd
V
FlashENP Flash Endurance (per block)
50,000
–
–
Erase/write cycles per block.
Erase/write cycles.
B
FlashENT Flash Endurance (total)[8]
1,800,0
00
–
–
FlashDR Flash Data Retention
10
–
Years
Note
8. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks
of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees
more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 38-12018 Rev. *O
Page 29 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
9.4 AC Electrical Characteristics
9.4.1 AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9-16. AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
24.96[9,10]
Units
Notes
FIMO245V Internal Main Oscillator Frequency for 24 MHz 23.04
(5V)
24
MHz Trimmed for 5V operation
using factory trim values.
FIMO243V Internal Main Oscillator Frequency for 24 MHz 22.08
(3.3V)
24
24
25.92[10,11]
24.06[10]
MHz Trimmed for 3.3V operation
using factory trim values.
FIMOUSB5 Internal Main Oscillator Frequency with USB
23.94
MHz -10°C ≤ TA ≤ 85°C
4.35 ≤ Vdd ≤ 5.15
(5V)
V
Frequency locking enabled and USB traffic
present.
FIMOUSB3 Internal Main Oscillator Frequency with USB
23.94
24
24.06[10]
MHz -0°C ≤ TA ≤ 70°C
3.15 ≤ Vdd ≤ 3.45
(3.3V)
V
Frequency locking enabled and USB traffic
present.
FCPU1
FCPU2
FBLK5
CPU Frequency (5V Nominal)
0.93
0.93
0
24
12
48
24.96[9,10]
12.96[10,11]
49.92[9,10,12]
MHz
MHz
CPU Frequency (3.3V Nominal)
Digital PSoC Block Frequency (5V Nominal)
MHz Refer to the AC Digital Block
Specifications.
FBLK3
F32K1
Digital PSoC Block Frequency (3.3V Nominal)
Internal Low Speed Oscillator Frequency
0
15
24
32
25.92[10,12]
64
MHz
kHz
ns
Jitter32k 32 kHz Period Jitter
–
100
50
Step24M 24 MHz Trim Step Size
Fout48M 48 MHz Output Frequency
–
–
kHz
46.08
48.0
49.92[9,11]
MHz Trimmed. Utilizing factory
trim values.
Jitter24M 24 MHz Period Jitter (IMO) Peak-to-Peak
1
–
–
0
300
–
ps
MHz
μs
FMAX
Maximum frequency of signal on row input or
row output.
12.96
–
TRAMP
Supply Ramp Time
–
Figure 9-2. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F24M
Notes
9. 4.75V < Vdd < 5.25V.
10. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
11. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3V.
12. See the individual user module data sheets for information on maximum frequencies for user modules
Document Number: 38-12018 Rev. *O
Page 30 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
9.4.2 AC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9-17. AC GPI/O Specifications
Symbol
FGPI/O
Description
Min
0
Typ
–
Max
12
18
18
–
Units
Notes
GPI/O Operating Frequency
MHz Normal Strong Mode
TRiseF
TFallF
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
3
–
ns
ns
ns
ns
Vdd = 4.5 to 5.25V, 10% - 90%
2
–
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
TRiseS
TFallS
10
10
27
22
–
Figure 9-3. GPI/O Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
9.4.3 AC Full Speed USB Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -10°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -10°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9-18. AC Full Speed (12 Mbps) USB Specifications
Symbol
TRFS
Description
Transition Rise Time
Min
4
Typ
–
Max
20
Units
ns
Notes
For 50 pF load.
TFSS
Transition Fall Time
4
–
20
ns
For 50 pF load.
For 50 pF load.
TRFMFS
Rise/Fall Time Matching: (TR/TF)
90
–
111
%
TDRATEFS Full Speed Data Rate
12 -
0.25%
12
12 +
0.25%
Mbps
Document Number: 38-12018 Rev. *O
Page 31 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
9.4.4 AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 9-19. 5V AC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
TROA
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10
pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
3.9
0.72
0.62
μs
μs
μs
TSOA
Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10
pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
5.9
0.92
0.72
μs
μs
μs
SRROA
Rising Slew Rate (20% to 80%)(10 pF load, Unity
Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.15
1.7
6.5
–
–
–
–
–
–
V/μs
V/μs
V/μs
SRFOA
Falling Slew Rate (20% to 80%)(10 pF load, Unity
Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.01
0.5
4.0
–
–
–
–
–
–
V/μs
V/μs
V/μs
BWOA
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.75
3.1
5.4
–
–
–
–
–
–
MHz
MHz
MHz
ENOA
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
Table 9-20. 3.3V AC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
TROA
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10
pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
–
–
–
–
3.92
0.72
μs
μs
TSOA
Falling Settling Time from 20% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
–
–
–
–
5.41
0.72
μs
μs
SRROA
Rising Slew Rate (20% to 80%)(10 pF load, Unity
Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
0.31
2.7
–
–
–
–
V/μs
V/μs
SRFOA
Falling Slew Rate (20% to 80%)(10 pF load, Unity
Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
0.24
1.8
–
–
–
–
V/μs
V/μs
BWOA
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
0.67
2.8
–
–
–
–
MHz
MHz
ENOA
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
Document Number: 38-12018 Rev. *O
Page 32 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 9-4. Typical AGND Noise with P2[4] Bypass
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 9-5. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
0.01
0.1
1
10
100
Freq (kHz)
Document Number: 38-12018 Rev. *O
Page 33 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
9.4.5 AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 9-21. AC Low Power Comparator Specifications
Symbol
Description
LPC response time
Min
Typ
Max
Units
Notes
TRLPC
–
–
50
μs
≥ 50 mV overdrive comparator
reference set within VREFLPC
.
9.4.6 AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9-22. AC Digital Block Specifications
Function
Description
Capture Pulse Width
Min
50[13]
Typ
–
Max
–
Units
Notes
Timer
ns
Maximum Frequency, No Capture
Maximum Frequency, With Capture
–
–
49.92
25.92
–
MHz 4.75V < Vdd < 5.25V.
–
50[13]
–
–
MHz
Counter Enable Pulse Width
Maximum Frequency, No Enable Input
–
ns
–
49.92
25.92
MHz 4.75V < Vdd < 5.25V.
MHz
Maximum Frequency, Enable Input
Kill Pulse Width:
–
–
Dead
Band
Asynchronous Restart Mode
Synchronous Restart Mode
Disable Mode
20
50[13]
50[13]
–
–
–
–
–
–
–
–
ns
ns
–
ns
Maximum Frequency
49.92
49.92
MHz 4.75V < Vdd < 5.25V.
MHz 4.75V < Vdd < 5.25V.
CRCPRS Maximum Input Clock Frequency
–
(PRS
Mode)
CRCPRS Maximum Input Clock Frequency
(CRC
Mode)
–
–
–
24.6
8.2
MHz
SPIM
Maximum Input Clock Frequency
Maximum Input Clock Frequency
–
–
MHz Maximum data rate at 4.1 MHz due
to 2 x over clocking.
SPIS
–
–
–
4.1
–
MHz
ns
Width of SS_ Negated Between Transmissions 50[13]
Trans-
mitter
Maximum Input Clock Frequency
–
24.6
MHz Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Receiver Maximum Input Clock Frequency
–
–
24.6
MHz Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Note
13. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 38-12018 Rev. *O
Page 34 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
9.4.7 AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9-23. AC External Clock Specifications
Symbol
Description
Min
23.94
47
Typ
24
50
–
Max
24.06
53
Units
MHz
%
Notes
FOSCEXT Frequency for USB Applications
–
–
Duty Cycle
Power up to IMO Switch
150
–
μs
9.4.8 AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9-24. 5V AC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
TROB
Rising Settling Time to 0.1%, 1V Step, 100pF
Load
Power = Low
Power = High
–
–
–
–
2.5
2.5
μs
μs
TSOB
Falling Settling Time to 0.1%, 1V Step, 100pF
Load
Power = Low
Power = High
–
–
–
–
2.2
2.2
μs
μs
SRROB
Rising Slew Rate (20% to 80%), 1V Step, 100
pF Load
Power = Low
Power = High
0.65
0.65
–
–
–
–
V/μs
V/μs
SRFOB
Falling Slew Rate (80% to 20%), 1V Step, 100
pF Load
Power = Low
Power = High
0.65
0.65
–
–
–
–
V/μs
V/μs
BWOBSS Small Signal Bandwidth, 20mVpp, 3dB BW,
100 pF Load
Power = Low
Power = High
0.8
0.8
–
–
–
–
MHz
MHz
BWOBLS Large Signal Bandwidth, 1Vpp, 3dB BW, 100
pF Load
Power = Low
Power = High
300
300
–
–
–
–
kHz
kHz
Document Number: 38-12018 Rev. *O
Page 35 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
Table 9-25. 3.3V AC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
TROB
Rising Settling Time to 0.1%, 1V Step, 100 pF
Load
Power = Low
Power = High
–
–
–
–
3.8
3.8
μs
μs
TSOB
Falling Settling Time to 0.1%, 1V Step, 100 pF
Load
Power = Low
Power = High
–
–
–
–
2.6
2.6
μs
μs
SRROB
Rising Slew Rate (20% to 80%), 1V Step, 100
pF Load
Power = Low
Power = High
0.5
0.5
–
–
–
–
V/μs
V/μs
SRFOB
Falling Slew Rate (80% to 20%), 1V Step, 100
pF Load
Power = Low
Power = High
0.5
0.5
–
–
–
–
V/μs
V/μs
BWOBSS Small Signal Bandwidth, 20mVpp, 3dB BW,
100 pF Load
Power = Low
Power = High
0.7
0.7
–
–
–
–
MHz
MHz
BWOBLS Large Signal Bandwidth, 1Vpp, 3dB BW, 100
pF Load
Power = Low
Power = High
200
200
–
–
–
–
kHz
kHz
9.4.9 AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9-26. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
Description
Rise Time of SCLK
Min
1
Typ
–
Max
20
20
–
Units
ns
Notes
Fall Time of SCLK
1
–
ns
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
–
8
MHz
ms
ms
ns
TERASEB Flash Erase Time (Block)
–
10
30
–
–
TWRITE
TDSCLK
Flash Block Write Time
–
–
Data Out Delay from Falling Edge of SCLK
–
45
50
Vdd > 3.6
3.0 ≤ Vdd ≤ 3.6
TDSCLK3 Data Out Delay from Falling Edge of SCLK
–
–
ns
Document Number: 38-12018 Rev. *O
Page 36 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
9.4.10 AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9-27. AC Characteristics of the I2C SDA and SCL Pins for Vdd
Standard Mode
Fast Mode
Symbol
Description
SCL Clock Frequency
Units
Notes
Min
0
Max
100
–
Min
0
Max
FSCLI2C
400
–
kHz
THDSTAI2 Hold Time (repeated) START Condition. After
this period, the first clock pulse is generated.
4.0
0.6
μs
C
TLOWI2C LOW Period of the SCL Clock
4.7
4.0
4.7
–
–
–
1.3
0.6
0.6
–
–
–
μs
μs
μs
THIGHI2C HIGH Period of the SCL Clock
TSUSTAI2 Setup Time for a Repeated START Condition
C
THDDATI2 Data Hold Time
C
0
250
4.0
4.7
–
–
–
–
–
–
0
100[14]
0.6
–
–
μs
ns
μs
μs
ns
TSUDATI2 Data Setup Time
C
TSUSTOI2 Setup Time for STOP Condition
C
–
TBUFI2C
Bus Free Time Between a STOP and START
Condition
1.3
–
TSPI2C
Pulse Width of spikes are suppressed by the
input filter.
0
50
Figure 9-6. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
SCL
TSPI2C
TLOWI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
TSUSTOI2C
TSUSTAI2C
THDDATI2C
THDSTAI2C
THIGHI2C
S
Sr
P
S
Note
14. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t
Š 250 ns must then be met. This automatically is the case
SU;DAT
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line t + t = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
rmax
SU;DAT
Document Number: 38-12018 Rev. *O
Page 37 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
10. Packaging Dimensions
This section illustrates the package specification for the CY8C24x94 PSoC devices, along with the thermal impedance for the package
and solder reflow peak temperatures.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 10-1. 56-Pin (8x8 mm) QFN
001-12921 **
Document Number: 38-12018 Rev. *O
Page 38 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
Figure 10-2. 56-Pin QFN (8 X 8 X 0.9 MM) - Sawn
001-53450 **
Figure 10-3. 68-Pin (8x8 mm x 0.89 mm) QFN
51-85214 *C
Document Number: 38-12018 Rev. *O
Page 39 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
Important Note
■ For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
■ Pinned vias for thermal conduction are not required for the low-power PSoC device.
Figure 10-4. 68-Pin SAWN QFN (8X8 mm X 0.90 mm)
001-09618 *A
Figure 10-5. 100-Ball (6x6 mm) VFBGA
51-85209 *B
Document Number: 38-12018 Rev. *O
Page 40 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
Figure 10-6. 100-Pin (14x14 x 1.4 mm) TQFP
51-85048 *C
10.1 Thermal Impedance
Table 10-1. Thermal Impedance for the Package
[15]
Package
Typical θJA
12.93 oC/W
56 QFN[16]
68 QFN[16]
13.05 oC/W
65 oC/W
100 VFBGA
100 TQFP
51 oC/W
10.2 Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 10-2. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature[17]
240oC
Maximum Peak Temperature
56 QFN
68 QFN
260oC
260oC
260oC
240oC
240oC
100 VFBGA
Notes
15. T = T + POWER x θ
J
A
JA
16. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.
o
o
17. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 C with Sn-Pb or 245 ± 5 C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications
Document Number: 38-12018 Rev. *O
Page 41 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
11. Development Tool Selection
11.1 Software
11.3 Evaluation Tools
All evaluation tools can be purchased from the Cypress Online
Store.
11.1.1 PSoC Designer™
At the core of the PSoC development software suite is PSoC
Designer, used to generate PSoC firmware applications. PSoC
11.3.1 CY3210-MiniProg1
Designer
is
available
free
of
charge
at
The CY3210-MiniProg1 kit enables a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
http://www.cypress.com/psocdesigner and includes a free C
compiler.
11.1.2 PSoC Programmer
■ MiniProg Programming Unit
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC programmer is available free of charge at
http://www.cypress.com/psocprogrammer.
■ MiniEval Socket Programming and Evaluation Board
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■ PSoC Designer Software CD
■ Getting Started Guide
11.2 Development Kits
All development kits can be purchased from the Cypress Online
Store.
■ USB 2.0 Cable
11.3.2 CY3210-PSoCEval1
11.2.1 CY3215-DK Basic Development Kit
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread-
boarding space to meet all of your evaluation needs. The kit
includes:
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface enables users to run, halt, and single step the
processor and view the content of specific memory locations.
Advance emulation features also supported through PSoC
Designer. The kit includes:
■ Evaluation Board with LCD Module
■ MiniProg Programming Unit
■ PSoC Designer Software CD
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■ PSoC Designer Software CD
■ Getting Started Guide
■ ICE-Cube In-Circuit Emulator
■ ICE Flex-Pod for CY8C29x66 Family
■ Cat-5 Adapter
■ USB 2.0 Cable
■ Mini-Eval Programming Board
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ iMAGEcraft C Compiler (Registration Required)
■ ISSP Cable
11.3.3 CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features a devel-
opment board for the CY8C24794-24LFXI PSoC device. Special
features of the board include both USB and capacitive sensing
development and debugging support. This evaluation board also
includes an LCD module, potentiometer, LEDs, an enunciator
and plenty of bread boarding space to meet all of your evaluation
needs. The kit includes:
■ USB 2.0 Cable and Blue Cat-5 Cable
■ 2 CY8C29466-24PXI 28-PDIP Chip Samples
■ PSoCEvalUSB Board
■ LCD Module
■ MIniProg Programming Unit
■ Mini USB Cable
■ PSoC Designer and Example Projects CD
■ Getting Started Guide
■ Wire Pack
Document Number: 38-12018 Rev. *O
Page 42 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
11.4 Device Programmers
All device programmers can be purchased from the Cypress
Online Store.
11.4.2 CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
11.4.1 CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
Note: CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
■ CY3207 Programmer Unit
■ PSoC ISSP Software CD
■ Modular Programmer Base
■ 3 Programming Module Cards
■ MiniProg Programming Unit
■ PSoC Designer Software CD
■ Getting Started Guide
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ USB 2.0 Cable
■ USB 2.0 Cable
11.5 Accessories (Emulation and Programming)
Table 11-1. Emulation and Programming Accessories
Part #
Pin Package
56 QFN
56 QFN
Flex-Pod Kit[18]
CY3250-24X94QFN
CY3250-24X94QFN
Foot Kit[19]
CY3250-56QFN-FK
CY3250-56QFN-FK
Adapter[20]
CY8C24794-24LFXI
CY8C24894-24LFXI
AS-56-28
AS-28-28-02SS-6ENG-GANG
11.5.1 3rd-Party Tools
11.5.2 Build a PSoC Emulator into Your Board
Several tools have been specially designed by the following
3rd-party vendors to accompany PSoC devices during devel-
opment and production. Specific details for each of these tools
are found at http://www.cypress.com under Design Resources >
Evaluation Boards.
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, see Application Note “Debugging - Build a PSoC
Emulator
into
Your
Board
-
AN2323”
at
http://www.cypress.com/an2323.
Notes
18. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
19. Foot kit includes surface mount feet that are soldered to the target PCB.
20. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters are found at
http://www.emulation.com.
Document Number: 38-12018 Rev. *O
Page 43 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
12. Ordering Information
Table 12-1. CY8C24x94 PSoC Device’s Key Features and Ordering Information
56-Pin (8x8 mm) QFN (Sawn) CY8C24794-24LTXI
16K 1K
16K 1K
-40°C to +85°C
-40°C to +85°C
4
4
6
6
50
50
48
48
2
2
No
No
56-Pin (8x8 mm) QFN (Sawn) CY8C24794-24LTXIT
(Tape and Reel)
56-Pin (8x8 mm) QFN
56-Pin (8x8 mm) QFN
56-Pin (8x8 mm) QFN
CY8C24894-24LTXI
CY8C24894-24LTXIT
CY8C24794-24LFXI
CY8C24794-24LFXIT
16K 1K
16K 1K
16K 1K
16K 1K
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
4
4
4
4
6
6
6
6
50
50
50
50
48
48
48
48
2
2
2
2
No
No
No
No
56-Pin (8x8 mm) QFN
(Tape and Reel)
56-Pin (8x8 mm) QFN
CY8C24894-24LFXI
CY8C24894-24LFXIT
16K 1K
16K 1K
-40°C to +85°C
-40°C to +85°C
4
4
6
6
49
49
47
47
2
2
Yes
Yes
56-Pin (8x8 mm) QFN
(Tape and Reel)
68 Pin OCD (8x8 mm) QFN[21] CY8C24094-24LFXI
16K 1K
16K 1K
16K 1K
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
4
4
4
6
6
6
56
56
56
48
48
48
2
2
2
Yes
Yes
Yes
68 Pin (8x8 mm) QFN
CY8C24994-24LFXI
CY8C24994-24LFXIT
68 Pin (8x8 mm) QFN
(Tape and Reel)
68-Pin QFN (Sawn)
68-Pin QFN (Sawn)
CY8C24994-24LTXI
CY8C24994-24LTXIT
CY8C24094-24BVXI
16K 1K
16K 1K
16K 1K
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
4
4
4
6
6
6
56
56
56
48
48
48
2
2
2
Yes
Yes
Yes
100-Ball OCD (6x6 mm)
VFBGA[21]
100-Ball (6x6 mm) VFBGA
100 Pin OCD TQFP[21]
68-Pin QFN (Sawn)
CY8C24994-24BVXI
CY8C24094-24AXI
CY8C24094-24LTXI
CY8C24094-24LTXIT
16K 1K
16K 1K
16K 1K
16K 1K
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
4
4
4
4
6
6
6
6
56
56
56
56
48
48
48
48
2
2
2
2
Yes
Yes
Yes
Yes
68-Pin QFN (Sawn)
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Document Number: 38-12018 Rev. *O
Page 44 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
12.1 Ordering Code Definitions
CY 8 C 24 XXX-SP XX
Package Type:
Thermal Rating:
C = Commercial
I = Industrial
PX = PDIP Pb-Free
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
LFX/LKX/LTX = QFN Pb-Free
AX = TQFP Pb-Free
E = Extended
BVX = VFBGA Pb-Free
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Note
21. This part may be used for in-circuit debugging. It is NOT available for production.
Document Number: 38-12018 Rev. *O
Page 45 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
13. Document History Page
Document Title: CY8C24094, CY8C24794, CY8C24894 and CY8C24994 PSoC® Programmable System-on-Chip™
Document Number: 38-12018
Submission
Date
Orig. of
Change
Rev. ECN No.
Description of Change
**
133189 01.27.2004
251672 See ECN
NWJ
New silicon and new document – Advance Data Sheet.
*A
SFV
First Preliminary Data Sheet. Changed title to encompass only the CY8C24794
because the CY8C24494 and CY8C24694 are not being offered by Cypress.
*B
*C
289742 See ECN
335236 See ECN
HMT
Add standard DS items from SFV memo. Add Analog Input Mux on pinouts. 2
MACs. Change 512 bytes of SRAM to 1K. Add dimension key to package. Remove
HAPI. Update diagrams, registers and specs.
HMT
Add CY logo. Update CY copyright. Update new CY.com URLs. Re-add ISSP
programming pinout notation. Add Reflow Temp. table. Update features (MAC,
Oscillator, and voltage range), registers (INT_CLR2/MSK2, second MAC), and
specs. (Rext, IMO, analog output buffer...).
*D
344318 See ECN
HMT
Add new color and logo. Expand analog arch. diagram. Fix I/O #. Update Electrical
Specifications.
*E
*F
346774 See ECN
349566 See ECN
HMT
HMT
Add USB temperature specifications. Make data sheet Final.
Remove USB logo. Add URL to preferred dimensions for mounting MLF
packages.
*G
*H
393164 See ECN
469243 See ECN
HMT
HMT
Add new device, CY8C24894 56-pin MLF with XRES pin. Add Fimousb3v char. to
specs. Upgrade to CY Perform logo and update corporate address and copyright.
Add ISSP note to pinout tables. Update typical and recommended Storage
Temperature per industrial specs. Update Low Output Level maximum I/OL
budget. Add FLS_PR1 to Register Map Bank 1 for users to specify which Flash
bank should be used for SROM operations. Add two new devices for a 68-pin QFN
and 100-ball VFBGA under RPNs: CY8C24094 and CY8C24994. Add two
packages for 68-pin QFN. Add OCD non-production pinouts and package
diagrams. Update CY branding and QFN convention. Add new Dev. Tool section.
Update copyright and trademarks.
*I
561158
See ECN
HMT
Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add
CY8C20x34 to PSoC Device Characteristics table. Add detailed dimensions to
56-pin QFN package diagram and update revision. Secure one package
diagram/manufacturing per QFN. Update emulation pod/feet kit part numbers. Fix
pinout type-o per TestTrack.
*J
728238 See ECN
2552459 08/14/08
HMT
Add CapSense SNR requirement reference. Update figure standards. Update
Technical Training paragraphs. Add QFN package clarifications and dimensions.
Update ECN-ed Amkor dimensioned QFN package diagram revisions. Reword
SNR reference. Add new 56-pin QFN spec.
*K
AZIE/PYRS
Add footnote on AGND descriptions to avoid using P2[4] for digital signaling as it
may add noise to AGND. Remove reference to CMP_GO_EN1 in Map Bank 1
Table on Address 65; this register has no functionality on 24xxx. Add footnote on
die sales. Add description 'Optional External Clock Input’ on P1[4] to match
description of P1[4].
*L
2616550 12/05/08
OGNE/PYRS Updated Programmable Pin Configuration detail.
Changed title from PSoC® Mixed-Signal Array to PSoC® Programmable
System-on-Chip™
*M
*N
2657956 02/11/09
DPT/PYRS
BRW
Added package diagram 001-09618 and updated Ordering Information table
Added Note in the Pin Information section on page 8.
2708135 05/18/2009
Removed reference to Hi-Tech Lite Compiler in the section Development Tools
Selection on page 42.
*O
2718162 06/11/2009
DPT
Added 56-Pin QFN (Sawn) package diagram and updated ordering information
Document Number: 38-12018 Rev. *O
Page 46 of 47
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
PSoC Solutions
General
psoc.cypress.com
clocks.cypress.com
wireless.cypress.com
memory.cypress.com
image.cypress.com
psoc.cypress.com/solutions
psoc.cypress.com/low-power
psoc.cypress.com/precision-analog
psoc.cypress.com/lcd-drive
psoc.cypress.com/can
Clocks & Buffers
Wireless
Low Power/Low Voltage
Precision Analog
LCD Drive
Memories
Image Sensors
CAN 2.0b
USB
psoc.cypress.com/usb
© Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-12018 Rev. *O
Revised June 11, 2009
Page 47 of 47
PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced
herein are property of the respective corporations.
[+] Feedback
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明