CY8C24X23_技术文档

PSoC™ Mixed-Signal Array

Final Data Sheet

CY8C21123,

CY8C21223, and CY8C21323

Features

■ Powerful Harvard Architecture Processor

■ M8C Processor Speeds to 24 MHz

■ Low Power at High Speed

■ Flexible On-Chip Memory

■ Precision, Programmable Clocking

■ Internal ±2.5% 24/48 MHz Oscillator

■ Internal Oscillator for Watchdog and Sleep

■ 4K Flash Program Storage 50,000 Erase/Write

Cycles

■ 256 Bytes SRAM Data Storage

■ In-System Serial Programming (ISSP™)

■ Partial Flash Updates

■ 2.4V to 5.25V Operating Voltage

■ Programmable Pin Configurations

■ 25 mA Drive on All GPIO

■ Operating Voltages Down to 1.0V Using

On-Chip Switch Mode Pump (SMP)

■ Industrial Temperature Range: -40°C to +85°C

■ Flexible Protection Modes

■ Pull Up, Pull Down, High Z, Strong, or Open

Drain Drive Modes on All GPIO

■ EEPROM Emulation in Flash

■ Advanced Peripherals (PSoC Blocks)

■ 4 Analog Type “E” PSoC Blocks Provide:

- 2 Comparators with DAC Refs

■ Up to 8 Analog Inputs on GPIO

■ Configurable Interrupt on All GPIO

■ Complete Development Tools

■ Free Development Software

(PSoC™ Designer)

■ Additional System Resources

- Single or Dual 8-Bit 8:1 ADC

■ Full-Featured, In-Circuit Emulator and

■ I²C™ Master, Slave and Multi-Master to

■ 4 Digital PSoC Blocks Provide:

- 8- to 32-Bit Timers, Counters, and PWMs

- CRC and PRS Modules

Programmer

400 kHz

■ Full Speed Emulation

■ Watchdog and Sleep Timers

■ Complex Breakpoint Structure

■ 128 Bytes Trace Memory

- Full-Duplex UART, SPI™ Master or Slave

- Connectable to All GPIO Pins

■ User-Configurable Low Voltage Detection

■ Integrated Supervisory Circuit

■ Complex Peripherals by Combining Blocks

■ On-Chip Precision Voltage Reference

PSoC™ Functional Overview

Port 1 Port 0

PSoC

CORE

The PSoC™ family consists of many Mixed-Signal Array with

On-Chip Controller devices. These devices are designed to

replace multiple traditional MCU-based system components

with one, low cost single-chip programmable component. A

PSoC device includes configurable blocks of analog and digital

logic, as well as programmable interconnect. This architecture

allows the user to create customized peripheral configurations,

to match the requirements of each individual application. Addi-

tionally, a fast CPU, Flash program memory, SRAM data mem-

ory, and configurable IO are included in a range of convenient

pinouts.

SystemBus

Global Digital Interconnect

Global Analog Interconnect

Flash

CPUCore

SROM

SRAM

Sleep and

Watchdog

Interrupt

Controller

(M8C)

Clock Sources

(Includes IMO and ILO)

The PSoC architecture, as illustrated on the left, is comprised of

four main areas: the Core, the System Resources, the Digital

System, and the Analog System. Configurable global bus

resources allow all the device resources to be combined into a

complete custom system. Each PSoC device includes four digi-

tal blocks. Depending on the PSoC package, up to two analog

comparators and up to 16 general purpose IO (GPIO) are also

included. The GPIO provide access to the global digital and

analog interconnects.

DIGITAL SYSTEM

ANALOG SYSTEM

Analog

Ref.

Digital

PSoC Block

Array

Analog

PSoC Block

Array

The PSoC Core

The PSoC Core is a powerful engine that supports a rich

instruction set. It encompasses SRAM for data storage, an

interrupt controller, sleep and watchdog timers, and IMO (inter-

nal main oscillator) and ILO (internal low speed oscillator). The

Sw itch

Mode

Pump

POR and LVD

System Resets

Internal

Voltage

Ref.

Digital

Clocks

I2C

SYSTEM RESOURCES

February 25, 2005

1

CY8C21x23 Final Data Sheet

PSoC™ Overview

CPU core, called the M8C, is a powerful processor with speeds

up to 24 MHz. The M8C is a four MIPS 8-bit Harvard architec-

ture microprocessor.

Port1

Port0

System Resources provide additional capability, such as digital

clocks to increase the flexibility of the PSoC mixed-signal

arrays, I2C functionality for implementing an I2C master, slave,

MultiMaster, an internal voltage reference that provides an

absolute value of 1.3V to a number of PSoC subsystems, a

switch mode pump (SMP) that generates normal operating volt-

ages off a single battery cell, and various system resets sup-

ported by the M8C.

To SystemBus

DigitalClocks

FromCore

ToAnalog

System

DIGITAL SYSTEM

DigitalPSoCBlockArray

Row 0

4

The Digital System is composed of an array of digital PSoC

blocks, which can be configured into any number of digital

peripherals. The digital blocks can be connected to the GPIO

through a series of global busses that can route any signal to

any pin. Freeing designs from the constraints of a fixed periph-

eral controller.

DBB00

DBB01

DCB02 DCB03

4

8

The Analog System is composed of four analog PSoC blocks,

supporting comparators and analog-to-digital conversion up to

8 bits in precision.

GlobalDigital

Interconnect

GIE[7:0]

GIO[7:0]

GOE[7:0]

GOO[7:0]

The Digital System

Digital System Block Diagram

The Digital System is composed of 4 digital PSoC blocks. Each

block is an 8-bit resource that can be used alone or combined

with other blocks to form 8, 16, 24, and 32-bit peripherals, which

are called user module references. Digital peripheral configura-

tions include those listed below.

The Analog System

The Analog System is composed of 4 configurable blocks to

allow creation of complex analog signal flows. Analog peripher-

als are very flexible and can be customized to support specific

application requirements. Some of the more common PSoC

analog functions (most available as user modules) are listed

below.

■ PWMs (8 to 32 bit)

■ PWMs with Dead band (8 to 32 bit)

■ Counters (8 to 32 bit)

■ Timers (8 to 32 bit)

■ Analog-to-digital converters (single or dual, with 8-bit resolu-

tion)

■ UART 8 bit with selectable parity (up to 4)

■ SPI master and slave

■ Pin-to-pin comparators (1)

■ Single-ended comparators (up to 2) with absolute (1.3V) ref-

■ I2C slave, master, multi-master (1 available as a System

erence or 8-bit DAC reference

Resource)

■ 1.3V reference (as a System Resource)

■ Cyclical Redundancy Checker/Generator (8 to 32 bit)

■ IrDA (up to 4)

In most PSoC devices, analog blocks are provided in columns

of three, which includes one CT (Continuous Time) and two SC

(Switched Capacitor) blocks. The CY8C21x23 devices provide

limited functionality Type “E” analog blocks. Each column con-

tains one CT block and one SC block.

■ Pseudo Random Sequence Generators (8 to 32 bit)

The digital blocks can be connected to any GPIO through a

series of global busses that can route any signal to any pin. The

busses also allow for signal multiplexing and for performing

logic operations. This configurability frees your designs from the

constraints of a fixed peripheral controller.

The number of blocks is on the device family which is detailed

in the table titled “PSoC Device Characteristics” on page 3.

Digital blocks are provided in rows of four, where the number of

blocks varies by PSoC device family. This allows you the opti-

mum choice of system resources for your application. Family

resources are shown in the table titled “PSoC Device Charac-

teristics” on page 3.

February 25, 2005

Document No. 38-12022 Rev. *G

2

CY8C21x23 Final Data Sheet

PSoC™ Overview

PSoC Device Characteristics

Depending on your PSoC device characteristics, the digital and

analog systems can have 16, 8, or 4 digital blocks and 12, 6, or

4 analog blocks. The following table lists the resources

available for specific PSoC device groups. The PSoC device

covered by this data sheet is highlighted below.

Array Input

Configuration

PSoC Device Characteristics

ACI0[1:0]

ACI1[1:0]

PSoC Device

Group

ACOL1MUX

Array

CY8C29x66

CY8C27x43

CY8C24794

CY8C24x23A

CY8C24x23

CY8C21x34

64

44

56

24

28

4

2

1

16

8

12

48

12

28

4

2

0

4

2

12

6

2K

32K

16K

4K

256 Bytes

1K

ACE00

ASE10

ACE01

ASE11

4

6

256 Bytes

512 Bytes

4

6

4K

4^a

4

8K

4^a

CY8C21x23

16

1

4

8

0

2

256 Bytes

4K

a. Limited analog functionality.

Analog System Block Diagram, CY8C21x23

Additional System Resources

System Resources, some of which have been previously listed,

provide additional capability useful to complete systems. Addi-

tional resources include a switch mode pump, low voltage

detection, and power on reset. Brief statements describing the

merits of each system resource are presented below.

■ Digital clock dividers provide three customizable clock fre-

quencies for use in applications. The clocks can be routed to

both the digital and analog systems. Additional clocks can be

generated using digital PSoC blocks as clock dividers.

■ The I2C module provides 100 and 400 kHz communication

over two wires. Slave, master, and multi-master modes are

all supported.

■ Low Voltage Detection (LVD) interrupts can signal the appli-

cation of falling voltage levels, while the advanced POR

(Power On Reset) circuit eliminates the need for a system

supervisor.

■ An internal 1.3 voltage reference provides an absolute refer-

ence for the analog system, including ADCs and DACs.

■ An integrated switch mode pump (SMP) generates normal

operating voltages from a single 1.2V battery cell, providing a

low cost boost converter.

February 25, 2005

Document No. 38-12022 Rev. *G

3

CY8C21x23 Final Data Sheet

PSoC™ Overview

Getting Started

Development Tools

PSoC Designer is a Microsoft^®Windows-based, integrated

development environment for the Programmable System-on-

Chip (PSoC) devices. The PSoC Designer IDE and application

runs on Windows NT 4.0, Windows 2000, Windows Millennium

(Me), or Windows XP. (Reference the PSoC Designer Func-

tional Flow diagram below.)

The quickest path to understanding the PSoC silicon is by read-

ing this data sheet and using the PSoC Designer Integrated

Development Environment (IDE). This data sheet is an over-

view of the PSoC integrated circuit and presents specific pin,

register, and electrical specifications. For in-depth information,

along with detailed programming information, reference the

PSoC Mixed-Signal Array Technical Reference Manual, which

can be found on http://www.cypress.com/psoc.

PSoC Designer helps the customer to select an operating con-

figuration for the PSoC, write application code that uses the

PSoC, and debug the application. This system provides design

database management by project, an integrated debugger with

In-Circuit Emulator, in-system programming support, and the

CYASM macro assembler for the CPUs.

For up-to-date Ordering, Packaging, and Electrical Specification

information, reference the latest PSoC device data sheets on

the web at http://www.cypress.com.

Development Kits

PSoC Designer also supports a high-level C language compiler

developed specifically for the devices in the family.

Development Kits are available from the following distributors:

Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store

contains development kits, C compilers, and all accessories for

PSoC development. Go to the Cypress Online Store web site at

http://www.cypress.com, click the Online Store shopping cart

icon at the bottom of the web page, and click PSoC (Program-

mable System-on-Chip) to view a current list of available items.

Context

Sensitive

Help

Graphical Designer

PSoC^TM

Interf ace

Designer

Technical Training

Free PSoC technical training is available for beginners and is

taught by a marketing or application engineer over the phone.

PSoC training classes cover designing, debugging, advanced

analog, as well as application-specific classes covering topics

such as PSoC and the LIN bus. Go to http://www.cypress.com,

click on Design Support located on the left side of the web

page, and select Technical Training for more details.

Importable

Design

Database

PSoC

Configuration

Sheet

Device

Database

TM

PSoC

Designer

Core

Application

Database

Consultants

Manufacturing

Information

File

Engine

Project

Database

Certified PSoC Consultants offer everything from technical

assistance to completed PSoC designs. To contact or become a

PSoC Consultant go to http://www.cypress.com, click on Design

Support located on the left side of the web page, and select

CYPros Consultants.

User

Modules

Library

Technical Support

PSoC application engineers take pride in fast and accurate

response. They can be reached with a 4-hour guaranteed

response at http://www.cypress.com/support/login.cfm.

Emulation

Pod

In-Circuit

Emulator

Device

Programmer

PSoC Designer Subsystems

Application Notes

A long list of application notes will assist you in every aspect of

your design effort. To view the PSoC application notes, go to

the http://www.cypress.com web site and select Application

Notes under the Design Resources list located in the center of

the web page. Application notes are sorted by date by default.

February 25, 2005

Document No. 38-12022 Rev. *G

4

CY8C21x23 Final Data Sheet

PSoC™ Overview

Debugger

PSoC Designer Software Subsystems

The PSoC Designer Debugger subsystem provides hardware

in-circuit emulation, allowing the designer to test the program in

a physical system while providing an internal view of the PSoC

device. Debugger commands allow the designer to read the

program and read and write data memory, read and write IO

registers, read and write CPU registers, set and clear break-

points, and provide program run, halt, and step control. The

debugger also allows the designer to create a trace buffer of

registers and memory locations of interest.

Device Editor

The device editor subsystem allows the user to select different

onboard analog and digital components called user modules

using the PSoC blocks. Examples of user modules are ADCs,

DACs, Amplifiers, and Filters.

The device editor also supports easy development of multiple

configurations and dynamic reconfiguration. Dynamic reconfig-

uration allows for changing configurations at run time.

Online Help System

PSoC Designer sets up power-on initialization tables for

selected PSoC block configurations and creates source code

for an application framework. The framework contains software

to operate the selected components and, if the project uses

more than one operating configuration, contains routines to

switch between different sets of PSoC block configurations at

run time. PSoC Designer can print out a configuration sheet for

a given project configuration for use during application pro-

gramming in conjunction with the Device Data Sheet. Once the

framework is generated, the user can add application-specific

code to flesh out the framework. It’s also possible to change the

selected components and regenerate the framework.

The online help system displays online, context-sensitive help

for the user. Designed for procedural and quick reference, each

functional subsystem has its own context-sensitive help. This

system also provides tutorials and links to FAQs and an Online

Support Forum to aid the designer in getting started.

Hardware Tools

In-Circuit Emulator

A low cost, high functionality ICE (In-Circuit Emulator) is avail-

able for development support. This hardware has the capability

to program single devices.

Design Browser

The Design Browser allows users to select and import precon-

figured designs into the user’s project. Users can easily browse

a catalog of preconfigured designs to facilitate time-to-design.

Examples provided in the tools include a 300-baud modem, LIN

Bus master and slave, fan controller, and magnetic card reader.

The emulator consists of a base unit that connects to the PC by

way of the parallel or USB port. The base unit is universal and

will operate with all PSoC devices. Emulation pods for each

device family are available separately. The emulation pod takes

the place of the PSoC device in the target board and performs

full speed (24 MHz) operation

Application Editor

In the Application Editor you can edit your C language and

Assembly language source code. You can also assemble, com-

pile, link, and build.

Assembler. The macro assembler allows the assembly code

to be merged seamlessly with C code. The link libraries auto-

matically use absolute addressing or can be compiled in relative

mode, and linked with other software modules to get absolute

addressing.

C Language Compiler. A C language compiler is available

that supports PSoC family devices. Even if you have never

worked in the C language before, the product quickly allows you

to create complete C programs for the PSoC family devices.

The embedded, optimizing C compiler provides all the features

of C tailored to the PSoC architecture. It comes complete with

embedded libraries providing port and bus operations, standard

keypad and display support, and extended math functionality.

February 25, 2005

Document No. 38-12022 Rev. *G

5

CY8C21x23 Final Data Sheet

PSoC™ Overview

Designing with User Modules

The development process for the PSoC device differs from that

of a traditional fixed function microprocessor. The configurable

analog and digital hardware blocks give the PSoC architecture

a unique flexibility that pays dividends in managing specification

change during development and by lowering inventory costs.

These configurable resources, called PSoC Blocks, have the

ability to implement a wide variety of user-selectable functions.

Each block has several registers that determine its function and

connectivity to other blocks, multiplexers, busses and to the IO

pins. Iterative development cycles permit you to adapt the hard-

ware as well as the software. This substantially lowers the risk

of having to select a different part to meet the final design

requirements.

DeviceEditor

Placement

and

Parameter

-ization

User

Module

Selection

Source

Code

Generator

Generate

Application

Application Editor

Source

Code

Editor

To speed the development process, the PSoC Designer Inte-

grated Development Environment (IDE) provides a library of

pre-built, pre-tested hardware peripheral functions, called “User

Modules.” User modules make selecting and implementing

peripheral devices simple, and come in analog, digital, and

mixed signal varieties. The standard User Module library con-

tains over 50 common peripherals such as ADCs, DACs Tim-

ers, Counters, UARTs, and other not-so common peripherals

such as DTMF Generators and Bi-Quad analog filter sections.

Project

Manager

Build

Manager

Build

All

Debugger

Each user module establishes the basic register settings that

implement the selected function. It also provides parameters

that allow you to tailor its precise configuration to your particular

application. For example, a Pulse Width Modulator User Mod-

ule configures one or more digital PSoC blocks, one for each 8

bits of resolution. The user module parameters permit you to

establish the pulse width and duty cycle. User modules also

provide tested software to cut your development time. The user

module application programming interface (API) provides high-

level functions to control and respond to hardware events at run

time. The API also provides optional interrupt service routines

that you can adapt as needed.

Event &

Breakpoint

Manager

Interface

to ICE

Storage

Inspector

User Module and Source Code Development Flows

The next step is to write your main program, and any sub-rou-

tines using PSoC Designer’s Application Editor subsystem.

The Application Editor includes a Project Manager that allows

you to open the project source code files (including all gener-

ated code files) from a hierarchal view. The source code editor

provides syntax coloring and advanced edit features for both C

and assembly language. File search capabilities include simple

string searches and recursive “grep-style” patterns. A single

mouse click invokes the Build Manager. It employs a profes-

sional-strength “makefile” system to automatically analyze all

file dependencies and run the compiler and assembler as nec-

essary. Project-level options control optimization strategies

used by the compiler and linker. Syntax errors are displayed in

a console window. Double clicking the error message takes you

directly to the offending line of source code. When all is correct,

the linker builds a HEX file image suitable for programming.

The API functions are documented in user module data sheets

that are viewed directly in the PSoC Designer IDE. These data

sheets explain the internal operation of the user module and

provide performance specifications. Each data sheet describes

the use of each user module parameter and documents the set-

ting of each register controlled by the user module.

The development process starts when you open a new project

and bring up the Device Editor, a graphical user interface (GUI)

for configuring the hardware. You pick the user modules you

need for your project and map them onto the PSoC blocks with

point-and-click simplicity. Next, you build signal chains by inter-

connecting user modules to each other and the IO pins. At this

stage, you also configure the clock source connections and

enter parameter values directly or by selecting values from

drop-down menus. When you are ready to test the hardware

configuration or move on to developing code for the project, you

perform the “Generate Application” step. This causes PSoC

Designer to generate source code that automatically configures

the device to your specification and provides the high-level user

module API functions.

The last step in the development process takes place inside the

PSoC Designer’s Debugger subsystem. The Debugger down-

loads the HEX image to the In-Circuit Emulator (ICE) where it

runs at full speed. Debugger capabilities rival those of systems

costing many times more. In addition to traditional single-step,

run-to-breakpoint and watch-variable features, the Debugger

provides a large trace buffer and allows you define complex

breakpoint events that include monitoring address and data bus

values, memory locations and external signals.

February 25, 2005

Document No. 38-12022 Rev. *G

6

CY8C21x23 Final Data Sheet

PSoC™ Overview

Document Conventions

Table of Contents

For an in depth discussion and more information on your PSoC

device, obtain the PSoC Mixed-Signal Array Technical Refer-

ence Manual on http://www.cypress.com. This data sheet

encompasses and is organized into the following chapters and

sections.

Acronyms Used

The following table lists the acronyms that are used in this doc-

ument.

Acronym

AC

Description

1.

Pin Information ............................................................. 8

alternating current

1.1 Pinouts ................................................................... 8

1.1.1 8-Pin Part Pinout ...................................... 8

1.1.2 16-Pin Part Pinout ..................................... 8

1.1.3 20-Pin Part Pinout .................................... 9

1.1.4 24-Pin Part Pinout ................................. 10

ADC

API

analog-to-digital converter

application programming interface

central processing unit

continuous time

CPU

CT

DAC

DC

digital-to-analog converter

direct current

2.

3.

Register Reference ..................................................... 11

EEPROM

FSR

GPIO

IO

electrically erasable programmable read-only memory

full scale range

2.1 Register Conventions ........................................... 11

2.2 Register Mapping Tables ..................................... 11

general purpose IO

Electrical Specifications ............................................ 14

input/output

3.1 Absolute Maximum Ratings ................................ 15

3.2 Operating Temperature ....................................... 15

3.3 DC Electrical Characteristics ................................ 15

3.3.1 DC Chip-Level Specifications ................... 15

3.3.2 DC General Purpose IO Specifications .... 16

3.3.3 DC Amplifier Specifications ..................... 17

3.3.4 DC Switch Mode Pump Specifications ..... 18

3.3.5 DC POR and LVD Specifications ............. 19

3.3.6 DC Programming Specifications ............... 20

3.4 AC Electrical Characteristics ................................ 21

3.4.1 AC Chip-Level Specifications ................... 21

3.4.2 AC General Purpose IO Specifications .... 23

3.4.3 AC Amplifier Specifications ...................... 24

3.4.4 AC Digital Block Specifications ................. 24

3.4.5 AC External Clock Specifications ............. 26

3.4.6 AC Programming Specifications ............... 27

3.4.7 AC I2C Specifications ............................... 27

IPOR

LSb

imprecise power on reset

least-significant bit

LVD

low voltage detect

MSb

PC

most-significant bit

program counter

POR

PPOR

PSoC™

PWM

ROM

SC

power on reset

precision power on reset

Programmable System-on-Chip

pulse width modulator

read only memory

switched capacitor

SMP

SRAM

switch mode pump

static random access memory

Units of Measure

4.

Packaging Information ............................................... 29

A units of measure table is located in the Electrical Specifica-

tions section. Table 3-1 on page 14 lists all the abbreviations

used to measure the PSoC devices.

4.1 Packaging Dimensions ......................................... 29

4.2 Thermal Impedances .......................................... 31

4.3 Solder Reflow Peak Temperature ........................ 31

5.

6.

Ordering Information .................................................. 32

Numeric Naming

5.1 Ordering Code Definitions ................................... 32

Hexidecimal numbers are represented with all letters in upper-

case with an appended lowercase ‘h’ (for example, ‘14h’ or

‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’

prefix, the C coding convention. Binary numbers have an

appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).

Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.

Sales and Service Information .................................. 33

6.1 Revision History .................................................. 33

6.2 Copyrights and Flash Code Protection ................ 33

February 25, 2005

Document No. 38-12022 Rev. *G

7

1. Pin Information

This chapter describes, lists, and illustrates the CY8C21x23 PSoC device pins and pinout configurations.

1.1

Pinouts

The CY8C21x23 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port

pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.

1.1.1

8-Pin Part Pinout

Table 1-1. 8-Pin Part Pinout (SOIC)

Type

CY8C21123 8-Pin PSoC Device

No.

Name

Description

Digital Analog

1

2

3

4

5

6

7

8

IO

I

P0[5]

Analog column mux input.

I2C Serial Clock (SCL), ISSP-SCLK.

Ground connection.

A, I, P0[5]

A, I, P0[3]

I2C SCL, P1[1]

1

2

3

8

7

6

5

Vdd

P0[4], A, I

P0[2], A, I

P0[3]

P1[1]

Vss

SOIC

Vss

P1[0], I2CSDA

Power

4

IO

P1[0]

P0[2]

P0[4]

Vdd

I2C Serial Data (SDA), ISSP-SDATA.

Analog column mux input.

Supply voltage.

I

LEGEND: A = Analog, I = Input, and O = Output.

1.1.2

16-Pin Part Pinout

Table 1-2. 16-Pin Part Pinout (SOIC)

Type

CY8C21223 16-Pin PSoC Device

Name

Description

No.

Digital Analog

1

2

3

4

5

IO

I

P0[7] Analog column mux input.

P0[5] Analog column mux input.

P0[3] Analog column mux input.

P0[1] Analog column mux input.

A,I,P0[7]

A, I,P0[5]

A, I,P0[3]

A, I,P0[1]

SMP

Vdd

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

P0[6],A,I

P0[4],A,I

P0[2],A,I

P0[0],A,I

P1[4],EXTCLK

P1[2]

SOIC

Power

SMP

Switch Mode Pump (SMP) connection to

required external components.

Vss

I2CSCL,P1[1]

Vss

6

Vss

Ground connection.

P1[0],I2CSDA

7

IO

P1[1] I2C Serial Clock (SCL), ISSP-SCLK.

Vss Ground connection.

8

Power

9

IO

P1[0] I2C Serial Data (SDA), ISSP-SDATA.

P1[2]

10

11

12

13

14

15

16

P1[4] Optional External Clock Input (EXTCLK).

P0[0] Analog column mux input.

P0[2] Analog column mux input.

P0[4] Analog column mux input.

P0[6] Analog column mux input.

I

Power

Vdd

Supply voltage.

LEGEND A = Analog, I = Input, and O = Output.

February 25, 2005

Document No. 38-12022 Rev. *G

8

CY8C21x23 Final Data Sheet

1. Pin Information

1.1.3

20-Pin Part Pinout

Table 1-3. 20-Pin Part Pinout (SSOP)

Type

CY8C21323 20-Pin PSoC Device

Name

Description

No.

Digital Analog

1

2

IO

I

P0[7]

P0[5]

P0[3]

P0[1]

Vss

Analog column mux input.

Ground connection.

A,I,P0[7]

A, I,P0[5]

A, I,P0[3]

A, I,P0[1]

Vss

Vdd

20

19

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

9

P0[6],A,I

P0[4],A,I

P0[2],A,I

P0[0],A,I

XRES

P1[6]

P1[4],EXTCLK

P1[2]

3

4

5

Power

SSOP

I2C SCL,P1[7]

I2C SDA,P1[5]

P1[3]

I2C SCL,P1[1]

Vss

6

IO

P1[7]

P1[5]

P1[3]

P1[1]

Vss

I2C Serial Clock (SCL).

I2C Serial Data (SDA).

7

8

9

I2C Serial Clock (SCL), ISSP-SCLK.

Ground connection.

P1[0],I2C SDA

10

11

12

13

IO

P1[0]

P1[2]

P1[4]

I2C Serial Data (SDA), ISSP-SDATA.

Optional External Clock Input (EXT-

CLK).

14

15

IO

P1[6]

Input

XRES

Active high external reset with internal

pull down.

16

17

18

19

20

IO

I

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

Analog column mux input.

Supply voltage.

Power

LEGEND A = Analog, I = Input, and O = Output.

February 25, 2005

Document No. 38-12022 Rev. *G

9

CY8C21x23 Final Data Sheet

1. Pin Information

1.1.4

24-Pin Part Pinout

Table 1-4. 24-Pin Part Pinout (MLF*)

Type

CY8C21323 24-Pin PSoC Device

Name

Description

No.

Digital Analog

1

2

IO

I

P0[1]

SMP

Analog column mux input.

Power

Switch Mode Pump (SMP) connection to

required external components.

3

4

Vss

Ground connection.

IO

P1[7]

P1[5]

P1[3]

P1[1]

NC

I2C Serial Clock (SCL).

I2C Serial Data (SDA).

5

A, I, P0[1]

SMP

18

17

16

15

14

13

P0[4], A, I

P0[2], A, I

1

2

3

4

5

6

7

I2C Serial Clock (SCL), ISSP-SCLK.

No connection.

Vss

MLF

(Top View)

P0[0], A, I

NC

XR ES

I2CSCL, P1[7]

I2C SDA, P1[5]

P1[3]

8

9

Power

Vss

Ground connection.

P1[6]

10

11

12

IO

P1[0]

P1[2]

P1[4]

I2C Serial Data (SDA), ISSP-SDATA.

Optional External Clock Input (EXT-

CLK).

13

14

IO

P1[6]

Input

XRES Active high external reset with internal

pull down.

15

16

17

18

19

NC

No connection.

IO

I

P0[0]

P0[2]

P0[4]

P0[6]

Analog column mux input.

20

21

Power

Vdd

Vss

Supply voltage.

Ground connection.

22

23

24

IO

I

P0[7]

P0[5]

P0[3]

Analog column mux input.

LEGEND A = Analog, I = Input, and O = Output.

* Note The MLF package has a center pad that must be connected to the

same ground as the Vss pin.

February 25, 2005

Document No. 38-12022 Rev. *G

10

2. Register Reference

This chapter lists the registers of the CY8C21x23 PSoC device. For detailed register information, reference the

PSoC™ Mixed-Signal Array Technical Reference Manual.

2.1

Register Conventions

2.2

Register Mapping Tables

The register conventions specific to this section are listed in the

following table.

The PSoC device has a total register address space of 512

bytes. The register space is referred to as IO space and is

divided into two banks. The XOI bit in the Flag register (CPU_F)

determines which bank the user is currently in. When the XOI

bit is set the user is in Bank 1.

Convention

Description

Read register or bit(s)

R

W

L

Write register or bit(s)

Logical register or bit(s)

Clearable register or bit(s)

Access is bit specific

Note In the following register mapping tables, blank fields are

Reserved and should not be accessed.

C

#

February 25, 2005

Document No. 38-12022 Rev. *G

11

CY8C21x23 Final Data Sheet

2. Register Reference

Register Map Bank 0 Table: User Space

PRT0DR

PRT0IE

PRT0GS

PRT0DM2

PRT1DR

PRT1IE

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

ASE10CR0

ASE11CR0

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

PRT1GS

PRT1DM2

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

I2C_CFG

I2C_SCR

I2C_DR

I2C_MSCR

INT_CLR0

INT_CLR1

RW

#

RW

#

RW

INT_CLR3

INT_MSK3

RW

DBB00DR0

DBB00DR1

DBB00DR2

DBB00CR0

DBB01DR0

DBB01DR1

DBB01DR2

DBB01CR0

DCB02DR0

DCB02DR1

DCB02DR2

DCB02CR0

DCB03DR0

DCB03DR1

DCB03DR2

DCB03CR0

#

AMX_IN

RW

#

INT_MSK0

INT_MSK1

INT_VC

RW

RC

W

RW

#

PWM_CR

CMP_CR0

CMP_CR1

RES_WDT

#

W

RW

#

RW

DEC_CR0

DEC_CR1

RW

#

ADC0_CR

ADC1_CR

#

W

RW

#

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

RW

W

RW

#

RDI0RI

RDI0SYN

RDI0IS

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

RW

ACE00CR1

ACE00CR2

RW

ACE01CR1

ACE01CR2

RW

CPU_F

RL

CPU_SCR1

CPU_SCR0

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

February 25, 2005

Document No. 38-12022 Rev. *G

12

CY8C21x23 Final Data Sheet

2. Register Reference

Register Map Bank 1 Table: Configuration Space

PRT0DM0

PRT0DM1

PRT0IC0

PRT0IC1

PRT1DM0

PRT1DM1

PRT1IC0

PRT1IC1

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

ASE10CR0

ASE11CR0

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

GDI_O_IN

GDI_E_IN

GDI_O_OU

GDI_E_OU

RW

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

OSC_GO_EN DD

RW

R

OSC_CR4

OSC_CR3

OSC_CR0

OSC_CR1

OSC_CR2

VLT_CR

VLT_CMP

ADC0_TR

ADC1_TR

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

DBB00FN

DBB00IN

DBB00OU

RW

CLK_CR0

CLK_CR1

ABF_CR0

AMD_CR0

RW

DBB01FN

DBB01IN

DBB01OU

RW

CMP_GO_EN 64

65

RW

AMD_CR1

ALT_CR0

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

RW

DCB02FN

DCB02IN

DCB02OU

RW

IMO_TR

ILO_TR

BDG_TR

ECO_TR

W

RW

W

CLK_CR3

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

RW

DCB03FN

DCB03IN

DCB03OU

RW

RDI0RI

RDI0SYN

RDI0IS

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

RW

ACE00CR1

ACE00CR2

RW

ACE01CR1

ACE01CR2

RW

CPU_F

RL

FLS_PR1

RW

CPU_SCR1

CPU_SCR0

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

February 25, 2005

Document No. 38-12022 Rev. *G

13

3. Electrical Specifications

This chapter presents the DC and AC electrical specifications of the CY8C21x23 PSoC device. For the most up to date electrical

specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.

Specifications are valid for -40^oC ≤ T ≤ 85^oC and T ≤ 100^oC, except where noted.

A

J

Refer to Table 3-15 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.

5.25

4.75

5.25

4.75

SLIMO

Mode=1

SLIMO

Mode=0

3.60

3.00

2.40

SLIMO

Mode=1

SLIMO SLIMO

Mode=1 Mode=1

SLIMO

Mode=0

3.00

2.40

93kHz

12MHz

CPUFrequency

24MHz

93kHz

6MHz

IMOFrequency

3MHz

12MHz

24MHz

Figure 3-1a. Voltage versus CPU Frequency

Figure 3-1b. Voltage versus IMO Frequency

The following table lists the units of measure that are used in this chapter.

Table 3-1: Units of Measure

Symbol

Unit of Measure

Symbol

Unit of Measure

^oC

dB

degree Celsius

µW

microwatts

decibels

mA

ms

mV

nA

ns

milli-ampere

milli-second

milli-volts

fF

femto farad

hertz

Hz

KB

1024 bytes

1024 bits

kilohertz

nanoampere

nanosecond

nanovolts

Kbit

kHz

kΩ

nV

Ω

kilohm

ohm

MHz

MΩ

µA

megahertz

megaohm

microampere

microfarad

microhenry

microsecond

microvolts

pA

pF

pp

ppm

ps

picoampere

picofarad

peak-to-peak

parts per million

picosecond

µF

µH

µs

sps

σ

samples per second

sigma: one standard deviation

volts

µV

µVrms

microvolts root-mean-square

V

February 2005

Document No. 38-12022 Rev. *G

14

CY8C21x23 Final Data Sheet

3. Electrical Specifications

3.1

Absolute Maximum Ratings

Table 3-2. Absolute Maximum Ratings

Symbol

Description

Min

-55

Typ

Max

+100

Units

^oC

Notes

T_STG

Storage Temperature

–

Higher storage temperatures will reduce data

retention time.

^oC

V

T_A

Ambient Temperature with Power Applied

-40

+85

Vdd

V_IO

Supply Voltage on Vdd Relative to Vss

DC Input Voltage

-0.5

–

+6.0

Vss - 0.5

Vdd + 0.5

V

V_IOZ

I_MIO

DC Voltage Applied to Tri-state

Vss - 0.5

-25

–

Vdd + 0.5

+50

V

Maximum Current into any Port Pin

mA

ESD

LU

Electro Static Discharge Voltage

Latch-up Current

2000

–

V

Human Body Model ESD.

200

mA

3.2

Operating Temperature

Table 3-3. Operating Temperature

Symbol

T_A

Description

Min

Typ

Max

Units

Notes

^oC

Ambient Temperature

Junction Temperature

-40

–

+85

T_J

-40

+100

The temperature rise from ambient to junction is

package specific. See “Thermal Impedances”

on page 31. The user must limit the power con-

sumption to comply with this requirement.

3.3

DC Electrical Characteristics

3.3.1

DC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 3-4. DC Chip-Level Specifications

Symbol

Description

Min

2.40

Typ

Max

5.25

Units

Notes

Vdd

Supply Voltage

–

3

V

See DC POR and LVD specifications, Table 3-11

on page 19.

Conditions are Vdd = 5.0V, 25^oC, CPU = 3 MHz,

SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2

= 93.75 kHz, VC3 = 0.366 kHz.

I_DD

Supply Current, IMO = 24 MHz

Supply Current, IMO = 6 MHz

–

4

mA

Conditions are Vdd = 3.3V, 25^oC, CPU = 3 MHz,

clock doubler disabled. VC1 = 375 kHz, VC2 =

23.4 kHz, VC3 = 0.091 kHz.

I_DD3

1.2

1.1

2

Conditions are Vdd = 2.55V, 25^oC, CPU = 3

MHz, clock doubler disabled. VC1 = 375 kHz,

VC2 = 23.4 kHz, VC3 = 0.091 kHz.

I_DD27

1.5

Vdd = 2.55V, 0^oC to 40^oC.

I_SB27

I_SB

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,

and internal slow oscillator active. Mid temperature range.

–

2.6

4

µA

V

Vdd = 3.3V, -40^oC ≤ T_A≤ 85^oC.

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,

and internal slow oscillator active.

–

2.8

5

V_REF

V_REF27

AGND

Reference Voltage (Bandgap)

Analog Ground

1.28

1.16

1.30

V_REF

1.32

1.330

Trimmed for appropriate Vdd. Vdd = 3.0V to

5.25V.

V

Trimmed for appropriate Vdd. Vdd = 2.4V to

3.0V.

V_REF

V

- 0.003

+ 0.003

February 25, 2005

Document No. 38-12022 Rev. *G

15

CY8C21x23 Final Data Sheet

3. Electrical Specifications

3.3.2

DC General Purpose IO Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and

are for design guidance only.

Table 3-5. 5V and 3.3V DC GPIO Specifications

Symbol

Description

Min

Typ

5.6

Max

Units

kΩ

Notes

R_PU

Pull up Resistor

4

8

–

R_PD

V_OH

Pull down Resistor

High Output Level

5.6

–

kΩ

Vdd - 1.0

V

IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads,

4 on even port pins (for example, P0[2], P1[4]),

4 on odd port pins (for example, P0[3], P1[5])).

80 mA maximum combined IOH budget.

V_OL

Low Output Level

–

0.75

0.8

V

IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads,

4 on even port pins (for example, P0[2], P1[4]),

4 on odd port pins (for example, P0[3], P1[5])).

150 mA maximum combined IOL budget.

V_IL

Input Low Level

Input High Level

Input Hysteresis

–

V

Vdd = 3.0 to 5.25.

V_IH

V_H

2.1

–

V

60

1

–

mV

nA

pF

I_IL

Input Leakage (Absolute Value)

Capacitive Load on Pins as Input

Capacitive Load on Pins as Output

–

Gross tested to 1 µA.

Package and pin dependent. Temp = 25^oC.

C_IN

C_OUT

–

3.5

10

–

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 3.0V and

-40°C ≤ T_A≤ 85°C. Typical parameters apply to 2.7V at 25°C and are for design guidance only.

Table 3-6. 2.7V DC GPIO Specifications

Symbol

Description

Min

Typ

5.6

Max

Units

kΩ

Notes

R_PU

Pull up Resistor

4

8

–

R_PD

V_OH

Pull down Resistor

High Output Level

5.6

–

kΩ

Vdd - 0.4

V

IOH = 2.5 mA (6.25 Typ), Vdd = 2.4 to 3.0V (16

mA maximum, 50 mA Typ combined IOH bud-

get).

V_OL

Low Output Level

–

0.75

V

IOL = 10 mA, Vdd = 2.4 to 3.0V (90 mA maxi-

mum combined IOL budget).

V_IL

Input Low Level

Input High Level

Input Hysteresis

–

0.75

–

V

Vdd = 2.4 to 3.0.

V_IH

V_H

2.0

–

V

60

1

–

mV

nA

pF

I_IL

Input Leakage (Absolute Value)

Capacitive Load on Pins as Input

Capacitive Load on Pins as Output

–

Gross tested to 1 µA.

Package and pin dependent. Temp = 25^oC.

C_IN

C_OUT

–

3.5

10

–

February 25, 2005

Document No. 38-12022 Rev. *G

16

CY8C21x23 Final Data Sheet

3. Electrical Specifications

3.3.3

DC Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 3-7. 5V DC Amplifier Specifications

Symbol

V_OSOA

TCV_OSOA

I_EBOA

Description

Min

Typ

2.5

Max

Units

mV

Notes

Input Offset Voltage (absolute value)

–

15

–

µV/^oC

Average Input Offset Voltage Drift

Input Leakage Current (Port 0 Analog Pins)

Input Capacitance (Port 0 Analog Pins)

Common Mode Voltage Range

10

200

4.5

–

pA

Gross tested to 1 µA.

Package and pin dependent. Temp = 25^oC.

C_INOA

9.5

pF

V

V_CMOA

0.0

Vdd - 1

G_OLOA

I_SOA

Open Loop Gain

80

–

dB

Amplifier Supply Current

10

30

µA

Table 3-8. 3.3V DC Amplifier Specifications

Symbol

V_OSOA

TCV_OSOA

I_EBOA

Description

Min

Typ

2.5

Max

Units

Notes

Input Offset Voltage (absolute value)

–

15

mV

µV/^oC

Average Input Offset Voltage Drift

Input Leakage Current (Port 0 Analog Pins)

Input Capacitance (Port 0 Analog Pins)

Common Mode Voltage Range

Open Loop Gain

–

10

200

4.5

–

pA

Gross tested to 1 µA.

Package and pin dependent. Temp = 25^oC.

C_INOA

V_CMOA

G_OLOA

I_SOA

–

9.5

pF

V

0

Vdd - 1

–

80

–

dB

µA

Amplifier Supply Current

10

30

Table 3-9. 2.7V DC Amplifier Specifications

Symbol

V_OSOA

TCV_OSOA

I_EBOA

Description

Min

Typ

Max

Units

Notes

Input Offset Voltage (absolute value)

–

2.5

10

200

4.5

–

15

mV

µV/^oC

Average Input Offset Voltage Drift

Input Leakage Current (Port 0 Analog Pins)

Input Capacitance (Port 0 Analog Pins)

Common Mode Voltage Range

Open Loop Gain

–

pA

Gross tested to 1 µA.

Package and pin dependent. Temp = 25^oC.

C_INOA

V_CMOA

G_OLOA

I_SOA

–

9.5

pF

V

0

Vdd - 1

–

80

–

dB

µA

Amplifier Supply Current

10

30

February 25, 2005

Document No. 38-12022 Rev. *G

17

CY8C21x23 Final Data Sheet

3. Electrical Specifications

3.3.4

DC Switch Mode Pump Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 3-10. DC Switch Mode Pump (SMP) Specifications

Symbol

V_PUMP5V

Description

Min

4.75

Typ

5.0

Max

5.25

Units

Notes

Configuration of footnote.^aAverage, neglecting

ripple. SMP trip voltage is set to 5.0V.

5V Output Voltage from Pump

V

Configuration of footnote.^aAverage, neglecting

ripple. SMP trip voltage is set to 3.25V.

V_PUMP3V

V_PUMP2V

I_PUMP

3.3V Output Voltage from Pump

2.6V Output Voltage from Pump

Available Output Current

3.00

2.45

3.25

2.55

3.60

2.80

Configuration of footnote.^aAverage, neglecting

ripple. SMP trip voltage is set to 2.55V.

Configuration of footnote.^a

V

_BAT= 1.8V, V_PUMP= 5.0V

5

8

–

mA

SMP trip voltage is set to 5.0V.

SMP trip voltage is set to 3.25V.

SMP trip voltage is set to 2.55V.

V_BAT= 1.5V, V_PUMP= 3.25V

V_BAT= 1.3V, V_PUMP= 2.55V

Input Voltage Range from Battery

Configuration of footnote.^aSMP trip voltage is

set to 5.0V.

V_BAT5V

1.8

1.0

1.2

–

5

5.0

3.3

2.8

–

V

Configuration of footnote.^aSMP trip voltage is

set to 3.25V.

V_BAT3V

Input Voltage Range from Battery

V

Configuration of footnote.^aSMP trip voltage is

set to 2.55V.

V_BAT2V

Input Voltage Range from Battery

V

Configuration of footnote.^a0^oC ≤ T_A≤ 100.

V_BATSTART

∆V_{PUMP_Line}

Minimum Input Voltage from Battery to Start Pump

Line Regulation (over Vi range)

V

1.25V at T_A= -40^oC.

Configuration of footnote.^aV_Ois the “Vdd Value

for PUMP Trip” specified by the VM[2:0] setting

in the DC POR and LVD Specification, Table 3-

11 on page 19.

–

%V_O

Configuration of footnote.^aV_Ois the “Vdd Value

for PUMP Trip” specified by the VM[2:0] setting

in the DC POR and LVD Specification, Table 3-

11 on page 19.

∆V_{PUMP_Load}

Load Regulation

–

5

–

%V_O

Configuration of footnote.^aLoad is 5 mA.

∆V_{PUMP_Ripple}Output Voltage Ripple (depends on cap/load)

–

100

50

–

mVpp

%

Configuration of footnote.^aLoad is 5 mA. SMP

trip voltage is set to 3.25V.

E₃

Efficiency

35

E₂

Efficiency

35

80

–

%

For I load = 1mA, V_PUMP= 2.55V, V_BAT= 1.3V,

10 uH inductor, 1 uF capacitor, and Schottky

diode.

F_PUMP

Switching Frequency

Switching Duty Cycle

–

1.3

50

–

MHz

%

DC_PUMP

a. L = 2 µH inductor, C = 10 µF capacitor, D = Schottky diode. See Figure 3-2.

1

D1

Vdd

V_PUMP

L₁

C1

SMP

V ss

+

V_BAT

PSoC^TM

Battery

Figure 3-2. Basic Switch Mode Pump Circuit

February 25, 2005

Document No. 38-12022 Rev. *G

18

CY8C21x23 Final Data Sheet

3. Electrical Specifications

3.3.5

DC POR and LVD Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 3-11. DC POR and LVD Specifications

Symbol

Description

Vdd Value for PPOR Trip

Min

Typ

Max

Units

Notes

Vdd must be greater than or equal to 2.5V

during startup, reset from the XRES pin, or

reset from Watchdog.

V_PPOR0

V_PPOR1

V_PPOR2

PORLEV[1:0] = 00b

PORLEV[1:0] = 01b

PORLEV[1:0] = 10b

2.36

2.40

V

–

2.82

4.55

2.95

4.70

Vdd Value for LVD Trip

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

2.51^a

V

V_LVD0

V_LVD1

V_LVD2

V_LVD3

V_LVD4

V_LVD5

V_LVD6

V_LVD7

2.40

2.85

2.95

3.06

4.37

4.50

4.62

4.71

2.45

2.92

3.02

3.13

4.48

4.64

4.73

4.81

2.99^b

3.09

3.20

4.55

4.75

4.83

4.95

Vdd Value for PUMP Trip

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

2.62^c

3.09

3.16

V_PUMP0

V_PUMP1

V_PUMP2

V_PUMP3

V_PUMP4

V_PUMP5

V_PUMP6

V_PUMP7

2.45

2.96

3.03

3.18

4.54

4.62

4.71

4.89

2.55

3.02

3.10

3.25

4.64

4.73

4.82

5.00

V

3.32^d

4.74

4.83

4.92

5.12

a. Always greater than 50 mV above V

(PORLEV = 00) for falling supply.

PPOR

b. Always greater than 50 mV above V

(PORLEV = 01) for falling supply.

PPOR

c. Always greater than 50 mV above V_LVD0

d. Always greater than 50 mV above V_LVD3

.

February 25, 2005

Document No. 38-12022 Rev. *G

19

CY8C21x23 Final Data Sheet

3. Electrical Specifications

3.3.6

DC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 3-12. DC Programming Specifications

Symbol

Description

Min

2.70

Typ

Max

Units

Notes

Vdd_IWRITE

Supply Voltage for Flash Write Operations

–

5

–

V

I_DDP

V_ILP

V_IHP

I_ILP

Supply Current During Programming or Verify

Input Low Voltage During Programming or Verify

Input High Voltage During Programming or Verify

–

25

0.8

–

mA

V

–

2.2

–

V

Input Current when Applying Vilp to P1[0] or P1[1] During

Programming or Verify

0.2

mA

Driving internal pull-down resistor.

I_IHP

Input Current when Applying Vihp to P1[0] or P1[1] During

Programming or Verify

–

1.5

mA

V_OLV

V_OHV

Output Low Voltage During Programming or Verify

Output High Voltage During Programming or Verify

–

Vss + 0.75

Vdd

V

Vdd - 1.0

Flash_ENPB

Flash_ENT

Flash_DR

Flash Endurance (per block)

50,000

–

Erase/write cycles per block.

Erase/write cycles.⁰

Flash Endurance (total)^a

Flash Data Retention

1,800,000⁰

10

–

0

–

Years

a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of

25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (and so forth to limit the total number of cycles to 36x50,000 and that no single block ever

sees more than 50,000 cycles).

For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to

the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

February 25, 2005

Document No. 38-12022 Rev. *G

20

CY8C21x23 Final Data Sheet

3. Electrical Specifications

3.4

AC Electrical Characteristics

3.4.1

AC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only..

Table 3-13. 5V and 3.3V AC Chip-Level Specifications

Symbol

F_IMO24

Description

Min

23.4

Typ

Max

24.6^a,b,c

Units

MHz

Notes

Internal Main Oscillator Frequency for 24 MHz

24

6

Trimmed for 5V or 3.3V operation using

factory trim values. See Figure 3-1b on

page 14. SLIMO mode = 0.

6.35^a,b,c

F_IMO6

Internal Main Oscillator Frequency for 6 MHz

5.75

MHz

Trimmed for 3.3V operation using factory

trim values. See Figure 3-1b on page 14.

SLIMO mode = 1.

24.6^a,b

12.3^b,c

F_CPU1

F_CPU2

F_BLK5

CPU Frequency (5V Nominal)

0.93

0

24

12

48

MHz

24 MHz only for SLIMO mode = 0.

CPU Frequency (3.3V Nominal)

Digital PSoC Block Frequency⁰(5V Nominal)

49.2^a,b,d

Refer to the AC Digital Block Specifica-

tions below.

24.6^b,d

64

F_BLK33

F_32K1

Digital PSoC Block Frequency (3.3V Nominal)

Internal Low Speed Oscillator Frequency

0

24

32

MHz

kHz

15

Jitter32k

T_XRST

32 kHz RMS Period Jitter

–

100

1400

–

200

ns

32 kHz Peak-to-Peak Period Jitter

External Reset Pulse Width

–

ns

10

40

–

µs

DC24M

Step24M

Fout48M

Jitter24M1

F_MAX

24 MHz Duty Cycle

50

60

%

24 MHz Trim Step Size

50

–

kHz

MHz

ps

49.2^a,c

48 MHz Output Frequency

46.8

–

48.0

300

–

Trimmed. Utilizing factory trim values.

24 MHz Peak-to-Peak Period Jitter (IMO)

Maximum frequency of signal on row input or row output.

Supply Ramp Time

–

12.3

–

MHz

µs

T_RAMP

0

–

a. 4.75V < Vdd < 5.25V.

b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.

c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.

d. See the individual user module data sheets for information on maximum frequencies for user modules.

Table 3-14. 2.7V AC Chip-Level Specifications

Symbol

F_IMO12

Description

Min

11.5

Typ

12⁰

Max

12.7^a,b,c

Units

MHz

Notes

Internal Main Oscillator Frequency for 12 MHz

Trimmed for 2.7V operation using factory

trim values. See Figure 3-1b on page 14.

SLIMO mode = 1.

6.35^a,b,c

F_IMO6

Internal Main Oscillator Frequency for 6 MHz

5.5

6

MHz

Trimmed for 2.7V operation using factory

trim values. See Figure 3-1b on page 14.

SLIMO mode = 1.

3.15^a,b

F_CPU1

CPU Frequency (2.7V Nominal)

0.093

0

3

MHz

24 MHz only for SLIMO mode = 0.

12.5^a,b,c

F_BLK27

Digital PSoC Block Frequency (2.7V Nominal)

12

Refer to the AC Digital Block Specifica-

tions below.

F_32K1

Internal Low Speed Oscillator Frequency

32 kHz RMS Period Jitter

8

32

150

1400

–

96

200

–

kHz

ns

Jitter32k

T_XRST

F_MAX

–

32 kHz Peak-to-Peak Period Jitter

External Reset Pulse Width

–

ns

10

–

µs

Maximum frequency of signal on row input or row output.

Supply Ramp Time

–

12.3

–

MHz

µs

T_RAMP

0

–

a. 2.4V < Vdd < 3.0V.

b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.

c. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum frequency for user modules.

February 25, 2005

Document No. 38-12022 Rev. *G

21

CY8C21x23 Final Data Sheet

3. Electrical Specifications

Jitter24M1

F_24M

Figure 3-3. 24 MHz Period Jitter (IMO) Timing Diagram

Jitter32k

F_32K1

Figure 3-4. 32 kHz Period Jitter (ILO) Timing Diagram

February 25, 2005

Document No. 38-12022 Rev. *G

22

CY8C21x23 Final Data Sheet

3. Electrical Specifications

3.4.2

AC General Purpose IO Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 3-15. 5V and 3.3V AC GPIO Specifications

Symbol

F_GPIO

Description

GPIO Operating Frequency

Min

Typ

Max

Units

MHz

Notes

Normal Strong Mode

0

–

12

TRiseF

TFallF

TRiseS

TFallS

Rise Time, Normal Strong Mode, Cload = 50 pF

Fall Time, Normal Strong Mode, Cload = 50 pF

Rise Time, Slow Strong Mode, Cload = 50 pF

Fall Time, Slow Strong Mode, Cload = 50 pF

3

–

18

–

ns

Vdd = 4.5 to 5.25V, 10% - 90%

Vdd = 3 to 5.25V, 10% - 90%

2

–

10

27

22

–

Table 3-16. 2.7V AC GPIO Specifications

Symbol

F_GPIO

Description

GPIO Operating Frequency

Min

Typ

Max

Units

Notes

0

–

3

MHz

Normal Strong Mode

TRiseF

TFallF

TRiseS

TFallS

Rise Time, Normal Strong Mode, Cload = 50 pF

Fall Time, Normal Strong Mode, Cload = 50 pF

Rise Time, Slow Strong Mode, Cload = 50 pF

Fall Time, Slow Strong Mode, Cload = 50 pF

6

–

50

ns

Vdd = 2.4 to 3.0V, 10% - 90%

6

–

18

40

120

90%

10%

GPIO

TRiseF

TRi seS

TFallF

TFallS

Figure 3-5. GPIO Timing Diagram

February 25, 2005

Document No. 38-12022 Rev. *G

23

CY8C21x23 Final Data Sheet

3. Electrical Specifications

3.4.3

AC Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.

Table 3-17. 5V and 3.3V AC Amplifier Specifications

Symbol

T_COMP1

Description

Min

Typ

Max

100

Units

ns

Notes

Comparator Mode Response Time, 50 mVpp Signal Cen-

tered on Ref

T_COMP2

Comparator Mode Response Time, 2.5V Input, 0.5V Over-

drive

300

ns

Table 3-18. 2.7V AC Amplifier Specifications

Symbol

T_COMP1

Description

Min

Max

Units

Notes

Comparator Mode Response Time, 50 mVpp Signal Cen-

tered on Ref

600

ns

T_COMP2

Comparator Mode Response Time, 1.5V Input, 0.5V Over-

drive

300

ns

3.4.4

AC Digital Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 3-19. 5V and 3.3V AC Digital Block Specifications

Function

Description

Maximum Block Clocking Frequency (> 4.75V)

Maximum Block Clocking Frequency (< 4.75V)

Capture Pulse Width

Min

Typ

Max

49.2

Units

MHz

Notes

4.75V < Vdd < 5.25V.

All

Functions

Timer

24.6

–

MHz

ns

3.0V < Vdd < 4.75V.

50^a

–

Maximum Frequency, No Capture

Maximum Frequency, With or Without Capture

Enable Pulse Width

–

49.2

24.6

–

MHz

ns

4.75V < Vdd < 5.25V.

–

Counter

50

–

Maximum Frequency, No Enable Input

Maximum Frequency, Enable Input

49.2

24.6

MHz

4.75V < Vdd < 5.25V.

–

Dead Band Kill Pulse Width:

Asynchronous Restart Mode

20

50

–

ns

Synchronous Restart Mode

Disable Mode

–

ns

–

ns

Maximum Frequency

49.2

MHz

4.75V < Vdd < 5.25V.

CRCPRS

Maximum Input Clock Frequency

–

(PRS Mode)

CRCPRS

(CRC Mode)

Maximum Input Clock Frequency

–

24.6

8.2

MHz

SPIM

SPIS

Maximum data rate at 4.1 MHz due to 2 x over

clocking.

Maximum Input Clock Frequency

–

4.1

–

MHz

ns

Width of SS_ Negated Between Transmissions

50

–

Transmitter Maximum Input Clock Frequency

24.6

MHz

Maximum data rate at 3.08 MHz due to 8 x over

clocking.

Receiver Maximum Input Clock Frequency

–

24.6

MHz

Maximum data rate at 3.08 MHz due to 8 x over

clocking.

a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).

February 25, 2005

Document No. 38-12022 Rev. *G

24

CY8C21x23 Final Data Sheet

3. Electrical Specifications

Table 3-20. 2.7V AC Digital Block Specifications

Function

Description

Min

Typ

Max

12.7

Units

MHz

Notes

All

Maximum Block Clocking Frequency

2.4V < Vdd < 3.0V.

Functions

Timer

100^a

Capture Pulse Width

–

ns

Maximum Frequency, With or Without Capture

Enable Pulse Width

–

12.7

–

MHz

ns

Counter

100

–

Maximum Frequency, No Enable Input

Maximum Frequency, Enable Input

12.7

MHz

–

Dead Band Kill Pulse Width:

Asynchronous Restart Mode

20

100

–

ns

Synchronous Restart Mode

Disable Mode

–

ns

–

ns

Maximum Frequency

12.7

MHz

CRCPRS

Maximum Input Clock Frequency

–

(PRS Mode)

CRCPRS

(CRC Mode)

Maximum Input Clock Frequency

–

12.7

6.35

MHz

SPIM

SPIS

Maximum data rate at 3.17 MHz due to 2 x over

clocking.

Maximum Input Clock Frequency

–

4.1

–

MHz

ns

Width of SS_ Negated Between Transmissions

100

–

Transmitter Maximum Input Clock Frequency

12.7

MHz

Maximum data rate at 1.59 MHz due to 8 x over

clocking.

Receiver Maximum Input Clock Frequency

–

12.7

MHz

Maximum data rate at 1.59 MHz due to 8 x over

clocking.

a. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).

February 25, 2005

Document No. 38-12022 Rev. *G

25

CY8C21x23 Final Data Sheet

3. Electrical Specifications

3.4.5

AC External Clock Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C

and are for design guidance only.

Table 3-21. 5V AC External Clock Specifications

Symbol

Description

Min

0.093

Typ

Max

24.6

Units

MHz

Notes

F_OSCEXT

Frequency

High Period

Low Period

–

20.6

150

5300

ns

µs

–

Power Up IMO to Switch

Table 3-22. 3.3V AC External Clock Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

F_OSCEXT

Frequency with CPU Clock divide by 1

0.093

–

MHz

Maximum CPU frequency is 12 MHz at 3.3V.

With the CPU clock divider set to 1, the external

clock must adhere to the maximum frequency

and duty cycle requirements.

12.3

F_OSCEXT

Frequency with CPU Clock divide by 2 or greater

0.186

24.6

MHz

If the frequency of the external clock is greater

than 12 MHz, the CPU clock divider must be set

to 2 or greater. In this case, the CPU clock

divider will ensure that the fifty percent duty

cycle requirement is met.

–

High Period with CPU Clock divide by 1

Low Period with CPU Clock divide by 1

Power Up IMO to Switch

41.7

150

–

5300

ns

µs

–

Table 3-23. 2.7V AC External Clock Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

6.06⁰

F_OSCEXT

Frequency with CPU Clock divide by 1

0.093

–

MHz

Maximum CPU frequency is 3 MHz at 2.7V.

With the CPU clock divider set to 1, the external

clock must adhere to the maximum frequency

and duty cycle requirements.

F_OSCEXT

Frequency with CPU Clock divide by 2 or greater

0.186

12.12

MHz

If the frequency of the external clock is greater

than 3 MHz, the CPU clock divider must be set

to 2 or greater. In this case, the CPU clock

divider will ensure that the fifty percent duty

cycle requirement is met.

–

High Period with CPU Clock divide by 1

Low Period with CPU Clock divide by 1

Power Up IMO to Switch

83.4

150

–

5300

ns

µs

–

February 25, 2005

Document No. 38-12022 Rev. *G

26

CY8C21x23 Final Data Sheet

3. Electrical Specifications

3.4.6

AC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C

and are for design guidance only.

Table 3-24. AC Programming Specifications

Symbol

Description

Min

Typ

Max

Units

ns

Notes

T_RSCLK

Rise Time of SCLK

Fall Time of SCLK

1

–

20

–

T_FSCLK

T_SSCLK

T_HSCLK

F_SCLK

1

–

ns

Data Set up Time to Falling Edge of SCLK

Data Hold Time from Falling Edge of SCLK

Frequency of SCLK

40

0

–

ns

–

ns

–

8

MHz

ms

ns

T_ERASEBFlash Erase Time (Block)

T_WRITEFlash Block Write Time

–

15

30

–

T_DSCLK3Data Out Delay from Falling Edge of SCLK

T_DSCLK2Data Out Delay from Falling Edge of SCLK

–

50

70

3.0 ≤ Vdd ≤ 3.6

2.4 ≤ Vdd ≤ 3.0

–

ns

2

3.4.7

AC I C Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 3-25. AC Characteristics of the I²C SDA and SCL Pins for Vcc ≥ 3.0V

Standard Mode

Min Max

100

Fast Mode

Min Max

Symbol

Description

Units

kHz

Notes

F_SCLI2C

SCL Clock Frequency

0

400

–

T_HDSTAI2CHold Time (repeated) START Condition. After this period, 4.0

the first clock pulse is generated.

–

0.6

µs

T_LOWI2C

T_HIGHI2C

LOW Period of the SCL Clock

HIGH Period of the SCL Clock

4.7

4.0

4.7

0

–

1.3

0.6

0

–

µs

T_SUSTAI2CSet-up Time for a Repeated START Condition

T_HDDATI2CData Hold Time

0

Data Set-up Time⁰

T_SUDATI2C

250⁰

4.0

–

100^a

0.6

–

ns⁰

T_SUSTOI2CSet-up Time for STOP Condition

–

µs

T_BUFI2C

T_SPI2C

Bus Free Time Between a STOP and START Condition

Pulse Width of spikes are suppressed by the input filter.

4.7

–

1.3

0

–

µs

50

ns

a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t

≥ 250 ns must then be met. This will automatically be the case if

SU;DAT

the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line

+ t = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

t

rmax SU;DAT

February 25, 2005

Document No. 38-12022 Rev. *G

27

CY8C21x23 Final Data Sheet

3. Electrical Specifications

Table 3-26. 2.7V AC Characteristics of the I²C SDA and SCL Pins (Fast Mode not Supported)

Standard Mode

Min Max

100

Fast Mode

Min Max

Symbol

Description

Units

kHz

Notes

F_SCLI2C

SCL Clock Frequency

0

–

T_HDSTAI2CHold Time (repeated) START Condition. After this period, 4.0

the first clock pulse is generated.

–

µs

T_LOWI2C

T_HIGHI2C

LOW Period of the SCL Clock

HIGH Period of the SCL Clock

4.7

4.0

4.7

0

–

µs

ns

µs

ns

T_SUSTAI2CSet-up Time for a Repeated START Condition

T_HDDATI2CData Hold Time

T_SUDATI2CData Set-up Time

250

4.0

4.7

–

T_SUSTOI2CSet-up Time for STOP Condition

T_BUFI2C

T_SPI2C

Bus Free Time Between a STOP and START Condition

Pulse Width of spikes are suppressed by the input filter.

SDA

T_SPI2C

T_LOWI2C

T_SUDATI2C

T_HDSTAI2C

T_BUFI2C

SCL

Figure 3-6. Definition for Timing for Fast/Standard Mode on the I²C Bus

February 25, 2005

Document No. 38-12022 Rev. *G

28

4. Packaging Information

This chapter illustrates the packaging specifications for the CY8C21x23 PSoC device, along with the thermal impedances for each

package and minimum solder reflow peak temperature.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of

the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at

http://www.cypress.com/support/link.cfm?mr=poddim.

4.1

Packaging Dimensions

PIN 1 ID

4

1

1. DIMENSIONS IN INCHES[MM] MIN.

MAX.

2. PIN 1 ID IS OPTIONAL,

ROUND ON SINGLE LEADFRAME

RECTANGULAR ON MATRIX LEADFRAME

0.150[3.810]

0.157[3.987]

3. REFERENCE JEDEC MS-012

4. PACKAGE WEIGHT 0.07gms

0.230[5.842]

0.244[6.197]

PART #

S08.15 STANDARD PKG.

SZ08.15 LEAD FREE PKG.

5

8

0.189[4.800]

0.196[4.978]

0.010[0.254]

0.016[0.406]

X 45°

SEATING PLANE

0.061[1.549]

0.068[1.727]

0.004[0.102]

0.050[1.270]

BSC

0.0075[0.190]

0.0098[0.249]

0.004[0.102]

0.0098[0.249]

0°~8°

0.016[0.406]

0.035[0.889]

0.0138[0.350]

0.0192[0.487]

51-85066 *C

Figure 4-1. 8-Lead (150-Mil) SOIC

February 25, 2005

Document No. 38-12022 Rev. *G

29

CY8C21x23 Final Data Sheet

4. Packaging Information

51-85022 *B

Figure 4-2. 16-Lead (150-Mil) SOIC

51-85077 *C

Figure 4-3. 20-Lead (210-MIL) SSOP

Document No. 38-12022 Rev. *G

February 25, 2005

30

CY8C21x23 Final Data Sheet

4. Packaging Information

51-85203 **

Figure 4-4. 24-Lead (4x4) MLF

4.2

Thermal Impedances

Table 4-1. Thermal Impedances per Package

Package

Typical θ_JA

186 ^oC/W

*

8 SOIC

125 ^oC/W

117 ^oC/W

40 ^oC/W

16 SOIC

20 SSOP

24 MLF

* T_J= T_A+ POWER x θ_JA

4.3

Solder Reflow Peak Temperature

Following is the minimum solder reflow peak temperature to achieve good solderability.

Table 4-2. Solder Reflow Peak Temperature

Package

Minimum Peak Temperature*

Maximum Peak Temperature

240^oC

260^oC

8 SOIC

16 SOIC

20 SSOP

24 MLF

*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220+/-5^oC

with Sn-Pb or 245+/-5^oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.

February 25, 2005

Document No. 38-12022 Rev. *G

31

5. Ordering Information

The following table lists the CY8C21x23 PSoC device’s key package features and ordering codes.

CY8C21x23 PSoC Device Key Features and Ordering Information

8 Pin (150-Mil) SOIC

CY8C21123-24SXI

CY8C21123-24SXIT

CY8C21223-24SXI

CY8C21223-24SXIT

CY8C21323-24PVXI

CY8C21323-24PVXIT

CY8C21323-24LFXI

CY8C21323-24LFXIT

4K

256

No

-40°C to +85°C

4

6

4

8

0

No

8 Pin (150-Mil) SOIC

(Tape and Reel)

6

16 Pin (150-Mil) SOIC

Yes -40°C to +85°C

12

16

No

16 Pin (150-Mil) SOIC

(Tape and Reel)

No

20 Pin (210-Mil) SSOP

No

-40°C to +85°C

Yes

20 Pin (210-Mil) SSOP

(Tape and Reel)

24 Pin (4x4) MLF

Yes -40°C to +85°C

24 Pin (4x4) MLF

(Tape and Reel)

5.1

Ordering Code Definitions

CY 8 C 21 xxx-24xx

Package Type:

PX = PDIP Pb-Free

SX = SOIC Pb-Free

Thermal Rating:

C = Commercial

I = Industrial

PVX = SSOP Pb-Free

LFX = MLF Pb-Free

AX = TQFP Pb-Free

E = Extended

Speed: 24 MHz

Part Number

Family Code

Technology Code: C = CMOS

Marketing Code: 8 = Cypress MicroSystems

Company ID: CY = Cypress

February 25, 2005

Document No. 38-12022 Rev. *G

32

6. Sales and Service Information

To obtain information about Cypress Semiconductor or PSoC sales and technical support, reference the following information.

Cypress Semiconductor

2700 162nd Street SW, Building D

Lynnwood, WA 98037

Phone: 800.669.0557

Facsimile: 425.787.4641

Web Sites:

Company Information – http://www.cypress.com

Sales – http://www.cypress.com/aboutus/sales_locations.cfm

Technical Support – http://www.cypress.com/support/login.cfm

6.1

Revision History

Document Title:

Document Number: 38-12022

Revision ECN # Issue Date Origin of Change

**

CY8C21x23 PSoC Mixed-Signal Array Final Data Sheet

Description of Change

New silicon and document (Revision **).

133248 01/28/2004 NWJ

208900 03/05/2004 NWJ

*A

*B

*C

Add new part, new package and update all ordering codes to Pb-free.

Expand and prepare Preliminary version.

03/18/2004 NWJ

212081

227321

05/19/2004 CMS Team

Update specs., data, format.

Updated Overview and Electrical Spec. chapters, along with 24-pin pinout. Added

CMP_GO_EN register (1,64h) to mapping table.

*D

See ECN

SFV

235973

290991

Update data sheet standards per SFV memo. Fix device table. Add part numbers to

pinouts and fine tune. Change 20-pin SSOP to CY8C21323. Add Reflow Temp. table.

Update diagrams and specs.

*E

*F

*G

HMT

301636 See ECN

324073 See ECN

DC Chip-Level Specification changes. Update links to new CY.com Portal.

Obtained clearer 16 SOIC package. Update Thermal Impedances and Solder Reflow

tables. Re-add pinout ISSP notation. Fix ADC type-o. Fix TMP register names. Update

Electrical Specifications. Add CY logo. Update CY copyright. Make data sheet Final.

Distribution: External/Public

Posting: None

6.2

Copyrights and Flash Code Protection

Copyrights

Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations.

The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other than circuitry

embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products

for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of

Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress

Semiconductor against all charges. Cypress Semiconductor products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety

applications, unless pursuant to an express written agreement with Cypress Semiconductor.

Flash Code Protection

Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices.

Cypress Semiconductor products meet the specifications contained in their particular data sheets. Cypress Semiconductor believes that its PSoC family of products is one

of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach

the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor nor any other semicon-

ductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."

Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress

Semiconductor are committed to continuously improving the code protection features of our products.

February 25, 2005

33


型号：	CY8C24X23
厂家：	CYPRESS
描述：	PSoC⑩ Mixed-Signal Array 的PSoC ™混合信号阵列
文件：	总33页 (文件大小：326K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C24X23 [CYPRESS]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E