CY8C25122-24PXI [CYPRESS]
Mixed-Signal Array with On-board Controller; 与板载控制器的混合信号阵列
| 型号： | CY8C25122-24PXI |
| 厂家： | 
CYPRESS |
| 描述： | Mixed-Signal Array with On-board Controller |
| 文件： | 总151页 (文件大小：1160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Configurable
Mixed-Signal Array
with On-board Controller
CY8C25122, CY8C26233, CY8C26443, CY8C26643
Device Data Sheet for Silicon Revision D
Programmable System-on-Chip (PSoC™)
May 17, 2005
Document #: 38-12010 CY Rev. *C
1
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Getting Started in the PSoC World!
The award winning PSoC Designer software and PSoC silicon are an integrated unit. The quickest path to understand-
ing the PSoC silicon is through the PSoC Designer software GUI. This data sheet is useful for understanding the
details of the PSOC integrated circuit, but is not a good starting point for a new PSoC developer seeking to get a gen-
eral overview of this new technology.
PSoC developers are NOT required to build their own ADCs, DACs, and other peripherals. Embedded in the PSoC
Designer software are the individual data sheets, performance graphs, and PSoC User Modules (graphically selected
code packets) for the peripherals, such as the incremental ADCs, DACs, LCD controllers, op amps, low-pass filters,
etc. With simple GUI-based selection, placement, and connection, the basic architecture of a design may be
developed within PSoC Designer software without ever writing a single line of code.
Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online
Store also contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress
Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web
page, and click PSoC (Programmable System-on-Chip) to view a current list of available items.
Free PSoC technical training is available for beginners and is taught by a marketing or application engineer over the
phone. PSoC training classes cover designing, debugging, advanced analog, as well as application-specific classes
covering topics such as PSoC and the LIN bus. Go to http://www.cypress.com, click on Design Support located on the
left side of the web page, and select Technical Training for more details.
Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or
become a PSoC Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web
page, and select CYPros Consultants.
PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.
Cypress Semiconductor
2700 162nd Street SW, Building D
Lynnwood, WA 98037
Phone: 425.787.4400
Fax: 425.787.4641
Application Support Hotline: 425.787.4814
© Cypress Semiconductor Corporation. 2000-2005. All rights reserved. PSoC™, PSoC Designer™, and Programmable System-on-Chip™ are PSoC-
related trademarks of Cypress Semiconductor Corporation. All other trademarks or registered trademarks referenced herein are property of the respec-
tive corporations.
The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other
than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor
does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result
in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes
all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress Semiconductor products are not warranted nor
intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with
Cypress Semiconductor.
Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices.
Cypress Semiconductor products meet the specifications contained in their particular Cypress Semiconductor Data Sheets. Cypress Semiconductor
believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be
methods, unknown to Cypress Semiconductor, that can breach the code protection features. Any of these methods, to our knowledge, would be dishon-
est and possibly illegal. Neither Cypress Semiconductor nor any other semiconductor manufacturer can guarantee the security of their code. Code pro-
tection does not mean that we are guaranteeing the product as "unbreakable." Cypress Semiconductor is willing to work with the customer who is
concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress Semiconductor are committed to continuously improv-
ing the code protection features of our products.
2
Document #: 38-12010 CY Rev. *C
May 17, 2005
The PSoC™ CY8C25122/CY8C26233/CY8C26443/CY8C26643 family of programmable sys-
tem-on-chip devices replace multiple MCU-based system components with one single-chip, con-
figurable device. A PSoC device includes configurable analog and digital peripheral blocks, a fast
CPU, Flash program memory, and SRAM data memory in a range of convenient pin-outs and
memory sizes. The driving force behind this innovative programmable system-on-chip comes
from user configurability of the analog and digital arrays: the PSoC blocks.
Programmable System-on-Chip (PSoC™) Blocks
Partial Flash updates
Flexible protection modes
On-chip, user configurable analog and digital
peripheral blocks
EEPROM emulation in Flash, up to 2,304 bytes
PSoC blocks can be used individually or in combina-
tion
Programmable Pin Configurations
12 Analog PSoC blocks provide:
Up to 11-bit Delta-Sigma ADC
Up to 8-bit Successive Approximation ADC
Up to 12-bit Incremental ADC
Up to 9-bit DAC
Schmitt trigger TTL I/O pins
Logic output drive to 25 mA with internal pull-up or
pull-down resistors, High Z, or strong driver
Interrupt on pin change
Analog output drive to 40 mA
Programmable gain amplifier
Programmable filters
Precision, Programmable Clocking
Internal 24/48 MHz Oscillator (+/- 2.5%, no external
components)
Differential comparators
8 Digital PSoC blocks provide:
External 32.768 kHz Crystal Oscillator (optional pre-
cision source for PLL)
Multipurpose timers: event timing, real-time clock,
pulse width modulation (PWM) and PWM with
deadband
Internal Low Speed Oscillator for Watchdog and
Sleep
CRC modules
Dedicated Peripherals
Full-duplex UARTs
SPI™ master or slave configuration
Watchdog and Sleep Timers
Flexible clocking sources for analog PSoC blocks
Powerful Harvard Architecture Processor with Fast
Multiply/Accumulate
Low Voltage Detection with user-configurable
threshold voltages
On-chip voltage reference
M8C processor instruction set
Processor speeds to 24 MHz
Register speed memory transfers
Flexible addressing modes
Fully Static CMOS Devices using advanced Flash
technology
Low power at high speed
Operating voltage from 3.0 to 5.25 V
Bit manipulation on I/O and memory
8x8 multiply, 32-bit accumulate
Operating voltage down to 1.0 V using on-chip
switch mode voltage pump
Flexible On-Chip Memory
Wide temperature range: -40 oC to + 85 oC
Flash program storage, 4K to 16K bytes, depending
on device
Complete Development Tools
50,000 erase/write cycles
Powerful integrated development environment
(PSoC™ Designer)
256 bytes SRAM data storage
In-System Serial Programming (ISSP™)
Low-cost, in-circuit emulator and programmer
May 17, 2005
Document #: 38-12010 CY Rev. *C
3
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
This page has intentionally been left blank.
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Document #: 38-12010 CY Rev. *C
May 17, 2005
Table of Contents
1.0 Functional Overview ......................................................................................................................14
1.1 Key Features ..............................................................................................................................14
1.2 Pin-out Descriptions ...................................................................................................................15
2.0 CPU Architecture ............................................................................................................................19
2.1 Introduction ................................................................................................................................19
2.2 CPU Registers ...........................................................................................................................20
2.3 Addressing Modes .....................................................................................................................21
2.4 Instruction Set Summary ...........................................................................................................25
3.0 Memory Organization .....................................................................................................................26
3.1 Flash Program Memory Organization ........................................................................................26
3.2 RAM Data Memory Organization ...............................................................................................26
4.0 Register Organization ....................................................................................................................26
4.1 Introduction ................................................................................................................................26
4.2 Register Bank 0 Map .................................................................................................................27
4.3 Register Bank 1 Map ................................................................................................................28
5.0 I/O Ports ...........................................................................................................................................29
5.1 Introduction ................................................................................................................................29
6.0 I/O Registers ...................................................................................................................................31
6.1 Port Data Registers ...................................................................................................................31
6.2 Port Interrupt Enable Registers .................................................................................................31
6.3 Port Global Select Registers .....................................................................................................32
7.0 Clocking ..........................................................................................................................................35
7.1 Oscillator Options .......................................................................................................................35
7.2 System Clocking Signals ............................................................................................................38
8.0 Interrupts .........................................................................................................................................42
8.1 Overview ....................................................................................................................................42
8.2 Interrupt Control Architecture .....................................................................................................44
8.3 Interrupt Vectors .........................................................................................................................44
8.4 Interrupt Masks ..........................................................................................................................45
8.5 Interrupt Vector Register ...........................................................................................................46
8.6 GPIO Interrupt ............................................................................................................................47
9.0 Digital PSoC Blocks .......................................................................................................................48
9.1 Introduction ................................................................................................................................48
9.2 Digital PSoC Block Bank 1 Registers .........................................................................................49
9.3 Digital PSoC Block Bank 0 Registers .........................................................................................54
9.4 Global Inputs and Outputs .........................................................................................................60
9.5 Available Programmed Digital Functionality ...............................................................................60
10.0 Analog PSoC Blocks ....................................................................................................................71
10.1 Introduction ..............................................................................................................................71
10.2 Analog System Clocking Signals .............................................................................................72
10.3 Array of Analog PSoC Blocks .................................................................................................72
10.4 Analog Reference Control ........................................................................................................73
10.5 Analog PSoC Block Clocking Options ......................................................................................76
10.6 Analog Clock Select Register ..................................................................................................77
10.7 Analog Continuous Time PSoC Blocks ....................................................................................80
May 17, 2005
Document #: 38-12010 CY Rev. *C
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
10.8 Analog Switch Cap Type A PSoC Blocks ................................................................................85
10.9 Analog Switch Cap Type B PSoC Blocks ................................................................................94
10.10 Analog Comparator Bus .......................................................................................................101
10.11 Analog Synchronization .......................................................................................................101
10.12 Analog I/O ............................................................................................................................103
10.13 Analog Modulator .................................................................................................................106
10.14 Analog PSoC Block Functionality .........................................................................................107
10.15 Temperature Sensing Capability ..........................................................................................108
11.0 Special Features of the CPU ......................................................................................................109
11.1 Multiplier/Accumulator ............................................................................................................109
11.2 Decimator ...............................................................................................................................112
11.3 Reset ......................................................................................................................................114
11.4 Sleep States ...........................................................................................................................116
11.5 Supply Voltage Monitor ..........................................................................................................118
11.6 Switch Mode Pump ................................................................................................................119
11.7 Internal Voltage Reference ....................................................................................................120
11.8 Supervisor ROM/System Supervisor Call Instruction .............................................................120
11.9 Flash Program Memory Protection ........................................................................................122
11.10 Programming Requirements and Step Descriptions ............................................................122
11.11 Programming Wave Forms .................................................................................................124
11.12 Programming File Format ....................................................................................................124
12.0 Development Tools ...................................................................................................................125
12.1 Overview ................................................................................................................................125
12.2 Integrated Development Environment Subsystems ...............................................................126
12.3 Hardware Tools ......................................................................................................................126
13.0 DC and AC Characteristics ........................................................................................................127
13.1 Absolute Maximum Ratings ..................................................................................................127
13.2 DC Characteristics .................................................................................................................129
13.3 AC Characteristics .................................................................................................................138
14.0 Packaging Information ..............................................................................................................143
14.1 Thermal Impedances per Package .......................................................................................148
15.0 Ordering Guide ..........................................................................................................................149
16.0 Document Revision History .......................................................................................................150
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Document #: 38-12010 CY Rev. *C
May 17, 2005
List of Tables
Table 1: Device Family Key Features.........................................................................................................14
Table 2: Pin-out 8 Pin.................................................................................................................................15
Table 3: Pin-out 20 Pin...............................................................................................................................15
Table 4: Pin-out 28 Pin...............................................................................................................................16
Table 5: Pin-out 44 Pin...............................................................................................................................16
Table 6: Pin-out 48 Pin...............................................................................................................................17
Table 7: CPU Registers and Mnemonics ...................................................................................................19
Table 8: Flags Register ..............................................................................................................................20
Table 9: Accumulator Register (CPU_A)....................................................................................................20
Table 10: Index Register (CPU_X).............................................................................................................21
Table 11: Stack Pointer Register (CPU_SP)..............................................................................................21
Table 12: Program Counter Register (CPU_PC)........................................................................................21
Table 13: Source Immediate ......................................................................................................................21
Table 14: Source Direct..............................................................................................................................22
Table 15: Source Indexed ..........................................................................................................................22
Table 16: Destination Direct .......................................................................................................................22
Table 17: Destination Indexed....................................................................................................................23
Table 18: Destination Direct Immediate .....................................................................................................23
Table 19: Destination Indexed Immediate..................................................................................................23
Table 20: Destination Direct Direct.............................................................................................................24
Table 21: Source Indirect Post Increment ..................................................................................................24
Table 22: Destination Indirect Post Increment............................................................................................24
Table 23: Instruction Set Summary (Sorted by Mnemonic)........................................................................25
Table 24: Flash Program Memory Map......................................................................................................26
Table 25: RAM Data Memory Map.............................................................................................................26
Table 26: Bank 0 ........................................................................................................................................27
Table 27: Bank 1 ........................................................................................................................................28
Table 28: Port Data Registers ....................................................................................................................31
Table 29: Port Interrupt Enable Registers ..................................................................................................31
Table 30: Port Global Select Registers ......................................................................................................32
Table 31: Port Drive Mode 0 Registers ......................................................................................................32
Table 32: Port Drive Mode 1 Registers ......................................................................................................33
Table 33: Port Interrupt Control 0 Registers...............................................................................................33
Table 34: Port Interrupt Control 1 Registers...............................................................................................34
Table 35: Internal Main Oscillator Trim Register ........................................................................................35
Table 36: Internal Low Speed Oscillator Trim Register..............................................................................36
Table 37: External Crystal Oscillator Trim Register....................................................................................37
Table 38: Typical Package Capacitances ..................................................................................................37
Table 39: System Clocking Signals and Definitions ...................................................................................38
Table 40: Oscillator Control 0 Register.......................................................................................................40
Table 41: Oscillator Control 1 Register.......................................................................................................40
Table 42: 24V1/24V2 Frequency Selection................................................................................................41
Table 43: Interrupt Vector Table.................................................................................................................44
Table 44: General Interrupt Mask Register ................................................................................................45
Table 45: Digital PSoC Block Interrupt Mask Register...............................................................................46
May 17, 2005
Document #: 38-12010 CY Rev. *C
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Table 46: Interrupt Vector Register ............................................................................................................46
Table 47: Digital Basic Type A/ Communications Type A Block xx Function Register...............................50
Table 48: Digital Basic Type A / Communications Type A Block xx Input Register ...................................51
Table 49: Digital Function Data Input Definitions .......................................................................................52
Table 50: Digital Basic Type A / Communications Type A Block xx Output Register.................................53
Table 51: Digital Function Outputs .............................................................................................................54
Table 52: Digital Basic Type A / Communications Type A Block xx Data Register 0,1,2...........................54
Table 53: R/W Variations per User Module Selection ................................................................................55
Table 54: Digital Basic Type A / Communications Type A Block xx Control Register 0.............................55
Table 55: Digital Basic Type A/Communications Type A Block xx Control Register 0...............................56
Table 56: Digital Communications Type A Block xx Control Register 0.....................................................57
Table 57: Digital Communications Type A Block xx Control Register 0.....................................................58
Table 58: Digital Communications Type A Block xx Control Register 0.....................................................59
Table 59: Global Input Assignments...........................................................................................................60
Table 60: Global Output Assignments........................................................................................................60
Table 61: Analog System Clocking Signals................................................................................................72
Table 62: AGND, RefHI, RefLO Operating Parameters .............................................................................74
Table 63: Analog Reference Control Register............................................................................................75
Table 64: Analog Column Clock Select Register........................................................................................76
Table 65: Analog Clock Select Register.....................................................................................................77
Table 66: Analog Continuous Time Block xx Control 0 Register................................................................82
Table 67: Analog Continuous Time Block xx Control 1 Register................................................................83
Table 68: Analog Continuous Time Type A Block xx Control 2 Register ...................................................84
Table 69: Analog Switch Cap Type A Block xx Control 0 Register ............................................................88
Table 70: Analog Switch Cap Type A Block xx Control 1 Register ............................................................90
Table 71: Analog Switch Cap Type A Block xx Control 2 Register ............................................................92
Table 72: Analog Switch Cap Type A Block xx Control 3 Register ............................................................93
Table 73: Analog Switch Cap Type B Block xx Control 0 Register ............................................................95
Table 74: Analog Switch Cap Type B Block xx Control 1 Register ............................................................97
Table 75: Analog Switch Cap Type B Block xx Control 2 Register ............................................................99
Table 76: Analog Switch Cap Type B Block xx Control 3 Register ..........................................................100
Table 77: Analog Comparator Control Register .......................................................................................101
Table 78: Analog Frequency Relationships..............................................................................................102
Table 79: Analog Synchronization Control Register.................................................................................102
Table 80: Analog Input Select Register....................................................................................................104
Table 81: Analog Output Buffer Control Register.....................................................................................106
Table 82: Analog Modulator Control Register ..........................................................................................107
Table 83: Multiply Input X Register...........................................................................................................110
Table 84: Multiply Input Y Register...........................................................................................................110
Table 85: Multiply Result High Register ...................................................................................................111
Table 86: Multiply Result Low Register ....................................................................................................111
Table 87: Accumulator Result 1 / Multiply/Accumulator Input X Register ................................................111
Table 88: Accumulator Result 0 / Multiply/Accumulator Input Y Register ................................................111
Table 89: Accumulator Result 3 / Multiply/Accumulator Clear 0 Register ................................................112
Table 90: Accumulator Result 2 / Multiply/Accumulator Clear 1 Register ................................................112
Table 91: Decimator/Incremental Control Register ..................................................................................113
Table 92: Decimator Data High Register..................................................................................................113
Table 93: Decimator Data Low Register...................................................................................................113
Table 94: Processor Status and Control Register ....................................................................................114
Table 95: Reset WDT Register.................................................................................................................116
Table 96: Voltage Monitor Control Register .............................................................................................118
Table 97: Bandgap Trim Register.............................................................................................................120
Table 98: CY8C25122, CY8C26233, CY8C26443, CY8C26643 (256 Bytes of SRAM) ..........................121
Table 99: Table Read for Supervisory Call Functions..............................................................................122
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Document #: 38-12010 CY Rev. *C
May 17, 2005
Table 100: Flash Program Memory Protection.........................................................................................122
Table 101: Programmer Requirements ....................................................................................................122
Table 102: Absolute Maximum Ratings....................................................................................................127
Table 103: Temperature Specifications....................................................................................................128
Table 104: DC Operating Specifications ..................................................................................................129
Table 105: 5V DC Operational Amplifier Specifications ...........................................................................130
Table 106: 3.3V DC Operational Amplifier Specifications ........................................................................131
Table 107: DC Analog Input Pin with Multiplexer Specifications..............................................................132
Table 108: DC Analog Input Pin to SC Block Specifications....................................................................132
Table 109: 5V DC Analog Output Buffer Specifications ...........................................................................132
Table 110: 3.3V DC Analog Output Buffer Specifications ........................................................................133
Table 111: DC Switch Mode Pump Specifications ...................................................................................134
Table 112: 5V DC Analog Reference Specifications................................................................................135
Table 113: 3.3V DC Analog Reference Specifications.............................................................................136
Table 114: DC Analog PSoC Block Specifications...................................................................................136
Table 115: DC Programming Specifications.............................................................................................137
Table 116: AC Operating Specifications...................................................................................................138
Table 117: 5V AC Operational Amplifier Specifications ...........................................................................139
Table 118: 3.3V AC Operational Amplifier Specifications ........................................................................140
Table 119: 5V AC Analog Output Buffer Specifications ...........................................................................141
Table 120: 3.3V AC Analog Output Buffer Specifications ........................................................................142
Table 121: AC Programming Specifications.............................................................................................142
Table 122: Thermal Impedances..............................................................................................................148
Table 123: Ordering Guide (Leaded)........................................................................................................149
Table 124: Ordering Guide (Pb-Free Denoted with an “X” in Ordering Code) .........................................149
Table 125: Document Revision History ....................................................................................................150
May 17, 2005
Document #: 38-12010 CY Rev. *C
9
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
10
Document #: 38-12010 CY Rev. *C
May 17, 2005
List of Figures
Figure 1: Block Diagram ............................................................................................................................13
Figure 2: CY8C25122 ................................................................................................................................15
Figure 3: CY8C26233 ................................................................................................................................15
Figure 4: 26443 PDIP/SOIC/SSOP ...........................................................................................................16
Figure 5: 26643 TQFP ...............................................................................................................................17
Figure 6: 26643 PDIP/SSOP .....................................................................................................................18
Figure 7: General Purpose I/O Pins ..........................................................................................................30
Figure 8: External Crystal Oscillator Connections .....................................................................................37
Figure 9: PSoC MCU Clock Tree of Signals ..............................................................................................39
Figure 10: Interrupts Overview ..................................................................................................................43
Figure 11: GPIO Interrupt Enable Diagram ...............................................................................................47
Figure 12: Digital Basic and Digital Communications PSoC Blocks ..........................................................49
Figure 13: Polynomial LFSR ......................................................................................................................65
Figure 14: Polynomial PRS .......................................................................................................................65
Figure 15: SPI Waveforms ........................................................................................................................68
Figure 16: Array of Analog PSoC Blocks ...................................................................................................72
Figure 17: Analog Reference Control Schematic ......................................................................................73
Figure 18: NMux Connections ...................................................................................................................78
Figure 19: PMux Connections ...................................................................................................................79
Figure 20: RBotMux Connections ..............................................................................................................79
Figure 21: Analog Continuous Time PSoC Blocks ....................................................................................81
Figure 22: Analog Switch Cap Type A PSoC Blocks .................................................................................86
Figure 23: AMux Connections ...................................................................................................................87
Figure 24: CMux Connections ...................................................................................................................87
Figure 25: BMuxSCA/SCB Connections ...................................................................................................88
Figure 26: Analog Switch Cap Type B PSoC Blocks .................................................................................95
Figure 27: Analog Input Muxing ...............................................................................................................103
Figure 28: Analog Output Buffers ............................................................................................................105
Figure 29: Multiply/Accumulate Block Diagram .......................................................................................110
Figure 30: Decimator Coefficients ...........................................................................................................112
Figure 31: Execution Reset .....................................................................................................................115
Figure 32: Three Sleep States .................................................................................................................117
Figure 33: Switch Mode Pump ................................................................................................................119
Figure 34: Programming Wave Forms ....................................................................................................124
Figure 35: PSoC Designer Functional Flow ............................................................................................125
Figure 36: CY8C25xxx/CY8C26xxx Voltage Frequency Graph ..............................................................127
Figure 37: 44-Lead Thin Plastic Quad Flat Pack A44 .............................................................................143
Figure 38: 20-Pin Shrunk Small Outline Package O20 ...........................................................................144
Figure 39: 28-Lead (210-Mil) Shrunk Small Outline Package O28 .........................................................145
Figure 40: 48-Lead Shrunk Small Outline Package O48 .........................................................................145
Figure 41: 20-Lead (300-Mil) Molded DIP P5 ..........................................................................................146
Figure 42: 28-Lead (300-Mil) Molded DIP P21 ........................................................................................146
Figure 43: 48-Lead (600-Mil) Molded DIP P25 ........................................................................................147
Figure 44: 20-Lead (300-Mil) Molded SOIC S5 .......................................................................................147
Figure 45: 28-Lead (300-Mil) Molded SOIC S21 .....................................................................................148
May 17, 2005
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Figure 46: 8-Lead (300-Mil) Molded DIP .................................................................................................148
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Document #: 38-12010 CY Rev. *C
May 17, 2005
I/O Ports
Analog Input
Muxing
Analog Output
Drivers
A
C
A
0
A
A
C
A
0
A
C
A
0
Global I/O
Programmable Interconnect
C
A
0
Clocks to
Analog
0
1
2
3
A
S
A
1
A
S
B
1
A
S
A
1
A
S
B
1
0
1
2
3
D
B
A
0
D
B
A
0
D
B
A
0
D
B
A
0
D
C
A
0
D
C
A
0
D
C
A
0
D
C
A
0
A
S
B
2
A
S
A
2
A
S
B
2
A
S
A
2
Comparator
Outputs
0
1
2
3
4
5
6
7
0
1
2
3
Array of Analog PSoC Blocks
Array of Digital PSoC Blocks
Flash Program
Memory
Oscillator
and PLL
MAC
Multiply
Accumulate
SRAM
Memory
M8C CPU
Core
Internal System Bus
Watchdog/
Sleep Timer
Interrupt
Controller
Decimator
LVD/POR
Figure 1: Block Diagram
May 17, 2005
Document #: 38-12010 CY Rev. *C
13
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
1.0
Functional Overview
The CPU heart of this next generation family of micro-
controllers is a high performance, 8-bit, M8C Harvard
architecture microprocessor. Separate program and
memory busses allow for faster overall throughput. Pro-
cessor clock speeds to 24 MHz are available. The pro-
cessor may also be run at lower clock speeds for power-
sensitive applications. A rich instruction set allows for
efficient low-level language support.
mode, the user can select the drive strength desired.
Any pin can serve as an interrupt source, and can be
selected to trigger on positive edges, negative edges, or
any change. Digital signal sources can be routed directly
from a pin to the digital PSoC blocks. Some pins have
additional capability to route analog signals to the analog
PSoC blocks.
Multiple oscillator options are available for use in clock-
ing the CPU, analog PSoC blocks and digital PSoC
blocks. These options include an internal main oscillator
running at 48/24 MHz, an external crystal oscillator for
use with a 32.768 kHz watch crystal, and an internal low-
speed oscillator for use in clocking the PSoC blocks and
the Watchdog/Sleep timer. User selectable clock divisors
allow for optimizing code execution speed and power
trade-offs.
All devices in this family include both analog and digital
configurable peripherals (PSoC blocks). These blocks
enable the user to define unique functions during config-
uration of the device. Included are twelve analog PSoC
blocks and eight digital PSoC blocks. Potential applica-
tions for the digital PSoC blocks are timers, counters,
UARTs, CRC generators, PWMs, and other functions.
The analog PSoC blocks can be used for SAR ADCs,
Multi-slope ADCs, programmable gain amplifiers, pro-
grammable filters, DACs, and other functions. Higher
order User Modules such as modems, complex motor
controllers, and complete sensor signal chains can be
created from these building blocks. This allows for an
unprecedented level of flexibility and integration in micro-
controller-based systems.
The different device types in this family provide various
amounts of code and data memory. The code space
ranges in size from 4K to 16K bytes of user programma-
ble Flash memory. This memory can be programmed
serially in either a programming Pod or on the user
board. The endurance on the Flash memory is 50,000
erase/write cycles. The data space is 256 bytes of user
SRAM.
A Multiplier/Accumulator (MAC) is available on all
devices in this family. The MAC is implemented on this
device as a peripheral that is mapped into the register
space. When an instruction writes to the MAC input reg-
isters, the result of an 8x8 multiply and a 32-bit accumu-
late are available to be read from the output registers on
the next instruction cycle.
A powerful and flexible protection model secures the
user’s sensitive information. This model allows the user
to selectively lock blocks of memory for read and write
protection. This allows partial code updates without
exposing proprietary information.
Devices in this family range from 8 pins through 48 pins
in PDIP, SOIC and SSOP packages.
The number of general purpose I/Os available in this
family of parts range from 6 to 44. Each of these I/O pins
has a variety of programmable options. In the output
1.1
Key Features
Table 1:
Device Family Key Features
CY8C25122
CY8C26233
CY8C26443
CY8C26643
Operating Frequency
Operating Voltage
Program Memory (KBytes)
Data Memory (Bytes)
Digital PSoC Blocks
Analog PSoC Blocks
I/O Pins
93.7kHz - 24MHz
93.7kHz - 24MHz 93.7kHz - 24MHz 93.7kHz - 24MHz
3.0 - 5.25V
3.0 - 5.25V
3.0 - 5.25V
16
3.0 - 5.25V
16
4
8
256
8
256
256
256
8
8
8
12
6
12
12
12
16
24
40/44
Yes
External Switch Mode Pump No
Available Packages 8 PDIP
Yes
Yes
20 PDIP
20 SOIC
20 SSOP
28 PDIP
28 SOIC
28 SSOP
48 PDIP
48 SSOP
44 TQFP
14
Document #: 38-12010 CY Rev. *C
May 17, 2005
Functional Overview
1.2
Pin-out Descriptions
Table 2:
Name
Pin-out 8 Pin
Table 3:
Pin-out 20 Pin
I/O
Pin
1
Description
Port 0[7] (Analog Input)
Port 0[5] (Analog Input/Output)
Port 1[1] / XtalIn / SCLK
Ground
Name
I/O
Pin
1
Description
P0[7] I/O
P0[5] I/O
P1[1] I/O
P0[7] I/O
P0[5] I/O
P0[3] I/O
P0[1] I/O
Port 0[7] (Analog Input)
Port 0[5] (Analog Input/Output)
Port 0[3] (Analog Input/Output)
Port 0[1] (Analog Input)
Switch Mode Pump
Port 1[7]
2
2
3
3
Vss
Power
4
4
P1[0] I/O
P0[2] I/O
P0[4] I/O
5
Port 1[0] / XtalOut / SDATA
Port 0[2] (Analog Input/Output)
Port 0[4] (Analog Input/Output)
Supply Voltage
SMP
O
5
6
P1[7] I/O
P1[5] I/O
P1[3] I/O
P1[1] I/O
6
7
7
Port 1[5]
Vcc
Power
8
8
Port 1[3]
9
Port 1[1] / XtalIn / SCLK
Vss
Power
10 Ground
P1[0] I/O
P1[2] I/O
P1[4] I/O
P1[6] I/O
11 Port 1[0] / XtalOut / SDATA
12 Port 1[2]
1
2
3
4
8
P0[7]
P0[5]
XtalIn/SCLK/P1[1]
V
cc
P0[4]
P0[2]
P1[0]/XtalOut/SDATA
7
6
5
13 Port 1[4]
14 Port 1[6]
V
ss
XRES
I
15 External Reset
P0[0] I/O
P0[2] I/O
P0[4] I/O
P0[6] I/O
16 Port 0[0] (Analog Input)
17 Port 0[2] (Analog Input/Output)
18 Port 0[4] (Analog Input/Output)
19 Port 0[6] (Analog Input)
20 Supply Voltage
Figure 2: CY8C25122
Vcc
Power
V
1
2
3
4
5
6
7
8
P0[7]
P0[5]
P0[3]
P0[1]
SMP
P1[7]
P1[5]
P1[3]
cc
20
19
18
17
16
15
14
13
12
11
P0[6]
P0[4]
P0[2]
P0[0]
XRES
P1[6]
P1[4]
P1[2]
9
10
XtalIn/SCLK/P1[1]
V
ss
P1[0]/XtalOut/SDATA
Figure 3: CY8C26233
May 17, 2005
Document #: 38-12010 CY Rev. *C
15
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Table 4:
Pin-out 28 Pin
I/O Pin
Name
Description
P0[7]
I/O
1
Port 0[7] (Analog Input)
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
SMP
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
cc
Port 0[5] (Analog Input/ Out-
put)
P0[6]
P0[4]
P0[2]
P0[0]
P0[5]
P0[3]
I/O
2
3
Port 0[3] (Analog Input/ Out-
put)
I/O
P2[6]/External Vref
P0[1]
P2[7]
P2[5]
I/O
I/O
I/O
4
5
6
Port 0[1] (Analog Input)
Port 2[7]
P2[4]
P2[2]
P2[0]
/External AGND
9
P1[7]
P1[5]
P1[3]
10
11
12
13
14
X
res
Port 2[5]
P1[6]
P1[4]
P1[2]
Port 2[3] (Non-Multiplexed
Analog Input)
XtalIn/SCLK/P1[1]
P2[3]
P2[1]
I/O
I/O
7
V
ss
P1[0]/XtalOut/SDATA
Port 2[1] (Non-Multiplexed
Analog Input)
8
9
Figure 4: 26443 PDIP/SOIC/SSOP
SMP
P1[7]
P1[5]
P1[3]
P1[1]
Vss
O
Switch Mode Pump
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
I
10 Port 1[7]
Table 5:
Pin-out 44 Pin
11 Port 1[5]
Name
I/O
I/O
Pin
Description
12 Port 1[3]
P2[5]
1
Port 2[5]
13 Port 1[1] / XtalIn / SCLK
14 Ground
Port 2[3] (Non-Multiplexed
Analog Input)
P2[3]
P2[1]
I/O
I/O
2
3
P1[0]
P1[2]
P1[4]
P1[6]
XRES
15 Port 1[0] / XtalOut / SDATA
16 Port 1[2]
Port 2[1] (Non-Multiplexed
Analog Input)
P3[7]
P3[5]
P3[3]
P3[1]
SMP
P4[7]
P4[5]
P4[3]
P4[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
I/O
I/O
I/O
I/O
O
4
5
6
7
8
9
Port 3[7]
17 Port 1[4]
Port 3[5]
18 Port 1[6]
Port 3[3]
19 External Reset
Port 3[1]
Port 2[0] (Non-Multiplexed
Analog Input)
P2[0]
P2[2]
I/O
I/O
20
Switch Mode Pump
Port 4[7]
Port 2[2] (Non-Multiplexed
Analog Input)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
21
10 Port 4[5]
P2[4]
P2[6]
P0[0]
I/O
I/O
I/O
22 Port 2[4] / External AGNDIn
23 Port 2[6] / External VREFIn
24 Port 0[0] (Analog Input)
11 Port 4[3]
12 Port 4[1]
13 Port 1[7]
Port 0[2] (Analog Input/Out-
put)
P0[2]
P0[4]
I/O
I/O
25
14 Port 1[5]
15 Port 1[3]
Port 0[4] (Analog Input/Out-
put)
26
16 Port 1[1] / XtalIn / SCLK
17 Ground
P0[6]
Vcc
I/O
27 Port 0[6] (Analog Input)
28 Supply Voltage
Power
P1[0]
P1[2]
P1[4]
P1[6]
P4[0]
P4[2]
P4[4]
18 Port 1[0] / XtalOut / SDATA
19 Port 1[2]
20 Port 1[4]
21 Port 1[6]
22 Port 4[0]
23 Port 4[2]
24 Port 4[4]
16
Document #: 38-12010 CY Rev. *C
May 17, 2005
Functional Overview
Table 5:
Pin-out 44 Pin, continued
Table 6:
Pin-out 48 Pin
I/O Pin
P4[6]
XRES
P3[0]
P3[2]
P3[4]
P3[6]
I/O
I
25 Port 4[6]
26 External Reset
27 Port 3[0]
28 Port 3[2]
29 Port 3[4]
30 Port 3[6]
Name
Description
P0[7]
I/O
1
Port 0[7] (Analog Input)
I/O
I/O
I/O
I/O
Port 0[5] (Analog Input/Out-
put)
P0[5]
P0[3]
I/O
2
3
Port 0[3] (Analog Input/Out-
put)
I/O
Port 2[0] (Non-Multiplexed
Analog Input)
P0[1]
P2[7]
P2[5]
I/O
I/O
I/O
4
5
6
Port 0[1] (Analog Input)
Port 2[7]
P2[0]
P2[2]
I/O
I/O
31
32
Port 2[2] (Non-Multiplexed
Analog Input)
Port 2[5]
Port 2[3] (Non-Multiplexed
Analog Input)
P2[3]
P2[1]
I/O
I/O
7
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vcc
I/O
I/O
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
I/O
33 Port 2[4] / External AGNDIn
34 Port 2[6] / External VREFIn
35 Port 0[0] (Analog Input)
36 Port 0[2] (Analog Input/Output)
37 Port 0[4] (Analog Input/Output)
38 Port 0[6] (Analog Input)
39 Supply Voltage
Port 2[1] (Non-Multiplexed
Analog Input)
8
9
P3[7]
P3[5]
P3[3]
P3[1]
SMP
P4[7]
P4[5]
P4[3]
P4[1]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
I/O
I/O
I/O
I/O
O
Port 3[7]
10 Port 3[5]
11 Port 3[3]
12 Port 3[1]
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
40 Port 0[7] (Analog Input)
41 Port 0[5] (Analog Input/Output)
42 Port 0[3] (Analog Input/Output)
43 Port 0[1] (Analog Input)
44 Port 2[7]
13 Switch Mode Pump
14 Port 4[7]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
15 Port 4[5]
16 Port 4[3]
17 Port 4[1]
18 Port 5[3]
19 Port 5[1]
20 Port 1[7]
21 Port 1[5]
22 Port 1[3]
23 Port 1[1] / XtalIn / SCLK
24 Ground
44 43 42 41 40 39 38 37 36 35 34
1
2
3
4
5
6
7
8
9
33
32
31
30
29
28
27
26
25
24
23
P2[4]/Ex AGNDIn
P2[2]
P2[0]
P3[6]
P3[4]
P2[5]
P2[3]
P2[1]
P3[7]
P3[5]
P3[3]
P3[1]
SMP
P4[7]
P4[5]
P4[3]
P1[0]
P1[2]
P1[4]
P1[6]
25 Port 1[0] / XtalOut / SDATA
26 Port 1[2]
P3[2]
P3[0]
27 Port 1[4]
28 Port 1[6]
X
res
P4[6]
P4[4]
P4[2]
10
11
12 13 14 15 16 17 18 19 20 21 22
Figure 5: 26643 TQFP
May 17, 2005
Document #: 38-12010 CY Rev. *C
17
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Table 6:
Pin-out 48 Pin, continued
P5[0]
P5[2]
P4[0]
P4[2]
P4[4]
P4[6]
XRES
P3[0]
P3[2]
P3[4]
P3[6]
I/O
I/O
I/O
I/O
I/O
I/O
I
29 Port 5[0]
30 Port 5[2]
31 Port 4[0]
32 Port 4[2]
33 Port 4[4]
34 Port 4[6]
35 External Reset
36 Port 3[0]
37 Port 3[2]
38 Port 3[4]
39 Port 3[6]
I/O
I/O
I/O
I/O
Port 2[0] (Non-Multiplexed
Analog Input)
P2[0]
P2[2]
I/O
I/O
40
41
Port 2[2] (Non-Multiplexed
Analog Input)
P2[4]
P2[6]
P0[0]
I/O
I/O
I/O
42 Port 2[4] / External AGNDIn
43 Port 2[6] / External VREFIn
44 Port 0[0] (Analog Input)
Port 0[2] (Analog Input/Out-
put)
P0[2]
P0[4]
I/O
I/O
45
Port 0[4] (Analog Input/Out-
put)
46
P0[6]
Vcc
I/O
47 Port 0[6] (Analog Input)
48 Supply Voltage
Power
1
2
3
4
5
6
7
8
48
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P3[7]
P3[5]
P3[3]
P3[1]
SMP
P4[7]
P4[5]
P4[3]
P4[1]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
V
P0[6]
P0[4]
P0[2]
cc
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P0[0]
P2[6]/External VrefIN
P2[4] /External AGNDIN
P2[2]
P2[0]
P3[6]
P3[4]
P3[2]
P3[0]
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
X
res
P4[6]
P4[4]
P4[2]
P4[0]
P5[2]
P5[0]
P1[6]
P1[4]
XtalIn/SCLK/P1[1]
P1[2]
P1[0]/XtalOut/SDATA
V
ss
Figure 6: 26643 PDIP/SSOP
18
Document #: 38-12010 CY Rev. *C
May 17, 2005
CPU Architecture
2.0
2.1
CPU Architecture
Introduction
This family of microcontrollers is based on a high perfor-
mance, 8-bit, Harvard architecture microprocessor. Five
registers control the primary operation of the CPU core.
These registers are affected by various instructions, but
are not directly accessible through the register space by
the user. For more details on addressing with the register
space, see section 4.0.
RET instructions, which manage the software stack. It
can also be affected by the SWAP and ADD instructions.
The Flag Register (CPU_F) has three status bits: Zero
Flag bit [1]; Carry Flag bit [2]; Supervisory State bit [3].
The Global Interrupt Enable bit [0] is used to globally
enable or disable interrupts. An extended I/O space
address, bit [4], is used to determine which bank of the
register space is in use. The user cannot manipulate the
Supervisory State status bit [3]. The flags are affected by
arithmetic, logic, and shift operations. The manner in
which each flag is changed is dependent upon the
instruction being executed (i.e., AND, OR, XOR... See
Table 23 on page 25).
Table 7:
CPU Registers and Mnemonics
Register Mnemonic
CPU_F
Flags
Program Counter
Accumulator
Stack Pointer
Index
CPU_PC
CPU_A
CPU_SP
CPU_X
The 16 bit Program Counter Register (CPU_PC) allows
for direct addressing of the full 16 Kbytes of program
memory space available in the largest members of this
family. This forms one contiguous program space, and
no paging is required.
The Accumulator Register (CPU_A) is the general-pur-
pose register that holds the results of instructions that
specify any of the source addressing modes.
The Index Register (CPU_X) holds an offset value that is
used in the indexed addressing modes. Typically, this is
used to address a block of data within the data memory
space.
The Stack Pointer Register (CPU_SP) holds the address
of the current top-of-stack in the data memory space. It is
affected by the PUSH, POP, LCALL, CALL, RETI, and
May 17, 2005
Document #: 38-12010 CY Rev. *C
19
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
2.2
CPU Registers
2.2.1 Flags Register
The Flags Register can only be set or reset with logical instruction.
Table 8:
Flags Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
Read/
Write
--
--
--
RW
XIO
R
RW
RW
RW
Bit Name
Reserved Reserved Reserved
Super
Carry
Zero
Global IE
Bit 7: Reserved
Bit 6: Reserved
Bit 5: Reserved
Bit 4: XIO Set by the user to select between the register banks
0 = Bank 0
1 = Bank 1
Bit 3: Super Indicates whether the CPU is executing user code or Supervisor Code. (This code cannot be accessed
directly by the user and is not displayed in the ICE debugger.)
0 = User Code
1 = Supervisor Code
Bit 2: Carry Set by CPU to indicate whether there has been a carry in the previous logical/arithmetic operation
0 = No Carry
1 = Carry
Bit 1: Zero Set by CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation
0 = Not Equal to Zero
1 = Equal to Zero
Bit 0: Global IE Determines whether all interrupts are enabled or disabled
0 = Disabled
1 = Enabled
2.2.2 Accumulator Register
Table 9:
Bit #
Accumulator Register (CPU_A)
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Read/Write
Bit Name
System
System
Data [6]
System
System
System
System
System
System
Data [7]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]: Data [7:0] 8-bit data value holds the result of any logical/arithmetic instruction that uses a source address-
ing mode
1. System - not directly accessible by the user
20
Document #: 38-12010 CY Rev. *C
May 17, 2005
CPU Architecture
2.2.3 Index Register
Table 10:
Index Register (CPU_X)
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
1
1
1
1
1
1
1
1
System
System
System
System
System
System
System
Data [1]
System
Data [0]
Bit Name
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Bit [7:0]: Data [7:0] 8-bit data value holds an index for any instruction that uses an indexed addressing mode
1. System - not directly accessible by the user
2.2.4 Stack Pointer Register
Table 11:
Stack Pointer Register (CPU_SP)
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
1
1
1
1
1
1
1
1
System
System
System
System
System
System
System
Data [1]
System
Bit Name
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [0]
Bit [7:0]: Data [7:0] 8-bit data value holds a pointer to the current top-of-stack
1. System - not directly accessible by the user
2.2.5 Program Counter Register
Table 12:
Program Counter Register (CPU_PC)
Bit #
POR
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/
Write
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
Name
Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data
[15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
Bit [15:0]: Data [15:0] 16-bit data value is the low-order/high-order byte of the Program Counter
1. System - not directly accessible by the user
2.3
Addressing Modes
require two sources. Instructions using this addressing
mode are two bytes in length.
2.3.1 Source Immediate
The result of an instruction using this addressing mode is
placed in the A register, the F register, the SP register, or
the X register, which is specified as part of the instruction
opcode. Operand 1 is an immediate value that serves as
a source for the instruction. Arithmetic instructions
Table 13: Source Immediate
Opcode
Operand 1
Instruction
Immediate Value
May 17, 2005
Document #: 38-12010 CY Rev. *C
21
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Examples:
added to the X register forming an address that points to
a location in either the RAM memory space or the regis-
;In this case, the immediate
ter space that is the source for the instruction. Arithmetic
instructions require two sources, the second source is
the A register or X register specified in the opcode.
Instructions using this addressing mode are two bytes.
;value of 7 is added with the
;Accumulator, and the result
;is placed in the
ADD A,
7
8
9
;Accumulator.
;In this case, the immediate
;value of 8 is moved to the X
;register.
Table 15: Source Indexed
MOV X,
AND F,
Opcode
Operand 1
Source Index
;In this case, the immediate
;value of 9 is logically
;ANDed with the F register
;and the result is placed in
;the F register.
Instruction
Examples:
;In this case, the
;value in the memory
;location at address
;X + 7 is added with
;the Accumulator, and
;the result is placed
;in the Accumulator.
2.3.2 Source Direct
ADD A,
[X+7]
The result of an instruction using this addressing mode is
placed in either the A register or the X register, which is
specified as part of the instruction opcode. Operand 1 is
an address that points to a location in either the RAM
memory space or the register space that is the source for
the instruction. Arithmetic instructions require two
sources, the second source is the A register or X register
specified in the opcode. Instructions using this address-
ing mode are two bytes in length.
;In this case, the
;value in the
;register space at
;address X + 8 is
;moved to the X
;register.
MOV X,
REG[X+8]
2.3.4 Destination Direct
Table 14: Source Direct
The result of an instruction using this addressing mode is
placed within either the RAM memory space or the regis-
ter space. Operand 1 is an address that points to the
location of the result. The source for the instruction is
either the A register or the X register, which is specified
as part of the instruction opcode. Arithmetic instructions
require two sources, the second source is the location
specified by Operand 1. Instructions using this address-
ing mode are two bytes in length.
Opcode
Operand 1
Instruction
Source Address
Examples:
;In this case, the
;value in the RAM
;memory location at
;address 7 is added
;with the Accumulator,
;and the result is
;placed in the
ADD
MOV
A,
X,
[7]
Table 16: Destination Direct
;Accumulator.
Opcode
Operand 1
;In this case, the
;value in the register
REG[8] ;space at address 8 is
;moved to the X
Instruction
Destination Address
;register.
2.3.3 Source Indexed
The result of an instruction using this addressing mode is
placed in either the A register or the X register, which is
specified as part of the instruction opcode. Operand 1 is
22
Document #: 38-12010 CY Rev. *C
May 17, 2005
CPU Architecture
source for the instruction is Operand 2, which is an
immediate value. Arithmetic instructions require two
sources, the second source is the location specified by
Operand 1. Instructions using this addressing mode are
three bytes in length.
Examples:
;In this case, the
;value in the memory
;location at address
;7 is added with the
;Accumulator, and the
;result is placed in
;the memory location
;at address 7. The
;Accumulator is
ADD
[7],
A
Table 18: Destination Direct Immediate
Opcode
Operand 1
Operand 2
Instruction
Destination Address Immediate Value
;unchanged.
;In this case, the
;Accumulator is moved
;to the register
;space location at
;address 8. The
;Accumulator is
;unchanged.
Examples:
;In this case, value in
;the memory location at
;address 7 is added to
;the immediate value of
;5, and the result is
;placed in the memory
;location at address 7.
MOV
REG[8], A
ADD [7],
5
2.3.5 Destination Indexed
;In this case, the
;immediate value of 6 is
;moved into the register
;space location at
;address 8.
The result of an instruction using this addressing mode is
placed within either the RAM memory space or the regis-
ter space. Operand 1 is added to the X register forming
the address that points to the location of the result. The
source for the instruction is the A register. Arithmetic
instructions require two sources, the second source is
the location specified by Operand 1 added with the X
register. Instructions using this addressing mode are two
bytes in length.
MOV REG[8], 6
2.3.7 Destination Indexed Immediate
The result of an instruction using this addressing mode is
placed within either the RAM memory space or the regis-
ter space. Operand 1 is added to the X register to form
the address of the result. The source for the instruction is
Operand 2, which is an immediate value. Arithmetic
instructions require two sources, the second source is
the location specified by Operand 1 added with the X
register. Instructions using this addressing mode are
three bytes in length.
Table 17: Destination Indexed
Opcode
Operand 1
Instruction
Destination Index
Example:
Table 19: Destination Indexed Immediate
;In this case, the value
;in the memory location
;at address X+7 is added
;with the Accumulator,
;and the result is placed
;in the memory location
;at address x+7. The
;Accumulator is
Opcode
Operand 1
Operand 2
Instruction
Destination Index
Immediate Value
ADD [X+7],
A
;unchanged.
2.3.6 Destination Direct Immediate
The result of an instruction using this addressing mode is
placed within either the RAM memory space or the regis-
ter space. Operand 1 is the address of the result. The
May 17, 2005
Document #: 38-12010 CY Rev. *C
23
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Examples:
Language User Guide for further details on MVI instruc-
tion.
;In this case, the
Table 21: Source Indirect Post Increment
;value in the memory
;location at address
;X+7 is added with
;the immediate value
;of 5, and the result
;is placed in the
;memory location at
;address X+7.
Opcode
Operand 1
Instruction
Source Address Address
ADD
[X+7],
5
Example:
;In this case, the value
;in the memory location at
;address 8 is an indirect
;address. The memory
;In this case, the
;immediate value of 6
;is moved into the
;location in the
;register space at
;address X+8.
MOV
REG[X+8], 6
;location pointed to by
;the indirect address is
;moved into the
MVI A,
[8]
;Accumulator. The
;indirect address is then
;incremented.
2.3.8 Destination Direct Direct
The result of an instruction using this addressing mode is
placed within the RAM memory. Operand 1 is the
address of the result. Operand 2 is an address that
points to a location in the RAM memory that is the source
for the instruction. This addressing mode is only valid on
the MOV instruction. The instruction using this address-
ing mode is three bytes in length.
2.3.10 Destination Indirect Post Increment
The result of an instruction using this addressing mode is
placed within the memory space. Operand 1 is an
address pointing to a location within the memory space,
which contains an address (the indirect address) for the
destination of the instruction. The indirect address is
incremented as part of the instruction execution. The
source for the instruction is the Accumulator. This
addressing mode is only valid on the MVI instruction.
The instruction using this addressing mode is two bytes
in length.
Table 20: Destination Direct Direct
Opcode
Operand 1
Operand 2
Instruction Destination Address Source Address
Example:
;In this case, the value
;in the memory location at
MOV [7], [8] ;address 8 is moved to the
;memory location at
Table 22: Destination Indirect Post Increment
Opcode
Operand 1
Instruction
Destination Address Address
;address 7.
Example:
2.3.9 Source Indirect Post Increment
;In this case, the
;value in the memory
;location at address 8
;is an indirect
;address. The
;Accumulator is moved
;into the memory
;location pointed to by
;the indirect address.
;The indirect address
;is then incremented.
The result of an instruction using this addressing mode is
placed in the Accumulator. Operand 1 is an address
pointing to a location within the memory space, which
contains an address (the indirect address) for the source
of the instruction. The indirect address is incremented as
part of the instruction execution. This addressing mode
is only valid on the MVI instruction. The instruction using
this addressing mode is two bytes in length. See Sec-
tion 7. Instruction Set in PSoC Designer: Assembly
MVI
[8],
A
24
Document #: 38-12010 CY Rev. *C
May 17, 2005
CPU Architecture
2.4
Instruction Set Summary
Table 23:
Instruction Set Summary (Sorted by Mnemonic)
Instruction Format
Flags
Instruction Format
Flags
Instruction Format
Flags
09
0A
0B
0C
0D
0E
4
6
7
7
8
9
2 ADC A, expr
2 ADC A, [expr]
2 ADC A, [X+expr]
2 ADC [expr], A
2 ADC [X+expr], A
3 ADC [expr], expr
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
76
77
7
8
2 INC [expr]
2 INC [X+expr]
C, Z
C, Z
Z
20
18
10
08
5
5
4
4
1 POP X
1 POP A
1 PUSH X
1 PUSH A
Z
Fx 13 2 INDEX
Ex
Cx
8x
Dx
Bx
Ax
7
5
5
5
5
5
2 JACC
2 JC
2 JMP
2 JNC
2 JNZ
2 JZ
7E 10 1 RETI
C, Z
7F
6A
6B
6C
8
4
7
8
1 RET
1 RLC A
2 RLC [expr]
2 RLC [X+expr]
0F 10 3 ADC [X+expr], expr
C, Z
C, Z
C, Z
Z
01
02
03
04
05
06
4
6
7
7
8
9
2 ADD A, expr
2 ADD A, [expr]
2 ADD A, [X+expr]
2 ADD [expr], A
2 ADD [X+expr], A
3 ADD [expr], expr
7C 13 3 LCALL
28 11 1 ROMX
7D
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
7
4
4
5
6
5
6
8
9
4
6
7
5
4
4
6
7
3 LJMP
1 MOV X, SP
2 MOV A, expr
6D
6E
6F
19
1A
1B
1C
1D
1E
4
7
8
4
6
7
7
8
9
1 RRC A
2 RRC [expr]
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
Z
Z
2 RRC [X+expr]
2 SBB A, expr
2 SBB A, [expr]
2 SBB A, [X+expr]
2 SBB [expr], A
2 SBB [X+expr], A
3 SBB [expr], expr
07 10 3 ADD [X+expr], expr
2 MOV A, [expr]
2 MOV A, [X+expr]
2 MOV [expr], A
2 MOV [X+expr], A
3 MOV [expr], expr
3 MOV [X+expr], expr
2 MOV X, expr
2 MOV X, [expr]
2 MOV X, [X+expr]
2 MOV [expr], X
1 MOV A, X
38
21
22
23
24
25
26
5
4
6
7
7
8
9
2 ADD SP, expr
2 AND A, expr
Z
Z
Z
Z
Z
Z
Z
C, Z
Z
Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
2 AND A, [expr]
2 AND A, [X+expr]
2 AND [expr], A
2 AND [X+expr], A
3 AND [expr], expr
1F 10 3 SBB [X+expr], expr
00 15 1 SSC
27 10 3 AND [X+expr], expr
70
41
11
12
13
14
15
16
4
6
7
7
8
9
2 SUB A, expr
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
4
9
2 AND F, expr
3 AND reg[expr], expr
2 SUB A, [expr]
2 SUB A, [X+expr]
2 SUB [expr], A
2 SUB [X+expr], A
3 SUB [expr], expr
Z
42 10 3 AND reg[X+expr], expr
1 MOV X, A
2 MOV A, reg[expr]
2 MOV A, reg[X+expr]
64
65
66
67
68
69
4
7
8
4
7
8
1 ASL A
Z
Z
2 ASL [expr]
2 ASL [X+expr]
1 ASR A
2 ASR [expr]
2 ASR [X+expr]
5F 10 3 MOV [expr], [expr]
17 10 3 SUB [X+expr], expr
60
61
62
63
5
6
8
9
2 MOV reg[expr], A
4B
4C
4D
4E
47
48
49
5
7
7
5
8
9
9
1 SWAP A, X
2 MOV reg[X+expr], A
3 MOV reg[expr], expr
3 MOV reg[X+expr], expr
2 SWAP A, [expr]
2 SWAP X, [expr]
1 SWAP A, SP
3 TST [expr], expr
3 TST [X+expr], expr
3 TST reg[expr], expr
Z
9x 11 2 CALL
Z
Z
Z
Z
Z
C, Z
Z
Z
Z
Z
39
3A
3B
3C
3D
73
78
79
7A
7B
30
5
7
8
8
9
4
4
4
7
8
9
4
4
2 CMP A, expr
2 CMP A, [expr]
2 CMP A, [X+expr]
3 CMP [expr], expr
3 CMP [X+expr], expr
1 CPL A
1 DEC A
1 DEC X
2 DEC [expr]
2 DEC [X+expr]
1 HALT
if (A=B) Z=1 3E 10 2 MVI A, [ [expr]++ ]
Z
Z
3F 10 2 MVI [ [expr]++ ], A
40
29
2A
2B
2C
2D
2E
2F 10 3 OR [X+expr], expr
43 3 OR reg[expr], expr
44 10 3 OR reg[X+expr], expr
71 2 OR F, expr
if (A<B) C=1
4
4
6
7
7
8
9
1 NOP
2 OR A, expr
2 OR A, [expr]
2 OR A, [X+expr]
2 OR [expr], A
2 OR [X+expr], A
3 OR [expr], expr
4A 10 3 TST reg[X+expr], expr
Z
Z
Z
Z
Z
Z
Z
Z
72
31
32
33
34
35
36
4
4
6
7
7
8
9
2 XOR F, expr
2 XOR A, expr
Z
C, Z
C, Z
C, Z
C, Z
2 XOR A, [expr]
2 XOR A, [X+expr]
2 XOR [expr], A
2 XOR [X+expr], A
3 XOR [expr], expr
Z
Z
Z
Z
9
74
75
1 INC A
1 INC X
C, Z
C, Z
37 10 3 XOR [X+expr], expr
45 3 XOR reg[expr], expr
46 10 3 XOR reg[X+expr], expr
4
C, Z
9
Note: Interrupt acknowledge to Interrupt Vector table = 13 cycles.
Z
May 17, 2005
Document #: 38-12010 CY Rev. *C
25
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
3.0
3.1
Memory Organization
Flash Program Memory
Organization
3.2
RAM Data Memory Organization
The stack on this device grows from low addresses to
high addresses. The Linker function within PSoC
Designer locates the bottom of the stack after the end of
Global Variables. This allows the stack to grow from just
after the Global Variables until 0xFF. The stack will wrap
back to 0x00 on an overflow condition.
Table 24:
Flash Program Memory Map
Address
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
Description
Reset Vector
Supply Monitor Interrupt Vector
DBA 00 PSoC Block Interrupt Vector
DBA 01 PSoC Block Interrupt Vector
DBA 02 PSoC Block Interrupt Vector
DBA 03 PSoC Block Interrupt Vector
DCA 04 PSoC Block Interrupt Vector
DCA 05 PSoC Block Interrupt Vector
DCA 06 PSoC Block Interrupt Vector
DCA 07 PSoC Block Interrupt Vector
Analog Column 0 Interrupt Vector
Analog Column 1 Interrupt Vector
Analog Column 2 Interrupt Vector
Analog Column 3 Interrupt Vector
GPIO Interrupt Vector
Table 25:
Address
RAM Data Memory Map
Description
0x00
0xXX
0xXY
0xXZ
0xYX
First General Purpose RAM Location
General Purpose RAM
General Purpose RAM
Last General Purpose RAM Location
Bottom of Hardware Stack
0xYY
0xFF
⇓ Stack Grows This Way ⇓
Top of Hardware Stack
4.0
4.1
Register Organization
Introduction
Sleep Timer Interrupt Vector
On-Chip User Program Memory Starts
Here
There are two register banks implemented on these
devices. Each bank contains 256 addresses. The pur-
pose of these register banks is to personalize and
parameterize the on-chip resources as well as read and
write data values.
0x0040
***
***
***
16K Flash Maximum Depending on Ver-
sion
0x3FFF
The user selects between the two banks by setting the
XIO bit in the CPU_F Flag Register.
In some cases, the same register is available on either
bank, for convenience. These registers (71h to 9fh) can
be accessed from either bank.
Note: All register addresses not shown are reserved and
should never be written. In addition, unused or reserved
bits in any register should always be written to 0.
26
Document #: 38-12010 CY Rev. *C
May 17, 2005
Register Organization
4.2
Register Bank 0 Map
Table 26:
Bank 0
PRT0DR
PRT0IE
PRT0GS
Reserved
PRT1DR
PRT1IE
PRT1GS
Reserved
PRT2DR
PRT2IE
PRT2GS
Reserved
PRT3DR
PRT3IE
00h 31
01h 31
02h 32
03h
04h 31
05h 31
06h 32
07h
08h 31
09h 31
0Ah 32
0Bh
0Ch 31
0Dh 31
0Eh 32
0Fh
RW
W
40h
ASA10CR0 80h 88
ASA10CR1 81h 90
ASA10CR2 82h 92
ASA10CR3 83h 93
ASB11CR0 84h 95
ASB11CR1 85h 97
ASB11CR2 86h 99
RW
RW
RW
RW
RW
RW
RW
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
41h
W
42h
43h
RW
W
W
44h
45h
46h
47h
ASB11CR3 87h 100 RW
RW
W
W
48h
ASA12CR0 88h 88
ASA12CR1 89h 90
ASA12CR2 8Ah 92
ASA12CR3 8Bh 93
ASB13CR0 8Ch 95
ASB13CR1 8Dh 97
ASB13CR2 8Eh 99
RW
RW
RW
RW
RW
RW
RW
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
RW
W
W
PRT3GS
Reserved
PRT4DR
PRT4IE
ASB13CR3 8Fh 100 RW
10h 31
11h 31
12h 32
13h
RW
W
W
ASB20CR0 90h 95
ASB20CR1 91h 97
ASB20CR2 92h 99
RW
RW
RW
51h
PRT4GS
Reserved
PRT5DR
PRT5IE
52h
53h
ASB20CR3 93h 100 RW
14h 31
15h 31
16h 32
17h
RW
W
W
54h
ASA21CR0 94h 88
ASA21CR1 95h 90
ASA21CR2 96h 92
ASA21CR3 97h 93
ASB22CR0 98h 95
ASB22CR1 99h 97
ASB22CR2 9Ah 99
RW
RW
RW
RW
RW
RW
RW
55h
PRT5GS
56h
57h
18h
58h
19h
59h
1Ah
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h 104 RW
61h
1Bh
ASB22CR3 9Bh 100 RW
1Ch
ASA23CR0 9Ch 88
RW
RW
RW
RW
1Dh
ASA23CR1 9Dh 90
1Eh
ASA23CR2 9Eh 92
1Fh
ASA23CR3 9Fh 93
A0h
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DBA00DR0 20h 54
DBA00DR1 21h 54
DBA00DR2 22h 54
DBA00CR0 23h 55
DBA01DR0 24h 54
DBA01DR1 25h 54
DBA01DR2 26h 54
DBA01CR0 27h 55
DBA02DR0 28h 54
DBA02DR1 29h 54
DBA02DR2 2Ah 54
DBA02CR0 2Bh 55
DBA03DR0 2Ch 54
DBA03DR1 2Dh 54
DBA03DR2 2Eh 54
DBA03CR0 2Fh 55
DCA04DR0 30h 54
DCA04DR1 31h 54
DCA04DR2 32h 54
DCA04CR0 33h 55
DCA05DR0 34h 54
DCA05DR1 35h 54
DCA05DR2 36h 54
DCA05CR0 37h 55
DCA06DR0 38h 54
DCA06DR1 39h 54
DCA06DR2 3Ah 54
DCA06CR0 3Bh 55
DCA07DR0 3Ch 54
DCA07DR1 3Dh 54
DCA07DR2 3Eh 54
DCA07CR0 3Fh 55
AMX_IN
INT_MSK0
INT_MSK1
INT_VC
E0h 45
E1h 46
E2h 46
E3h 116 RW
E4h 113 RW
E5h 113
E6h 113 RW
E7h
E8h 110
E9h 110
EAh 111
EBh 111
RW
RW
RW
A1h
Reserved
62h
A2h
ARF_CR
CMP_CR
ASY_CR
63h 73
64h 101
65h 102
66h
RW
A3h
RES_WDT
DEC_DH/DEC_CL
DEC_DL
1
1
A4h
A5h
R
A6h
DEC_CR
67h
A7h
Reserved
68h
A8h
MUL_X
W
W
R
69h
A9h
MUL_Y
6Ah
AAh
ABh
ACh
ADh
AEh
AFh
MUL_DH
6Bh
MUL_DL
R
6Ch
ACC_DR1/MAC_X
ACC_DR0/MAC_Y
ECh 111 RW
EDh 111 RW
6Dh
6Eh
ACC_DR3/MAC_CL0 EEh 112 RW
ACC_DR2/MAC_CL1 EFh 112 RW
6Fh
70h
B0h
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
1
ACA00CR0 71h 82
ACA00CR1 72h 83
ACA00CR2 73h 84
Reserved 74h
RW
RW
RW
B1h
B2h
B3h
B4h
ACA01CR0 75h 82
ACA01CR1 76h 83
ACA01CR2 77h 84
Reserved 78h
ACA02CR0 79h 82
ACA02CR1 7Ah 83
ACA02CR2 7Bh 84
Reserved 7Ch
RW
RW
RW
B5h
B6h
B7h
B8h
RW
RW
RW
B9h
BAh
BBh
BCh
BDh
BEh
BFh
ACA03CR0 7Dh 82
ACA03CR1 7Eh 83
ACA03CR2 7Fh 84
RW
RW
RW
CPU_SCR
FFh 114
May 17, 2005
Document #: 38-12010 CY Rev. *C
27
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
4.3
Register Bank 1 Map
Table 27:
Bank 1
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
PRT5DM1
PRT5IC0
PRT5IC1
00h 32
01h 33
02h 33
03h 34
04h 32
05h 33
06h 33
07h 34
08h 32
09h 33
0Ah 33
0Bh 34
0Ch 32
0Dh 33
0Eh 33
0Fh 34
10h 32
11h 33
12h 33
13h 34
14h 32
15h 33
16h 33
17h 34
18h
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
40h
ASA10CR0 80h 88 RW
C0h
41h
ASA10CR1 81h 90 RW
C1h
42h
ASA10CR2 82h 92 RW
C2h
43h
ASA10CR3 83h 93 RW
C3h
44h
ASB11CR0 84h 95 RW
C4h
45h
ASB11CR1 85h 97 RW
C5h
46h
ASB11CR2 86h 99 RW
C6h
47h
ASB11CR3 87h 100 RW
C7h
48h
ASA12CR0 88h 88 RW
C8h
49h
ASA12CR1 89h 90 RW
C9h
4Ah
ASA12CR2 8Ah 92 RW
CAh
4Bh
ASA12CR3 8Bh 93 RW
CBh
4Ch
ASB13CR0 8Ch 95 RW
CCh
4Dh
ASB13CR1 8Dh 97 RW
CDh
4Eh
ASB13CR2 8Eh 99 RW
CEh
4Fh
ASB13CR3 8Fh 100 RW
CFh
50h
ASB20CR0 90h 95 RW
D0h
51h
ASB20CR1 91h 97 RW
D1h
52h
ASB20CR2 92h 99 RW
D2h
53h
ASB20CR3 93h 100 RW
D3h
54h
ASA21CR0 94h 88 RW
D4h
55h
ASA21CR1 95h 90 RW
D5h
56h
ASA21CR2 96h 92 RW
D6h
57h
ASA21CR3 97h 93 RW
D7h
58h
ASB22CR0 98h 95 RW
D8h
19h
59h
ASB22CR1 99h 97 RW
D9h
1Ah
5Ah
ASB22CR2 9Ah 99 RW
DAh
1Bh
5Bh
ASB22CR3 9Bh 100 RW
DBh
1Ch
5Ch
ASA23CR0 9Ch 88 RW
DCh
1Dh
5Dh
ASA23CR1 9Dh 90 RW
DDh
1Eh
5Eh
ASA23CR2 9Eh 92 RW
DEh
1Fh
5Fh
ASA23CR3 9Fh 93 RW
DFh
DBA00FN
DBA00IN
DBA00OU
Reserved
DBA01FN
DBA01IN
DBA01OU
Reserved
DBA02FN
DBA02IN
DBA02OU
Reserved
DBA03FN
DBA03IN
DBA03OU
Reserved
DCA04FN
DCA04IN
DCA04OU
Reserved
DCA05FN
DCA05IN
DCA05OU
Reserved
DCA06FN
DCA06IN
DCA06OU
Reserved
DCA07FN
DCA07IN
DCA07OU
Reserved
20h 50 RW CLK_CR0
21h 51 RW CLK_CR1
22h 53 RW ABF_CR
60h 76 RW
61h 77 RW
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
OSC_CR0
OSC_CR1
Reserved
VLT_CR
Reserved
Reserved
Reserved
Reserved
IMO_TR
E0h 40 RW
E1h 40 RW
E2h
E3h 118 RW
E4h
E5h
E6h
62h 106
W
23h
AMD_CR
63h 107 RW
64h
24h 50 RW
25h 51 RW
26h 53 RW
27h
28h 50 RW
29h 51 RW
2Ah 53 RW
2Bh
65h
66h
67h
E7h
68h
E8h 35
E9h 36
EAh 120
EBh 37
ECh
W
W
W
W
69h
ILO_TR
BDG_TR
ECO_TR
6Ah
6Bh
2Ch 50 RW
2Dh 51 RW
2Eh 53 RW
2Fh
6Ch
6Dh
EDh
6Eh
EEh
6Fh
EFh
30h 50 RW
70h
F0h
31h 51 RW ACA00CR0
32h 53 RW ACA00CR1
71h 82 RW
72h 83 RW
73h 84 RW
74h
F1h
F2h
33h
ACA00CR2
F3h
34h 50 RW Reserved
35h 51 RW ACA01CR0
36h 53 RW ACA01CR1
F4h
75h 82 RW
76h 83 RW
77h 84 RW
78h
79h 82 RW
7Ah 83 RW
7Bh 84 RW
7Ch
F5h
F6h
37h
ACA01CR2
F7h
38h 50 RW Reserved
39h 51 RW ACA02CR0
3Ah 53 RW ACA02CR1
F8h
F9h
FAh
3Bh
ACA02CR2
FBh
3Ch 50 RW Reserved
3Dh 51 RW ACA03CR0
3Eh 53 RW ACA03CR1
FCh
7Dh 82 RW
7Eh 83 RW
7Fh 84 RW
FDh
FEh
1
3Fh
ACA03CR2
CPU_SCR
FFh 114
1. Read/Write access is bit-specific or varies by function. See register.
28
Document #: 38-12010 CY Rev. *C
May 17, 2005
I/O Ports
5.0
5.1
I/O Ports
Introduction
Up to five 8-bit-wide I/O ports (P0-P4) and one 4-bit wide
I/O port (P5) are implemented. The number of general
purpose I/Os implemented and connected to pins
depends on the individual part chosen. All port bits are
independently programmable and have the following
capabilities:
The circumstances are that during sleep, the reference
voltage on the capacitor is refreshed periodically at the
sleep system duty cycle. Between refresh cycles, this
voltage may leak slightly to either the positive supply or
ground. If pins P2[4] or P2[6] are in a high state, the leak-
age to the positive supply is accelerated (especially at
high temperature). Since the reference voltage is com-
pared to the supply to detect a low voltage condition, this
accelerated leakage to the positive supply voltage will
cause that voltage to appear lower than it actually is,
leading to the generation of a false Low Voltage Detect
interrupt.
General-purpose digital input readable by the CPU.
General-purpose digital output writable by the CPU.
Independent control of data direction for each port
bit.
Independent access for each port bit to Global Input
and Global Output busses.
Port 0 and Port 2 have additional analog input and/or
analog output capability. The specific routing and multi-
plexing of analog signals is shown in the following dia-
gram:
Interrupt programmable to assert on rising edge,
falling edge, or change from last pin state read.
Output drive strength programmable in logic 0 and 1
states as strong, resistive (pull-up or pull-down), or
high impedance.
A slew rate controlled output mode is available.
In high impedence, the digital input can be disabled
to lower power consumption.
Port 1, Pin 0 is used in conjunction with device Test
Mode and does not behave the same as other I/O ports
immediately after reset. A device reset with Power On
Reset (POR) will drive P1[0] high for 8 ms immediately
after POR is released because there is a CPU hold-off
time of approximately 64 ms before code execution
begins. It will then drive P1[0] low for 8 ms. This can
impact external circuits connected to Port 1, Pin 0.
In System Sleep State, GPIO Pins P2[4] and P2[6]
should be held to a logic low or a false Low Voltage
Detect interrupt may be triggered. The cause is in the
System Sleep State, the internal Bandgap reference
generator is turned off and the reference voltage is main-
tained on a capacitor.
May 17, 2005
Document #: 38-12010 CY Rev. *C
29
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
GPIO
InterruptEnable
(INT_MSK0:5)
From
Other
GPIO
Pins
Rise
IM0
IM1
1
D
Q
GPIO Int
IM0
IM1
Fall
Interrupt Mode
IM1 IM0
Output
D
Q
0
0
1
1
0
1
0
1
Suppress Interrupt
Falling Edge
En
IM0
IM1
Rising Edge
GPIO Read
Change
Change from last read
To CPU Bus
DM0
DM1
Global Select
Global Input Line
Analog In (Ports 0 and 2 Only)
Bonding
Pad
Analog Out (Port 0 Only)
VDD
Drive Mode
DM1 DM0
DM0
DM1
Output
0
0
1
1
0
1
0
1
Resistive Pulldown
Strong Drive
CPU Bus
VDD
High Z (off)
Resistive Pullup
D
5.6K
Q
GPIO Write
DM1
DM0
Global Out
Global Select
5.6K
VSS
DM0
DM1
VSS
Figure 7: General Purpose I/O Pins
30
Document #: 38-12010 CY Rev. *C
May 17, 2005
I/O Registers
6.0
6.1
I/O Registers
Port Data Registers
Table 28:
Port Data Registers
Bit #
POR
7
0
6
5
0
4
0
3
0
2
0
1
0
0
0
0
Read/Write
Bit Name
RW
RW
RW
RW
RW
RW
RW
RW
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]: Data [7:0] When written is the bits for output on port pins. When read is the state of the port pins
Port 0 Data Register (PRT0DR, Address = Bank 0, 00h)
Port 1 Data Register (PRT1DR, Address = Bank 0, 04h)
Port 2 Data Register (PRT2DR, Address = Bank 0, 08h)
Port 3 Data Register (PRT3DR, Address = Bank 0, 0Ch)
Port 4 Data Register (PRT4DR, Address = Bank 0, 10h)
Port 5 Data Register (PRT5DR, Address = Bank 0, 14h) Note: Port 5 is 4-bits wide, Bit [3:0]
6.2
Port Interrupt Enable Registers
Table 29:
Port Interrupt Enable Registers
Bit #
POR
7
6
0
5
0
4
0
3
0
2
1
0
0
W
0
W
0
W
0
W
Read/Write
Bit Name
W
W
W
W
Int En [7]
Int En [6] Int En [5] Int En [4] Int En [3]
Int En [2]
Int En [1]
Int En [0]
Bit [7:0]: Int En [7:0] When written sets the pin interrupt state
0 = Interrupt disabled for pin
1 = Interrupt enabled for pin
Port 0 Interrupt Enable Register (PRT0IE, Address = Bank 0, 01h)
Port 1 Interrupt Enable Register (PRT1IE, Address = Bank 0, 05h)
Port 2 Interrupt Enable Register (PRT2IE, Address = Bank 0, 09h)
Port 3 Interrupt Enable Register (PRT3IE, Address = Bank 0, 0Dh)
Port 4 Interrupt Enable Register (PRT4IE, Address = Bank 0, 11h)
Port 5 Interrupt Enable Register (PRT5IE, Address = Bank 0, 15h) Note: Port 5 is 4-bits wide
May 17, 2005
Document #: 38-12010 CY Rev. *C
31
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
6.3
Port Global Select Registers
Table 30:
Bit #
Port Global Select Registers
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
POR
Read/Write
W
W
W
W
W
W
W
W
GlobSel
[7]
GlobSel
[6]
GlobSel
[5]
GlobSel
[4]
GlobSel
[3]
GlobSel
[2]
GlobSel
[1]
GlobSel
[0]
Bit Name
Bit [7:0]: Global Select [7:0] When written determines whether a pin is connected to the Global Input Bus and Glo-
bal Output Bus
0 = Not Connected
1 = Connected
Drive Mode xx = Global Select Register 0 = Standard CPU controlled port (Default)
Drive Mode 1 0 (High Z) = Global Select Register 1 = Direct Drive of associated Global Input line
Drive Mode 0 0, 0 1, 1 1 = Global Select Register 1 = Direct Receive from associated Global Output line
Port 0 Global Select Register (PRT0GS, Address = Bank 0, 02h)
Port 1 Global Select Register (PRT1GS, Address = Bank 0, 06h)
Port 2 Global Select Register (PRT2GS, Address = Bank 0, 0Ah)
Port 3 Global Select Register (PRT3GS, Address = Bank 0, 0Eh)
Port 4 Global Select Register (PRT4GS, Address = Bank 0, 12h)
Port 5 Global Select Register (PRT5GS, Address = Bank 0, 16h) Note: If implemented, Port 5 is 4-bits wide
6.3.1 Port Drive Mode 0 Registers
Table 31:
Port Drive Mode 0 Registers
Bit #
POR
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Read/Write
Bit Name
W
W
W
W
W
W
W
W
DM0 [7]
DM0 [6]
DM0 [5]
DM0 [4]
DM0 [3]
DM0 [2]
DM0 [1]
DM0 [0]
Bit [7:0]: DM0 [7:0] The two Drive Mode bits that control a particular port pin are treated as a pair and are decoded
as follows:
Port Data Register Bit 0 = Drive Mode 0 0 = 0 Resistive (Default)
Port Data Register Bit 0 = Drive Mode 0 1 = 0 Strong
Port Data Register Bit 0 = Drive Mode 1 0 = High Z
Port Data Register Bit 0 = Drive Mode 1 1 = 0 Strong
Port Data Register Bit 1 = Drive Mode 0 0 = 1 Strong
Port Data Register Bit 1 = Drive Mode 0 1 = 1 Strong
Port Data Register Bit 1 = Drive Mode 1 0 = High Z
Port Data Register Bit 1 = Drive Mode 1 1 = 1 Resistive
Port 0 Drive Mode 0 Register (PRT0DM0, Address = Bank 1, 00h)
Port 1 Drive Mode 0 Register (PRT1DM0, Address = Bank 1, 04h)
Port 2 Drive Mode 0 Register (PRT2DM0, Address = Bank 1, 08h)
Port 3 Drive Mode 0 Register (PRT3DM0, Address = Bank 1, 0Ch)
Port 4 Drive Mode 0 Register (PRT4DM0, Address = Bank 1, 10h)
Port 5 Drive Mode 0 Register (PRT5DM0, Address = Bank 1, 14h) Note: Port 5 is 4-bits wide
32
Document #: 38-12010 CY Rev. *C
May 17, 2005
I/O Registers
6.3.2 Port Drive Mode 1 Registers
Table 32:
Port Drive Mode 1 Registers
Bit #
POR
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Read/Write
Bit Name
W
W
W
W
W
W
W
W
DM1 [7]
DM1 [6]
DM1 [5]
DM1 [4]
DM1 [3]
DM1 [2]
DM1 [1]
DM1 [0]
Bit [7:0]: DM1 [7:0] See truth table for Port Drive Mode 0 Registers, above
Port 0 Drive Mode 1 Register (PRT0DM1, Address = Bank 1, 01h)
Port 1 Drive Mode 1 Register (PRT1DM1, Address = Bank 1, 05h)
Port 2 Drive Mode 1 Register (PRT2DM1, Address = Bank 1, 09h)
Port 3 Drive Mode 1 Register (PRT3DM1, Address = Bank 1, 0Dh)
Port 4 Drive Mode 1 Register (PRT4DM1, Address = Bank 1, 11h)
Port 5 Drive Mode 1 Register (PRT5DM1, Address = Bank 1, 15h) Note: Port 5 is 4-bits wide
6.3.3 Port Interrupt Control 0 Registers
Table 33:
Port Interrupt Control 0 Registers
Bit #
POR
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Read/Write
Bit Name
W
W
W
W
W
W
W
W
IC0 [7]
IC0 [6]
IC0 [5]
IC0 [4]
IC0 [3]
IC0 [2]
IC0 [1]
IC0 [0]
Bit [7:0]: IC0 [7:0] The two Interrupt Control bits that control a particular port pin are treated as a pair and are
decoded as follows:
IC1 [x], IC0 [x] = 0 0 = Disabled (Default)
IC1 [x], IC0 [x] = 0 1 = Falling Edge (-)
IC1 [x], IC0 [x] = 1 0 = Rising Edge (+)
IC1 [x], IC0 [x] = 1 1 = Change from Last Direct Read
Port 0 Interrupt Control 0 Register (PRT0IC0, Address = Bank 1, 02h)
Port 1 Interrupt Control 0 Register (PRT1IC0, Address = Bank 1, 06h)
Port 2 Interrupt Control 0 Register (PRT2IC0, Address = Bank 1, 0Ah)
Port 3 Interrupt Control 0 Register (PRT3IC0, Address = Bank 1, 0Eh)
Port 4 Interrupt Control 0 Register (PRT4IC0, Address = Bank 1, 12h)
Port 5 Interrupt Control 0 Register (PRT5IC0, Address = Bank 1, 16h) Note: Port 5 is 4-bits wide
May 17, 2005
Document #: 38-12010 CY Rev. *C
33
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
6.3.4 Port Interrupt Control 1 Registers
Table 34:
Port Interrupt Control 1 Registers
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
W
W
W
W
W
W
W
W
Bit Name
IC1 [7]
IC1 [6]
IC1 [5]
IC1 [4]
IC1 [3]
IC1 [2]
IC1 [1]
IC1 [0]
Bit [7:0]: IC1 [7:0] See truth table for Port Interrupt Control 0 Registers, above
Port 0 Interrupt Control 1 Register (PRT0IC1, Address = Bank 1, 03h)
Port 1 Interrupt Control 1 Register (PRT1IC1, Address = Bank 1, 07h)
Port 2 Interrupt Control 1 Register (PRT2IC1, Address = Bank 1, 0Bh)
Port 3 Interrupt Control 1 Register (PRT3IC1, Address = Bank 1, 0Fh)
Port 4 Interrupt Control 1 Register (PRT4IC1, Address = Bank 1, 13h)
Port 5 Interrupt Control 1 Register (PRT5IC1, Address = Bank 1, 17h) Note: Port 5 is 4-bits wide
34
Document #: 38-12010 CY Rev. *C
May 17, 2005
Clocking
7.0
Clocking
7.1
Oscillator Options
7.1.1
Internal Main Oscillator
The internal main oscillator outputs two frequencies, 48
MHz and 24 MHz. In the absence of a high-precision
input source from the external oscillator, the accuracy of
for which factory calibration was set. The factory-pro-
grammed trim value is selected using the Table Read
Supervisor Call, and is documented in 11.8.
o
o
this circuit is +/- 2.5% (between 0 C and +85 C). No
external components are required to achieve this level of
accuracy. The Internal Main Oscillator Trim Register
(IMO_TR) is used to calibrate this oscillator into specified
tolerance. Factory-programmed trim values are available
for 5.0V and 3.3V operation. The 5.0V value is loaded in
the IMO_TR register upon reset. This register must be
adjusted when the operating voltage is outside the range
There is an option to phase lock this oscillator to the
External Crystal Oscillator. The choice of crystal and its
inherent accuracy will determine the overall accuracy of
the oscillator. The External Crystal Oscillator must be
stable prior to locking the frequency of the Internal Main
Oscillator to this reference source.
Table 35: Internal Main Oscillator Trim Register
Bit #
POR
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
FS
FS
FS
FS
W
FS
FS
FS
FS
Read/Write
W
W
W
W
W
W
W
IMOTrim IMO Trim
[7] [6]
IMO Trim
[5]
IMO Trim
[4]
IMO Trim
[3]
IMO Trim
[2]
IMO Trim IMO Trim
[1] [0]
Bit Name
Bit [7:0]: IMO Trim [7:0] Data value stored will alter the trimmed frequency of the Internal Main Oscillator. A larger
value in this register will increase the speed of the Internal Main Oscillator
1. FS = Factory set trim value
Internal Main Oscillator Trim Register (IMO_TR, Address = Bank 1, E8h)
7.1.2 Internal Low Speed Oscillator
An internal low speed oscillator of nominally 32 kHz is
available to generate sleep wake-up interrupts and
Watchdog resets if the user does not want to attach a
32.768 kHz watch crystal. This oscillator can also be
used as a clocking source for the digital PSoC blocks.
The oscillator operates in two different modes. A trim
value is written to the Internal Low Speed Oscillator Trim
Register (ILO_TR), shown below, upon reset. See sec-
tion 13.0 for accuracy information. When the IC is put
into sleep mode this oscillator drops into an ultra low cur-
rent state and the accuracy is reduced.
This register sets the adjustment for the Internal Low
Speed Oscillator. The value placed in this register is
based on factory testing. It is recommended that the user
not alter this value.
May 17, 2005
Document #: 38-12010 CY Rev. *C
35
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Table 36:
Internal Low Speed Oscillator Trim Register
Bit #
POR
7
6
5
4
3
2
1
0
1
1
1
1
1
1
0
0
FS
FS
FS
FS
FS
FS
Read/
Write
--
W
W
W
W
W
W
W
ILO Trim
[5]
ILO Trim
[4]
ILO Trim
[3]
ILO Trim
[2]
ILO Trim
[1]
ILO Trim
[0]
Bit Name
Reserved Disable
Bit 7: Reserved
Bit 6: Disable
0 = Low Speed Oscillator is on
1 = Low Speed Oscillator is off (minimum power state)
Bit [5:0]: ILO Trim [5:0] Data value stored will alter the trimmed frequency of the Internal Low Speed Oscillator. (Not
recommended for customer alteration)
1. FS = Factory set trim value
Internal Low Speed Oscillator Trim Register (ILO_TR, Address = Bank 1, E9h)
7.1.3
External Crystal Oscillator
The XtalIn and XtalOut pins support connection of a
32.768 kHz watch crystal to drive the 32K clock. To con-
nect to the external crystal, the XtalIn and XtalOut pins’
drive modes must be set to High Z. To enable the exter-
nal crystal oscillator, bit 7 of the Oscillator Control 0 Reg-
ister (OSC_CR0) must be set (default is off). Note that
the Internal Low Speed Oscillator continues to run when
this external function is selected. It runs until the oscilla-
tor is automatically switched over when the sleep timer
reaches terminal count. External feedback capacitors to
ond interval, created by the Sleep Interrupt logic.
The 1-second interval gives the oscillator time to
stabilize before it becomes the active source. The
Sleep Interrupt need not be enabled for the switch
over to occur. The user may want to reset the sleep
timer (if this does not interfere with any ongoing
real-time clock operation), to guarantee the interval
length.
5. The user must wait the 1-second stabilization period
prior to engaging the PLL mode to lock the Internal
Main Oscillator frequency to the External Crystal
Oscillator frequency.
V
are required.
cc
If the proper settings are selected in PSoC Designer, the
The firmware steps involved in switching between the
Internal Low Speed Oscillator and External Crystal Oscil-
lator are as follows:
above steps are automatically done in boot.asm.
Note: Transitions between oscillator domains may pro-
duce glitches on the 32K clock bus. Functions that
require accuracy on the 32K clock should be enabled
after the transition in oscillator domains.
1. At reset, the chip begins operation using the Internal
Low Speed Oscillator.
2. User immediately selects a sleep interval of 1 sec-
ond in the Oscillator Control 0 Register (OSC_CR0),
as the oscillator stabilization interval.
The External Crystal Oscillator Trim Register (ECO_TR)
sets the adjustment for the External Crystal Oscillator.
The value placed in this register at reset is based on fac-
tory testing. This register does not adjust the frequency
of the External Crystal Oscillator. It is recommended that
the user not alter this value.
3. User selects External Crystal Oscillator by setting bit
[7] in Oscillator Control 0 Register (OSC_CR0) to 1.
4. The External Crystal Oscillator becomes the
selected 32.768 kHz source at the end of the 1-sec-
36
Document #: 38-12010 CY Rev. *C
May 17, 2005
Clocking
Table 37:
External Crystal Oscillator Trim Register
Bit #
POR
7
6
5
0
--
4
0
--
3
2
1
0
1
1
1
1
1
1
FS
FS
FS
FS
FS
FS
Read/Write
Bit Name
W
W
W
W
W
W
PSSDC [1] PSSDC [0] Reserved Reserved
Amp [1]
Amp [0]
Bias [1]
Bias [0]
Bit [7:6]: PSSDC [1:0] Power System Sleep Duty Cycle. (Not recommended for customer alteration)
0 0 = 1/128
0 1 = 1/512
1 0 = 1/32
1 1 = 1/8
Bit 5: Reserved
Bit 4: Reserved
Bit [3:2]: Amp [1:0] Sets the amplitude of the adjustment. (Not recommended for customer alteration)
Bit [1:0]: Bias [1:0] Sets the bias of the adjustment. (Not recommended for customer alteration)
1. FS = Factory set trim value
External Crystal Oscillator Trim Register (ECO_TR, Address = Bank 1, EBh)
7.1.4
External Crystal Oscillator Component Connections and Selections
Vcc
cc
V
C1
C2
XtalOut
XtalIn
Crystal
Figure 8: External Crystal Oscillator Connections
Table 38:
Package
Typical Package Capacitances
Package Capacitance
Crystal – 32.768 kHz watch crystal such as EPSON
C-002RX (12.5 pF load capacitance)
Capacitors – C1, C2
8 PDIP
0.9 pF
Use NPO-type ceramic caps
C1 = C2 = 25 pF - (Package Cap) - (Board Parasitic
Cap)
20 PDIP
20 SOIC
20 SSOP
28 PDIP
28 SOIC
28 SSOP
44 TQFP
48 PDIP
48 SSOP
2 pF
1 pF
0.5 pF
2 pF
Note: Use this equation if you do not employ PLL mode.
If you do employ PLL with the External Crystal Oscillator,
see Application Note AN2027 under Support at http://
www.cypressmicro.com for equation and details. An
error of 1 pF in C1 and C2 gives about 3 ppm error in fre-
quency.
1 pF
0.5 pF
0.5 pF
5 pF
0.6 pF
May 17, 2005
Document #: 38-12010 CY Rev. *C
37
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
1. Select a CPU frequency of 3 MHz or less.
2. Enable the PLL.
7.1.5 Phase-Locked Loop (PLL) Operation
The Phase-Locked Loop (PLL) function generates the
system clock with crystal accuracy. It is designed to pro-
vide a 23.986 MHz oscillator when utilized with an exter-
nal 32.768 kHz crystal. Although the PLL provides
crystal accuracy it requires time to lock onto the refer-
ence frequency when first starting. After the External
Crystal Oscillator has been selected and enabled, the
following procedure should be followed to enable the
PLL and allow for proper frequency lock:
3. Wait at least 10 ms.
4. Set CPU to a faster frequency, if desired. To do this,
write the bits CPU[2:0] in the OSC_CR0 register.
The CPU frequency will immediately change when
these bits are set.
If the proper settings are selected in PSoC Designer, the
above steps are automatically done in boot.asm.
7.2
System Clocking Signals
There are twelve system-clocking signals that are used
throughout the device. Referenced frequencies are
based on use of 32.768 kHz crystal. The names of these
signals and their definitions are as follows:
Table 39:
System Clocking Signals and Definitions
Signal
48M
Definition
The direct 48 MHz output from the Internal Main Oscillator.
The direct 24 MHz output from the Internal Main Oscillator.
24M
The 24 MHz output from the Internal Main Oscillator that has been passed through a user-selectable 1
to 16 divider {F = 24 MHz / (1 to 16) = 24 MHz to 1.5 MHz}. The divider value is found in the Oscillator
Control 1 Register (OSC_CR1). Note that the divider will be N+1, based on a value of N written into the
register bits.
24V1
24V2
The 24V1 signal that has been passed through an additional user-selectable 1 to 16 divider {F = 24
MHz / ((1 to 16) * (1 to 16)) = 24 MHz to 93.7 kHz}. The divider value is found in the Oscillator Control 1
Register (OSC_CR1). Note that the divider will be N+1, based on a value of N written into the register
bits.
32K
The multiplexed output of either the Internal Low Speed Oscillator or the External Crystal Oscillator.
The output from the Internal Main Oscillator that has been passed through a divider that has 8 user
selectable ratios ranging from 1:1 to 1:256, yielding frequencies ranging from 24 MHz to 93.7 kHz.
CPU
The 32K system-clocking signal that has been passed through a divider that has 4 user selectable
6
15
SLP
ratios ranging from 1:2 to 1:2 , yielding frequencies ranging from 512 Hz to 1 Hz. This signal is used
to clock the sleep timer period.
38
Document #: 38-12010 CY Rev. *C
May 17, 2005
Clocking
The following diagram shows the PSoC MCU Clock Tree of signals 48M through SLP:
PLL Lock Enable
OSC_CR0[6]
IMO Trim Register
IMO_TR[7:0]
48 MHz
24 MHz
48M
24M
Internal
Main
Oscillator
Phase
Lock Loop
24V1 Clock Divisor
OSC_CR1[7:4]
÷ 732
24V1
24V2
÷ n
24V2 Clock Divisor
OSC_CR1[3:0]
ECO Trim Register
ECO_TR[7:0]
÷ n
Vcc
CPU Clock Divisor
OSC_CR0[2:0]
P1[1]
External
Crystal
Oscillator
÷ 1
÷ 2
÷ 4
CPU
P1[0]
÷ 8
÷ 16
÷ 32
÷ 128
÷ 256
32 kHz Select
OSC_CR0[7]
ILO Trim Register
ILO_TR[7:0]
Vcc
32K
SLP
Internal
Low Speed
Oscillator
Sleep Clock Divisor
OSC_CR0[4:3]
÷ 26
÷ 29
÷ 212
÷ 215
Figure 9: PSoC MCU Clock Tree of Signals
CPU and Sleep Timer Clock Options
7.2.1
The CPU is clocked off the CPU system-clocking signal,
which can be configured to run at one of eight rates. This
selection is independent from all other clock selection
functions. It is completely safe for the CPU to change its
clock rate without a timing hazard. The CPU clock period
is determined by setting the CPU[2:0] bits in the Oscilla-
tor Control 0 Register (OSC_CR0).
The sleep timer is clocked off the SLP system-clocking
signal. The SLEEP[1] and SLEEP[0] bits in the Oscillator
Control 0 Register (OSC_CR0) allow the user to select
from the four available periods.
May 17, 2005
Document #: 38-12010 CY Rev. *C
39
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Table 40:
Oscillator Control 0 Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
32k Select PLL Mode Reserved
Sleep [1]
Sleep [0]
CPU [2]
CPU [1]
CPU [0]
Bit 7: 32k Select
0 = Internal low precision 32 kHz oscillator
1 = External Crystal Oscillator
Bit 6: PLL Mode
0 = Disabled
1 = Enabled, Internal Main Oscillator is locked to External Crystal Oscillator
Bit 5: Reserved
Bit [4:3]: Sleep [1:0]
0 0 = 512 Hz or 1.95 ms period
0 1 = 64 Hz or 15.6 ms period
1 0 = 8 Hz or 125 ms period
1 1 = 1 Hz or 1 s period
Bit [2:0]: CPU [2:0]
0 0 0 = 3 MHz
0 0 1 = 6 MHz
0 1 0 = 12 MHz
0 1 1 = 24 MHz
1 0 0 = 1.5 MHz
1 0 1 = 750 kHz
1 1 0 = 187.5 kHz
1 1 1 = 93.7 kHz
Oscillator Control 0 Register (OSC_CR0, Address = Bank 1, E0h)
Table 41:
Oscillator Control 1 Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
24V1 [3]
24V1 [2]
24V1 [1]
24V1 [0]
24V2 [3]
24V2 [2]
24V2 [1]
24V2 [0]
Bit [7:4]: 24V1 [3:0] 4-bit data value determines the divider value for the 24V1 system-clocking signal. Note that the
4-bit data value equals n-1, where n is the desired divider value, as illustrated in PSoC MCU Clock Tree of Signals.
See Table 42 on page 41.
Bit [3:0]: 24V2 [3:0] 4-bit data value determines the divider value for the 24V2 system-clocking signal. Note that the
4-bit data value equals n-1, where n is the desired divider value, as illustrated in the PSoC MCU Clock Tree of Sig-
nals. See Table 42 on page 41.
Oscillator Control 1 Register (OSC_CR1, Address = Bank 1, E1h)
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May 17, 2005
Clocking
24V1 and 24V2 based on the value written to the
OSC_CR1 register.
7.2.2 24V1/24V2 Frequency Selection
The following table shows the resulting frequencies for
Table 42:
24V1/24V2 Frequency Selection
Reg.
Value
24V1
MHz
Reg.
Value
24V1
MHz
Reg.
Value
24V1
MHz
Reg.
Value
24V1
MHz
24V2 kHz
24V2 kHz
24V2 kHz
24V2 kHz
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
24.00
24000.00
12000.00
8000.00
6000.00
4800.00
4000.00
3428.57
3000.00
2666.67
2400.00
2181.82
2000.00
1846.15
1714.29
1600.00
1500.00
12000.00
6000.00
4000.00
3000.00
2400.00
2000.00
1714.29
1500.00
1333.33
1200.00
1090.91
1000.00
923.08
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
4.80
4800.00
2400.00
1600.00
1200.00
960.00
800.00
685.71
600.00
533.33
480.00
436.36
400.00
369.23
342.86
320.00
300.00
4000.00
2000.00
1333.33
1000.00
800.00
666.67
571.43
500.00
444.44
400.00
363.64
333.33
307.69
285.71
266.67
250.00
3428.57
1714.29
1142.86
857.14
685.71
571.43
489.80
428.57
380.95
342.86
311.69
285.71
263.74
244.90
228.57
214.29
3000.00
1500.00
1000.00
750.00
600.00
500.00
428.57
375.00
333.33
300.00
272.73
250.00
230.77
214.29
200.00
187.5
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
2.67
2666.67
1333.33
888.89
666.67
533.33
444.44
380.95
333.33
296.30
266.67
242.42
222.22
205.13
190.48
177.78
166.67
2400.00
1200.00
800.00
600.00
480.00
400.00
342.86
300.00
266.67
240.00
218.18
200.00
184.62
171.43
160.00
150.00
2181.82
1090.91
727.27
545.45
436.36
363.64
311.69
272.73
242.42
218.18
198.35
181.82
167.83
155.84
145.45
136.36
2000.00
1000.00
666.67
500.00
400.00
333.33
285.71
250.00
222.22
200.00
181.82
166.67
153.85
142.86
133.33
125.00
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
1.85
1846.15
923.08
615.38
461.54
369.23
307.69
263.74
230.77
205.13
184.62
167.83
153.85
142.01
131.87
123.08
115.38
1714.29
857.14
571.43
428.57
342.86
285.71
244.90
214.29
190.48
171.43
155.84
142.86
131.87
122.45
114.29
107.14
1600.00
800.00
533.33
400.00
320.00
266.67
228.57
200.00
177.78
160.00
145.45
133.33
123.08
114.29
106.67
100.00
1500.00
750.00
500.00
375.00
300.00
250.00
214.29
187.50
166.67
150.00
136.36
125.00
115.38
107.14
100.00
93.75
24.00
24.00
24.00
24.00
24.00
24.00
24.00
24.00
24.00
24.00
24.00
24.00
24.00
24.00
24.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
12.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
6.00
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.80
4.00
4.00
4.00
4.00
4.00
4.00
4.00
4.00
4.00
4.00
4.00
4.00
4.00
4.00
4.00
4.00
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.43
3.00
3.00
3.00
3.00
3.00
3.00
3.00
3.00
3.00
3.00
3.00
3.00
3.00
3.00
3.00
3.00
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.67
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.40
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00
2.00
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
857.14
800.00
750.00
8000.00
4000.00
2666.67
2000.00
1600.00
1333.33
1142.86
1000.00
888.89
800.00
727.27
666.67
615.38
571.43
533.33
500.00
6000.00
3000.00
2000.00
1500.00
1200.00
1000.00
857.14
6.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00
750.00
666.67
600.00
545.45
500.00
461.54
428.57
400.00
375.00
May 17, 2005
Document #: 38-12010 CY Rev. *C
41
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
7.2.3
Digital PSoC Block Clocking Options
All digital PSoC block clocks are a user-selectable
choice of 48M, 24V1, 24V2, or 32K, as well as clocking
signals from other digital PSoC blocks or general pur-
pose I/O pins. There are a total of 16 possible clock
options for each digital PSoC block. See the Digital
PSoC Block section for details.
8.0
8.1
Interrupts
Overview
Interrupts can be generated by the General Purpose I/O
lines, the Power monitor, the internal Sleep Timer, the
eight Digital PSoC blocks, and the four analog columns.
Every interrupt has a separate enable bit, which is con-
tained in the General Interrupt Mask Register
(INT_MSK0) and the Digital PSoC Block Interrupt Mask
Register (INT_MSK1). When the user writes a “1” to a
particular bit position, this enables the interrupt associ-
ated with that position. There is a single Global Interrupt
Enable bit in the Flags Register (CPU_F), which can dis-
able all interrupts, or enable those interrupts that also
have their individual interrupt bit enabled. During a reset,
the enable bits in the General Interrupt Mask Register
(INT_MASK0), the enable bits in the Digital PSoC Block
Interrupt Mask Register (INT_MSK1) and the Global
Interrupt Enable bit in the Flags Register (CPU_F) are all
cleared. The Interrupt Vector Register (INT_VC) holds
the interrupt vector for the highest priority pending inter-
rupt when read, and when written will clear all pending
interrupts.
If there is only one interrupt pending and an instruction is
executed that would mask that pending interrupt (by
clearing the corresponding bit in either of the interrupt
mask registers at address E0h or E1h in Bank 0), the
CPU will take that interrupt. Since the pending interrupt
has been cleared and there are no others, the resulting
interrupt vector is 0000h and the CPU will jump to the
user code at the beginning of Flash. To address this
issue, use the macro defined in m8c.inc called
"M8C_DisableIntMask" in PSoC Designer. This macro
brackets the register write with a disable then an enable
of global interrupts.
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Document #: 38-12010 CY Rev. *C
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Interrupts
General Interrupt Mask Register
Bit Bit Bit Bit Bit Bit Bit Bit
7
6
5
4
3
2
1
0
R
Interrupt
Source
IRQ
Q
IRQ
Flip Flop
“1”
D
IRQ
Priority
Decode
Logic
Interrupt
Vector Table
Interrupt Vector
IRQ
Reset or Decoded Int Ack
or Iwrite to INT_VC Register
R
Interrupt
Source
IRQ
Q
IRQ
Flip Flop
D
“1”
Bit Bit Bit Bit Bit Bit Bit Bit
7
6
5
4
3
2
1
0
Digital PSoC Block Interrupt
Mask Register
Figure 10: Interrupts Overview
May 17, 2005
Document #: 38-12010 CY Rev. *C
43
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Each digital PSoC block has its own unique Interrupt
8.2
Interrupt Control Architecture
Vector and Interrupt Enable bit. There are also individual
interrupt vectors for each of the Analog columns, Supply
Voltage Monitor, Sleep Timer and General Purpose I/Os.
The interrupt controller contains a separate flip-flop for
each interrupt. When an interrupt is generated, it is regis-
tered as a pending interrupt. It will stay pending until it is
serviced, a reset occurs, or there is a write to the
INT_VC Register. A pending interrupt will only generate
an interrupt request when enabled by the appropriate
mask bit in the Digital PSoC Block Interrupt Mask Regis-
ter (INT_MSK1) or General Interrupt Mask Register
(INT_MSK0), and the Global IE bit in the CPU_F register
is set.
8.3
Interrupt Vectors
Table 43: Interrupt Vector Table
Address
Description
Additionally, for GPIO Interrupts, the appropriate enable
and interrupt-type bits for each I/O pin must be set (see
section 6.0, Table 29 on page 31, Table 33 on page 33,
and Table 34 on page 34). For Analog Column Inter-
rupts, the interrupt source must be set (see section 10.10
and Table 77 on page 101).
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0040
1
2
3
4
5
6
7
8
9
Supply Monitor Interrupt Vector
DBA00 PSoC Block Interrupt Vector
DBA01 PSoC Block Interrupt Vector
DBA02 PSoC Block Interrupt Vector
DBA03 PSoC Block Interrupt Vector
DCA04 PSoC Block Interrupt Vector
DCA05 PSoC Block Interrupt Vector
DCA06 PSoC Block Interrupt Vector
DCA07 PSoC Block Interrupt Vector
During the servicing of any interrupt, the MSB and LSB
of Program Counter and Flag registers (CPU_PC and
CPU_F) are stored onto the program stack by an auto-
matic CALLinstruction (13 cycles) generated during the
interrupt acknowledge process. The user firmware may
preserve and restore processor state during an interrupt
using the PUSH and POP instructions. The memory ori-
ented CPU architecture requires minimal state saving
during interrupts, providing very fast interrupt context
switching. The Program Counter and Flag registers
(CPU_PC and CPU_F) are restored when the RETI
instruction is executed. If two or more interrupts are
pending at the same time, the higher priority interrupt
(lower priority number) will be serviced first.
10 Acolumn 0 Interrupt Vector
11 Acolumn 1 Interrupt Vector
12 Acolumn 2 Interrupt Vector
13 Acolumn 3 Interrupt Vector
14 GPIO Interrupt Vector
15 Sleep Timer Interrupt Vector
On-Chip Program Memory Starts
The interrupt process vectors the Program Counter to
the appropriate address in the Interrupt Vector Table.
Typically, these addresses contain JMP instructions to
the start of the interrupt handling routine for the interrupt.
After a copy of the Flag Register is stored on the stack,
the Flag Register is automatically cleared. This disables
all interrupts, since the Global IE flag bit is now cleared.
Executing a RETI instruction restores the Flag register,
and re-enables the Global Interrupt bit.
Nested interrupts can be accomplished by re-enabling
interrupts inside an interrupt service routine. To do this,
set the IE bit in the Flag Register. The user must store
sufficient information to maintain machine state if this is
done.
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Interrupts
8.4
Interrupt Masks
Table 44:
General Interrupt Mask Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
Reserved
Sleep
GPIO
Acolumn3 Acolumn2 Acolumn1 Acolumn0
Voltage Monitor
Bit 7: Reserved
Bit 6: Sleep Interrupt Enable Bit (see 11.4)
0 = Disabled
1 = Enabled
Bit 5: GPIO Interrupt Enable Bit (see 8.6)
0 = Disabled
1 = Enabled
Bit [4]: Acolumn 3 Interrupt Enable Bit (see 10.0)
0 = Disabled
1 = Enabled
Bit [3]: Acolumn 2 Interrupt Enable Bit (see 10.0)
0 = Disabled
1 = Enabled
Bit [2]: Acolumn 1 Interrupt Enable Bit (see 10.0)
0 = Disabled
1 = Enabled
Bit [1]: Acolumn 0 Interrupt Enable Bit (see 10.0)
0 = Disabled
1 = Enabled
Bit 0: Voltage Monitor Interrupt Enable Bit (see 11.5)
0 = Disabled
1 = Enabled
General Interrupt Mask Register (INT_MSK0, Address = Bank 0, E0h)
May 17, 2005
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45
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Table 45:
Bit #
Digital PSoC Block Interrupt Mask Register
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
POR
Read/Write
Bit Name
RW
RW
RW
RW
RW
DBA03
RW
DBA02
RW
DBA01
RW
DBA00
DCA07
DCA06
DCA05
DCA04
Bit 7: DCA07 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 6: DCA06 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 5: DCA05 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 4: DCA04 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 3: DBA03 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 2: DBA02 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 1: DBA01 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 0: DBA00 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Digital PSoC Block Interrupt Mask Register (INT_MSK1, Address = Bank 0, E1h)
8.5
Interrupt Vector Register
Table 46:
Interrupt Vector Register
Bit #
POR
7
0
6
0
5
0
4
0
3
0
2
1
0
0
0
0
Read/Write
Bit Name
RW
RW
RW
Data[5]
RW
RW
Data[3]
RW
RW
RW
Data[0]
Data[7]
Data[6]
Data[4]
Data[2]
Data[1]
Bit [7:0]: Data [7:0]
8-bit data value holds the interrupt vector for the highest priority pending interrupt. Writing to this register will clear all
pending interrupts
Interrupt Vector Register (INT_VC, Address = Bank 0, E2h)
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Interrupts
8.6
GPIO Interrupt
GPIO Interrupts are polarity configurable and pin-wise
maskable (within each Port’s pin configuration registers).
They all share the same interrupt priority and vector.
the Port x Interrupt Enable Registers (PRTxIE). There
are user selectable options to generate an interrupt on 1)
any change from the last read state, 2) rising edge, and
3) falling edge.
Any general purpose I/O can be used as an interrupt
source. The GPIO bit in the General Interrupt Mask Reg-
ister (INT_MSK0) must be set to enable pin interrupts, as
well as the enable bits for each pin, which are located in
When Interrupt on Change is selected, the state of the
GPIO pin is stored when the port is read. Changes from
this state will then assert the interrupt, if enabled.
R
“1”
D
IRQ
Q
All GPIO INTOUTs
To Priority
Decode Logic
GPIO Cell
OR
INTOUTn
PIN
Int Logic
GPIO Int Enable
BIT S, INT_MSK0
GPIO BIT IE
PORTX IE Register
(PRT0IE...PRT5IE)
Figure 11: GPIO Interrupt Enable Diagram
For a GPIO interrupt to occur, the following steps must
be taken:
6. Because the GPIO interrupts all share the same
interrupt vector, the source for the GPIO interrupt
must be cleared before any other GPIO interrupt will
occur (i.e., the OR gate in Figure 11: “ors” all of the
INTOUTn signals together). If any of the INTOUTn
signals are high, the flip-flop in Figure 11: will not
see a rising edge and no IRQ will occur.
1. The pin Drive Mode must be set so the pin can be
an input.
2. The pin must be enabled to generate an interrupt by
setting the appropriate bit in the Port interrupt
Enable Register (PRTxIE).
3. The edge type for the interrupt must be set in the
Port Interrupt Control 0 and Control 1 Registers
(PRTxIC0 and PRTxIC1). Edge type must be set to
a value other than 00.
4. The GPIO bit must be set in the General Interrupt
Mask Register (INT_MSK0).
5. The Global Interrupt Enable bit must be set.
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47
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
9.0
9.1
Digital PSoC Blocks
Introduction
PSoC blocks are user configurable system resources.
On-chip digital PSoC blocks reduce the need for many
MCU part types and external peripheral components.
Digital PSoC blocks can be configured to provide a wide
variety of peripheral functions. PSoC Designer Software
Integrated Development Environment provides auto-
mated configuration of PSoC blocks by simply selecting
the desired functions. PSoC Designer then generates
the proper configuration information and can print a
device data sheet unique to that configuration.
dependent on the overall block function selected by the
user.
The one Control Register (DBA00CR0-DCA07CR0) is
designated Control 0. The function of this register and its
bit mapping is dependent on the overall block function
selected by the user.
If the CPU frequency is 24 MHz and a PSoC timer/
counter of 24-bits or longer is operating at 48 MHz, a
write to the block Control Register to enable it (for exam-
ple, a call to Timer_1_Start) may not start the block prop-
erly. In the failure case, the first count will typically be
indeterminate as the upper bytes fail to make the first
count correctly. However, on the first terminal count, the
correct period will be loaded and counted thereafter.
Digital PSoC blocks provide up to eight, 8-bit multipur-
pose timers/counters supporting multiple event timers,
real-time clocks, Pulse Width Modulators (PWM), and
CRCs. In addition to all PSoC block functions, communi-
cation PSoC blocks support full-duplex UARTs and SPI
master or slave functions.
As shown in Figure 12:, there are a total of eight 8-bit
digital PSoC blocks in this device family configured as a
linear array. Four of these are the Digital Basic Type A
blocks and four are the Digital Communications Type A
blocks. Each of these digital PSoC blocks can be config-
ured independently, or used in combination.
Each digital PSoC block has a unique Interrupt Vector
and Interrupt Enable bit. Functions can be stopped or
started with a user-accessible Enable bit.
The Timer/Counter/CRC/PRS/Deadband functions are
available on the Digital Basic Type A blocks and also the
Digital Communications Type A blocks. The UART and
SPI communications functions are only available on the
Digital Communications Type A blocks.
There are three configuration registers: the Function
Register (DBA00FN-DCA07FN) to select the block func-
tion and mode, the Input Register (DBA00IN-DCA07IN)
to select data input and clock selection, and the Output
Register (DBA00OU-DCA07OU) to select and enable
function outputs.
The three data registers are designated Data
0
(DBA00DR0-DCA07DR0), Data (DBA00DR1-
1
DCA07DR1), and Data 2 (DBA00DR2-DCA07DR2). The
function of these registers and their bit mapping is
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Document #: 38-12010 CY Rev. *C
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Digital PSoC Blocks
Global Outputs [3:0]
Global Inputs [3:0]
DBA0
DBA1
DBA2
DBA3
(Basic Block)
(Basic Block)
(Basic Block)
(Basic Block)
*Decimator/
Incremental
*Broadcast
DCA4
DCA5
DCA6
DCA7
(Comm Block)
(Comm Block)
(Comm Block)
(Comm Block)
*Decimator/
Incremental
Global Inputs [7:4]
Global Outputs [7:4]
Figure 12: Digital Basic and Digital Communications PSoC Blocks
*Three of the digital blocks have special functions. DBA3 is a Broadcast block, with output directly available to
all digital blocks as a clock or data input. Blocks DBA2 and DCA6 have selectable connections to support
Delta Sigma and Incremental A/D converters.
9.2
Digital PSoC Block Bank 1
Registers
9.2.1 Digital Basic Type A / Communications
Type A Block xx Function Register
The Digital Basic Type A/ Communications Type A Block
xx Function Register (DBA00FN-DCA07FN) consists of
3 bits [2:0] to select the block function, 2 bits [4:3] to
select mode of operation, and 1 bit [5] to indicate the last
block in a group of chained blocks.
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Table 47:
Digital Basic Type A/ Communications Type A Block xx Function Register
Bit #
POR
7
0
6
0
5
0
4
0
3
0
2
1
0
0
0
0
Read/Write
Bit Name
RW
RW
RW
RW
RW
RW
RW
RW
Reserved Reserved End Mode 1
Mode 0
Function [2]
Function [1]
Function [0]
Bit 7: Reserved
Bit 6: Reserved
Bit 5: End
0 = PSoC block is not the end of a chained function (End should not be set to 0 in block DCA07)
1 = PSoC block is the end of a chained function, or is an unchained PSoC block
Bit 4: Mode 1 The definition of the Mode [1] bit depends on the block function selected
Timer: The Mode [1] bit signifies the Compare Type
0 = Less Than or Equal
1 = Less Than
Counter: The Mode [1] bit signifies the Compare Type
0 = Less Than or Equal
1 = Less Than
CRC/PRS: The Mode [1] bit is unused in this function
Deadband: The Mode [1] bit is unused in this function
UART: The Mode[1] bit signifies the Interrupt Type (Transmitter only)
0 = Transmit: Interrupt on TX_Reg Empty
1 = Transmit: Interrupt on TX Complete
SPI: The Mode[1] bit signifies the Interrupt Type
0 = Master: Interrupt on TX Reg Empty, Slave: Interrupt on RX Reg Full
1 = Master: Interrupt on SPI Complete, Slave: Interrupt on SPI Complete
Bit 3: Mode 0 The definition of the Mode [0] bit depends on the block function selected
Timer: The Mode [0] bit signifies Interrupt Type
0 = Terminal Count
1 = Compare True
Counter: The Mode [0] bit signifies Interrupt Type
0 = Terminal Count
1 = Compare True
CRC/PRS: The Mode [0] bit is unused in this function
Deadband: The Mode [0] bit is unused in this function
UART: The Mode [0] bit signifies the Direction
0 = Receive
1 = Transmit
SPI: The Mode [0] bit signifies the Type
0 = Master
1 = Slave
Bit [2:0]: Function [2:0] The Function [2:0] bits select the block function which determines the basic hardware configuration
0 0 0 = Timer (chainable)
0 0 1 = Counter (chainable)
0 1 0 = CRC/PRS (Cyclical Redundancy Checker or Pseudo Random Sequencer) (chainable)
0 1 1 = Reserved
1 0 0 = Deadband for Pulse Width Modulator
1 0 1 = UART (function only available on DCA type blocks)
1 1 0 = SPI (function only available on DCA type blocks)
1 1 1 = Reserved
Digital Basic Type A Block 00 Function Register
Digital Basic Type A Block 01 Function Register
Digital Basic Type A Block 02 Function Register
Digital Basic Type A Block 03 Function Register
Digital Communications Type A Block 04 Function Register
(DBA00FN, Address = Bank 1, 20h)
(DBA01FN, Address = Bank 1, 24h)
(DBA02FN, Address = Bank 1, 28h)
(DBA03FN, Address = Bank 1, 2Ch)
(DCA04FN, Address = Bank 1, 30h)
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Digital PSoC Blocks
Digital Communications Type A Block 05 Function Register
Digital Communications Type A Block 06 Function Register
Digital Communications Type A Block 07 Function Register
(DCA05FN, Address = Bank 1, 34h)
(DCA06FN, Address = Bank 1, 38h)
(DCA07FN, Address = Bank 1, 3Ch)
9.2.2
Digital Basic Type A / Communications Type A Block xx Input Register
The Digital Basic Type A / Communications Type A Block
xx Input Register (DBA00IN-DCA07IN) consists of 4 bits
[3:0] to select the block input clock and 4 bits [7:4] to
select the primary data/enable input. The actual usage of
the input data/enable is function dependent.
Table 48:
Digital Basic Type A / Communications Type A Block xx Input Register
Bit #
POR
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Read/Write
Bit Name
RW
RW
RW
RW
RW
RW
RW
RW
Data [3]
Data [2]
Data [1] Data [0] Clock [3]
Clock [2]
Clock [1]
Clock [0]
Bit [7:4]: Data [3:0] Data Enable Source Select
0 0 0 0 = Data = 0
0 0 0 1 = Data = 1
0 0 1 0 = Digital Block 03
0 0 1 1 = Chain Function to Previous Block
0 1 0 0 = Analog Column Comparator 0
0 1 0 1 = Analog Column Comparator 1
0 1 1 0 = Analog Column Comparator 2
0 1 1 1 = Analog Column Comparator 3
1 0 0 0 = Global Output[0] (for Digital Blocks 00 to 03) or Global Output[4] (for Digital Blocks 04 to 07)
1 0 0 1 = Global Output[1] (for Digital Blocks 00 to 03) or Global Output[5] (for Digital Blocks 04 to 07)
1 0 1 0 = Global Output[2] (for Digital Blocks 00 to 03) or Global Output[6] (for Digital Blocks 04 to 07)
1 0 1 1 = Global Output[3] (for Digital Blocks 00 to 03) or Global Output[7] (for Digital Blocks 04 to 07)
1 1 0 0 = Global Input[0] (for Digital Blocks 00 to 03) or Global Input[4] (for Digital Blocks 04 to 07)
1 1 0 1 = Global Input[1] (for Digital Blocks 00 to 03) or Global Input[5] (for Digital Blocks 04 to 07)
1 1 1 0 = Global Input[2] (for Digital Blocks 00 to 03) or Global Input[6] (for Digital Blocks 04 to 07)
1 1 1 1 = Global Input[3] (for Digital Blocks 00 to 03) or Global Input[7] (for Digital Blocks 04 to 07)
Bit [3:0]: Clock [3:0] Clock Source Select
0 0 0 0 = Clock Disabled
0 0 0 1 = Global Output[4] (for Digital Blocks 00 to 03) or Global Output[0] (for Digital Blocks 04 to 07)
0 0 1 0 = Digital Block 03 (Primary Output)
0 0 1 1 = Previous Digital PSoC block (Primary Output)
0 1 0 0 = 48M
0 1 0 1 = 24V1
0 1 1 0 = 24V2
0 1 1 1 = 32k
1 0 0 0 = Global Output[0] (for Digital Blocks 00 to 03) or Global Output[4] (for Digital Blocks 04 to 07)
1 0 0 1 = Global Output[1] (for Digital Blocks 00 to 03) or Global Output[5] (for Digital Blocks 04 to 07)
1 0 1 0 = Global Output[2] (for Digital Blocks 00 to 03) or Global Output[6] (for Digital Blocks 04 to 07)
1 0 1 1 = Global Output[3] (for Digital Blocks 00 to 03) or Global Output[7] (for Digital Blocks 04 to 07)
1 1 0 0 = Global Input[0] (for Digital Blocks 00 to 03) or Global Input[4] (for Digital Blocks 04 to 07)
1 1 0 1 = Global Input[1] (for Digital Blocks 00 to 03) or Global Input[5] (for Digital Blocks 04 to 07)
1 1 1 0 = Global Input[2] (for Digital Blocks 00 to 03) or Global Input[6] (for Digital Blocks 04 to 07)
1 1 1 1 = Global Input[3] (for Digital Blocks 00 to 03) or Global Input[7] (for Digital Blocks 04 to 07)
Digital Basic Type A Block 00 Input Register
Digital Basic Type A Block 01 Input Register
Digital Basic Type A Block 02 Input Register
Digital Basic Type A Block 03 Input Register
Digital Communications Type A Block 04 Input Register
Digital Communications Type A Block 05 Input Register
(DBA00IN, Address = Bank 1, 21h)
(DBA01IN, Address = Bank 1, 25h)
(DBA02IN, Address = Bank 1, 29h)
(DBA03IN, Address = Bank 1, 2Dh)
(DCA04IN, Address = Bank 1, 31h)
(DCA05IN, Address = Bank 1, 35h)
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Digital Communications Type A Block 06 Input Register
Digital Communications Type A Block 07 Input Register
(DCA06IN, Address = Bank 1, 39h)
(DCA07IN, Address = Bank 1, 3Dh)
The Data/Enable source select [3:0] bits select between
multiple inputs to the Digital PSoC Blocks. These inputs
serve as Clock Enables or Data Input depending on the
Digital PSoC Block’s programmed function. If “Chain
Function to Previous” data input is selected for Data/
Enable then the selected Digital PSoC block receives its
Data, Enable, Zero Detect, and all chaining information
from the previous digital PSoC block. The data inputs
that are selected from the GPIO pins (through the Global
Input Bus) are synchronized to the 24 MHz clock. The
following table shows the function dependent meaning of
the data input.
The Clock[3:0] bits select multiple sources for the clock
for each digital PSoC block. The sources for each digital
PSoC block clock are selected from the Global Input
Bus, System Clocks, and other neighboring digital PSoC
blocks. As shown in the table, Digital PSoC Blocks 0-3
can interface to Global I/Os 00-03, and Digital PSoC
block 04-07 can interface to Global I/Os 4-7. It is impor-
tant to note that clock inputs selected from the GPIO pins
(through the Global Input Bus) are not synchronized.
This may cause indeterminate results if the CPU reads a
block register as it is changing in response to an external
clock. CPU reads must be manually synchronized, either
through the block interrupt, or through a multiple read
and voting scheme.
Table 49:
Digital Function Data Input Definitions
Function
Data Input
Positive Edge Capture
Count Enable (Active High)
Data Input
Timer
Counter
CRC
PRS
N/A
Deadband
TX UART
RX UART
SPI Master
SPI Slave
Kill Signal (Active High)
N/A
RX Data In
MISO (Master In/Slave Out)
MOSI (Master Out/Slave In)
9.2.3
Digital Basic Type A / Communications Type A Block xx Output Register
The digital PSoC block’s outputs can be selected to drive
associated Global Output Bus signals via the Output
Select bits. In addition, the output drive can be selec-
tively enabled in this register. The SPI Slave has an aux-
iliary input which is also controlled by selections in this
register.
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Digital PSoC Blocks
Table 50:
Digital Basic Type A / Communications Type A Block xx Output Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
AUX Out
Enable
AUX IO Sel
[1]
AUX IO Sel
[0]
Out
Enable
Out Sel
[1]
Out Sel
[0]
Bit Name
Reserved
Reserved
Bit 7: Reserved
Bit 6: Reserved
Bit 5: AUX Out Enable
0 = Disable Auxiliary Output
1 = Enable Auxiliary Output (function dependent)
Bit [4:3]: AUX IO Sel [1:0] Function-dependent selection of auxiliary input or output
0 0 = Drive Global Output[0] (for Digital Blocks 00 to 03) or
Input from Global Input[4] or Drive Global Output [4] (for Digital Blocks 04 to 07)
0 1 = Drive Global Output[1] (for Digital Blocks 00 to 03) or
Input from Global Input[5] or Drive Global Output[5] (for Digital Blocks 04 to 07)
1 0 = Drive Global Output[2] (for Digital Blocks 00 to 03) or
Input from Global Input[6] or Drive Global Output[6] (for Digital Blocks 04 to 07)
1 1 = Drive Global Output[3] (for Digital Blocks 00 to 03) or
Input from Global Input[7] or Drive Global Output[7] (for Digital Blocks 04 to 07)
Bit 2: Out Enable
0 = Disable Primary Output
1 = Enable Primary Output (function dependant)
Bit [1:0]: Out Sel [1:0] Primary Output
0 0 = Drive Global Output[0] (for Digital Blocks 00 to 03) or Drive Global Output[4] (for Digital Blocks 04 to 07)
0 1 = Drive Global Output[1] (for Digital Blocks 00 to 03) or Drive Global Output[5] (for Digital Blocks 04 to 07)
1 0 = Drive Global Output[2] (for Digital Blocks 00 to 03) or Drive Global Output[6] (for Digital Blocks 04 to 07)
1 1 = Drive Global Output[3] (for Digital Blocks 00 to 03) or Drive Global Output[7] (for Digital Blocks 04 to 07)
Digital Basic Type A Block 00 Output Register
Digital Basic Type A Block 01 Output Register
Digital Basic Type A Block 02 Output Register
Digital Basic Type A Block 03 Output Register
Digital Communications Type A Block 04 Output Register
Digital Communications Type A Block 05 Output Register
Digital Communications Type A Block 06 Output Register
Digital Communications Type A Block 07 Output Register
(DBA00OU, Address = Bank 1, 22h)
(DBA01OU, Address = Bank 1, 26h)
(DBA02OU, Address = Bank 1, 2Ah)
(DBA03OU, Address = Bank 1, 2Eh)
(DCA04OU, Address = Bank 1, 32h)
(DCA05OU, Address = Bank 1, 36h)
(DCA06OU, Address = Bank 1, 3Ah)
(DCA07OU, Address = Bank 1, 3Eh)
The Primary Output is the source for “Previous Digital PSoC Block” or “Digital Block 03,” selections for the “Clock
Source Select” in the Digital Basic Type A/Communications Type A Block xx Input Register (Table 48 on page 51).
A digital PSoC block may have 0, 1, or 2 outputs depending on its function, as shown in the following table:
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Table 51:
Function
Digital Function Outputs
Primary Output
Auxiliary Output
Compare True
Auxiliary Input
N/A
Timer
Terminal Count
Compare True
N/A
Counter
CRC
Terminal Count
N/A
N/A
N/A
N/A
N/A
N/A
N/A
SS_
Compare True
PRS
Serial Data
F0
Compare True
Deadband
TX UART
RX UART
SPI Master
SPI Slave
F1
TX Data Out
N/A
N/A
N/A
SCLK
N/A
MOSI
MISO
9.3
Digital PSoC Block Bank 0 Registers
There are four user registers within each digital PSoC
block: three data registers, and one status/control regis-
ter. The three data registers are DR0, which is a shifter/
counter, and DR1 and DR2 registers, which contain data
used during the operation. The status/control register
(CR0) contains an enable bit that is used for all configu-
rations. In addition, it contains function-specific status
and control, which is outlined below.
9.3.1
Digital Basic Type A / Communications Type A Block xx Data Register 0,1,2
Digital Basic Type A / Communications Type A Block xx Data Register 0,1,2
Table 52:
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Read/Write
Bit Name
VF
VF
VF
VF
VF
VF
VF
VF
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]: Data [7:0]
1. Varies by function/User Module selection. (See Table 53 on page 55.)
Digital Basic Type A Block 00 Data Register 0
Digital Basic Type A Block 00 Data Register 1
Digital Basic Type A Block 00 Data Register 2
Digital Basic Type A Block 01 Data Register 0
Digital Basic Type A Block 01 Data Register 1
Digital Basic Type A Block 01 Data Register 2
Digital Basic Type A Block 02 Data Register 0
Digital Basic Type A Block 02 Data Register 1
Digital Basic Type A Block 02 Data Register 2
Digital Basic Type A Block 03 Data Register 0
Digital Basic Type A Block 03 Data Register 1
Digital Basic Type A Block 03 Data Register 2
Digital Communications Type A Block 04 Data Register 0
Digital Communications Type A Block 04 Data Register 1
Digital Communications Type A Block 04 Data Register 2
Digital Communications Type A Block 05 Data Register 0
Digital Communications Type A Block 05 Data Register 1
Digital Communications Type A Block 05 Data Register 2
Digital Communications Type A Block 06 Data Register 0
Digital Communications Type A Block 06 Data Register 1
(DBA00DR0, Address = Bank 0, 20h)
(DBA00DR1, Address = Bank 0, 21h)
(DBA00DR2, Address = Bank 0, 22h)
(DBA01DR0, Address = Bank 0, 24h)
(DBA01DR1, Address = Bank 0, 25h)
(DBA01DR2, Address = Bank 0, 26h)
(DBA02DR0, Address = Bank 0, 28h)
(DBA02DR1, Address = Bank 0, 29h)
(DBA02DR2, Address = Bank 0, 2Ah)
(DBA03DR0, Address = Bank 0, 2Ch)
(DBA03DR1, Address = Bank 0, 2Dh)
(DBA03DR2, Address = Bank 0, 2Eh)
(DCA04DR0, Address = Bank 0, 30h)
(DCA04DR1, Address = Bank 0, 31h)
(DCA04DR2, Address = Bank 0, 32h)
(DCA05DR0, Address = Bank 0, 34h)
(DCA05DR1, Address = Bank 0, 35h)
(DCA05DR2, Address = Bank 0, 36h)
(DCA06DR0, Address = Bank 0, 38h)
(DCA06DR1, Address = Bank 0, 39h)
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Digital PSoC Blocks
Digital Communications Type A Block 06 Data Register 2
Digital Communications Type A Block 07 Data Register 0
Digital Communications Type A Block 07 Data Register 1
Digital Communications Type A Block 07 Data Register 2
(DCA06DR2, Address = Bank 0, 3Ah)
(DCA07DR0, Address = Bank 0, 3Ch)
(DCA07DR1, Address = Bank 0, 3Dh)
(DCA07DR2, Address = Bank 0, 3Eh)
Table 53:
Function
Timer
R/W Variations per User Module Selection
DR0
R/W
DR1
Period Value
R/W
DR2
Capture Value
Compare Value
Seed Value
R/W
RW
1
Count
Count
W
R
1
1
1
1
Counter
CRC
Period Value
W
W
W
RW
RW
RW
R
R
R
R
Current Value/CRC Residue
Current Value
Polynomial Mask Value
Polynomial Mask Value
PRS
Seed Value
Deadband Count
Period Value
Not Used
W
Not Used
RW
R
RX UART
TX UART
SPI
Shifter
Shifter
Shifter
NA
NA
NA
NA
W
Data Register
Not Used
Data Register
TX Data Register
NA
R
RX Data Register
1. Each time the register is read, its value is written to the DR2 register.
9.3.2
Digital Basic Type A / Communications Type A Block xx Control Register 0
Digital Basic Type A / Communications Type A Block xx Control Register 0
Table 54:
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Read/Write
Bit Name
VF
VF
VF
VF
VF
VF
VF
VF
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]: Data [7:0]
1. Varies by function.
Digital Basic Type A Block 00 Control Register 0
Digital Basic Type A Block 01 Control Register 0
Digital Basic Type A Block 02 Control Register 0
Digital Basic Type A Block 03 Control Register 0
Digital Communications Type A Block 04 Control Register 0
Digital Communications Type A Block 05 Control Register 0
Digital Communications Type A Block 06 Control Register 0
Digital Communications Type A Block 07 Control Register 0
(DBA00CR0, Address = Bank 0, 23h)
(DBA01CR0, Address = Bank 0, 27h)
(DBA02CR0, Address = Bank 0, 2Bh)
(DBA03CR0, Address = Bank 0, 2Fh)
(DCA04CR0, Address = Bank 0, 33h)
(DCA05CR0, Address = Bank 0, 37h)
(DCA06CR0, Address = Bank 0, 3Bh)
(DCA07CR0, Address = Bank 0, 3Fh)
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
9.3.3
Digital Basic Type A/Communications Type A Block xx Control Register 0 When Used
as Timer, Counter, CRC, and Deadband
Note that the data in this register, as well as the following
three registers, are a mapping of the functions of the
variables selected in the associated Digital Basic Type A/
Communications Type A Block xx Control Register 0.
Table 55:
Digital Basic Type A/Communications Type A Block xx Control Register 0...
Bit #
POR
7
--
--
6
--
--
5
--
--
4
--
--
3
--
--
2
--
--
1
--
--
0
0
Read/Write
Bit Name
RW
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Enable
Bit 7: Reserved
Bit 6: Reserved
Bit 5: Reserved
Bit 4: Reserved
Bit 3: Reserved
Bit 2: Reserved
Bit 1: Reserved
Bit 0: Enable
0 = Function Disabled
1 = Function Enabled
Digital Basic Type A Block 00 Control Register 0
Digital Basic Type A Block 01 Control Register 0
Digital Basic Type A Block 02 Control Register 0
Digital Basic Type A Block 03 Control Register 0
Digital Communications Type A Block 04 Control Register 0
Digital Communications Type A Block 05 Control Register 0
Digital Communications Type A Block 06 Control Register 0
Digital Communications Type A Block 07 Control Register 0
(DBA00CR0, Address = Bank 0, 23h)
(DBA01CR0, Address = Bank 0, 27h)
(DBA02CR0, Address = Bank 0, 2Bh)
(DBA03CR0, Address = Bank 0, 2Fh)
(DCA04CR0, Address = Bank 0, 33h)
(DCA05CR0, Address = Bank 0, 37h)
(DCA06CR0, Address = Bank 0, 3Bh)
(DCA07CR0, Address = Bank 0, 3Fh)
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Digital PSoC Blocks
9.3.4
Digital Communications Type A Block xx Control Register 0 When Used as UART Trans-
mitter
Table 56:
Digital Communications Type A Block xx Control Register 0...
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
--
--
R
R
--
RW
RW
RW
TX Reg
Empty
Parity
Enable
Bit Name
Reserved Reserved
TX Complete
Reserved Parity Type
Enable
Bit 7: Reserved
Bit 6: Reserved
Bit 5: TX Complete
0 = Indicates that if a transmission has been initiated, it is still in progress
1 = Indicates that the current transmission is complete (including framing bits)
Optional interrupt source for TX UART. Reset when this register is read.
Bit 4: TX Reg Empty
0 = Indicates TX Data register is not available to accept another byte (writing to register will cause data to be lost)
1 = Indicates TX Data register is available to accept another byte
Note that the interrupt does not occur until at least 1 byte has been previously written to the TX Data Register
Default interrupt source for TX UART. Reset when the TX Data Register (Data Register 1) is written.
Bit 3: Reserved
Bit 2: Parity Type
0 = Even
1 = Odd
Bit 1: Parity Enable
0 = Parity Disabled
1 = Parity Enabled
Bit 0: Enable
0 = Function Disabled
1 = Function Enabled
Digital Communications Type A Block 04 Control Register 0
Digital Communications Type A Block 05 Control Register 0
Digital Communications Type A Block 06 Control Register 0
Digital Communications Type A Block 07 Control Register 0
(DCA04CR0, Address = Bank 0, 33h)
(DCA05CR0, Address = Bank 0, 37h)
(DCA06CR0, Address = Bank 0, 3Bh)
(DCA07CR0, Address = Bank 0, 3Fh)
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
9.3.5
Digital Communications Type A Block xx Control Register 0 When Used as UART
Receiver
Table 57:
Digital Communications Type A Block xx Control Register 0...
Bit #
POR
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Read/Write
R
R
R
R
R
RW
RW
RW
Parity
Error
Framing
Error
RX Reg
Full
Parity
Type
Parity
Enable
Bit Name
Overrun
RX Active
Enable
Bit 7: Parity Error
0 = Indicates no parity error detected in the last byte received
1 = Indicates a parity error detected in the last byte received
Reset when this register is read
Bit 6: Overrun
0 = Indicates that no overrun has taken place
1 = Indicates the RX Data register was overwritten with a new byte before the previous one had been read
Reset when this register is read
Bit 5: Framing Error
0 = Indicates correct stop bit
1 = Indicates a missing STOP bit
Reset when this register is read
Bit 4: RX Active
0 = Indicates no communication currently in progress
1 = Indicates a start bit has been received and a byte is currently being received
Bit 3: RX Reg Full
0 = Indicates the RX Data register is empty
1 = Indicates a byte has been loaded into the RX Data register
Interrupt source for RXUART. Reset when the RX Data register is read (Data Register 2)
Bit 2: Parity Type
0 = Even
1 = Odd
Bit 1: Parity Enable
0 = Parity Disabled
1 = Parity Enabled
Bit 0: Enable
0 = Function Disabled
1 = Function Enabled
Digital Communications Type A Block 04 Control Register 0
Digital Communications Type A Block 05 Control Register 0
Digital Communications Type A Block 06 Control Register 0
Digital Communications Type A Block 07 Control Register 0
(DCA04CR0, Address = Bank 0, 33h)
(DCA05CR0, Address = Bank 0, 37h)
(DCA06CR0, Address = Bank 0, 3Bh)
(DCA07CR0, Address = Bank 0, 3Fh)
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Digital PSoC Blocks
9.3.6
Digital Communications Type A Block xx Control Register 0 When Used as SPI Trans-
ceiver
Table 58:
Digital Communications Type A Block xx Control Register 0...
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
R
R
R
R
RW
RW
RW
TX Reg
Empty
RX Reg
Full
Clock
Phase
Clock
Polarity
Bit Name
LSB First
Overrun
SPI Complete
Enable
Bit 7: LSB First
0 = MSB First
1 = LSB First
Bit 6: Overrun
0 = Indicates that no overrun has taken place
1 = Indicates the RX Data register was overwritten with a new byte before the previous one had been read
Reset when this register is read
Bit 5: SPI Complete
0 = Indicates the byte is in process of shifting out
1 = Indicates the byte has been shifted out (reset when register is read)
Optional interrupt source for both SPI Master and SPI Slave. Reset when this register is read
Bit 4: TX Reg Empty
0 = Indicates the TX Data register is not available to accept another byte
1 = Indicates the TX Data register is available to accept another byte
Default interrupt source for SPI Master. Reset when the TX Data Register (Data Register 1) is written.
Bit 3: RX Reg Full
0 = Indicates the RX Data register is empty
1 = Indicates a byte has been loaded into the RX Data register
Default interrupt source for SPI Slave. Reset when the RX Data Register (Data Register 2) is read
Bit 2: Clock Phase
0 = Data changes on leading edge and is latched on trailing edge
1 = Data is latched on leading edge and is changed on trailing edge
Bit 1: Clock Polarity
0 = Non-inverted (clock idle state is low)
1 = Inverted (clock idle state is high)
Bit 0: Enable
0 = Function Disabled
1 = Function Enabled
Digital Communications Type A Block 04 Control Register 0
Digital Communications Type A Block 05 Control Register 0
Digital Communications Type A Block 06 Control Register 0
Digital Communications Type A Block 07 Control Register 0
(DCA04CR0, Address = Bank 0, 33h)
(DCA05CR0, Address = Bank 0, 37h)
(DCA06CR0, Address = Bank 0, 3Bh)
(DCA07CR0, Address = Bank 0, 3Fh)
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
This allows digital PSoC blocks to route their inputs and
outputs to pins using the global I/O buses.
9.4
Global Inputs and Outputs
Global Inputs and Outputs provide additional capability
to route clock and data signals to the digital PSoC
blocks. Digital PSoC blocks are connected to the global
input and output lines by configuring the PSoC block
Input and Output registers (DBA00IN-DCA07IN,
DBA00OU-DCA07OU). These global input and output
lines form an 8-bit global input bus and an 8-bit global
output bus. Four Digital PSoC blocks have access to the
upper half of these buses, while the other four access
the lower half, per the configuration register. These glo-
bal input/output buses may be connected to the I/O pins
on a per-pin basis using the pin configuration registers.
9.4.1 Input Assignments
The PSoC block Input Register defines the selection of
Global Inputs to digital PSoC blocks. Only 4 of the Global
Inputs bus lines are available as selections to a given
digital PSoC block as shown in the table below. Once the
Global Input has been selected using the PSoC block
Input Register selection bits, a GPIO pin must be config-
ured to drive the selected Global Input. This configura-
tion may be set in the Port Global Select Register. The
GPIO direction must also be set to input mode by config-
uring the Port Drive Mode Registers to select High Z.
Table 59:
Global Input Assignments
Global
Global
Global
Global
Global
Global
Global
Global
Input [7]
Input [6]
Input [5]
Input [4]
Input [3]
Input [2]
Input [1]
Input [0]
Port x[7]
Port x[6]
Port x[5]
Port x[4]
Port x[3]
Port x[2]
Port x[1]
Port x[0]
PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07
PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07
PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07
PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07
PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03
PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03
PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03
PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03
9.4.2
Output Assignments
The PSoC block Output Register defines the selection of
the Global Output bus line to be driven by the digital
PSoC blocks. Only 4 of the Global Output bus lines are
available as selections to a given digital PSoC block as
shown in the table below. The Global Output bus has two
functions. Since Global Outputs are also selectable as
inputs to digital PSoC blocks, signals can be routed
between blocks using this bus. In addition, Global Out-
puts may drive out to GPIO pins. In this case, once the
Global Output has been selected using the PSoC block
Output Register selection bits, a GPIO pin must be con-
figured to select the Global Output to drive to the pin.
This configuration may be set in the Port Global Select
Register. The GPIO direction must also be set to output
mode (which is the default) by configuring the Port Drive
Mode Registers to one of the available driving strengths.
Table 60:
Global Output Assignments
Global
Global
Global
Global
Global
Global
Global
Global
Output [7]
Output [6]
Output [5]
Output [4]
Output [3]
Output [2]
Output [1]
Output [0]
Port x[7]
Port x[6]
Port x[5]
Port x[4]
Port x[3]
Port x[2]
Port x[1]
Port x[0]
PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07
PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07
PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07
PSoC Block 04
PSoC Block 05
PSoC Block 06
PSoC Block 07
PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03
PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03
PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03
PSoC Block 00
PSoC Block 01
PSoC Block 02
PSoC Block 03
9.5
Available Programmed Digital Functionality
9.5.1
9.5.1.1
Timer with Optional Capture
generator. A down counter lies at the heart of the timer
functions. Rate generators divide their clock source by
an integer value. Hardware or software generated events
Summary
The timer function continuously measures the amount of
time in “ticks” between two events, and provides a rate
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Digital PSoC Blocks
trigger capture operations that permit calculation of
elapsed “ticks.” Timer-configured PSoC blocks may be
chained to arbitrary lengths in 8 bit increments.
current count is less than (or less than or equal to) the
value in Data Register 2 (compare type controlled by
Mode[1] in the PSoC block Function Register). The auxil-
iary output can be routed via Global Output lines. The
PSoC block Output Register (DBA00OU-DCA07OU)
controls output options.
9.5.1.2
Registers
Data Register 1 establishes the period or integer clock
division value. Data Register 0 holds the current state of
the down counter. If the function is disabled, writing a
period into Data Register 1, will automatically load Data
Register 0. It is also automatically reloaded on the clock
cycle after it reaches zero, the terminal count value.
When a capture event occurs, the current value of Data
Register 0 is transferred to Data Register 2. The cap-
tured value in Data Register 2 may then be read by the
CPU. In addition to the hardware capture input, A CPU
read of Data Register 0 generates a software capture
event. This read will return 0 as data. A subsequent read
of Data Register 2 will return the captured value. Control
Register 0 contains one bit to enable/disable the func-
tion.
9.5.1.5
Interrupts
Interrupts may be generated in either of two ways. First,
the PSoC block may optionally generate an interrupt on
the rising edge of Terminal Count or the rising edge of
the Compare True signal. The selection of interrupt
source is determined by the MODE[0] bit of the PSoC
block Function Register (DBA00FN-DCA07FN). The
MODE[1] bit controls whether the comparison operation
is “less than” or “less than or equal to.” If capture events
are disabled, Data Register 2 can be used to create a
periodic interrupt with a particular offset from the terminal
count.
9.5.1.6
1. Constraints
Hardware/software synchronous capture is only
Usage Notes
9.5.1.3
Inputs
There are two inputs, the Source Clock and the Hard-
ware Capture signal. The down counter is decremented
on the rising-edge of the Source Clock. A hardware cap-
ture event is signaled by a rising edge of the Hardware
Capture signal. This is synchronized to the 24 MHz sys-
tem clock and the data is synchronously transferred to
Data Register 2. The Hardware Capture Signal is OR’ed
with a software capture signal that is generated when
Data Register 0 is read directly by the CPU. In order to
use the software capture mechanism, the Hardware
Capture signal input selection must be low. The multi-
plexers selecting these input sources are controlled by
the PSoC block Input Register (DBA00IN-DCA07IN).
available with a clocking rate of 24 MHz and below.
2. Software Capture
When a capture event occurs, all bytes in a multi-
byte timer transfer simultaneously from the current
count (Data Register 0) to the capture register (Data
Register 2). To generate a software capture event,
only the least significant Data Register 0 byte needs
to be read by the CPU. This causes the same simul-
taneous transfer as a hardware event.
3. Disabled State
When the Control Register Enable bit is set to ‘0’,
the internal block clock is turned off. A write to Data
Register 1 (Period) is loaded directly into Data Reg-
ister 0 (Counter) to initialize or reset the count. All
outputs are low and the block interrupt is held low.
Disabling a timer does not affect the current count
value and it may be read by the CPU. However,
since hardware/software capture is disabled in this
state, two reads are required to read each byte of a
multi-byte register. One to transfer each Data Regis-
ter 0 count value to the associated Data Register 2
capture register, then one to read the result in Data
Register 2.
9.5.1.4
Outputs
The Terminal Count signal is the primary output and it
exhibits a duty cycle that is the reciprocal of the period
value contained in Data Register 1. In other words, it is
high during the source clock cycle when the value in
Data Register 0 is zero and low otherwise. The Terminal
Count can be routed to additional analog or digital PSoC
blocks or via Global Output lines. The auxiliary output is
the Compare True signal. This output is high when the
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
4. Capture vs. Compare
Register 2.
Control Register 0 contains one bit to
enable/disable the function.
A capture event will overwrite Data Register 2. This
is also the register that holds the compare value.
Therefore, using the capture function may not be
compatible with using the timer compare function.
9.5.2.3
Inputs
There are two primary inputs, the Source Clock and the
Enable signal. When the Enable signal is high, the down
counter is decremented on the rising-edge of the Source
Clock. The multiplexers selecting these inputs are con-
trolled by the PSoC block Input Register (DBA00IN-
DCA07IN).
9.5.2 Counter with Optional Compare (Pulse-
Width) Output
9.5.2.1
Summary
Conceptually, a counter measures the number of events
between “ticks,” however, this distinction between
counter and timer blurs because both functions provide a
complete range of clock selections. The counter trades
the timer’s hardware capture for a clock gate or ”enable”
and provides a means of adjusting the duty cycle of its
output so that it can double as a pulse-width modulator.
A down counter lies at the heart of the counter function.
Counter-configured PSoC blocks may be chained to
arbitrary lengths in 8 bit increments.
9.5.2.4
Outputs
The counter function drives its primary output signal,
Compare True, high on the falling edge of the Source
Clock when the value in Data Register 0 is less (or less
than or equal to) the value in Data Register 2. The duty
cycle of the pulse-width modulator formed in this way is
the ratio of Data Register 2 (or Data Register 2 minus
one) to Data Register 1. The choice of compare opera-
tors is determined by the MODE[1] bit. The Compare
value can be routed to additional analog or digital PSoC
blocks or via Global Output lines The auxiliary output sig-
nal is the Terminal Count signal which can be routed via
Global Output lines. The PSoC block Output Register
(DBA00OU-DCA07OU) controls output options.
In a Counter User Module, the data input is an enable for
counting. Normally, when the enable goes low, the
counter will hold the current count. However, if the
enable happens to go low in the same clock period as
Terminal Count (count of all 0's), one additional count will
occur that will reload the counter from the Period Regis-
ter. Once the counter is reloaded from the Period Regis-
ter, counting will stop.
9.5.2.5
Interrupts
Interrupts may be generated in either of two ways. First,
the PSoC block may optionally generate an interrupt on
the rising edge of Terminal Count or the rising edge of
the Compare signal. The selection of interrupt source is
determined by the MODE[0] bit of the PSoC block Func-
tion Register (DBA00FN-DCA07FN). The MODE[1] bit
controls whether the comparison operation is “less than”
or “less than or equal to.”
9.5.2.2
Registers
Data Register 1 establishes the period of the counter.
Data Register 0 holds the current state of the down
counter. If the function is disabled, writing a period into
Data Register 1, will automatically load Data Register 0.
It is also automatically reloaded on the clock cycle after it
reaches zero, the terminal count value. The value in
Data Register 2 (compare value) is continually compared
to Data Register 0 (count value) to establish the output
pulse-width (duty cycle). Reading Data Register 0 to
obtain the current value of the down counter may occur
only when the function is disabled. When read, this
transfers the value from Data Register 0 to Data Register
2 and returns a 0 on the data bus. The value transferred
to Data Register 2 can then be directly read by the CPU.
However, reading the count value in this manner will
overwrite any previously written compare value in Data
9.5.2.6
1. Enable Input
The enable input is synchronous and when low
Usage Notes
forces the counter into a ‘hold’ state. Outputs are
unaffected by the state of the enable input. If an
external source is selected as the enable input, it is
synchronized to the 24 MHz clock.
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Digital PSoC Blocks
2. Disabled State
9.5.3.2
Registers
When the Control Register Enable bit is set to ‘0’,
the internal block clock is turned off. A write to Data
Register 1 (Period) is loaded directly into Data Reg-
ister 0 (Counter) to initialize or reset the count. All
outputs are low and the block interrupt is held low.
Disabling a counter does not affect the current count
value and it may be read by the CPU. Two reads are
required to read each byte of a multi-byte register.
One to transfer each Data Register 0 count value to
the associated Data Register 2 capture register,
then one to read the result in Data Register 2.
Data Register 1 stores the count that controls the
elapsed dead time. Data Register 0 holds the current
state of the dead-time down counter. If the function is
disabled, writing a period into Data Register 1, will auto-
matically load Data Register 0 with the deadband period.
This period is automatically re-loaded into the counter on
each edge of the input signal. Data Register 2 is unused.
Control Register 0 contains one bit to enable/disable the
function.
3. Reading the Count Value
9.5.3.3
Inputs
A CPU read of Data Register 0 (count value) will
overwrite Data Register 2 (compare value). There-
fore, when reading the current count, a previously
written compare value will be overwritten.
The input controls the period and duty cycle of the dead-
band generator outputs. This input is fixed to be derived
from the primary output of the previous block. If this sig-
nal is pulse-width modulated, i.e., if a PWM block is con-
figured as the previous block, the dead-band outputs will
be similarly modulated. The F0 output corresponds to
the duty cycle of the input (less the dead time) and F1 to
the duty cycle of the inverted input (again, less the dead
time). The clock input to the dead-band generator con-
trols the rate at which the down counter is decremented.
The primary data input is the “Kill” Signal. When this sig-
nal is asserted high, both F0 and F1 outputs will go low.
The multiplexers selecting these input are controlled by
the PSoC block Input Register (DBA00IN-DCA07IN).
4. Extra Count
In a Counter User Module, the data input is an
enable for counting. Normally, when the enable
goes low, the counter will hold the current count.
However, if the enable happens to go low in the
same clock period as Terminal Count (count of all
0's), one additional count will occur that will reload
the counter from the Period Register. Once the
counter is reloaded from the Period Register, count-
ing will stop.
9.5.3 Deadband Generator
9.5.3.1
Summary
9.5.3.4
Outputs
The Deadband function produces two output waveforms,
F0 and F1, with the same frequency as the input, but
“under-lapped” so they are never both high at the same
time. An 8-bit down counter controls the length of the
“dead time” during which both output signals are low.
When the deadband function detects a rising edge on
the input waveform, the F1 output signal goes low and
the counter decrements from its initial value to its termi-
nal count. When the down counter reaches zero, the F0
output signal goes high. The process reverses on the
falling edge of the input waveform so that after the same
dead time, F1 goes high until the input signal transitions
again. Dead-band generator PSoC blocks cannot be
chained to increase the width of the down counter
beyond 8 bits or 256 dead-time “ticks.”
Both the F0 and F1 outputs can be driven onto the Glo-
bal Output bus. If the next PSoC block selects “Previous
PSoC block” for its clock input, it only “sees” the F0 out-
put of the dead-band function. The PSoC block Output
Register (DBA00OU-DCA07OU) controls output options.
9.5.3.5
Interrupts
The rising edge of the F0 signal provides the interrupt for
this block.
9.5.3.6
1. Constraints
The dead time must not exceed the minimum of the
Usage Notes
input signal’s pulse-width high and pulse-width low
time, less two CPU clocks. Dead time equals the
period of the input clock times one plus the value
written to Data Register 1.
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2. Enabling
PSoC blocks can be chained to increase the width of the
numbers and, hence, the length of the sequence. A
The data input to the Dead-Band function is hard-
ware to the primary output of the previous block,
which is typically programmed to be a PWM. The
proper order for enabling these blocks (writing the
Control Register 0) is PWM first, then Dead-Band.
chain of N PSoC blocks can generate numbers from 2-
8N
to 8N-bits wide and sequences of up to 2 -1 distinct val-
ues.
9.5.4.2
Registers
3. Disabled State
Data Register 0 implements a linear-feedback shift regis-
ter. Data Register 2 holds the “seed” value and when the
block is disabled, a write to Data Register 2 is loaded
directly into Data Register 0 (The block must be disabled
when writing this value). Data Register 1 specifies the
polynomial and width of the numbers in the sequence
(see 9.5.4.6).
When the Control Register Enable bit is set to ‘0’,
the internal block clock is turned off. A write to Data
Register 1 (Period) is loaded directly into Data Reg-
ister 0 (Counter) to initialize or reset the dead-band
time. All outputs are low and the block interrupt is
held low.
4. Asserting the Kill Signal
When the Kill signal is asserted high, both outputs
FO and F1 are held low. When the Kill signal is
selected from an external source through a Global
Input, it is synchronized to the 24 MHz clock and
therefore has up to 42 ns of latency.
9.5.4.3
Inputs
The clock input determines the rate at which the output
sequence is produced. The data input must be set to low
for the block to function as a PRS. The multiplexer for
selecting these inputs is controlled by the PSoC block
Input Register (DBA00IN-DCA07IN).
5. Negating the Kill Signal
The Kill signal may be negated at any time. How-
ever, the output may be enabled at an arbitrary time
with respect to the F0 and F1 generation. If exact
timing is required when re-enabling the F0 and F1
outputs, the following procedure is recommended:
9.5.4.4
Outputs
The PRS function drives the output serial data stream
synchronous with the input clock. The output bits change
on the rising edge of the input clock. The output may be
driven on the Global Output bus or to the subsequent
digital PSoC block. The PSoC block Output Register
(DBA00OU-DCA07OU) controls output options.
1.Kill is asserted.
2.Write to Control Register 0 to disable the
block.
3.Write to Data Register 1 (Deadband time) to
initialize the period.
9.5.4.5
Interrupts
4.Kill is eventually negated.
The PRS function provides an interrupt based on the
Compare signal between Data Register 0 and Data Reg-
ister 2. Data Register 2 is initially loaded with the “seed”
value, and therefore a periodic interrupt will be gener-
ated when the PRS count matches the seed value.
5.Write to Control Register 0 to enable the
block.
9.5.4 PRS - Pseudo-Random Sequence
Generator
9.5.4.1
Summary
The PRS function generates an output waveform corre-
sponding to a sequence of pseudo-random numbers. A
linear-feedback shift register generates the sequence
according to a user-specified polynomial. The width of
the numbers in the sequence is variable and the initial
value is determined by a user-defined “seed” value. PRS
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The PRS function utilizes a different “modular” architec-
ture with one XOR gate between each bit of the shift reg-
ister. A maximal sequence equivalent to that produced
by the previous realization is generated by the following
modular LFSR
9.5.4.6
Determining the Polynomial
A simple linear-feedback shift register, or LFSR, uses an
XOR gate to “add” the values of one or more bits and
feed the result back into the least-significant bit. One
possible realization of a 6-bit LFSR providing a maximal
sequence of 63 six-bit values is shown here:
+
1 2 3 4 5
6
Figure 13: Polynomial LFSR
B
Figure 14: Polynomial PRS
Denote the first implementation as a (6, 1) LFSR, where
6 gives the length of the output codes and 1 indicates the
tap which feeds the XOR gate along with the final bit.
Then the modular form just shown is denoted as a [6, 5]
LFSR. In general, the equivalent modular form of a sim-
The current LFSR value can only be read when the
block is disabled by setting the Control Register bit 0
to low. Each byte of the current LFSR value (in the
case of a multi-byte block) must be read individually.
The Data Register 0 byte (LFSR), which returns 0,
then the Data Register 1 byte, which returns the
actual value.
ple N bit LFSR with M taps denoted by (N, t , t , …, t ) is
1
2
M
given by the notation [N, N-t , N-t , …, N-t ]. Once the
1
2
M
9.5.5 CRC - Cyclic Redundancy Check
form (and thus the notation) is determined, the value of
Data Register 1 is easily determined. The bit corre-
sponding to the length and all tap bits are turned on; the
others are zero. Thus, the polynomial specification for
Data Register 1 to implement a [6, 5] LFSR is
00110000b, or 30h. A maximal sequence PRS for 8-bits
giving 255 codes is [8, 4, 3, 2] with polynomial
10001110b or 8Eh.
9.5.5.1
Summary
The CRC uses a shift register and XOR gates like the
PRS function. However, instead of an output bit stream,
the CRC function expects an input bit stream. Function-
ally the CRC block is identical to the PRS with the excep-
tion of the selected input data. Input data must be
presented synchronously to the clock. A polynomial
specification permits the length of the input sequence
over which the cyclic redundancy check computes a
result to be varied. CRC-configured PSoC blocks can be
chained to form longer results.
9.5.4.7
Usage Notes
1. Disabled State
When the Control Register Enable bit is set to ‘0’,
the internal block clock is turned off. A write to Data
Register 2 (Seed) is loaded directly into Data Regis-
ter 0 (LFSR) to initialize or reset the seed value. All
outputs are low and the block interrupt is held low.
9.5.5.2
Registers
Data Register 0 implements a linear-feedback shift regis-
ter. Data Register 2 holds the “seed” value and when the
block is disabled, a write to Data Register 2 is loaded
2. Reading the LFSR
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directly into Data Register 0 (The block must be disabled
CCIT example, two PSoC blocks must be chained
together. Data Register 1 in the high-order PSoC block
would take the value 10001000b (88h) and the corre-
sponding register in the low-order PSoC block would
take 00010000b (10h).
when writing this value). Data Register 1 specifies the
polynomial and width of the numbers in the sequence
(see “Specifying the Polynomial”, below). Once the input
bit stream is complete, the result may be read by first
reading Data Register 0, which returns 0, then reading
Data Register 2, which returns the actual result.
9.5.5.7
Usage Notes
1. Disabled State
9.5.5.3
Inputs
When the Control Register Enable bit is set to ‘0’,
the internal block clock is turned off. A write to Data
Register 2 (Seed) is loaded directly into Data Regis-
ter 0 (LFSR) to initialize or reset the seed value. All
outputs are low and the block interrupt is held low.
The clock input determines the rate at which the input
sequence is processed. The data input selects the data
stream to process. It is assumed that the data is valid on
the positive edge of the clock input. The multiplexer for
selecting these inputs is controlled by the PSoC block
Input Register (DBA00IN-DCA07IN).
2. Reading the CRC value
After the data stream has been processed by the
LFSR, the residue is the CRC value. The current
LFSR value can only be read when the block is dis-
abled by setting the Control Register bit 0 to low.
Each byte of the current LFSR value (in the case of
a multi-byte block) must be read individually. The
Data Register 0 byte (LFSR) must be read, which
returns 0, then the Data Register 2 byte, which
returns the actual value.
9.5.5.4
Outputs
Like the PRS, the CRC function drives the output serial
data stream with the most significant bit of CRC process-
ing synchronous with the input clock. Normally the CRC
output is not used. The output may be driven on the Glo-
bal Output bus or to the subsequent digital PSoC block.
The PSoC block Output Register (DBA00OU-
DCA07OU) controls output options.
9.5.6 Universal Asynchronous Receiver
9.5.6.1
Summary
9.5.5.5
Interrupts
The Universal Asynchronous Receiver implements the
input half of a basic 8-bit UART. Start and Stop bits are
recognized and stripped. Parity type and parity validation
are configurable features. This function requires a Digital
Communications Type PSoC block and cannot be
chained for longer data words.
The CRC function provides an interrupt based on the
Compare signal between Data Register 0 and Data Reg-
ister 2.
9.5.5.6
Specifying the Polynomial
Computation of an N-bit result is generally specified by a
9.5.6.2
Registers
0
polynomial with N+1 terms, the last of which is the X
0
The function shifts incoming data into Data Register 0.
Once complete, the byte is transferred to Data Register 2
from which it may be read. Data Register 2 acts as a 1
byte receive buffer. Data Register 1 is not used by this
function. Control Register 0 (DCA04CR0-DCA07CR0)
enables the function, provides the means to configure
parity checking, and a full set of status indications. See
the register definition for full details.
term, where X =1. For example, the widely used CRC-
16
12
5
CCIT 16-bit polynomial is X +X +X +1. The PSoC
0
block CRC function assumes the presence of the X
term so that the polynomial for an N-bit result can be
expressed by an N-bit rather than N+1 bit specification.
To obtain the PSoC block register specification, write an
N+1 bit binary number corresponding to the full polyno-
mial, with 1’s for each term present. The CRC-CCIT
polynomial would be 10001000000100001b. Simply
0
drop the right-most bit (the X term) to obtain the register
specification for the PSoC block. To implement the CRC-
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Digital PSoC Blocks
9.5.6.3
Inputs
9.5.7.2
Registers
A baud-rate clock running at 8 times the desired input bit
rate is selected by the clock-input multiplexer The serial
data input and clock input are controlled by the Input
Register (DCA04IN-DCA07IN).
When Data Register 0 is empty and a new byte has been
written to Data Register 1, the function transfers the byte
to Data Register 0 and shifts it out along with a start bit,
optionally a parity bit and a stop bit. Once Data Register
0 is loaded with the byte to shift out, Data Register 0 can
be immediately loaded with the next byte to transmit, act-
ing as a 1 byte transmit buffer. Data Register 2 is not
used by this function. The PSoC block’s Control Register
0 (DCA04CR0-DCA07CR0) configures the parity type
and enable. It also provides status information to enable
detection of transmission complete.
9.5.6.4
Outputs
None.
9.5.6.5
Interrupts
The function can be configured to generate an interrupt
on RXREGFULL (Receive Register Full) status (Data
Register 2 is full)
9.5.7.3
Inputs
A baud-rate clock running at 8 times the desired output
bit rate is selected by the clock-input multiplexer con-
trolled by the PSoC block Input Register (DCA04IN-
DCA07IN). The Data Input multiplexer is ignored by this
function.
9.5.6.6
Usage Notes
1. Reading the Status
Reading Control Register 0, which contains the sta-
tus bits, automatically resets all status bits to 0 with
the exception of RX Reg Full. Reading Data Regis-
ter 2 (Receive Data Register) clears the RX Reg Full
status.
9.5.7.4
Outputs
The transmitter’s serial data output appears at the PSoC
block output and may be driven onto one of the Global
Output bus lines. The PSoC block Output Register
(DCA04OU-DCA07OU) controls output options.
2. Using Interrupts
RX Reg Full status generates an interrupt but the
Receive Data Register (Data Register 2) must be
read to clear the RX Reg Full status. If this registers
is not read in the interrupt routine, the status will not
be cleared and further interrupts will be suppressed.
9.5.7.5
Interrupts
If enabled, the function will generate an interrupt when
the TX Reg Empty status is set (Data Register 1 is
empty). Optionally, the interrupt can be set to TX Com-
plete status, which indicates all bits of a given byte have
been sent, including framing bits. This option is selected
based on the Mode[1] bit in the Function Register.
If the stop bit in a transmitted byte is missing, the
receiver will declare a framing error. Once this
occurs, this missing stop bit can be interpreted as
the start bit of the next byte, which will produce
another framing error.
9.5.7 Universal Asynchronous Transmitter
9.5.7.6
Usage Notes
9.5.7.1
Summary
1. TX Reg Empty Interrupt
The Universal Asynchronous Transmitter implements the
output half of a basic 8-bit UART. Start and Stop bits are
generated. Parity bit generation and type are config-
urable features. This function requires a Digital Commu-
nications Type PSoC block. It cannot be chained for
longer data words.
An initial byte must be written to the TX Data Regis-
ter (Data Register 1) to enable subsequent TX Reg
Empty status interrupts. This does not apply if the
TX Complete interrupt source is selected.
2. Reading the Status
Reading Control Register 0, which contains the sta-
tus bits, automatically resets the status bits to 0,
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except for TX Reg Empty. TX Reg Empty is auto-
matically cleared when a byte is written to the TX
Data Register (Data Register 1).
9.5.8 SPI Master - Serial Peripheral Interface
(SPIM)
9.5.8.1
Summary
3. Using CPU Interrupts
The SPI Master function provides a full-duplex synchro-
nous data transceiver that also generates a bit clock for
the data. This function requires a Digital Communica-
tions Type PSoC block. It cannot be chained for longer
data words. This Digital Communications Type PSoC
block supports SPI modes for 0, 1, 2, and 3. See Figure
15: for waveforms of the Clock Phase modes.
TX Reg Empty status or optionally TX Complete sta-
tus generates the block interrupt. Executing the
interrupt routine does not automatically clear status.
If TX Complete is selected as the interrupt source,
Control Register 0 (status) must be read in the inter-
rupt routine to clear the status. If TX Reg Empty is
selected, a byte must be written to the TX Data Reg-
ister (Data Register 1) to clear the status. If the sta-
tus is not cleared, further interrupts will be
suppressed.
Clock Phase 0 (Mode 0, 1)
Data registered on the leading edge of the clock
Data output on the trailing edge of the clock
SS_ (required for slav e)
Polarity=0, Mode 0
SCLK
Polarity=1, Mode 1
MOSI/MISO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit7
Clock Phase 1 (Mode 2, 3)
Data output on the leading edge of the clock
Data registered on the trailing edge of the clock
SS_ (optional for slav e)
Polarity=0, Mode 2
SCLK
Polarity=1, Mode 3
MOSI/MISO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Figure 15: SPI Waveforms
0, the received byte is transferred into Data Register 2
from where it can be read. Simultaneously, the next byte
to transmit, if available, is transferred from Data Register
1 into Data Register 0. Control Register 0 (DCA04CR0-
DCA07CR0) provides status information and configures
the function for one of the four standard modes, which
configure the interface based on clock polarity and
phase with respect to data.
9.5.8.2
Registers
Data Register 0 provides a shift register for both incom-
ing and outgoing data. Output data is written to Data
Register 1 (TX Data Register). When this block is idle, a
write to the TX Data Register will initiate a transmission.
Input data is read from Data Register 2 (RX Data Regis-
ter). When Data Register 0 is empty, its value is updated
from Data Register 1, if new data is available. As data
bits are shifted in, the transmit bits are shifted out. After
the 8 bits are transmitted and received by Data Register
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Digital PSoC Blocks
If the SPI Master block is being used to receive data,
“dummy” bytes must be written to the TX Data Register
in order to initiate transmission/reception of each byte.
interrupt routine does not automatically clear status.
If SPI Complete is selected as the interrupt source,
Control Register 0 (status) must be read in the inter-
rupt routine to clear the status. If TX Reg Empty sta-
tus is selected, a byte must be written to the TX
Data Register (Data Register 1) to clear the status. If
the interrupting status is not cleared further inter-
rupts will be suppressed.
9.5.8.3
Inputs
MISO (master-in, slave-out) is selected by the input mul-
tiplexer. The clock input multiplexer selects a clock that
runs at twice the desired data rate. The SPIM function
divides the input clock by 2 to obtain the 50% duty-cycle
required for proper timing. The input multiplexer is con-
trolled by the PSoC block Input Register (DCA04IN-
DCA07IN).
9.5.9 SPI Slave - Serial Peripheral Interface
(SPIS)
9.5.9.1
Summary
The SPI Slave function provides a full-duplex bi-direc-
tional synchronous data transceiver that requires an
externally provided bit clock for the data. This function
requires a Digital Communications Type PSoC block. It
cannot be chained for longer data words. This Digital
Communications Type PSoC block supports SPI modes
for 0, 1, 2, and 3. See Figure 15: for waveforms of the
supported modes.
9.5.8.4
Outputs
There are two outputs, both of which can be enabled
onto the Global Output bus. The MOSI (master-out,
slave-in) data line provides the output serial data. The
second output is the bit-clock derived by dividing the
input clock by 2 to ensure a 50% duty-cycle. The PSoC
block Output Register (DCA04OU-DCA07OU) controls
output options.
9.5.9.2
Registers
Data Register 0 provides a shift register for both incom-
ing and outgoing data. Output data is written to Data
Register 1 (TX Data Register). Input data is read from
Data Register 2 (RX Data Register). When Data Register
0 is empty, its value is updated from Data Register 1. As
new data bits are shifted in, the transmit bits are shifted
out. After the 8 bits are transmitted and received by Data
Register 0, the received byte is transferred into Data
Register 2 from which it can be read. Simultaneously, the
next byte to transmit, if available, is transferred from
Data Register 1 into Data Register 0. Control Register 0
(DCA04CR0-DCA07CR0) provides status information
and configures the function for one of the four standard
modes, which configure the interface based on clock
polarity and phase with respect to data.
Note: The SPIM function does not provide the SS_ sig-
nal that may be used by a corresponding SPI Slave.
However, this can be implemented with a GPIO pin and
supporting firmware if desired.
9.5.8.5
Interrupts
When enabled, the function generates an interrupt on TX
Reg Empty status (Data Register 1 empty). If Mode[1] in
the Function Register is set, the SPI Master will generate
an interrupt on SPI Complete.
9.5.8.6
Usage Notes
1. Reading the Status
Reading Control Register 0, which contains the sta-
tus bits, automatically resets the status bits to 0 with
the exception of TX Reg Empty, which is cleared
when a byte is written to the TX Data Register (Data
Register 1), and the RX Reg Full, which is cleared
when a byte is read from the RX Data Register
(Data Register 2).
9.5.9.3
Inputs
The SPIS function has three inputs. The Input Register
(DCA04IN-DCA07IN) controls the input multiplexer,
which selects the MOSI data stream. It also controls the
clock selection multiplexer from which the function
obtains the master’s bit clock. The AUX-IO bits of the
Output Register (DCA04OU-DCA07OU) select a Global
Input signal from which the SS_ (Slave Select) signal is
obtained. It is important to note that the SS_ signal can
2. Using Interrupts
TX Reg Empty status or optionally SPI Complete
status generates the block interrupt. Executing the
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only be input from GPIO input pins (Global Input Bus).
Register 2) to clear the status. If the interrupting sta-
tus is not cleared further interrupts will be sup-
pressed.
There is no way to enable the SS_internally. In SPI
modes 2 & 3, where SS is not required between each
byte, the external pin may be grounded.
4. Synchronization of CPU Interaction
Important: The AUX Out Enable bit (bit 5) of the Output
Register (DCA04OU-DCA07OU) must be set to 0 to dis-
able it.
Because the SPI Slave is clocked asynchronously
by the master SCLK, transfer of data between the
TX Register to shifter and shifter to RX Register
occurs asynchronously.
9.5.9.4
Outputs
Either polling or interrupts can be used to detect that
a byte has been received and is ready to read. How-
ever, on the TX side, the user is responsible for
implementing a protocol that ensures there is
enough set-up time from the TX Data Register write
to the first clock (mode 2, 3) or SS_ (mode 0, 1) from
the master.
The function output is the MISO (master-in, slave-out)
signal, which may be driven on the Global Output bus
and is selected by Output Register (DCA04OU-
DCA07OU).
9.5.9.5
Interrupts
When enabled, the function generates an interrupt on
RX Reg Full status (Data Register 2 full). If Mode[1] of
the Function Register is set, the interrupt will be gener-
ated on SPI Complete status.
9.5.9.6
Usage Notes
1. Reading the Status
Reading Control Register 0, which contains the sta-
tus bits, automatically resets the status bits to 0 with
the exception of TX Reg Empty, which is cleared
when a byte is written to the TX Data Register (Data
Register 1), and the RX Reg Full, which is cleared
when a byte is read from the RX Data Register
(Data Register 2).
2. Multi-Slave Environment
The SS_ signal does not have any affect on the out-
put from the slave. The output of the slave at the
end of a reception/transmission is always the first bit
sent (the MSB, unless LSBF option is selected, then
it’s the LSB). To implement a multi-slave environ-
ment, a GPIO interrupt may be configured on the
SS_ input, and the Slave output strength may be
toggled between driving and High Z in firmware.
3. Using Interrupts
RX Reg Full status or SPI Complete status gener-
ates an interrupt. Executing the interrupt routine
does not automatically clear status. If SPI Complete
is selected as the interrupt source, Control Register
0 (status) must be read in the interrupt routine to
clear the status. If RX Reg Full status is selected, a
byte must be read from the RX Data Register (Data
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Analog PSoC Blocks
10.0 Analog PSoC Blocks
10.1 Introduction
PSoC blocks are user configurable system resources.
On-chip analog PSoC blocks reduce the need for many
MCU part types and external peripheral components.
Analog PSoC blocks can be configured to provide a wide
variety of peripheral functions. PSoC Designer Software
Integrated Development Environment provides auto-
mated configuration of PSoC blocks by simply selecting
the desired functions. PSoC Designer then generates
the proper configuration information and can print a
device data sheet unique to that configuration.
bit Incremental and 11-bit Delta-Sigma ADC, successive
approximation ADCs up to 6 bits, DACs up to 8 bits, pro-
grammable gain stages, sample and hold circuits, pro-
grammable filters, comparators, and a temperature
sensor.
The analog functionality provided is as follows:
A/D and D/A converters, programmable gain blocks,
comparators, and switched capacitor filters.
Single ended configuration is cost effective for rea-
sonable speed / accuracy, and provides simple
interface to most real-world analog inputs and out-
puts.
Each of the analog blocks has many potential inputs and
several outputs. The inputs to these blocks include ana-
log signals from external sources, intrinsic analog sig-
nals driven from neighboring analog blocks or various
voltage reference sources.
Support is provided for sensor interfaces, audio
codes, embedded modems, and general-purpose
op amp circuits.
Flexible, System on-a-Chip programmability, provid-
ing variations in functions.
There are three discrete outputs from each analog block
(there are an additional two discrete outputs in the Con-
tinuous Time blocks), 1) the analog output bus (ABUS),
which is an analog bus resource that is shared by all of
the analog blocks in a column, 2) the comparator bus
(CBUS), which is a digital bus resource that is shared by
all of the analog blocks in a column, and 3) the output
bus (OUT, (plus GOUT and LOUT in the Continuous
Time blocks)), which is an analog bus resource that is
shared by all of the analog blocks in a column and con-
nects to one of the analog output buffers, to send a sig-
nal externally to the device. There are also intrinsic
outputs that connect to neighboring analog blocks.
For a given function, easily selected trade-offs of
accuracy and resolution with speed, resources
(number of analog blocks), and power dissipated for
that application.
The analog section is an “Analog Computation Unit,”
providing programmed steering of signal flow and
selecting functionality through register-based control
of analog switches. It also sets coefficients in
Switched Capacitor Filters and noise shaping
(Delta-Sigma) modulators, as well as programs gain
or attenuation settings in amplifier configurations.
The architecture provides continuous time blocks
and discrete time (Switched Capacitor) blocks. The
continuous time blocks allow selection of precision
amplifier or comparator circuitry using programma-
ble resistors as passive configuration and parameter
setting elements. The Switched Capacitor (SC)
blocks allow configuration of DACs, Delta Sigma,
incremental or Successive Approximation ADCs, or
Switched Capacitor filters with programmable coeffi-
cients.
Twelve analog PSoC blocks are available separately or
combined with the digital PSoC blocks. A precision inter-
nal voltage reference provides accurate analog compari-
sons. A temperature sensor input is provided to the
analog PSoC block array supporting applications like
battery chargers and data acquisition without requiring
external components.
There are three analog PSoC block types: Continuous
Time (CT) blocks, and Type A and Type B Switch Capac-
itor (SC) blocks. CT blocks provide continuous time ana-
log functions. SC blocks provide ADC and DAC analog
functions. Currently, supported analog functions are 12-
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10.2 Analog System Clocking Signals
Table 61:
Signal
Analog System Clocking Signals
Definition
A system-clocking signal that is driven by the clock output of a digital PSoC block and can be selected
by the user to drive the clocking signal to an analog column. Any of the 8 digital PSoC blocks can be
muxed into this line using the ACLK0[2:0] bits in the Analog Clock Select Register (CLK_CR1).
ACLK0
ACLK1
A system-clocking signal that is driven by the clock output of a digital PSoC block and can be selected
by the user to drive the clocking signal to an analog column. Any of the 8 digital PSoC blocks can be
muxed into this line using the ACLK1[2:0] bits in the Analog Clock Select Register (CLK_CR1).
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 0. This signal is
derived from the muxed input of the 24V1, 24V2, ACLK0, and ACLK1 system clock signals. The output
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4. The
Acolumn0[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
Acolumn0
Acolumn1
Acolumn2
Acolumn3
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 1. This signal is
derived from the muxed input of the 24V1, 24V2, ACLK0, and ACLK1 system clock signals. The output
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4.The
Acolumn1[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 2. This signal is
derived from the muxed input of the 24V1, 24V2, ACLK0, and ACLK1 system clock signals. The output
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4. The
Acolumn2[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 3. This signal is
derived from the muxed input of the 24V1, 24V2, ACLK0, and ACLK1 system clock signals. The output
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4. The
Acolumn3[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
10.3 Array of Analog PSoC Blocks
Analog
Analog
Analog
Analog
Column 0
Column 1
Column 2
Column 3
ACA00
ASA10
ASB20
ACA01
ACA02
ASA12
ASB22
ACA03
ASB13
ASA23
ASB11
ASA21
Figure 16: Array of Analog PSoC Blocks
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Analog PSoC Blocks
10.4 Analog Reference Control
The reference generator establishes a set of three inter-
nally fixed reference voltages for the whole chip, AGND,
RefHi and RefLo. The 8C26xxx is a single supply part,
with no negative voltage available or applicable. Analog
ground (AGND) is constructed near mid-supply. This
ground is routed to all analog blocks and separately buff-
ered within each block. There may be a small offset volt-
age between buffered analog grounds, as indicated in
the AC/DC Characteristics section. RefHi and RefLo sig-
nals are generated, buffered and routed to the analog
blocks. RefHi is used to set the conversion range (i.e.,
span) of analog to digital (ADC) and digital to analog
(DAC) converters. RefHi and RefLo can be used to set
thresholds in comparators.
Vcc
Vbandgap
Port 2.6
RefHI to
Analog
Blocks
x12
Distributed
Gound
2*Vbandgap
Port 2.4
Vcc/2
AGND
Ground Buffer in
Each Analog
Block
RefLO to
Analog
Blocks
Vss
Figure 17: Analog Reference Control Schematic
Alternatively, the power supply can be scaled to provide
10.4.1 Bandgap Test
analog ground and references; this is particularly useful
for signals, which are ratiometric to the power supply
voltage.
BGT
Bandgap Test is used for factory testing of the
internal reference voltage testing.
10.4.2 Bias Level
User supplied external precision references can be con-
nected to Port 2 inputs (available on 28 pin and larger
parts). This is useful in setting reference for specific cus-
tomer applications such as a +/-1.000 V (from AGND)
ADC scale. References derived from Port 2 inputs are
limited to the same output voltage range as the op-amps
in the analog blocks.
HBE
Controls the bias level for all analog functions. It
operates with the power setting in each block to set the
parameters of that block. Most applications will benefit
most from the low bias level. At high bias, the analog
block op-amps have faster slew rate but slightly less volt-
age swing and higher noise.
10.4.3 AGND, RefHI, RefLO
REF
Sets Analog Array Reference Control, selecting
specific combinations of voltage for analog ground and
references. Many of these reference voltages are based
on the precision internal reference, a Silicon band gap
operating at 1.300 Volts. This reference has good ther-
mal stability and power supply rejection.
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Table 62:
AGND, RefHI, RefLO Operating Parameters
AGND RefHI
Source Voltage Source
V /2
RefLO
Source Voltage
1.2 V
Notes
Voltage
3.8 V
V +Vbg
V -Vbg
000
2.5 V
5.0 V System
cc
cc
cc
1.65 V
2.95 V
0.35 V
3.3 V System
1
1
1
001
010
P2[4]
Vcc/2
P2[4]+P2[6]
Vcc
P2[4]-P2[6]
Vss
User Adjustable
2.2 V
3.2 V
1.2 V
2.5 V
1.65 V
5.0 V
3.3 V
0.0 V
0.0 V
5.0 V System
3.3 V System
011
100
2*Vbg
2*Vbg
2.6 V
2.6 V
2*Vbg+Vbg
2*Vbg+P2[6]
P2[4]+Vbg
3.9 V
2*Vbg-Vbg
2*Vbg-P2[6]
P2[4]-Vbg
1.3 V
Not for 3.3 V Systems
Not for 3.3 V Systems
User Adjustable
1
1
3.6 V
1.6 V
1
1
1
101
110
111
P2[4]
2.2 V
3.5 V
0.9 V
Reserved
Reserved
1. Example shown for AGND P2[4] = 2.2 V and Ref P2[6] = 1.0 V
10.4.4 Analog Array Power Control
PWR
Sets Analog Array Power Control. Analog array
power is controlled through the bias circuits in the Con-
tinuous Time blocks and separate bias circuits in the
Switched Capacitor blocks. Continuous Time blocks
(ACAxx) can be operated to make low power compara-
tors independent of Switched Capacitor (ASAxx and
ASBxx) blocks, without their power consumption.
The reference array supplies voltage to all blocks and
current to the Switched Capacitor blocks. At higher block
clock rates, there is increased reference current
demand; the reference power should be set equal to the
highest power level of the analog blocks used.
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Analog PSoC Blocks
Table 63:
Analog Reference Control Register
Bit #
POR
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Read/Write
Bit Name
RW
BGT
RW
HBE
RW
REF[2]
RW
REF[1]
RW
REF[0]
RW
RW
RW
PWR[2]
PWR[1]
PWR[0]
Bit 7: BGT Bandgap Test used for internal reference voltage testing (customer should not alter; must be written as 0)
Bit 6: HBE Bias level control for op-amps
0 = Low bias mode for analog array
1 = High bias mode for analog array
Bit [5:3]: REF [2:0] Analog Array Reference Control
AGND
High/Low
± Bandgap
± P2[6]
0 0 0 = Vcc/2
0 0 1 = P2[4]
0 1 0 = Vcc/2
± Vcc/2
0 1 1 = 2 Bandgap ± Bandgap
1 0 0 = 2 Bandgap ± P2[6]
1 0 1 = P2[4]
± Bandgap
1 1 0 = Reserved
1 1 1 = Reserved
Bit [2:0]: PWR [2:0] Analog Array Power Control
0 0 0 = All Analog Off
0 0 1 = SC Off, REFPWR Low
0 1 0 = SC Off, REFPWR Med
0 1 1 = SC Off, REFPWR High
1 0 0 = All Analog Off
1 0 1 = SC On, REFPWR Low
1 1 0 = SC On, REFPWR Med
1 1 1 = SC On, REFPWR High
Analog Reference Control Register (ARF_CR, Address = Bank 0, 63h)
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
10.5 Analog PSoC Block Clocking Options
All analog PSoC blocks in a particular Analog Column
share the same clock signal. Choosing the clocking for
an analog PSoC block is a two-step process.
2. Next, the user must select the source for the
Acolumn0, Acolumn1, Acolumn2, and Acolumn3
system-clocking signals. The user will choose the
clock for Acolumnx[1:0] bits in the Analog Column
Clock Select Register (CLK_CR0). Each analog
PSoC block in a particular Analog Column is
clocked from the Acolumn[x] system-clocking sig-
nal for that column. (Note that the Acolumn[x] sig-
nals have a 1:4 divider on them.)
1. First, if the user wants to use the ACLK0 and
ACLK1 system-clocking signals, the digital PSoC
blocks that serve as the source for these signals
must be selected. This selection is made in the Ana-
log Clock Select Register (CLK_CR1).
10.5.1 Analog Column Clock Select Register
Table 64:
Analog Column Clock Select Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Acolumn3 Acolumn3 Acolumn2 Acolumn2 Acolumn1 Acolumn1 Acolumn0 Acolumn0
Bit Name
[1]
[0]
[1]
[0]
[1]
[0]
[1]
[0]
Bit [7:6]: Acolumn3 [1:0]
0 0 = 24V1
0 1 = 24V2
1 0 = ACLK0
1 1 = ACLK1
Bit [5:4]: Acolumn2 [1:0]
0 0 = 24V1
0 1 = 24V2
1 0 = ACLK0
1 1 = ACLK1
Bit [3:2]: Acolumn1 [1:0]
0 0 = 24V1
0 1 = 24V2
1 0 = ACLK0
1 1 = ACLK1
Bit [1:0]: Acolumn0 [1:0]
0 0 = 24V1
0 1 = 24V2
1 0 = ACLK0
1 1 = ACLK1
Analog Column Clock Select Register (CLK_CR0, Address = Bank 1, 60h)
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Analog PSoC Blocks
10.6 Analog Clock Select Register
Table 65:
Analog Clock Select Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
Reserved
SHDIS
ACLK1 [2] ACLK1 [1] ACLK1 [0] ACLK0 [2] ACLK0 [1] ACLK0 [0]
Bit 7: Reserved
Bit 6: SHDIS During normal operation of an SC block for the amplifier of a column enabled to drive the output bus,
the connection is only made for the last half of PHI2 (during PHI1 and for the first half of PHI2, the output bus floats
at the last voltage to which it was driven). This forms a sample and hold operation using the output bus and its asso-
ciated capacitance. This design prevents the output bus from being perturbed by the intermediate states of the SC
operation (often a reset state for PHI1 and settling to the valid state during PHI2)
Following are the exceptions: 1) If the ClockPhase bit in CR0 (for the SC block in question) is set to 1, then the out-
put is enabled for the whole of PHI2. 2) If the SHDIS signal is set in bit 6 of the Analog Clock Select Register, then
sample and hold operation is disabled for all columns and all enabled outputs of SC blocks are connected to their
respective output busses for the entire period of their respective PHI2s
0 = Sample and hold function enabled
1 = Sample and hold function disabled
Bit [5:3]: ACLK1 [2:0]
0 0 0 = Digital Basic Type A Block 00
0 0 1 = Digital Basic Type A Block 01
0 1 0 = Digital Basic Type A Block 02
0 1 1 = Digital Basic Type A Block 03
1 0 0 = Digital Communications Type A Block 04
1 0 1 = Digital Communications Type A Block 05
1 1 0 = Digital Communications Type A Block 06
1 1 1 = Digital Communications Type A Block 07
Bit [2:0]: ACLK0 [2:0] Same configurations as ACLK1 [2:0]
0 0 0 = Digital Basic Type A Block 00
0 0 1 = Digital Basic Type A Block 01
0 1 0 = Digital Basic Type A Block 02
0 1 1 = Digital Basic Type A Block 03
1 0 0 = Digital Communications Type A Block 04
1 0 1 = Digital Communications Type A Block 05
1 1 0 = Digital Communications Type A Block 06
1 1 1 = Digital Communications Type A Block 07
Analog Clock Select Register (CLK_CR1, Address = Bank 1, 61h)
There are a total of twelve analog PSoC blocks imple-
mented for each of the following types; Analog Continu-
ous Time Type A (ACAxx), Analog Switch Cap Type A
(ASAxx), and Analog Switch Cap Type B (ASBxx).
These blocks are arranged in an array of three rows by
four columns. Each column has one of each type of
PSoC block, and the individual PSoC blocks are identi-
fied by the row and column in which they reside.
There are two primary types of analog PSoC blocks.
Both types contain one op-amp but their principles of
operation are quite different. Continuous-time PSoC
blocks employ three configuration registers and use
resistors to condition amplifier response. Switched
capacitor blocks have one comparator and four configu-
ration registers and operate as discrete-time sampling
operators. In both types, the configuration registers are
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
divided into distinct bit fields. Some bit fields set the
neighbors by means of three multiplexers. (Note that
unlike the switched capacitor blocks, the continuous time
blocks in the current family of parts only have one sub-
type.) The three are the non-inverting input multiplexer,
"PMux," the inverting input multiplexer, "NMux," and the
"RBotMux" which controls the node at the bottom of the
resistor string. The bit fields, which control these multi-
plexers, are named PMux, NMux, and RBotMux, respec-
tively. The following diagrams show how each
multiplexer connects its ACA block connect to its neigh-
bors. Each arrow points from an input source, either a
PSoC block, bus or reference voltage to the block where
it is used. Each arrow is labeled with the value to which
the bit-field must be set to select that input source.
PSoC block's resistor ratios or capacitor values. Others
configure switches and multiplexers that form connec-
tions between internal block nodes. Additionally, a block
may be connected via local interconnection resources to
neighboring analog PSoC blocks, reference voltage
sources, input multiplexers and output busses. Specific
advantages and applications of each type are treated
separately below.
10.6.1 Local Interconnect
Analog continuous-time PSoC blocks occupy the top
row, (row 0) of the analog array. Designated ACA for
analog continuous-time subtype "A," each connects to its
10.6.1.1
NMux
N (Inverting) Input Multiplexer Connections
REFLO
(2)
REFHI
REFLO
REFHI
REFLO
(43)
(43)
(43)
(43)
(3)
(3)
(2)
(2)
(3)
(3)
(0)
(2)
(0)
(0)
(0)
(6)
ACA
00
ACA
01
ACA
02
ACA
03
(13)
(13)
(1)
(1)
(6)
(6)
(6)
AGND
AGND
(5)
(5)
(5)
(5)
AGND
ASA
10
ASB
11
ASA
12
ASB
13
ASB
20
ASA
21
ASB
22
ASA
23
Figure 18: NMux Connections
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Analog PSoC Blocks
10.6.1.2
PMux
P (Non-inverting) Input Multiplexer Connections
Port
Port
Port
Port
Inputs
Inputs
Inputs
Inputs
ABUS 0
ABUS 1
(6)
ABUS 2
ABUS 3
(1)
(1)
(1)
(1)
(6)
(6)
(6)
(0)
REFLO
(2)
(5)
(0)
(0)
(2)
(5)
REFLO
(0)
(3)
(2)
(5)
(2)
(5)
ACA
00
ACA
01
ACA
02
ACA
03
(3)
(3)
(3)
AGND
AGND
(4)
(4)
(4)
(4)
AGND
ASA
10
ASB
11
ASA
12
ASB
13
ASB
20
ASA
21
ASB
22
ASA
23
Figure 19: PMux Connections
10.6.1.3
RBotMux
RB Input Multiplexer Connections
VSS
VSS
VSS
VSS
(2)
(13)
(2)
(0)
(2)
(3)
ACA
00
ACA
01
ACA
02
ACA
03
(0)
(13)
(0)
(0)
(1)
(1)
(3)
(3)
(3)
(3)
AGND
AGND
AGND
AGND
ASA
10
ASB
11
ASA
12
ASB
13
ASB
20
ASA
21
ASB
22
ASA
23
Figure 20: RBotMux Connections
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
10.7 Analog Continuous Time PSoC Blocks
10.7.1 Introduction
The Analog Continuous Time PSoC blocks are built
around an operational amplifier. There are several ana-
log muxes that are controlled by register-bit settings in
the control registers that determine the signal topology
inside the block. There is also a precision resistor matrix
that is located in the feedback path for the op-amp, and
is controlled by register-bit setting. There is also an ana-
log comparator connected to the output OUT, which con-
verts analog comparisons into digital signals.
There are five discrete outputs from this block. These
outputs are:
1. The analog output bus (ABUS), which is an analog
bus resource that is shared by all of the analog
blocks in the analog column for that block.
2. The comparator bus (CBUS), which is a digital bus
that is a resource that is shared by all of the analog
blocks in a column for that block.
3. The output bus (OUT, GOUT and LOUT), which is
an analog bus resource that is shared by all of the
analog blocks in a column and connects to one of
the analog output buffers, to send a signal externally
to the device.
This block supports Programmable Gain or attenuation
Op-Amp Circuits, (Differential Gain) Instrumentation
Amplifiers (using two CT Blocks), Continuous time high
frequency anti-aliasing filters, and modest response-time
analog comparators.
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Analog PSoC Blocks
TestMux
REFHI
REFLO
AGND
Gain
ABUS
OUT
AnalogBus
PMuxOut
CompCap
Power
CBUS
CompBus
Block Inputs
Port Input
ABUS
CLatch
CPhase
GOUT
AGND
VCC
PMux
NMux
Block Inputs
RTopMux
AGND
LOUT
REFHI, LO
FB
Gain
RTapMux
RBotMux
GIN
LIN
SCBLK
VSS
AGND
Figure 21: Analog Continuous Time PSoC Blocks
10.7.2 Registers
10.7.2.1
Analog Continuous Time Block xx Control 0 Register
The RTopMux and RBotMux bits control the connection
of the two ends of the resistor string. The RTopMux bit
controls the top end of the resistor string, which can
either be connected to Vcc or to the op-amp output. The
RBotMux bits control the connection of the bottom end of
the resistor string.
The RTapMux bits control the center tap of the resistor
string. Note that only relative weighting of units is given
in the table.
The Gain and Loss columns correspond to the gain or
loss obtained if the RTopMux and Gain bits are set so
that the overall amplifier provides gain or loss.
The Gain bit controls whether the resistor string is con-
nected around the op-amp as for gain (center tap to
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
inverting op-amp input) or for loss (center tap to output of
Note that connections between GIN and GOUT, and LIN
and LOUT are automatically resolved by PSoC Designer
when they are set in a differential configuration with an
adjacent CT block.
the block). Note that setting Gain alone does not guaran-
tee a gain or loss block. Routing of the other ends of the
resistor determine this.
Table 66:
Analog Continuous Time Block xx Control 0 Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
RTap-
Mux[3]
RTap-
Mux[2]
RTap-
Mux[1]
RTap-
Mux[0]
Bit Name
Gain
RTopMux
RBotMux[1]
RBotMux[0]
Bit [7:4]: RTapMux [3:0] Encoding for selecting 1 of 16 resistor taps
0 0 0 0 = Rf 15 = Ri 01 = Loss .0625 / Gain 16.00
0 0 0 1 = Rf 14 = Ri 02 = Loss .1250 / Gain 8.000
0 0 1 0 = Rf 13 = Ri 03 = Loss .1875 / Gain 5.333
0 0 1 1 = Rf 12 = Ri 04 = Loss .2500 / Gain 4.000
0 1 0 0 = Rf 11 = Ri 05 = Loss .3125 / Gain 3.200
0 1 0 1 = Rf 10 = Ri 06 = Loss .3750 / Gain 2.667
0 1 1 0 = Rf 09 = Ri 07 = Loss .4375 / Gain 2.286
0 1 1 1 = Rf 08 = Ri 08 = Loss .5000 / Gain 2.000
1 0 0 0 = Rf 07 = Ri 09 = Loss .5625 / Gain 1.778
1 0 0 1 = Rf 06 = Ri 10 = Loss .6250 / Gain 1.600
1 0 1 0 = Rf 05 = Ri 11 = Loss .6875 / Gain 1.455
1 0 1 1 = Rf 04 = Ri 12 = Loss .7500 / Gain 1.333
1 1 0 0 = Rf 03 = Ri 13 = Loss .8125 / Gain 1.231
1 1 0 1 = Rf 02 = Ri 14 = Loss .8750 / Gain 1.143
1 1 1 0 = Rf 01 = Ri 15 = Loss .9375 / Gain 1.067
1 1 1 1 = Rf 00 = Ri 16 = Loss 1.000 / Gain 1.000
Bit 3: Gain Select gain or loss configuration for output tap
0 = Loss
1 = Gain
Bit 2: RTopMux Encoding for feedback resistor select
0 = Rtop to Vcc
1 = Rtop to op-amp’s output
Bit [1:0]: RBotMux [1:0] Encoding for feedback resistor select
ACA00
ACA01
AGND
Vss
ACA01
ACA00
AGND
Vss
ACA02
ACA03
AGND
Vss
ACA03
ACA02
AGND
Vss
0 0 =
0 1 =
1 0 =
1 1 =
ASA10
ASB11
ASA12
ASB13
Analog Continuous Time Block 00 Control 0 Register (ACA00CR0, Address = Bank 0/1, 71h)
Analog Continuous Time Block 01 Control 0 Register (ACA01CR0, Address = Bank 0/1, 75h)
Analog Continuous Time Block 02 Control 0 Register (ACA02CR0, Address = Bank 0/1, 79h)
Analog Continuous Time Block 03 Control 0 Register (ACA03CR0, Address = Bank 0/1, 7Dh)
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Analog PSoC Blocks
10.7.2.2
Analog Continuous Time Block xx Control 1 Register
The PMux bits control the multiplexing of inputs to the
non-inverting input of the op-amp. There are physically
only 7 inputs.
CompBus controls a tri-state buffer that drives the com-
parator logic. If no PSoC block in the analog column is
driving the comparator bus, it will be driven low externally
to the blocks.
th
The 8 code (111) will leave the input floating. This is not
AnalogBus controls the analog output bus. A CMOS
switch connects the op-amp output to the analog bus.
desirable, and should be avoided.
The NMux bits control the multiplexing of inputs to the
inverting input of the op-amp. There are physically only 7
inputs.
Table 67:
Analog Continuous Time Block xx Control 1 Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name AnalogBus CompBus
NMux2
NMux1
NMux0
PMux2
PMux1
PMux0
Bit 7: AnalogBus Enable output to the analog bus
0 = Disable analog bus driven by this block
1 = Enable analog bus driven by this block
Bit 6: CompBus Enable output to the comparator bus
0 = Disable comparator bus driven by this block
1 = Enable comparator bus driven by this block
Bit [5:3]: NMux [2:0] Encoding for negative input select
ACA00
ACA01
AGND
REFLO
REFHI
ACA00
ASA10
ASB11
ACA01
ACA00
AGND
REFLO
REFHI
ACA01
ASB11
ASA10
ACA02
ACA03
AGND
REFLO
REFHI
ACA02
ASA12
ASB13
ACA03
ACA02
AGND
REFLO
REFHI
ACA03
ASB13
ASA12
0 0 0 =
0 0 1 =
0 1 0 =
0 1 1 =
1
1 0 0 =
1 0 1 =
1 1 0 =
1 1 1 =
Reserved Reserved Reserved Reserved
Bit [2:0]: PMux [2:0] Encoding for positive input select
ACA00
ACA01
ACA02
ACA03
0 0 0 = REFLO
ACA02
ACA01
REFLO
0 0 1 = Port Inputs Port Inputs Port Inputs Port Inputs
0 1 0 = ACA01
0 1 1 = AGND
1 0 0 = ASA10
1 0 1 = ASB11
1 1 0 = ABUS0
ACA00
AGND
ASB11
ASA10
ABUS1
ACA03
AGND
ASA12
ASB13
ABUS2
ACA02
AGND
ASB13
ASA12
ABUS3
1 1 1 = Reserved Reserved Reserved Reserved
1. This in fact is the feedback input of the MUX.
Analog Continuous Time Block 00 Control 1 Register (ACA00CR1, Address = Bank 0/1, 72h)
Analog Continuous Time Block 01 Control 1 Register (ACA01CR1, Address = Bank 0/1, 76h)
Analog Continuous Time Block 02 Control 1 Register (ACA02CR1, Address = Bank 0/1, 7Ah)
Analog Continuous Time Block 03 Control 1 Register (ACA03CR1, Address = Bank 0/1, 7Eh)
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
10.7.2.3
Analog Continuous Time Type A Block xx Control 2 Register
CPhase controls which internal clock phase the compar-
ator data is latched on.
can be obtained if the amplifier is being used as a com-
parator.
CLatch controls whether the latch is active or if it is
always transparent.
TestMux – selects block bypass mode for testing and
characterization purposes.
CompCap controls whether the compensation capacitor
is switched in or not in the op-amp. By not switching in
the compensation capacitance, a much faster response
Power – encoding for selecting 1 of 4 power levels. The
blocks always power up in the off state.
Table 68:
Analog Continuous Time Type A Block xx Control 2 Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
CPhase
CLatch
CompCap TestMux[2] TestMux[1] TestMux[0] Power[1]
Power[0]
Bit 7: CPhase
0 = Comparator Control latch transparent on PHI1
1 = Comparator Control latch transparent on PHI2
Bit 6: CLatch
0 = Comparator Control latch is always transparent
1 = Comparator Control latch is active
Bit 5: CompCap
0 = Comparator Mode
1 = Op-amp Mode
Bit [4:2]: TestMux [2:0] Select block bypass mode for testing and characterization purposes
ACA00 ACA01
1 0 0 = Positive Input to…ABUS0 ABUS1
ACA02 ACA03
ABUS2 ABUS3
ABUS2 ABUS3
ABUS2 ABUS3
ABUS2 ABUS3
1 0 1 = AGND to…
1 1 0 = REFLO to…
1 1 1 = REFHI to…
0 x x = All Paths Off
ABUS0 ABUS1
ABUS0 ABUS1
ABUS0 ABUS1
Bit [1:0]: Power [1:0] Encoding for selecting 1 of 4 power levels
0 0 = Off
0 1 = Low (60 µA)
1 0 = Med (150 µA)
1 1 = High (500 µA)
Analog Continuous Time Block 00 Control 2 Register (ACA00CR2, Address = Bank 0/1, 73h)
Analog Continuous Time Block 01 Control 2 Register (ACA01CR2, Address = Bank 0/1, 77h)
Analog Continuous Time Block 02 Control 2 Register (ACA02CR2, Address = Bank 0/1, 7Bh)
Analog Continuous Time Block 03 Control 2 Register (ACA03CR2, Address = Bank 0/1, 7Fh)
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Analog PSoC Blocks
10.8 Analog Switch Cap Type A PSoC Blocks
10.8.1
Introduction
The Analog Switch Cap Type A PSoC blocks are built
around an operational amplifier. There are several ana-
log muxes that are controlled by register-bit settings in
the control registers that determine the signal topology
inside the block. There are also four arrays of unit value
capacitors that are located in the feedback path for the
op-amp, and are switched by two phase clocks, PHI1
and PHI2. These four capacitor arrays are labeled A Cap
Array, B Cap Array, C Cap Array, and F Cap Array. There
is also an analog comparator connected to the output
OUT, which converts analog comparisons into digital sig-
nals.
There are three discrete outputs from this block. These
outputs are:
1. The analog output bus (ABUS), which is an analog
bus resource that is shared by all of the analog
blocks in the analog column for that block.
2. The comparator bus (CBUS), which is a digital bus
that is a resource that is shared by all of the analog
blocks in a column for that block.
3. The output bus (OUT), which is an analog bus
resource that is shared by all of the analog blocks in
a column and connects to one of the analog output
buffers, to send a signal externally to the device.
SC Integrator Block A supports Delta-Sigma, Successive
Approximation and Incremental A/D Conversion, Capaci-
tor DACs, and SC filters. It has three input arrays of bina-
rily-weighted switched capacitors, allowing user
programmability of the capacitor weights. This provides
summing capability of two (CDAC) scaled inputs, and a
non-switched capacitor input. Since the input of SC
Block A has this additional switched capacitor, it is con-
figured for the input stage of such a switched capacitor
biquad filter. When followed by an SC Block B Integrator,
this combination of blocks can be used to provide a full
Switched Capacitor Biquad.
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
φ1*AutoZero
BQTAP
C Inputs
CCap
0..31 C
FCap
16,32 C
(φ2+!AutoZero)
* FSW1
φ1* FSW0
ACMux
ACap
0..31 C
φ1
φ2
φ2+AutoZero
A Inputs
REFHI
REFLO
AGND
φ1 *
!AutoZero
OUT
ARefMux
ASign
AnalogBus*φ2B
ABUS
CBUS
BCap
0..31 C
φ2
Power
CompBus
B Inputs
φ1
BMuxSCA
Figure 22: Analog Switch Cap Type A PSoC Blocks
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Analog PSoC Blocks
10.8.2 Local Interconnect
10.8.2.1 AMux
A Input Multiplexer
Connections
ACA
00
ACA
01
ACA
02
ACA
03
(1)
(1)
(1)
(1)
ASA
10
ASB
11
ASA
12
ASB
13
P2.2
(2)
(1)
(2)
(1)
RefHi
RefHi
(1)
RefHi
(1)
ASB
20
ASA
21
ASB
22
ASA
23
P2.1
(2)
(2)
ABUS0
ABUS2
ABUS3
VTemp
Figure 23: AMux Connections
10.8.2.2
CMux
C Input Multiplexer
Connections
ACA
00
ACA
01
ACA
02
ACA
03
ASA
10
ASB
11
ASA
12
ASB
13
ASB
20
ASA
21
ASB
22
ASA
23
Figure 24: CMux Connections
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
However, when the bit is high, it also overrides the two
low order bits, forcing the A and C branches to the same
10.8.2.3
ACMux
The ACMux, as shown in Analog Switch Cap Type A
Block xx Control 1 Register, controls the input muxing for
both the A and C capacitor branches. The high order bit,
ACMux[2], selects one of two inputs for the C branch.
source. The resulting condition is used to construct low
pass biquad filters. See the individual AMux and CMux
diagrams.
10.8.2.4
BMuxSCA/SCB
B Input Multiplexer Connections
ACA
00
ACA
01
ACA
02
ACA
03
(1)
(1)
(1)
(1)
ASA
10
ASB
11
ASA
12
ASB
13
(2)
(2)
(2)
P2.3
ASB
20
ASA
21
ASB
22
ASA
23
(2)
P2.0
ABUS3
TRefGND
Figure 25: BMuxSCA/SCB Connections
AnalogBus bit in Control 2 Register (ASA10CR2,
ASA12CR2, ASA21CR2, ASA23CR2).
10.8.3 Registers
10.8.3.1
Analog Switch Cap Type A Block xx
Control 0 Register
ASign controls the switch phasing of the switches on the
bottom plate of the ACap capacitor. The bottom plate
samples the input or the reference.
FCap controls the size of the switched feedback capaci-
tor in the integrator.
The ACap bits set the value of the capacitor in the A
path.
ClockPhase controls the internal clock phasing relative
to the input clock phasing. ClockPhase affects the output
of the analog column bus which is controlled by the
Table 69:
Analog Switch Cap Type A Block xx Control 0 Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
FCap
ClockPhase
ASign
ACap[4]
ACap[3]
ACap[2]
ACap[1]
ACap[0]
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Analog PSoC Blocks
Table 69:
Analog Switch Cap Type A Block xx Control 0 Register, continued
Bit 7: FCap F Capacitor value selection bit
0 = 16 capacitor units
1 = 32 capacitor units
Bit 6: ClockPhase Clock phase select, will invert clocks internal to the blocks. During normal operation of an SC
block for the amplifier of a column enabled to drive the output bus, the connection is only made for the last half of
PHI2 (during PHI1 and for the first half of PHI2, the output bus floats at the last voltage to which it was driven). This
forms a sample and hold operation using the output bus and its associated capacitance. This design prevents the
output bus from being perturbed by the intermediate states of the SC operation (often a reset state for PHI1 and set-
tling to the valid state during PHI2)
Following are the exceptions: 1) If the ClockPhase bit in CR0 (for the SC block in question) is set to 1, then the out-
put is enabled for the whole of PHI2. 2) If the SHDIS signal is set in bit 6 of the Analog Clock Select Register, then
sample and hold operation is disabled for all columns and all enabled outputs of SC blocks are connected to their
respective output busses for the entire period of their respective PHI2s
0 = Internal PHI1 = External PHI1
1 = Internal PHI1 = External PHI2
This bit also affects the latching of the comparator output (CBUS). Both clock phases, PHI1 and PHI2, are involved in
the output latching mechanism. The capture of the next value to be output from the latch (capture point event) hap-
pens during the falling edge of one clock phase, and the rising edge of the other clock phase will cause the value to
come out (output point event). This bit determines which clock phase triggers the capture point event, and the other
clock will trigger the output point event. The value output to the comparator bus will remain stable between output
point events.
0 = Capture Point Event triggered by Falling PHI2, Output Point Event triggered by Rising PHI1
1 = Capture Point Event triggered by Falling PHI1, Output Point Event triggered by Rising PHI2
Bit 5: ASign
0 = Input sampled on Internal PHI1, Reference Input sampled on internal PHI2
1 = Input sampled on Internal PHI2, Reference Input sampled on internal PHI1
Bit [4:0]: ACap [4:0] Binary encoding for 32 possible capacitor sizes for A Capacitor:
0 0 0 0 0 = 0 Capacitor units in array
0 0 0 0 1 = 1 Capacitor units in array
0 0 0 1 0 = 2 Capacitor units in array
0 0 0 1 1 = 3 Capacitor units in array
0 0 1 0 0 = 4 Capacitor units in array
0 0 1 0 1 = 5 Capacitor units in array
0 0 1 1 0 = 6 Capacitor units in array
0 0 1 1 1 = 7 Capacitor units in array
0 1 0 0 0 = 8 Capacitor units in array
0 1 0 0 1 = 9 Capacitor units in array
0 1 0 1 0 = 10 Capacitor units in array
0 1 0 1 1 = 11 Capacitor units in array
0 1 1 0 0 = 12 Capacitor units in array
0 1 1 0 1 = 13 Capacitor units in array
0 1 1 1 0 = 14 Capacitor units in array
0 1 1 1 1 = 15 Capacitor units in array
1 0 0 0 0 = 16 Capacitor units in array
1 0 0 0 1 = 17 Capacitor units in array
1 0 0 1 0 = 18 Capacitor units in array
1 0 0 1 1 = 19 Capacitor units in array
1 0 1 0 0 = 20 Capacitor units in array
1 0 1 0 1 = 21 Capacitor units in array
1 0 1 1 0 = 22 Capacitor units in array
1 0 1 1 1 = 23 Capacitor units in array
1 1 0 0 0 = 24 Capacitor units in array
1 1 0 0 1 = 25 Capacitor units in array
1 1 0 1 0 = 26 Capacitor units in array
1 1 0 1 1 = 27 Capacitor units in array
1 1 1 0 0 = 28 Capacitor units in array
1 1 1 0 1 = 29 Capacitor units in array
1 1 1 1 0 = 30 Capacitor units in array
1 1 1 1 1 = 31 Capacitor units in array
Analog Switch Cap Type A Block 10 Control 0 Register (ASA10CR0, Address = Bank 0/1, 80h)
Analog Switch Cap Type A Block 12 Control 0 Register (ASA12CR0, Address = Bank 0/1, 88h)
Analog Switch Cap Type A Block 21 Control 0 Register (ASA21CR0, Address = Bank 0/1, 94h)
Analog Switch Cap Type A Block 23 Control 0 Register (ASA23CR0, Address = Bank 0/1, 9Ch)
May 17, 2005
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
10.8.3.2
Analog Switch Cap Type A Block xx Control 1 Register
ACMux controls the input muxing for both the A and C
capacitor branches. The high order bit, ACMux[2],
selects one of two inputs for the C branch. However,
when the bit is high, it also overrides the two low order
bits, forcing the A and C branches to the same source.
The resulting condition is used to construct low pass
biquad filters.
The BCap bits set the value of the capacitor in the B
path.
Table 70:
Analog Switch Cap Type A Block xx Control 1 Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
ACMux[2] ACMux[1] ACMux[0]
BCap[4]
BCap[3]
BCap[2]
BCap[1]
BCap[0]
Bit [7:5] ACMux [2:0] Encoding for selecting A and C inputs. (Note that available mux inputs vary by individual
PSoC block.)
ASA10
ASA21
ASA12
ASA23
A Inputs C Inputs
A Inputs C Inputs
A Inputs C Inputs
ACA02 ACA02
ASB13 ACA02
REFHI ACA02
ASB22 ACA02
ACA03 Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
A Inputs C Inputs
0 0 0 = ACA00 ACA00
0 0 1 = ASB11 ACA00
0 1 0 = REFHI ACA00
0 1 1 = ASB20 ACA00
1 0 0 = ACA01Reserved
1 0 1 = Reserved Reserved
1 1 0 = Reserved Reserved
1 1 1 = Reserved Reserved
ASB11
ASB20
REFHI
Vtemp
ASA10
ASB11
ASB11
ASB11
ASB11
Reserved
ASB13
ASB22
REFHI
ASB13
ASB13
ASB13
ABUS3 ASB13
ASA12
Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Bit [4:0]: BCap [4:0] Binary encoding for 32 possible capacitor sizes for B Capacitor:
0 0 0 0 0 = 0 Capacitor units in array
0 0 0 0 1 = 1 Capacitor units in array
0 0 0 1 0 = 2 Capacitor units in array
0 0 0 1 1 = 3 Capacitor units in array
0 0 1 0 0 = 4 Capacitor units in array
0 0 1 0 1 = 5 Capacitor units in array
0 0 1 1 0 = 6 Capacitor units in array
0 0 1 1 1 = 7 Capacitor units in array
0 1 0 0 0 = 8 Capacitor units in array
0 1 0 0 1 = 9 Capacitor units in array
0 1 0 1 0 = 10 Capacitor units in array
0 1 0 1 1 = 11 Capacitor units in array
0 1 1 0 0 = 12 Capacitor units in array
0 1 1 0 1 = 13 Capacitor units in array
0 1 1 1 0 = 14 Capacitor units in array
0 1 1 1 1 = 15 Capacitor units in array
1 0 0 0 0 = 16 Capacitor units in array
1 0 0 0 1 = 17 Capacitor units in array
1 0 0 1 0 = 18 Capacitor units in array
1 0 0 1 1 = 19 Capacitor units in array
1 0 1 0 0 = 20 Capacitor units in array
1 0 1 0 1 = 21 Capacitor units in array
1 0 1 1 0 = 22 Capacitor units in array
1 0 1 1 1 = 23 Capacitor units in array
1 1 0 0 0 = 24 Capacitor units in array
1 1 0 0 1 = 25 Capacitor units in array
1 1 0 1 0 = 26 Capacitor units in array
1 1 0 1 1 = 27 Capacitor units in array
1 1 1 0 0 = 28 Capacitor units in array
1 1 1 0 1 = 29 Capacitor units in array
1 1 1 1 0 = 30 Capacitor units in array
1 1 1 1 1 = 31 Capacitor units in array
Analog Switch Cap Type A Block 10 Control 1 Register (ASA10CR1, Address = Bank 0/1, 81h)
Analog Switch Cap Type A Block 12 Control 1 Register (ASA12CR1, Address = Bank 0/1, 89h)
Analog Switch Cap Type A Block 21 Control 1 Register (ASA21CR1, Address = Bank 0/1, 95h)
Analog Switch Cap Type A Block 23 Control 1 Register (ASA23CR1, Address = Bank 0/1, 9Dh)
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Analog PSoC Blocks
10.8.3.3
Analog Switch Cap Type A Block xx Control 2 Register
AnalogBus gates the output to the analog column bus.
The output on the analog column bus is affected by the
state of the ClockPhase bit in Control 0 Register
(ASA10CR0, ASA12CR0, ASA21CR0, ASA23CR0). If
AnalogBus is set to 0, the output to the analog column
bus is tri-stated. If AnalogBus is set to 1, the signal that is
output to the analog column bus is selected by the
ClockPhase bit. If the ClockPhase bit is 0, the block out-
put is gated by sampling clock on last part of PHI2. If the
ClockPhase bit is 1, the block output continuously drives
the analog column bus.
CompBus controls the output to the column comparator
bus. Note that if the comparator bus is not driven by any-
thing in the column, it is pulled low. The comparator out-
put is evaluated on the rising edge of internal PHI1 and
is latched so it is available during internal PHI2.
AutoZero controls the shorting of the output to the invert-
ing input of the op-amp. When shorted, the op-amp is
basically a follower. The output is the op-amp offset. By
using the feedback capacitor of the integrator, the block
can memorize the offset and create an offset cancella-
tion scheme. AutoZero also controls a pair of switches
between the A and B branches and the summing node of
the op-amp. If AutoZero is enabled, then the pair of
switches is active. AutoZero also affects the function of
the FSW1 bit in Control 3 Register.
The CCap bits set the value of the capacitor in the C
path.
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Table 71:
Analog Switch Cap Type A Block xx Control 2 Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
AnalogBus CompBus
AutoZero
CCap[4]
CCap[3]
CCap[2]
CCap[1]
CCap[0]
Bit 7: AnalogBus Enable output to the analog bus
0 = Disable output to analog column bus
1 = Enable output to analog column bus
(The output on the analog column bus is affected by the state of the ClockPhase bit in Control 0 Register
(ASA10CR0, ASA12CR0, ASA21CR0, ASA23CR0). If AnalogBus is set to 0, the output to the analog column bus is
tri-stated. If AnalogBus is set to 1, the signal that is output to the analog column bus is selected by the ClockPhase
bit. If the ClockPhase bit is 0, the block output is gated by sampling clock on last part of PHI2. If the ClockPhase bit
is 1, the block output continuously drives the analog column bus.)
Bit 6: CompBus Enable output to the comparator bus
0 = Disable output to comparator bus
1 = Enable output to comparator bus
Bit 5: AutoZero Bit for controlling gated switches
0 = Shorting switch is not active. Input cap branches shorted to op-amp input
1 = Shorting switch is enabled during internal PHI1. Input cap branches shorted to analog ground during internal
PHI1 and to op-amp input during internal PHI2.
Bit [4:0]: CCap [4:0] Binary encoding for 32 possible capacitor sizes for C Capacitor:
0 0 0 0 0 = 0 Capacitor units in array
0 0 0 0 1 = 1 Capacitor units in array
0 0 0 1 0 = 2 Capacitor units in array
0 0 0 1 1 = 3 Capacitor units in array
0 0 1 0 0 = 4 Capacitor units in array
0 0 1 0 1 = 5 Capacitor units in array
0 0 1 1 0 = 6 Capacitor units in array
0 0 1 1 1 = 7 Capacitor units in array
0 1 0 0 0 = 8 Capacitor units in array
0 1 0 0 1 = 9 Capacitor units in array
0 1 0 1 0 = 10 Capacitor units in array
0 1 0 1 1 = 11 Capacitor units in array
0 1 1 0 0 = 12 Capacitor units in array
0 1 1 0 1 = 13 Capacitor units in array
0 1 1 1 0 = 14 Capacitor units in array
0 1 1 1 1 = 15 Capacitor units in array
1 0 0 0 0 = 16 Capacitor units in array
1 0 0 0 1 = 17 Capacitor units in array
1 0 0 1 0 = 18 Capacitor units in array
1 0 0 1 1 = 19 Capacitor units in array
1 0 1 0 0 = 20 Capacitor units in array
1 0 1 0 1 = 21 Capacitor units in array
1 0 1 1 0 = 22 Capacitor units in array
1 0 1 1 1 = 23 Capacitor units in array
1 1 0 0 0 = 24 Capacitor units in array
1 1 0 0 1 = 25 Capacitor units in array
1 1 0 1 0 = 26 Capacitor units in array
1 1 0 1 1 = 27 Capacitor units in array
1 1 1 0 0 = 28 Capacitor units in array
1 1 1 0 1 = 29 Capacitor units in array
1 1 1 1 0 = 30 Capacitor units in array
1 1 1 1 1 = 31 Capacitor units in array
Analog Switch Cap Type A Block 10 Control 2 Register (ASA10CR2, Address = Bank 0/1, 82h)
Analog Switch Cap Type A Block 12 Control 2 Register (ASA12CR2, Address = Bank 0/1, 8Ah)
Analog Switch Cap Type A Block 21 Control 2 Register (ASA21CR2, Address = Bank 0/1, 96h)
Analog Switch Cap Type A Block 23 Control 2 Register (ASA23CR2, Address = Bank 0/1, 9Eh)
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Analog PSoC Blocks
10.8.3.4
Analog Switch Cap Type A Block xx Control 3 Register
ARefMux selects the reference input of the A capacitor
branch.
enabled at all times. If the AutoZero bit is 1, the switch is
enabled only when the internal PHI2 is high.
FSW1 is used to control a switch in the integrator capac-
itor path. It connects the output of the op-amp to the inte-
grating cap. The state of the switch is affected by the
FSW0 is used to control a switch in the integrator capac-
itor path. It connects the output of the op-amp to analog
ground.
state of the AutoZero bit in Control
2 Register
BMuxSCA controls the muxing to the input of the B
capacitor branch.
(ASA10CR2, ASA12CR2, ASA21CR2, ASA23CR2). If
the FSW1 bit is set to 0, the switch is always disabled. If
the FSW1 bit is set to 1, the AutoZero bit determines the
state of the switch. If the AutoZero bit is 0, the switch is
Power – encoding for selecting 1 of 4 power levels. The
block always powers up in the off state.
Table 72:
Bit #
Analog Switch Cap Type A Block xx Control 3 Register
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
ARefMux[1] ARefMux[0] FSW[1]
FSW[0] BMuxSCA[1] BMuxSCA[0] Power[1] Power[0]
Bit [7:6]: ARefMux [1:0] Encoding for selecting reference input
0 0 = Analog ground is selected
0 1 = REFHI input selected (This is usually the high reference)
1 0 = REFLO input selected (This is usually the low reference)
1 1 = Reference selection is driven by the comparator (When output comparator node is set high, the input is set to
REFHI. When set low, the input is set to REFLO)
Bit 5: FSW1 Bit for controlling gated switches
0 = Switch is disabled
1 = If the FSW1 bit is set to 1, the state of the switch is determined by the AutoZero bit. If the AutoZero bit is 0, the
switch is enabled at all times. If the AutoZero bit is 1, the switch is enabled only when the internal PHI2 is high
Bit 4: FSW0 Bits for controlling gated switches
0 = Switch is disabled
1 = Switch is enabled when PHI1 is high
Bit [3:2] BMuxSCA [1:0] Encoding for selecting B inputs. (Note that the available mux inputs vary by individual
PSoC block.)
ASA10
ASA21 ASA12 ASA23
0 0 = ACA00 ASB11 ACA02 ASB13
0 1 = ASB11 ASB20
ASB13 ASB22
ASB11 P2.0
1 0 = P2.3
ASB22
1 1 = ASB20
T GND ASB22 ABUS3
ref
Bit [1:0]: Power [1:0] Encoding for selecting 1 of 4 power levels
0 0 = Off
0 1 = 10 µA, typical
1 0 = 50 µA, typical
1 1 = 200 µA, typical
Analog Switch Cap Type A Block 10 Control 3 Register (ASA10CR3, Address = Bank 0/1, 83h)
Analog Switch Cap Type A Block 12 Control 3 Register (ASA12CR3, Address = Bank 0/1, 8Bh)
Analog Switch Cap Type A Block 21 Control 3 Register (ASA21CR3, Address = Bank 0/1, 97h)
Analog Switch Cap Type A Block 23 Control 3 Register (ASA23CR3, Address = Bank 0/1, 9Fh)
May 17, 2005
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
10.9 Analog Switch Cap Type B PSoC Blocks
10.9.1
Introduction
The Analog Switch Cap Type B PSoC blocks are built
around an operational amplifier. There are several ana-
log muxes that are controlled by register-bit settings in
the control registers that determine the signal topology
inside the block. There are also four arrays of unit value
capacitors that are located in the feedback path for the
op-amp, and are switched by two phase clocks, PHI1
and PHI2. These four capacitor arrays are labeled A Cap
Array, B Cap Array, C Cap Array, and F Cap Array. There
is also an analog comparator connected to the output
OUT, which converts analog comparisons into digital sig-
nals.
There are three discrete outputs from this block. These
outputs are:
1. The analog output bus (ABUS), which is an analog
bus resource that is shared by all of the analog
blocks in the analog column for that block.
2. The comparator bus (CBUS), which is a digital bus
that is a resource that is shared by all of the analog
blocks in a column for that block.
3. The output bus (OUT), which is an analog bus
resource that is shared by all of the analog blocks in
a column and connects to one of the analog output
buffers, to send a signal externally to the device.
The SCB block also supports Delta-Sigma, Successive
Approximation and Incremental A/D Conversion, Capaci-
tor DACs, and SC filters. It has two input arrays of
switched capacitors, and a Non-Switched capacitor feed-
back array from the output. When preceded by an SC
Block A Integrator, the combination can be used to pro-
vide a full Switched Capacitor Biquad.
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Analog PSoC Blocks
φ1*AutoZero
FCap
16,32 C
CCap
0..31 C
(φ2+!AutoZero)
* FSW1
BQTAP
φ1* FSW0
A Mux
ACap
0..31 C
φ1
φ2
φ2+AutoZero
A Inputs
REFHI
REFLO
AGND
φ1 *
!AutoZero
OUT
ARefMux
ASign
AnalogBus*φ2B
ABUS
BCap
0..31 C
φ2 +!BSW
φ2+!BSW
φ1*BSW
Power
CompBus
CBUS
B Inputs
φ1*BSW
BMuxSCB
Figure 26: Analog Switch Cap Type B PSoC Blocks
10.9.2
Registers
Analog Switch Cap Type B Block xx Control 0 Register
10.9.2.1
FCap controls the size of the switched feedback capaci-
tor in the integrator.
ASign controls the switch phasing of the switches on the
bottom plate of the A capacitor. The bottom plate sam-
ples the input or the reference.
ClockPhase controls the internal clock phasing relative
to the input clock phasing. ClockPhase affects the output
of the analog column bus which is controlled by the
The ACap bits set the value of the capacitor in the A
path.
AnalogBus bit in Control
2 Register (ASB11CR2,
ASB13CR2, ASB20CR2, ASB22CR2).
Table 73:
Analog Switch Cap Type B Block xx Control 0 Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
FCap
ClockPhase
ASign
ACap[4]
ACap[3]
ACap[2]
ACap[1]
ACap[0]
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Table 73:
Analog Switch Cap Type B Block xx Control 0 Register, continued
Bit 7: FCap F Capacitor value selection bit
0 = 16 capacitor units
1 = 32 capacitor units
Bit 6: ClockPhase Clock phase select, will invert clocks internal to the blocks. During normal operation of an SC
block for the amplifier of a column enabled to drive the output bus, the connection is only made for the last half of
PHI2 (during PHI1 and for the first half of PHI2, the output bus floats at the last voltage to which it was driven). This
forms a sample and hold operation using the output bus and its associated capacitance. This design prevents the
output bus from being perturbed by the intermediate states of the SC operation (often a reset state for PHI1 and
settling to the valid state during PHI2)
Following are the exceptions: 1) If the ClockPhase bit in CR0 (for the SC block in question) is set to 1, then the out-
put is enabled for the whole of PHI2. 2) If the SHDIS signal is set in bit 6 of the Analog Clock Select Register, then
sample and hold operation is disabled for all columns and all enabled outputs of SC blocks are connected to their
respective output busses for the entire period of their respective PHI2s
0 = Internal PHI1 = External PHI1
1 = Internal PHI1 = External PHI2
This bit also affects the latching of the comparator output (CBUS). Both clock phases, PHI1 and PHI2, are involved
in the output latching mechanism. The capture of the next value to be output from the latch (capture point event)
happens during the falling edge of one clock phase, and the rising edge of the other clock phase will cause the
value to come out (output point event). This bit determines which clock phase triggers the capture point event, and
the other clock will trigger the output point event. The value output to the comparator bus will remain stable
between output point events.
0 = Capture Point Event triggered by Falling PHI2, Output Point Event triggered by Rising PHI1
1 = Capture Point Event triggered by Falling PHI1, Output Point Event triggered by Rising PHI2
Bit 5: ASign
0 = Input sampled on Internal PHI1, Reference Input sampled on internal PHI2
1 = Input sampled on Internal PHI2, Reference Input sampled on internal PHI1
Bit [4:0]: ACap [4:0] Binary encoding for 32 possible capacitor sizes for A Capacitor:
0 0 0 0 0 = 0 Capacitor units in array
0 0 0 0 1 = 1 Capacitor units in array
0 0 0 1 0 = 2 Capacitor units in array
0 0 0 1 1 = 3 Capacitor units in array
0 0 1 0 0 = 4 Capacitor units in array
0 0 1 0 1 = 5 Capacitor units in array
0 0 1 1 0 = 6 Capacitor units in array
0 0 1 1 1 = 7 Capacitor units in array
0 1 0 0 0 = 8 Capacitor units in array
0 1 0 0 1 = 9 Capacitor units in array
0 1 0 1 0 = 10 Capacitor units in array
0 1 0 1 1 = 11 Capacitor units in array
0 1 1 0 0 = 12 Capacitor units in array
0 1 1 0 1 = 13 Capacitor units in array
0 1 1 1 0 = 14 Capacitor units in array
0 1 1 1 1 = 15 Capacitor units in array
1 0 0 0 0 = 16 Capacitor units in array
1 0 0 0 1 = 17 Capacitor units in array
1 0 0 1 0 = 18 Capacitor units in array
1 0 0 1 1 = 19 Capacitor units in array
1 0 1 0 0 = 20 Capacitor units in array
1 0 1 0 1 = 21 Capacitor units in array
1 0 1 1 0 = 22 Capacitor units in array
1 0 1 1 1 = 23 Capacitor units in array
1 1 0 0 0 = 24 Capacitor units in array
1 1 0 0 1 = 25 Capacitor units in array
1 1 0 1 0 = 26 Capacitor units in array
1 1 0 1 1 = 27 Capacitor units in array
1 1 1 0 0 = 28 Capacitor units in array
1 1 1 0 1 = 29 Capacitor units in array
1 1 1 1 0 = 30 Capacitor units in array
1 1 1 1 1 = 31 Capacitor units in array
Analog Switch Cap Type B Block 11 Control 0 Register (ASB11CR0, Address = Bank 0/1, 84h)
Analog Switch Cap Type B Block 13 Control 0 Register (ASB13CR0, Address = Bank 0/1, 8Ch)
Analog Switch Cap Type B Block 20 Control 0 Register (ASB20CR0, Address = Bank 0/1, 90h)
Analog Switch Cap Type B Block 22 Control 0 Register (ASB22CR0, Address = Bank 0/1, 98h)
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Analog PSoC Blocks
10.9.2.2
Analog Switch Cap Type B Block xx Control 1 Register
AMux controls the input muxing for the A capacitor
branch.
The BCap bits set the value of the capacitor in the B
path.
Table 74:
Analog Switch Cap Type B Block xx Control 1 Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
AMux[2]
AMux[1]
AMux[0]
BCap[4]
BCap[3]
BCap[2]
BCap[1]
BCap[0]
Bit [7:5]: AMux [2:0] Input muxing select for A capacitor branch. (Note that available mux inputs vary by individual
PSoC block.)
ASB11
ASB13
ACA03
P2.2
ASA12
ASA23
REFHI
ACA02
ASB20
ASA10
P2.1
ASA21
ABUS0
REFHI
ASB11
ASB22
ASA12
ASA21
ASA23
ABUS2
REFHI
ASB13
0 0 0 = ACA01
0 0 1 = ASA12
0 1 0 = ASA10
0 1 1 = ASA21
1 0 0 = REFHI
1 0 1 = ACA00
1 1 0 = Reserved Reserved Reserved Reserved
1 1 1 = Reserved Reserved Reserved Reserved
Bit [4:0]: BCap [4:0] Binary encoding for 32 possible capacitor sizes for B Capacitor:
0 0 0 0 0 = 0 Capacitor units in array
0 0 0 0 1 = 1 Capacitor units in array
0 0 0 1 0 = 2 Capacitor units in array
0 0 0 1 1 = 3 Capacitor units in array
0 0 1 0 0 = 4 Capacitor units in array
0 0 1 0 1 = 5 Capacitor units in array
0 0 1 1 0 = 6 Capacitor units in array
0 0 1 1 1 = 7 Capacitor units in array
0 1 0 0 0 = 8 Capacitor units in array
0 1 0 0 1 = 9 Capacitor units in array
0 1 0 1 0 = 10 Capacitor units in array
0 1 0 1 1 = 11 Capacitor units in array
0 1 1 0 0 = 12 Capacitor units in array
0 1 1 0 1 = 13 Capacitor units in array
0 1 1 1 0 = 14 Capacitor units in array
0 1 1 1 1 = 15 Capacitor units in array
1 0 0 0 0 = 16 Capacitor units in array
1 0 0 0 1 = 17 Capacitor units in array
1 0 0 1 0 = 18 Capacitor units in array
1 0 0 1 1 = 19 Capacitor units in array
1 0 1 0 0 = 20 Capacitor units in array
1 0 1 0 1 = 21 Capacitor units in array
1 0 1 1 0 = 22 Capacitor units in array
1 0 1 1 1 = 23 Capacitor units in array
1 1 0 0 0 = 24 Capacitor units in array
1 1 0 0 1 = 25 Capacitor units in array
1 1 0 1 0 = 26 Capacitor units in array
1 1 0 1 1 = 27 Capacitor units in array
1 1 1 0 0 = 28 Capacitor units in array
1 1 1 0 1 = 29 Capacitor units in array
1 1 1 1 0 = 30 Capacitor units in array
1 1 1 1 1 = 31 Capacitor units in array
Analog Switch Cap Type B Block 11 Control 1 Register (ASB11CR1, Address = Bank 0/1, 85h)
Analog Switch Cap Type B Block 13 Control 1 Register (ASB13CR1, Address = Bank 0/1, 8Dh)
Analog Switch Cap Type B Block 20 Control 1 Register (ASB20CR1, Address = Bank 0/1, 91h)
Analog Switch Cap Type B Block 22 Control 1 Register (ASB22CR1, Address = Bank 0/1, 99h)
May 17, 2005
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
10.9.2.3
Analog Switch Cap Type B Block xx Control 2 Register
AnalogBus gates the output to the analog column bus.
The output on the analog column bus is affected by the
state of the ClockPhase bit in Control 0 Register
(ASB11CR0, ASB13CR0, ASB20CR0, ASB22CR0). If
AnalogBus is set to 0, the output to the analog column
bus is tri-stated. If AnalogBus is set to 1, the ClockPhase
bit selects the signal that is output to the analog-column
bus. If the ClockPhase bit is 0, the block output is gated
by sampling clock on last part of PHI2. If the ClockPhase
bit is 1, the block ClockPhase continuously drives the
analog column bus.
CompBus controls the output to the column comparator
bus. Note that if the comparator bus is not driven by any-
thing in the column, it is pulled low. The comparator out-
put is evaluated on the rising edge of internal PHI1 and
is latched so it is available during internal PHI2.
AutoZero controls the shorting of the output to the invert-
ing input of the op-amp. When shorted, the op-amp is
basically a follower. The output is the op-amp offset. By
using the feedback capacitor of the integrator, the block
can memorize the offset and create an offset cancella-
tion scheme. AutoZero also controls a pair of switches
between the A and B branches and the summing node of
the op-amp. If AutoZero is enabled, then the pair of
switches is active. AutoZero also affects the function of
the FSW1 bit in Control 3 Register.
The CCap bits set the value of the capacitor in the C
path.
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Analog PSoC Blocks
Table 75:
Analog Switch Cap Type B Block xx Control 2 Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
AnalogBus CompBus
AutoZero
CCap[4]
CCap[3]
CCap[2]
CCap[1]
CCap[0]
Bit 7: AnalogBus Enable output to the analog bus
0 = Disable output to analog column bus
1 = Enable output to analog column bus
(The output on the analog column bus is affected by the state of the ClockPhase bit in Control 0 Register
(ASB11CR0, ASB13CR0, ASB20CR0, ASB22CR0). If AnalogBus is set to 0, the output to the analog column bus is
tri-stated. If AnalogBus is set to 1, the ClockPhase bit selects the signal that is output to the analog column bus. If the
ClockPhase bit is 0, the block output is gated by sampling clock on last part of PHI2. If the ClockPhase bit is 1, the
block output continuously drives the analog column bus)
Bit 6: CompBus Enable output to the comparator bus
0 = Disable output to comparator bus
1 = Enable output to comparator bus
Bit 5: AutoZero Bit for controlling gated switches
0 = Shorting switch is not active. Input cap branches shorted to op-amp input
1 = Shorting switch is enabled during internal PHI1. Input cap branches shorted to analog ground during internal
PHI1 and to op-amp input during internal PHI2.
Bit [4:0]: CCap [4:0] Binary encoding for 32 possible capacitor sizes for C Capacitor:
0 0 0 0 0 = 0 Capacitor units in array
0 0 0 0 1 = 1 Capacitor units in array
0 0 0 1 0 = 2 Capacitor units in array
0 0 0 1 1 = 3 Capacitor units in array
0 0 1 0 0 = 4 Capacitor units in array
0 0 1 0 1 = 5 Capacitor units in array
0 0 1 1 0 = 6 Capacitor units in array
0 0 1 1 1 = 7 Capacitor units in array
0 1 0 0 0 = 8 Capacitor units in array
0 1 0 0 1 = 9 Capacitor units in array
0 1 0 1 0 = 10 Capacitor units in array
0 1 0 1 1 = 11 Capacitor units in array
0 1 1 0 0 = 12 Capacitor units in array
0 1 1 0 1 = 13 Capacitor units in array
0 1 1 1 0 = 14 Capacitor units in array
0 1 1 1 1 = 15 Capacitor units in array
1 0 0 0 0 = 16 Capacitor units in array
1 0 0 0 1 = 17 Capacitor units in array
1 0 0 1 0 = 18 Capacitor units in array
1 0 0 1 1 = 19 Capacitor units in array
1 0 1 0 0 = 20 Capacitor units in array
1 0 1 0 1 = 21 Capacitor units in array
1 0 1 1 0 = 22 Capacitor units in array
1 0 1 1 1 = 23 Capacitor units in array
1 1 0 0 0 = 24 Capacitor units in array
1 1 0 0 1 = 25 Capacitor units in array
1 1 0 1 0 = 26 Capacitor units in array
1 1 0 1 1 = 27 Capacitor units in array
1 1 1 0 0 = 28 Capacitor units in array
1 1 1 0 1 = 29 Capacitor units in array
1 1 1 1 0 = 30 Capacitor units in array
1 1 1 1 1 = 31 Capacitor units in array
Analog Switch Cap Type B Block 11 Control 2 Register (ASB11CR2, Address = Bank 0/1, 86h)
Analog Switch Cap Type B Block 13 Control 2 Register (ASB13CR2, Address = Bank 0/1, 8Eh)
Analog Switch Cap Type B Block 20 Control 2 Register (ASB20CR2, Address = Bank 0/1, 92h)
Analog Switch Cap Type B Block 22 Control 2 Register (ASB22CR2, Address = Bank 0/1, 9Ah)
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
10.9.2.4
Analog Switch Cap Type B Block xx Control 3 Register
ARefMux selects the reference input of the A capacitor
branch.
FSW0 is used to control a switch in the integrator capac-
itor path. It connects the output of the op-amp to analog
ground.
FSW1 is used to control a switch in the integrator capac-
itor path. It connects the output of the op-amp to the inte-
grating cap. The state of the switch is affected by the
BSW is used to control switching in the B branch. If dis-
abled, the B capacitor branch is a continuous time
branch like the C branch of the SC A Block. If enabled,
then on internal PHI1, both ends of the cap are switched
to analog ground. On internal PHI2, one end is switched
to the B input and the other end is switched to the sum-
ming node.
state of the AutoZero bit in Control
2 Register
(ASB11CR2, ASB13CR2, ASB20CR2, ASB22CR2). If
the FSW1 bit is set to 0, the switch is always disabled. If
the FSW1 bit is set to 1, the AutoZero bit determines the
state of the switch. If the AutoZero bit is 0, the switch is
enabled at all times. If the AutoZero bit is 1, the switch is
enabled only when the internal PHI2 is high.
BMuxSCB controls muxing to the input of the B capacitor
branch. The B branch can be switched or unswitched.
Table 76:
Analog Switch Cap Type B Block xx Control 3 Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
ARefMux[1] ARefMux[0]
FSW[1]
FSW[0]
BSW
BMuxSCB Power[1]
Power[0]
Bit [7:6]: ARefMux [1:0] Encoding for selecting reference input
0 0 = Analog ground is selected
0 1 = REFHI input selected (This is usually the high reference)
1 0 = REFLO input selected (This is usually the low reference)
1 1 = Reference selection is driven by the comparator (When output comparator node is set high, the input is set to
REFHI. When set low, the input is set to REFLO)
Bit 5: FSW1 Bit for controlling gated switches
0 = Switch is disabled
FSW1 bit is set to 1; the state of the switch is determined by the AutoZero bit. If the AutoZero bit is 0, the switch is
enabled at all times. If the AutoZero bit is 1, the switch is enabled only when the internal PHI2 is high
Bit 4: FSW0 Bits for controlling gated switches
0 = Switch is disabled
1 = Switch is enabled when PHI1 is high
Bit 3: BSW Enable switching in branch
0 = B branch is a continuous time path
1 = B branch is switched with internal PHI2 sampling
Bit 2: BMuxSCB Encoding for selecting B inputs. (Note that the available mux inputs vary by individual PSoC block)
ASB11 ASB13 ASB20 ASB22
0 = ACA00 ACA02 ASB11 ASB13
1 = ACA01 ACA03 ASA10 ASA12
Bit [1:0]: Power [1:0] Encoding for selecting 1 of 4 power levels
0 0 = Off
0 1 = 10 µA, typical
1 0 = 50 µA, typical
1 1 = 200 µA, typical
Analog Switch Cap Type B Block 11 Control 3 Register (ASB11CR3, Address = Bank 0/1, 87h)
Analog Switch Cap Type B Block 13 Control 3 Register (ASB13CR3, Address = Bank 0/1, 8Fh)
Analog Switch Cap Type B Block 20 Control 3 Register (ASB20CR3, Address = Bank 0/1, 93h)
Analog Switch Cap Type B Block 22 Control 3 Register (ASB22CR3, Address = Bank 0/1, 9Bh)
100
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Analog PSoC Blocks
10.10 Analog Comparator Bus
Each analog column has a dedicated comparator bus
associated with it. Every analog PSoC block has a com-
parator output that can drive out on this bus, but the
comparator output from only one analog block in a col-
umn can be actively driving the comparator bus for that
column at any one time. The output on the comparator
bus can drive into the digital blocks, and is also available
to be read in the Analog Comparator Control Register
(CMP_CR, Address = Bank 0,64H).
The output from the analog block that is actively driving
the bus may also be latched internal to the analog block
itself.
In the Continuous Time analog blocks, the CPhase and
CLatch bits inside the Analog Continuous Time Type A
Block xx Control Register 2 determine whether the out-
put signal on the comparator bus is latched inside the
block, and if it is, which clock phase it is latched on.
In the Switched Capacitor analog blocks, the output on
the comparator bus is always latched. The ClockPhase
bit in the Analog SwitchCap Type A Block xx Control
Register 0 or the Analog SwitchCap Type B Block xx
Control Register 0 determines the phase on which this
data is latched and available.
The comparator bus is latched before it is available to
either drive the digital blocks, or be read in the Analog
Comparator Control Register. The latch for each compar-
ator bus is transparent (the output tracks the input) dur-
ing the high period of PHI2. During the low period of
PHI2 the latch retains the value on the comparator bus
during the high to low transition of PHI2.
Table 77:
Analog Comparator Control Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
R
R
R
R
RW
RW
RW
RW
Bit Name
COMP 3
COMP 2
COMP 1
COMP 0
AINT 3
AINT 2
AINT 1
AINT 0
Bit 7: COMP 3 COMP 3 bit [0] indicates the state of the analog comparator bus for the Analog Column x
Bit 6: COMP 2 COMP 2 bit [0] indicates the state of the analog comparator bus for the Analog Column x
Bit 5: COMP 1 COMP 1 bit [0] indicates the state of the analog comparator bus for the Analog Column x
Bit 4: COMP 0 COMP 0 bit [0] indicates the state of the analog comparator bus for the Analog Column x
Bit 3: AINT 3 AINT 3 bit [0] or [1] (as defined below) selects the Analog Interrupt Source for the Analog Column x
Bit 2: AINT 2 AINT 2 bit [0] or [1] (as defined below) selects the Analog Interrupt Source for the Analog Column x
Bit 1: AINT 1 AINT 1 bit [0] or [1] (as defined below) selects the Analog Interrupt Source for the Analog Column x
Bit 0: AINT 0 AINT 0 bit [0] or [1] (as defined below) selects the Analog Interrupt Source for the Analog Column x
0 = Comparator bus
1 = PHI2 (Falling edge of PHI2 causes an interrupt)
Analog Comparator Control Register (CMP_CR, Address = Bank 0, 64h)
10.11 Analog Synchronization
For high precision analog operation, it may be necessary
to precisely time when updated register values are avail-
able to the analog PSOC blocks. The optimum time to
update values in Switch Cap registers is at the beginning
of the PHI1 active period. The SYNCEN bit in the Analog
Synchronization Control Register is designed to address
this. (The AINT bits of the Analog Comparator Register
(CMP_CR) are another way to address it with interrupts.)
When the SYNCEN bit is set, a subsequent write instruc-
tion to any register in a Switch Cap block will cause the
CPU to stall until the rising edge of PHI1. This mode is in
effect until the SYNCEN bit is cleared.
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
The SAR hardware accelerator is a block of specialized
ware accelerator. The DAC and SAR User Modules
operate in this mode. The analog column clock fre-
quency must not be a power of two multiple (2, 4, 8...)
higher than the CPU clock frequency. Under this condi-
tion, the CPU will never recover from a stall.
hardware designed to sequence the SAR algorithm for
efficient A/D conversion. A SAR ADC is implemented
conceptually with a DAC of the desired precision, and a
comparator. This functionality can be configured from
one or more PSoC blocks. For each conversion, the firm-
ware should initialize the ASY_CR register as defined
below, and set the sign bit of the DAC as the first guess
in the algorithm. A sequence of OR instructions (Read,
Modify, Write) to the DAC (CR0) register is then exe-
cuted. Each of these OR instructions causes the SAR
hardware to read the current state of the comparator,
checking the validity of the previous guess. It either
clears it or leaves it set, accordingly. The next LSB in the
DAC register is also set as the next guess. Six OR
instructions will complete the conversion of a 6-bit DAC.
The resulting DAC code, which matches the input volt-
age to within 1 LSB, is then read back from the DAC
CR0 register.
See the list of relationships (in MHz) that will fail:
Table 78:
Analog Column Clock
3.
Analog Frequency Relationships
CPU Clock
1.5, 0.75, .018, 0.093
0.75, 0.18, 0.093
0.18, 0.093
1.5
0.75
0.37
0.18
0.18, 0.093
0.093
You can still run the CPU clock slower than the column
clock if the relationship is not a power of two multiple.
For example, you can run at 0.6 MHz, which is not a
power of two multiple of any CPU frequency and there-
fore any CPU frequency can be selected. If the CPU fre-
quency is greater than or equal to the analog column
clock, there is not a problem.
10.11.1 Analog Stall and Analog Stall Lockup
Stall lockup affects the operation of stalled IO writes,
such as DAC writes and the stalled IOR of the SAR hard-
Table 79:
Analog Synchronization Control Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
--
W
W
W
RW
RW
RW
RW
SARCOUNT SARCOUNT SARCOUNT
[2] [1] [0]
SAR-
SIGN
SARCOL
[1]
SARCOL
[0]
SYN-
CEN
Bit Name
Reserved
Bit 7: Reserved
Bit [6:4]: SARCOUNT [2:0] Initial SAR count. Load this field with the number of bits to process. In a typical 6-bit
SAR, the value would be 6
Bit 3: SARSIGN Adjust the SAR comparator based on the type of block addressed. In a DAC configuration with
more than one PSoC block (more than 6-bits), this bit would be 0 when processing the most significant block and 1
when processing the least significant block. This is because the least significant block of a DAC is an inverting input
to the most significant block
Bit [2:1]: SARCOL [1:0] Column select for SAR comparator input. The DAC portion of the SAR can reside in any of
the appropriate positions in the analog PSOC block array. However, once the comparator block is positioned (and it
is possible to have the DAC and comparator in the same block), this should be the column selected
Bit 0: SYNCEN Set to 1, will stall the CPU until the rising edge of PHI1, if a write to a register within an analog Switch
Cap block takes place
Analog Synchronization Control Register (ASY_CR, Address = Bank 0, 65h)
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Analog PSoC Blocks
10.12 Analog I/O
10.12.1
Analog Input Muxing
ACI0
MUX
ACI1
MUX
MUX
ACI2
MUX
ACI3
ACM0
ACM1
ACM2
ACM3
ACol1Mux
AC1
ACol2Mux
AC2
AC0
BUF
BUF
BUF
AC3
BUF
ACA00
ACA01
ASB11
ASA21
ACA02
ASA12
ASB22
ACA03
ASB13
ASA23
P2[3]
ASA10
ASB20
P2[2]
P2[0]
P2[1]
Figure 27: Analog Input Muxing
10.12.2 Analog Input Select Register
This register controls the analog muxes that feed signals
in from port pins into each Analog Column. Each of the
Analog Columns can have up to four port bits connected
to its muxed input. Analog Columns 01 and 02 (ACI1 and
ACI2) have additional muxes that allow selection
between separate column multiplexers (see Analog Input
Muxing diagram above). The AC1Mux and AC2Mux bit
fields control the bits for those muxes and are located in
the Analog Output Buffer Control Register (ABF_CR).
There are four additional analog inputs that go directly
into the Switch Capacitor PSoC blocks.
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Table 80:
Analog Input Select Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
ACI3 [1]
ACI3 [0]
ACI2 [1]
ACI2 [0]
ACI1 [1]
ACI1 [0]
ACI0 [1]
ACI0 [0]
Bit [7:6]: ACI3 [1:0]
0 0 = ACM3 P0[0]
0 1 = ACM3 P0[2]
1 0 = ACM3 P0[4]
1 1 = ACM3 P0[6]
Bit [5:4]: ACI2 [1:0]
0 0 = ACM2 P0[1]
0 1 = ACM2 P0[3]
1 0 = ACM2 P0[5]
1 1 = ACM2 P0[7]
ACol2Mux (ABF_CR, Address = Bank1, 62h)
0 = AC2 = ACM2
1 = AC2 = ACM3
Bit [3:2]: ACI1 [1:0]
0 0 = ACM1 P0[0]
0 1 = ACM1 P0[2]
1 0 = ACM1 P0[4]
1 1 = ACM1 P0[6]
ACol1Mux (ABF_CR, Address = Bank1, 62h)
0 = AC1 = ACM1
1 = AC1 = ACM0
Bit [1:0]: ACI0 [1:0]
0 0 = ACM0 P0[1]
0 1 = ACM0 P0[3]
1 0 = ACM0 P0[5]
1 1 = ACM0 P0[7]
Analog Input Select Register (AMX_IN, Address = Bank 0, 60h)
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Analog PSoC Blocks
10.12.3
Analog Output Buffers
The user has the option to output up to four analog sig-
nals on the pins of the device. This is done by enabling
the analog output buffers associated with each Analog
Column. The enable bits for the analog output buffers
are contained in the Analog Output Buffer Control Regis-
ter (ABF_CR).
P0[3]
P0[5]
P0[4]
P0[2]
ACA 00
ASA 10
ASB 20
ACA 01
ASB 11
ASA 21
ACA 02
ACA 03
ASB 13
ASA 23
ASA 12
ASB 22
Figure 28: Analog Output Buffers
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
10.12.4 Analog Output Buffer Control Register
Table 81:
Analog Output Buffer Control Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
W
W
W
W
W
W
--
W
Bit Name
ACol1Mux ACol2Mux ABUF1EN ABUF2EN ABUF0EN ABUF3EN Reserved
PWR
Bit 7: ACol1Mux
0 = Set column 1 input to column 1 input mux output
1 = Set column 1 input to column 0 input mux output
Bit 6: ACol2Mux
0 = Set column 2 input to column 2 input mux output
1 = Set column 2 input to column 3 input mux output
Bit 5: ABUF1EN Enables the analog output buffer for Analog Column 1 (Pin P0[5])
0 = Disable analog output buffer
1 = Enable analog output buffer
Bit 4: ABUF2EN Enables the analog output buffer for Analog Column 2 (Pin P0[4])
0 = Disable analog output buffer
1 = Enable analog output buffer
Bit 3: ABUF0EN Enables the analog output buffer for Analog Column 0 (Pin P0[3])
0 = Disable analog output buffer
1 = Enable analog output buffer
Bit 2: ABUF3EN Enables the analog output buffer for Analog Column 3 (Pin P0[2])
0 = Disable analog output buffer
1 = Enable analog output buffer
Bit [1]: Reserved Must be left as 0
Bit [0]: PWR Determines power level of all output buffers
0 = Low output power
1 = High output power
Analog Output Buffer Control Register (ABF_CR, Address = Bank 1, 62h)
10.13 Analog Modulator
The user has the capability to use the Analog Switch
Cap Type A PSoC Blocks in Columns 0 and 2 as ampli-
tude modulators. The Analog Modulator Control Register
(AMD_CR) allows the user to select the appropriate
modulating signal. When the modulating signal is low,
the polarity follows the setting of the ASign bit set in the
Analog Switch Cap Type
A Control 0 Register
(ASAxxCR0). When this signal is high, the normal gain
polarity of the PSoC block is inverted.
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Analog PSoC Blocks
Table 82:
Analog Modulator Control Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
Reserved Reserved Reserved Reserved AMOD2[1] AMOD2[0] AMOD0[1] AMOD0[0]
Bit 7: Reserved
Bit 6: Reserved
Bit 5: Reserved
Bit 4: Reserved
Bit [3:2]: AMOD2[1], AMOD2[0] Selects the modulation signal for Analog Column 2
0 0 = No Modulation
0 1 = Global Output [0]
1 0 = Global Output [4]
1 1 = Digital Basic Type A Block 03
Bit [1:0]: AMOD0[1], AMOD0[0] Selects the modulation signal for Analog Column 0
0 0 = No Modulation
0 1 = Global Output [0]
1 0 = Global Output [4]
1 1 = Digital Basic Type A Block 03
Analog Modulator Control Register (AMD_CR, Address = Bank 1, 63h)
10.14 Analog PSoC Block Functionality
Amplitude Modulators
Amplitude Demodulators
Sine-Wave Generators
Sine-Wave Detectors
Sideband Detection
Sideband Stripping
Audio Output Drive
DTMF Generator
The analog PSoC blocks can be used to implement a
wide range of functions, limited only by the designer’s
imagination. The following functions operate within the
capability of the analog PSoC blocks using one analog
PSoC block, multiple analog blocks, a combination of
more than one type of analog block, or a combination of
analog and digital PSoC blocks. Most of these functions
are currently available as User Modules in PSoC
Designer. Others will be added in the future.
FSK Modulator
Delta-Sigma A/D Converters
Successive Approximation A/D Converters
Incremental A/D Converters
Programmable Gain/Loss Stage
Analog Comparators
By modifying registers, as described in this Data Sheet,
users can configure PSoC blocks to perform these func-
tions and more.
Zero-Crossing Detectors
Low-Pass Filter
Band-Pass Filter
Notch Filter
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10.15 Temperature Sensing Capability
A temperature-sensitive voltage derived from the Band
Gap sensing on the die is buffered and available as an
analog input into the Analog Switch Cap Type A Block
ASA21. Temperature sensing allows protection of device
operating ranges for fail-safe applications. Temperature
sensing combined with a long sleep timer interval (to
allow the die to approximate ambient temperature) can
give an approximate ambient temperature for data acqui-
sition and battery charging applications. The user may
also calibrate the internal temperature rise based on a
known current consumption.
The temperature sensor input to the ASA21 block is
labeled VTemp, and its associated ground reference is
labeled TRefGND (see Figure 22:, Figure 24:).
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Special Features of the CPU
11.0 Special Features of the CPU
11.1 Multiplier/Accumulator
A fast, on-chip signed 2’s complement MAC (Multiply/
Accumulate) function is provided to assist the main CPU
with digital signal processing applications. Multiply
results, as well as the lower 2 bytes of the Accumulator,
are available immediately after the input registers are
written. The upper 2 bytes require a single instruction
delay before reading. The MAC function is tied directly
on the internal data bus, and is mapped into the register
space. The following MAC block diagram provides data
flow information. The user has the choice to either cause
a multiply/accumulate function to take place, or a multi-
ply only function. The user selects which operation is
performed by the choice of input register. The multiply
function occurs immediately whenever the MUL_X or the
MUL_Y multiplier input registers are written, and the
result is available in the MUL_DH and MUL_DL multiplier
result registers. The Multiply/Accumulate function is exe-
cuted whenever there is a write to the MAC_X or the
MAC_Y Multiply/Accumulate input registers, and the
result is available in the ACC_DR3, ACC_DR2,
ACC_DR1, and ACC_DR0 accumulator result registers.
A write to MUL_X or MAC_X is input as the X value to
both the multiply and Multiply/Accumulate functions. A
write to MUL_Y or MAC_Y is input as the Y value to both
the multiply and Multiply/Accumulate functions. A write to
the MAC_CL0 or MAC_CL1 registers will clear the value
in the four accumulate registers.
An extra instruction must be inserted between the follow-
ing sequences of MAC operations to provide extra delay.
If this is not done, the Accumulator results will be inaccu-
rate.
a. Two MAC instructions in succession:
mov reg[MAC_X],a
nop //add nop or any other instruction
mov reg[MAC_X],a
For sequence a., there is no workaround, the nop or
other instruction must be inserted.
b. A MAC instruction followed by a read of the
most significant Accumulator bytes:
mov reg[MAC_X],a
nop //add nop or any other instruction
mov a,[ACC_DR2] // or ACC_DR3
For sequence b., the least significant Accumulator bytes
(ACC_DR0, ACC_DR1) may be reliably read directly
after the MAC instruction.
Writing to the multiplier registers (MUL_X, MUL_Y), and
reading the result back from the multiplier product regis-
ters (MUL_DH, MUL_DL), is not affected by this problem
and does not have any restrictions.
Operation of the Multiply/Accumulate function relies on
proper multiplicand input. The first value of each multipli-
cand must be placed into MUL_X (or MUL_Y) register to
avoid causing a Multiply/Accumulate to occur. The sec-
ond multiplicand must be placed into MAC_Y (or
MAC_X) thereby triggering the Multiply/Accumulate
function.
MUL_X, MUL_Y, MAC_X, and MAC_Y are 8-bit signed
input registers. MUL_DL and MUL_DH form a 16-bit
signed output. ACC_DR0, ACC_DR1, ACC_DR2 and
ACC_DR3 form a 32-bit signed output.
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
MUL_DH
MUL_DL
To
MUL_X or MAC_X
MUL_Y or MAC_Y
Internal
System
Bus
ACC_DR3
Z out, 16 BIT
16 BIT
MULTIPLIER
ACC_DR2
ACC_DR1
ACC_DR0
32-BIT
ACCUMULATOR
32-BIT ACC
MA C_CL1
MA C_CL0
Figure 29: Multiply/Accumulate Block Diagram
Multiply Input X Register
Table 83:
Bit #
POR
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Read/Write
Name
W
W
W
W
W
W
W
W
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]: Data [7:0] 8-bit data is the input value for X multiplier
Multiply Input X Register (MUL_X, Address = Bank 0, E8h)
Table 84:
Multiply Input Y Register
Bit #
POR
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Read/Write
Bit Name
W
W
W
W
W
W
W
W
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]: Data [7:0] 8-bit data is the input value for Y multiplier
Multiply Input Y Register (MUL_Y, Address = Bank 0, E9h)
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Special Features of the CPU
Table 85:
Multiply Result High Register
Bit #
POR
7
6
5
4
3
2
1
0
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Read/Write
Bit Name
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]: Data [7:0] 8-bit data value is the high order result of the multiply function
Multiply Result High Register (MUL_DH, Address = Bank 0, EAh)
Table 86:
Multiply Result Low Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Read/Write
Bit Name
R
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]: Data [7:0] 8-bit data value is the low order result of the multiply function
Multiply Result Low Register (MUL_DL, Address = Bank 0, EBh)
Table 87:
Accumulator Result 1 / Multiply/Accumulator Input X Register
Bit #
POR
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Read/Write
Bit Name
RW
RW
RW
RW
RW
RW
RW
RW
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]: Data [7:0]
8-bit data value when read is the next to lowest order result of the multiply/accumulate function
8-bit data value when written is the X multiplier input to the multiply/accumulate function
Accumulator Result 1 / Multiply/Accumulator Input X Register (ACC_DR1 / MAC_X, Address = Bank 0, ECh)
Table 88:
Accumulator Result 0 / Multiply/Accumulator Input Y Register
Bit #
POR
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Read/Write
Bit Name
RW
RW
RW
RW
RW
RW
RW
RW
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]: Data [7:0]
8-bit data value when read is the lowest order result of the multiply/accumulate function
8-bit data value when written is the Y multiplier input to the multiply/accumulate function
Accumulator Result 0 / Multiply/Accumulator Input Y Register (ACC_DR0 / MAC_Y, Address = Bank 0, EDh)
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Table 89:
Accumulator Result 3 / Multiply/Accumulator Clear 0 Register
Bit #
POR
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Read/Write
Bit Name
RW
RW
RW
RW
RW
RW
RW
RW
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]: Data [7:0]
8-bit data value when read is the highest order result of the multiply/accumulate function
Any 8-bit data value when written will cause all four Accumulator result registers to clear
Accumulator Result 3 / Multiply/Accumulator Clear 0 Register (ACC_DR3 / MAC_CL0, Address = Bank 0, EEh)
Table 90:
Accumulator Result 2 / Multiply/Accumulator Clear 1 Register
Bit #
POR
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Read/Write
Bit Name
RW
RW
RW
RW
RW
RW
RW
RW
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]: Data [7:0]
8-bit data value when read is next to highest order result of the multiply/accumulate function
Any 8-bit data value when written will cause all four Accumulator result registers to clear
Accumulator Result 2 / Multiply/Accumulator Clear 1 Register (ACC_DR2 / MAC_CL1, Address = Bank 0, EFh)
11.2 Decimator
The output of a ∆−Σ modulator is a high-speed, single bit
A/D converter. A single bit A/D converter is of little use to
anyone and must be converted to a lower speed multiple
bit output. Converting this high-speed single bit data
stream to a lower speed multiple bit data stream requires
a data decimator.
A “divide by n” decimator is a digital filter that takes the
single bit data at a fast rate and outputs multiple bits at
th
one n the speed. For a single stage ∆−Σ converter, the
2
optimal filter has a sinc response. This filter can be
implemented as a finite impulse response (FIR) filter and
for a “divide by n” implementation should have the follow-
ing coefficients:
Coeff
n
0
t
2n-1
n-1
0
Figure 30: Decimator Coefficients
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Special Features of the CPU
This filter is implemented using a combination of hard-
ware and software resources. Hardware is used to accu-
mulate the high-speed in-coming data while the software
is used to process the lower speed, enhanced resolution
data for output.
Table 91:
Decimator/Incremental Control Register
Bit #
POR
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Read/Write
Bit Name
RW
RW
RW
RW
RW
RW
RW
RW
IGEN [3] IGEN [2]
IGEN [1]
IGEN [0]
ICCKSEL
DCol [1]
DCol [0]
DCLKSEL
Bit [7:4]: IGEN [3:0] Individual enables for each analog column that gates the Analog Comparator based on the
ICCKSEL input (Bit 3)
Bit 3: ICCKSEL Clock select for Incremental gate function
0 = Digital Basic Type A Block 02
1 = Digital Communications Type A Block 06
Bit [2:1]: DCol [1:0] Selects Analog Column Comparator source
0 0 = Analog Column Comparator 0
0 1 = Analog Column Comparator 1
1 0 = Analog Column Comparator 2
1 1 = Analog Column Comparator 3
Bit 0: DCLKSEL Clock select for Decimator latch
0 = Digital Basic Type A Block 02
1 = Digital Communications Type A Block 06
Decimator Incremental Register (DEC_CR, Address = Bank 0, E6h)
Table 92:
Decimator Data High Register
Bit #
POR
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Read/Write
Bit Name
RW
RW
RW
RW
RW
RW
RW
RW
Data [7]
Data [6]
Data [5]
Data [4]
Data [3] Data [2]
Data [1]
Data [0]
Bit [7:0]: Data [7:0]
8-bit data value when read is the high order byte within the 16-bit decimator data registers
Any 8-bit data value when written will cause both the Decimator Data High (DEC_DH) and Decimator Data Low
(DEC_DL) registers to be cleared
Decimator High Register (DEC_DH / DEC_CL, Address = Bank 0, E4h)
Table 93:
Decimator Data Low Register
Bit #
POR
7
6
5
4
3
2
1
0
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Read/Write
Bit Name
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]: Data [7:0]
8-bit data value when read is the low order byte within the 16 bit decimator data registers
Decimator Data Low Register (DEC_DL, Address = Bank 0, E5h)
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
11.3 Reset
tively. The firmware can interrogate these bits to deter-
mine the cause of a reset.
11.3.1 Overview
The microcontroller supports two types of resets. When
reset is initiated, all registers are restored to their default
states and all interrupts are disabled.
The microcontroller resumes execution from ROM
address 0x0000 after a reset. The internal clocking mode
is active after a reset, until changed by user firmware. In
addition, the Sleep / Watchdog Timer is reset to its mini-
mum interval count.
Reset Types: Power On Reset (POR), External Reset
(X ), and Watchdog Reset (WDR).
res
The occurrence of a reset is recorded in the Status and
Control Register (CPU_SCR). Bits within this register
record the occurrence of POR and WDR Reset respec-
Important: The CPU clock defaults to divide by 8 mode
at POR to guarantee operation at the low Vcc that might
be present during the supply ramp.
Table 94:
Processor Status and Control Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
Read/
Write
1
1
R
--
RW
--
--
RW
R/C
R/C
Bit Name
IES
Reserved
WDRS
PORS
Sleep
Reserved Reserved
Stop
Bit 7: IES Global interrupt enable status from CPU Flag register
0 = Global interrupts disabled
1 = Global interrupts enabled
Bit 6: Reserved
Bit 5: WDRS
WDRS is set by the CPU to indicate that a Watchdog Reset event has occurred. The user can read this bit to deter-
mine the type of reset that has occurred. The user can clear but not set this bit
0 = No WDR
1 = A WDR event has occurred
Bit 4: PORS
PORS is set by the CPU to indicate that a Power On Reset event has occurred. The user can read this bit to deter-
mine the type of reset that has occurred. The user can clear but not set this bit
0 = No POR
1 = A POR event has occurred. (Note that WDR events will not occur until this bit is cleared)
Bit 3: Sleep Set by the user to enable CPU sleep state. CPU will remain in sleep mode until any interrupt is pending
0 = Normal operation
1 = Sleep
Bit 2: Reserved
Bit 1: Reserved
Bit 0: Stop Set by the user to halt the CPU. The CPU will remain halted until a reset (WDR or POR) has taken place
0 = Normal CPU operation
1 = CPU is halted (not recommended)
1. C = Clear
Status and Control Register (CPU_SCR, Address = Bank 0/1, FFh)
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Special Features of the CPU
11.3.2
Power On Reset (POR)
Power On Reset (POR) occurs every time the power to
the device is switched on. POR is released when the
supply is typically 2.2V +/-12% for the upward supply
transition, with typically 120mV of hysterisis during the
power on transient. Bit 4 of the Status and Control Regis-
ter (CPU_SCR) is set to record this event (the register
contents are set to 00010000 by the POR). After a POR,
the microprocessor is suspended for 64 ms. This pro-
vides time for the Vcc supply to stabilize after the POR
trip, before CPU operation begins. If the Vcc voltage
drops below the POR downward supply trip point (2.1V
+/-12%, once the internal reference is established), POR
is reasserted.
Important: The PORS status bit is set at POR and can
only be cleared by the user, and cannot be set by firm-
ware.
11.3.3
Execution Reset
The following diagram illustrates the sequence of events
(in time) for execution reset, from voltage stabilization on
through execution of user’s code. Once voltage trips
POR and after 64 ms, the CPU starts boot calibration.
Boot calibration takes 2,502 cycles, with the CPU run-
ning at 3 MHz. This results in approximately 800 µs for
the time between beginning boot calibration and reset
vector. At reset vector, the boot.asm must execute
before user code begins running. (boot.asm contains
device configurations from PSoC Designer. The time it
takes boot.asm to execute varies depending on device
configuration settings such as CPU speed.)
3.0V (Good)
TrVdd
V
cc
Power
3.0 - 5.5
POR 2.2V ± 12%
64 ms
2502 ~
Reset
Vector
Boot
Calibration
boot.asm
Start CPU
3 MHz
User Code
Figure 31: Execution Reset
The only exception to this is if a POR event takes place,
which will disable the WDT.
11.3.4 External Reset (Xres
)
Pulling the X pin high for a minimum of 10 µS forces
res
The sleep timer is used to generate the sleep time period
and the watchdog time period. The sleep timer divides
down the 32K system clock, and thereby produces the
sleep time period. The user can program the sleep time
period to be one of 4 multiples of the period of the 32K
clock. When the sleep time elapses (sleep timer over-
flows), an interrupt to the Sleep Timer Interrupt Vector
will be generated.
the microcontroller to perform a Power On Reset (POR).
The X
pin does not require a pull-down resistor for
res
operation and can be tied directly to ground, or left open.
11.3.5 Watchdog Timer Reset (WDR)
The user has the option to enable the WDT. The WDT is
enabled by clearing the PORS bit. Once the PORS bit is
cleared, the Watchdog Timer (WDT) cannot be disabled.
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The Watchdog Timer period is automatically set to be 3
This timer chain is also used to time the startup for the
external 32 kHz crystal oscillator. When selecting the
external 32 kHz oscillator, a value of 1 second must be
selected as the sleep interval. When the sleep interrupt
occurs, the 32 kHz oscillator source will switch from
internal to the crystal. The device does not have to be
put into sleep for this event to occur. Note that if too short
of a sleep interval is given, the crystal oscillator will not
be stable prior to switch over and the results will be
unpredictable.
counts of the Sleep Timer overflows. This represents
between two and three sleep intervals depending on the
count in the Sleep Timer at the previous WDT clear.
When this timer reaches 3, a WDR is generated.
The user can either clear the WDT, or the WDT and the
Sleep Timer. Whenever the user writes to the Reset
WDT Register (RES_WDT), the WDT will be cleared. If
the data that is written is the hex value 38H, the Sleep
Timer will also be cleared at the same time.
Table 95:
Reset WDT Register
Bit #
POR
7
0
6
5
0
4
0
3
0
2
0
1
0
0
0
0
W
Read/Write
Bit Name
W
W
W
W
W
W
W
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]: Data [7:0] Any write to this register will clear Watchdog Timer, a write of 38h will also clear the Sleep Timer
Reset WDT Register (RES_WDT, Address = Bank 0, E3h)
11.4 Sleep States
There are three sleep states that can be used to lower
the overall power consumption on the device. The three
states are CPU Sleep, Analog Sleep, and Full Sleep.
enable bits within each analog PSoC block. Setting the
Analog Array Power Control bits will restore the function
to those analog PSoC blocks that were previously in use.
The user should take into account the required settling
time after an analog PSoC block is enabled before it will
provide the maximum precision.
The CPU can only be put to sleep by the firmware. This
is accomplished by setting the Sleep Bit in the Status
and Control Register (CPU_SCR). This stops the CPU
from executing instructions, and the CPU will remain
asleep until an interrupt comes pending, or there is a
reset event (either a Power On Reset, or a Watchdog
Timer Reset). While in the CPU Sleep state, all clocking
signals derived from the Internal Main Oscillator are
inactivated, including the 48M, 24M, 24V1, and 24V2
system clocking signals. The Internal Low Speed Oscilla-
tor will continue to operate during the CPU Sleep state.
The function of any analog or digital PSoC block that is
clocked from these system-clocking signals will stop dur-
ing the CPU Sleep state.
For greatest power savings, the user should put the
device in the Full Sleep state. This is accomplished by
first transitioning to the Analog Sleep state, and then set-
ting the Sleep Bit in the CPU_SCR Register to the Full
Sleep state. The CPU will be stopped at this point, and
either an interrupt or reset event is required to transition
back to the Analog Sleep state.
The Voltage Reference and Supply Voltage Monitor drop
into (fully functional) power-reduced states. All interrupts
remain active. The Internal Low Speed Oscillator
remains running (it will however drop into a less accu-
rate, low-power state). If enabled, the External Crystal
Oscillator will continue running throughout sleep (the
Internal Low Speed Oscillator is disabled if the External
Crystal Oscillator is selected). Only the occurrence of an
The user can also put all the analog PSoC block circuits
to sleep. This is accomplished by resetting the Analog
Array Power Control bits in the Analog Reference Con-
trol Register (ARF_CR), which overrides the individual
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Special Features of the CPU
interrupt will wake the part from sleep. The Stop bit in the
Status and Control Register (CPU_SCR) must be
cleared for a part to resume out of sleep.
CPU Running
Any digital PSoC block that is clocked by a System Clock
other than the 32K system-clocking signal or external
pins will be stopped, as these clocks do not run in sleep
mode.
Analog
Sleep
Run
The Internal Main Oscillator restarts immediately on exit-
ing either the Full Sleep or CPU Sleep modes. Analog
functions must be re-enabled by firmware. If the External
Crystal Oscillator is used and the internal PLL is
enabled, the PLL will take many cycles to change from
its initial 2.5% accuracy to track that of the External Crys-
tal Oscillator. If the PLL is enabled, there will be a 30µs
(one full 32K cycle) delay hold-off time for the CPU to let
the VCO and PLL stabilize. If the PLL is not enabled, the
hold-off time is one half of the 32K cycle. For further
details on PLL, see 7.0.
CPU Sleep
Full Sleep
CPU not Running
Figure 32: Three Sleep States
The Sleep interrupt allows the microcontroller to wake up
periodically and poll system components while maintain-
ing very low average power consumption. The sleep
interrupt may also be used to provide periodic interrupts
during non-sleep modes.
In System Sleep State, GPIO Pins P2[4] and P2[6]
should be held to a logic low or a false Low Voltage
Detect interrupt may be triggered. The cause is in the
System Sleep State, the internal Bandgap reference
generator is turned off and the reference voltage is main-
tained on a capacitor.
The circumstances are that during sleep, the reference
voltage on the capacitor is refreshed periodically at the
sleep system duty cycle. Between refresh cycles, this
voltage may leak slightly to either the positive supply or
ground. If pins P2[4] or P2[6] are in a high state, the leak-
age to the positive supply is accelerated (especially at
high temperature). Since the reference voltage is com-
pared to the supply to detect a low voltage condition, this
accelerated leakage to the positive supply voltage will
cause that voltage to appear lower than it actually is,
leading to the generation of a false Low Voltage Detect
interrupt.
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117
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
11.5 Supply Voltage Monitor
The Supply Voltage Monitor detector generates an inter-
rupt whenever Vcc drops below a pre-programmed
value. There are eight voltage trip points that are select-
able by setting the VM [2:0] bit in the Voltage Monitor
Control Register (VLT_CR). These bits also select the
Switch Mode Pump trip points. The Supply Voltage Mon-
itor will remain active when the device enters sleep
mode.
Table 96:
Voltage Monitor Control Register
Bit #
POR
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read/
Write
W
--
--
--
--
W
W
W
Bit Name
SMP
Reserved Reserved Reserved Reserved
VM [2]
VM [1]
VM [0]
Bit 7: SMP Disables SMP function
0 = Switch Mode Pump enabled, default
1 = Switch Mode Pump disabled
Bit 6: Reserved
Bit 5: Reserved
Bit 4: Reserved
Bit 3: Reserved
Bit [2:0]: VM [2:0]
Low Voltage Detection
Switch Mode Pump
1
0 0 0 = 2.95 Trip Voltage 0 0 0 = 3.17 Trip Voltage
0 0 1 = 3.02 Trip Voltage 0 0 1 = 3.25 Trip Voltage
0 1 0 = 3.17 Trip Voltage 0 1 0 = 3.42 Trip Voltage
0 1 1 = 3.71 Trip Voltage 0 1 1 = 3.94 Trip Voltage
1 0 0 = 4.00 Trip Voltage 1 0 0 = 4.19 Trip Voltage
1 0 1 = 4.48 Trip Voltage 1 0 1 = 4.64 Trip Voltage
1 1 0 = 4.56 Trip Voltage 1 1 0 = 4.82 Trip Voltage
1 1 1 = 4.64 Trip Voltage 1 1 1 = 5.00 Trip Voltage
1. Voltages are ideal typical values. Tolerances are in Table 104 on page 129.
Voltage Monitor Control Register (VLT_CR, Address = Bank 1, E3h)
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Special Features of the CPU
11.6 Switch Mode Pump
This feature is available on the CY8C26xxx versions
within this family. During the time Vcc is ramping from 0
up and boot sequence, firmware can disable the SMP
function by writing Voltage Monitor Control Register
(VLT_CR) bit 7 to a 1.
Volts to POR V (2.2V +/- 12%), IC operation is held off
trip
by the POR circuit and the Switch Mode Pump is
enabled. The pump is realized by connecting an external
inductor between the battery voltage and SMP, with an
When the IC is put into sleep mode, the power supply
pump will remain running to maintain voltage. This may
result in higher than specification sleep current depend-
ing upon application. If the user desires, the pump may
be disabled during precision measurements (such as A/
D conversions) and then re-enabled (writing B7 to 1 and
then back to 0 again). The user, however, is responsible
for making the operation happen quickly enough to guar-
antee supply holdup (by the bypass capacitor) sufficient
for continued operation.
external diode pointing from SMP to the V pin (which
cc
must have a bypass capacitance of at least 0.1uF con-
nected to V ). This circuitry will pump Vcc to the Switch
cc
Mode Pump value specified in the Voltage Monitor Con-
trol Register (VLT_CR), shown above. Battery voltage
values down to 0.9 V during operation are supported, but
this circuitry is not guaranteed to start for battery volt-
ages below 1.2 V. Once the IC is enabled after its power
VCC
Power For All Circuitry
SMP
SMP
Control
Logic
SMP Reset
X RST
Reset
To Rest Of
Circuitry
Figure 33: Switch Mode Pump
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119
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
11.7 Internal Voltage Reference
An internal bandgap voltage reference source is pro-
vided on-chip. This reference is used for the Supply Volt-
age Monitor, and can also be accessed by the user as a
reference voltage for analog operations. There is a
Bandgap Oscillator Trim Register (BDG_TR) used to cal-
ibrate this reference into specified tolerance. Factory-
programmed trim values are available for 5.0V and 3.3V
operation. The 5.0V value is loaded in the BDG_TR reg-
ister upon reset. This register must be adjusted when
operating voltage outside the range for which factory cal-
ibration was set. Changing the factory-programmed trim
value is done using the Table Read Supervisor Call rou-
tine, and is documented in 11.8.
Table 97:
Bandgap Trim Register
Bit #
POR
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
FS
FS
FS
FS
FS
FS
FS
FS
Read/Write
Bit Name
W
W
W
W
W
W
W
W
FMRD
BGT[2]
BGT[1]
BGT[0]
BGO[3]
BGO[2]
BGO[1]
BGO[0]
Bit 7: FMRD
0 = Enable voltage divider between BG and Flash (User must not use other than this setting)
1 = Disable voltage divider between BG and Flash (Test purposes only)
Bit [6:4]: BGT [2:0] Provides Temperature Curve compensation
Bit [3:0]: BGO [3:0] Provides +/- 5% Offset Trim to center Vbg to 1.30V
1. FS = Factory set trim value
Bandgap Trim Register (BDG_TR, Address = Bank 1, EAh)
11.8 Supervisor ROM/System Supervisor Call Instruction
The parts in this family have a Supervisor ROM to man-
age the programming, erasure, and protection of the on-
chip Flash user program space. The Supervisor ROM
also gives the user the capability to read the internal
product ID, access factory trim values, as well as calcu-
late checksums on blocks of the Flash memory space.
eters when utilizing these functions. The parameters are
written to 5 bytes of an 8-byte block near the top of RAM
memory space.
Access to these functions must be through the Flash
APIs provided in PSoC Designer and described in Appli-
cation Note AN2015.
The System Supervisor Call instruction (SSC, opcode/
byte 00h) provides the method for the user to access the
pre-existing routines in the Supervisor ROM to imple-
ment these functions. This instruction sets the Flags
Register (CPU_F) bit 3 to 1 and performs an interrupt to
address 0000 into the Supervisory ROM. The flag and
old PC are pushed onto the Stack. The fact that the flag
pushed has F[3] = 1 is irrelevant as the RETIinstruction
always clears F[3]. The Supervisory code at 0000 does a
JACC table lookup based on the Accumulator value,
which is effectively another level of instruction encoding.
This service table implements the vectors to the various
supervisory functions. The user must set several param-
The following table documents each function, as well as
the required parameter values:
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Special Features of the CPU
Table 98:
CY8C25122, CY8C26233, CY8C26443, CY8C26643 (256 Bytes of SRAM)
Input SRAM Data
Output SRAM Data
Operation Function
F8h F9h FAh
FBh
FCh
FDh FEh FFh F8h F9h FAh FBh FCh FDh FEh FFh
Calibrates
then sets
PC and SP
values to 0
1
00 NA
NA
NA
NA
NA
NA
NA
0
NA
0
NA
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Reset
Move block
of 64 bytes
of FLASH
data into
SRAM
SP
+3
Blk
ID
Read Block
Write Block2
01 3Ah
Pointer
0
0
Program
block of
FLASH with 02 3Ah
SP
+3
Blk
ID
Pointer Clock
0
0
0
0
0
*
*
*
*
*
*
data from
SRAM
Erase block
03 3Ah
SP
+3
Blk
ID
Erase Block
NA
NA
Clock
Clock
0
0
0
0
0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
of FLASH
Set memory
SP
+3
Protect Block3
protection
bits4
04 3Ah
NA
NA
Erase all
FLASH data
SP
+3
Erase All3
05 3Ah
06 3Ah
NA
NA
Clock
NA
0
0
0
Read device
type code
SP
+3
Tbl
ID
TV
(0)
TV
(1)
TV
(2)
TV
(3)
TV
(4)
TV
(5)
TV
(6)
TV
(7)
Table Read
NA
NA
NA
Calculate
FLASH
checksum
for data
range speci-
fied
Blk
Cou
nter
SP
+3
CS
H
Checksum
Calibrate5
07 3Ah
08 3Ah
NA
NA
NA
NA
0
0
0
CSL
*
*
*
*
*
*
*
*
*
*
*
*
Sets user-
writable reg-
isters to
SP
+3
NA
0
0
default
1. This is a software-only reset.
2. This operation should only be invoked by calling a function in the FlashBlock library. Device specifications are no
longer guaranteed if this function is directly called by the user’s code.
3. This function can only be invoked by the device programmer, not by user’s code.
4. The address is hard coded by algorithm.
5. User-writeable registers include Main Oscillator Trim (IMO_TR), Internal Low Speed Oscillator Trim (ILO_TR), and
Bandgap Trim (BDG_TR).
Notes:
NA: Not applicable
*: Indeterminate
Blk ID: Number of 64-byte block within FLASH memory space
Clock: CPU system clocking signal value
Pointer: Address of first byte of 64-byte block within SRAM memory space
TV: Table value
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121
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
register is modified during the Table Read Supervisory
Call, and must be saved and restored if needed after the
call completes.
11.8.1 Additional Function for Table Read
Supervisory Call
The Table Read supervisory operation will return the Ver-
sion ID in the Accumulator. The value in the Accumulator
is divided into a high and low nibble, indicating major and
minor revisions, respectively. Note: The value in the X
A[7:4]: Major silicon revisions.
A[3:0]: Minor silicon revisions.
Table 99:
Table Read for Supervisory Call Functions
Table
ID
Function
TV(0)
TV(1)
TV(2)
TV(3)
TV(4)
TV(5)
TV(6)
TV(7)
Produc-
tion Sili-
con ID
Silicon ID Silicon ID
1
Reserved Reserved Reserved Reserved Reserved Reserved
00
1
0
Provides
trim value
for Inter-
nal Main
Oscillator Refer-
and Inter- ence trim
Internal
Voltage
Internal
Voltage
Refer-
ence trim tor trim
value for value for
Internal
Main
Oscilla-
Internal
Main
01
Oscillator Reserved Reserved
trim value
for 3.3V
Reserved Reserved
nal Volt-
age
value for
3.3V
5.0V
5.0V
Refer-
ence
1. Determines silicon revision values in Accumulator and X registers.
11.9 Flash Program Memory Protection
The user has the option to define the access to the Flash
11.10 Programming Requirements and
Step Descriptions
memory. A flexible system allows the user to select one
of four protection modes for each 64-byte block within
the Flash, based on the particular application. The pro-
tection mechanism is implemented by a device program-
mer using the System Supervisor Call. When this
command is executed, two bits within the data pro-
grammed into the Flash will select the protection mode.
It is not intended that the protection byte will be modified
by the user’s code. The following table lists the available
protection options:
The pins in the following table are critical for the pro-
grammer:
Table 101: Programmer Requirements
Pin
Name
Programmer HW Pin
Requirements
Function
Serial Data In/Out
Serial Clock
Drive TTL Levels,
Read TTL, High Z
SDATA
SCLK
Drive TTL levEl Clock
Signal
Table 100: Flash Program Memory Protection
Power Supply
Ground Connec-
tion
Low Resistance
Ground Connection
V
Mode
Bits
External External Internal
ss
Mode Name
Read
Write
Write
00
Unprotected
Enabled Enabled
Disabled Enabled
Enabled
0V, 3.0V, 5V, & 5.4V.
0.1V Accuracy. 20mA
Current Capability
Power Supply
Positive Voltage
V
cc
Factory
Upgrade
01
Enabled
10
11
Field Upgrade
Full Protection
Disabled Disabled Enabled
Disabled Disabled Disabled
Note: Mode 10 is the default.
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Special Features of the CPU
11.10.1 Data File Read
Erase All
WAIT-AND-POLL
The user’s data file should be read into the programmer.
The checksum should be calculated by the programmer
for each record and compared to the record checksum
stored in the file for each record. If there is an error, a
message should be sent to the user explaining that the
file has a checksum error and the programming should
not be allowed to continue.
11.10.2.3 Program
The Flash is programmed with the contents of the user’s
programming file. This is accomplished by the following
sequence:
For num_block = 0 to max_data_block
For address =0 to 63
11.10.2 Programmer Flow
WRITE-BYTE(address,data):
End for address loop
The following sequence (with descriptions) is the main
flow used to program the devices: (Note that failure at
any step will result in termination of the flow and an error
message to the device programmer’s operator.)
SET-CLK-FREQ(num_MHz_times_5)
SET-BLOCK-NUM(num_block)
PROGRAM-BLOCK
WAIT-AND-POLL
End for num_block loop
11.10.2.1 Verify Silicon ID
11.10.2.4 Verify (at Low Vcc and High Vcc)
The silicon ID is read and verified against the expected
value. If it is not the expected value, then the device is
failed and an error message is sent to the device pro-
grammer’s operator.
The device data is read out to compare to the data in the
user’s programming file. This is accomplished by the fol-
lowing sequence:
For num_block = 0 to max_data_block
SET-BLOCK-NUM (num_block)
VERIFY-SETUP
This test will detect a bad connection to the programmer
or an incorrect device selection on the programmer.
Wait & POLL the SDATA for a high to
low transition
For address =0 to max_byte_per_block
READ-BYTE(address,data)
End for address loop
The silicon ID test is required to be first in the flow and
cannot be bypassed. The sequence is as follows:
Set Vcc=0V
Set SDATA=HighZ
Set SCLK=VILP
End for num_block loop
Set Vcc=Vccp
Note: This should be done 2 times; once at Vcc=Vcclv
Start the programmer’s SCLK driver
“free running”
WAIT-AND-POLL
and once at Vcc=Vcchv.
11.10.2.5 Set Security
ID-SETUP
WAIT-AND-POLL
READ-ID-WORD
The security operation protects certain blocks from being
read or changed. This is done at the end of the flow so
that the security does not interfere with the verify step.
Security is set with the following sequence:
Notes: See “DC Specifications“ table in section 13 for
value of Vccp and VILP. See “AC Specifications” table in
section 13 for value of frequency for the SCLK driver
(Fsclk).
For address =0 to 63
WRITE-SECURITY-BYTE(address,data):
End for address loop
SET-CLK-FREQ(num_MHz_times_5)
SECURE
11.10.2.2 Erase
The Flash memory is erased. This is accomplished by
the following sequence:
WAIT-AND-POLL
Note: This sequence is done at Vcc=Vccp.
SET-CLK-FREQ(num_MHz_times_5)
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CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
11.10.2.6 Device Checksum (at Low Vcc and High Vcc)
The device checksum is retrieved from the device and
compared to the “Device Checksum” from the user’s file
(Note that this is NOT the same thing as the “Record
Checksum.”) The checksum is retrieved from the device
with the following sequence:
Note: This should be done 2 times; once at Vcc=Vcchv
and once at Vcc=Vcclv.
11.10.2.7 Power Down
The last step is to power down the device. This is
accomplished by the following sequence:
CHECKSUM-SETUP(max_data_block)
WAIT-AND-POLL
READ-CHECKSUM(data)
Set SDATA=HighZ (float pin P1[0])
Set SCLK=0V (Vin on pin P1[1]=Vilp)
Set Vcc = 0V
11.11 Programming Wave Forms
Vcc
OUT
OUT
IN
IN
SDATA
Tssclk Thsclk
SCLK
Figure 34: Programming Wave Forms
Notes:
1
2
Vcc is only turned off (0V) at the very beginning and the very end of the flow - not within the programming flow.
When the programmer puts the driver on SDATA in a High Z (floating) state, the SDATA pin will float to a low
due to an internal device pull down circuit.
SCLK is set to VILP during the power up and power down; at other times the SCLK is “free running.” The fre-
quency of the hardware’s SCLK signal must be known by the software because the value (entered in the num-
ber of MegaHertz multiplied by the number 5) must be passed into the device with the SET-CLK-FREQ()
mnemonic.
3
11.12 Programming File Format
The programming file is created by PSoC Designer, the
Cypress MicroSystems development tool. This tool gen-
erates the programming file in an Intel Hex format.
The programmer should assume the data is 30h/HALT if
it is not specified in the user’s data file.
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Development Tools
12.0 Development Tools
Graphical
Designer
Interface
Context
Sensitive Help
Commands
Results
Device
Database
PSoC
Configuration
Sheet
PSoC
Designer
Application
Database
Manufacturing
Info File
Project
Database
Emulation
Pod
In-Circuit
Emulator
Device
Programmer
Figure 35: PSoC Designer Functional Flow
12.1 Overview
The Cypress MicroSystems PSoC Designer is
a
Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
Microsoft® Windows-based, integrated development
environment for the Programmable System-on-Chip
(PSoC) devices. The PSoC Designer runs on Windows
98, Windows NT 4.0, Windows 2000, Windows Millen-
nium (Me), or Windows XP.
PSoC Designer also supports a high-level C language
compiler developed specifically for the devices in the
family.
PSoC Designer helps the customer to select an operat-
ing configuration for the microcontroller, write application
code that uses the microcontroller, and debug the appli-
cation. This system provides design database manage-
ment by project, an integrated debugger with In-Circuit
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125
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
12.2 Integrated Development Environment Subsystems
code to be merged seamlessly with C code. The link
libraries automatically use absolute addressing or can be
compiled in relative mode, and linked with other software
modules to get absolute addressing.
12.2.1 Online Help System
The online help system displays online, context-sensitive
help for the user. Designed for procedural and quick ref-
erence, each functional subsystem has its own context-
sensitive help. This system also provides tutorials and
links to FAQs and an Online Support Forum to aid the
designer in getting started.
The compiler comes complete with embedded libraries
providing port and bus operations, standard keypad and
display support, and extended math functionality.
12.2.2 Device Editor
12.2.5 Debugger
PSoC Designer has several main functions. The Device
Editor subsystem lets the user select different onboard
analog and digital component configurations for the
PSoC blocks. PSoC Designer sets up power-on initial-
ization tables for selected PSoC block configurations and
creates source code for an application framework. The
framework contains software to operate the selected
components and, if the project uses more than one oper-
ating configuration, contains routines to switch between
different sets of PSoC block configurations at runtime.
PSoC Designer can print out a configuration sheet for
given project configuration for use during application pro-
gramming in conjunction with the Device Data Sheet.
Once the framework is generated, the user can add
application-specific code to flesh out the framework. It’s
also possible to change the selected components and
regenerate the framework.
The PSoC Designer Debugger subsystem provides
hardware in-circuit emulation, allowing the designer to
test the program in a physical system while providing an
internal view of the PSoC device. Debugger commands
allow the designer to read and write program and data
memory, read and write I/O registers, read and write
CPU registers, set and clear breakpoints, and provide
program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers
and memory locations of interest.
12.3 Hardware Tools
12.3.1 In-Circuit Emulator
A low cost, high functionality ICE is available for devel-
opment support. This hardware has the capability to pro-
gram single devices.
12.2.3 Assembler
The included CYASM macro assembler supports the
M8C microcontroller instruction set and generates a load
file ready for device programming or system debugging
using the ICE hardware.
12.2.4 C Language Software Development
A C language compiler supports Cypress MicroSystems’
PSoC family devices. Even if you have never worked in
the C language before, the product quickly allows you to
create complete C programs for the PSoC family
devices.
The embedded, optimizing C compiler provides all the
features of C tailored to the PSoC architecture. It
includes a built-in macro assembler allowing assembly
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DC and AC Characteristics
13.0 DC and AC Characteristics
o
o
o
Specifications are valid for -40 C </= T </= 85 C and T </= 100 C as specified, except where noted. Specifications
A
J
o
o
o
for devices running at 24 MHz are valid at -40 C </= T </= 70 C and T </= 82 C.
A
J
5.25
4.75
3.00
93 kHz
12 MHz
24 MHz
CPU Frequency
Figure 36: CY8C25xxx/CY8C26xxx Voltage Frequency Graph
13.1 Absolute Maximum Ratings
Table 102: Absolute Maximum Ratings
Symbol
Absolute Maximum Ratings
Storage Temperature
Minimum
-65
Typical
Maximum
Unit
C
1
o
o
-
-
-
-
-
-
+100
Ambient Temperature with Power Applied
Supply Voltage on V Relative to V
-40
+85
C
-0.5
-0.5
+6.0
V
cc
ss
V
V
+0.5
DC Input Voltage
V
cc
cc
V
-0.5
+0.5
DC Voltage Applied to Tri-state
V
ss
Maximum Current into any Port Pin
-25
-50
-
+50
+50
mA
Maximum Current into any Port Pin Config-
ured as Analog Driver
-
-
mA
2
o
Junction Temperature up to 12 MHz
100
C
o
Junction Temperature at 24 MHz
Static Discharge Voltage
Latch-up Current
-
-
-
-
82
-
C
2000
200
V
-
mA
1. Higher storage temperatures will reduce data retention time.
May 17, 2005
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127
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
2. The temperature rise from junction to ambient is package specific. (See Table 122 on page 149 for thermal imped-
ances of available packages.) User must limit power consumption to comply with this requirement.
Table 103: Temperature Specifications
Symbol
Temperature Specifications
Ambient Temperature
Junction Temperature
Minimum
-40
Typical
24
Maximum
Unit
C
o
o
T
+85
100
A
T
-40
J
C
128
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May 17, 2005
DC and AC Characteristics
13.2 DC Characteristics
Table 104: DC Operating Specifications
Symbol
DC Operating Specifications
Minimum
3.00
Unit
Typical
Maximum
5.25
V
Supply Voltage
-
V
cc
1
2
3
I
I
I
Supply Current
-
5
-
mA
µA
µA
V
8
5
5
cc
Sleep (Mode) Current
-
sb
Sleep (Mode) Current with Crystal Oscillator
Reference Voltage (Bandgap)
Input Low Voltage
-
3
sbxtl
4
V
V
V
V
V
1.275
1.3
-
1.325
ref
-
0.8
V
il
Input High Voltage
2.2
-
-
-
V
ih
h
Hysterisis Voltage
-
-
60
-
mV
V
5
Output Low Voltage
ol
Vss+0.75
6
V
Output High Voltage
V
-1.0
-
-
V
oh
cc
R
Pull Up Resistor Value
Pull Down Resistor Value
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
Capacitive Load on Pins as Output
4000
4000
-
5600
5600
0.1
1.7
1.7
Ideal
8000
8000
5
Ω
pu
R
Ω
pd
I
µA
pF
pF
V
il
7
C
C
V
0.5
0.5
10
in
7
10
out
8
8
8
LVD and SMP Tolerance
0.95 x Ideal
1.05 x Ideal
LVD
o
1. Conditions are 5.0V, 25 C, 3 MHz.
o
2. Without Crystal Oscillator, V = 3.3 V, TA <= 85 C.
cc
o
o
3. Conditions are 3.0V <= V <= 3.6V, -40 C <= TA <= 85 C. Correct operation assumes a properly loaded, 1 uW
cc
maximum drive level, 32.768 kHz crystal.
4. Trimmed for appropriate V .
cc
5. Isink = 25 mA, V = 4.5 V (maximum of 8 IO sinking, 4 on each side of the IC).
cc
6. Isource =10 mA, V = 4.5 V (maximum of 8 IO sourcing, 4 on each side of the IC).
cc
7. Package dependent.
8. Ideal values are +/- 5% absolute tolerance and +/- 1% tolerance relative to each other (for adjacent levels).
May 17, 2005
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129
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
13.2.1
DC Operational Amplifier Specifications
5V Specifications
13.2.1.1
The following table lists guaranteed maximum and mini-
mum specifications for the voltage and temperature
PSoC blocks. The guaranteed specifications are mea-
sured in the Analog Continuous Time PSoC block. Typi-
cal parameters apply to 5V at 25°C and are for design
guidance only. For 3.3V operation, see Table 106 on
page 131.
ranges, 5V +/- 5% and -40°C <= T <= 85°C. The Opera-
A
tional Amplifier is a component of both the Analog Con-
tinuous Time PSoC blocks and the Analog Switch Cap
Table 105: 5V DC Operational Amplifier Specifications
Symbol
5V DC Operational Amplifier Specifications
Input Offset Voltage (Absolute Value)
Minimum
Typical Maximum
Unit
mV
-
7
30
-
Average Input Offset Voltage Drift
-
+24
3
µV/°C
nA
1
-
1000
Input Leakage Current
2
.30
.34
.40
pF
Input Capacitance
3
V
- 1.0
.5
-
-
-
VDC
dB
Common Mode Voltage Range
cc
Common Mode Rejection Ratio
Open Loop Gain
80
80
-
-
dB
High Output Voltage Swing (Worst Case Internal Load)
Bias = Low
Bias = Medium
Bias = High
V
V
V
- .4
- .4
- .4
cc
cc
cc
-
-
-
-
-
-
V
V
V
Low Output Voltage Swing (Worst Case Internal Load)
Bias = Low
Bias = Medium
Bias = High
-
-
-
-
-
-
0.1
0.1
0.1
V
V
V
Supply Current (Including Associated AGND Buffer)
Bias = Low
Bias = Medium
Bias = High
-
-
-
125
280
760
300
600
1500
µA
µA
µA
Supply Voltage Rejection Ratio
60
-
-
dB
1. The leakage current includes the Analog Continuous Time PSoC block mux and the analog input mux. The leak-
age related to the General Purpose I/O pins is not included here.
2. The Input Capacitance includes the Analog Continuous Time PSoC block mux and the analog input mux. The
capacitance of the General Purpose I/O pins is not included here.
3. The common-mode input voltage range is measured through an analog output buffer. The specification includes
the limitations imposed by the characteristics of the analog output buffer.
130
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May 17, 2005
DC and AC Characteristics
13.2.1.2
3.3V Specifications
The following table lists guaranteed maximum and mini-
mum specifications for the voltage and temperature
Cap PSoC blocks. The guaranteed specifications are
measured in the Analog Continuous Time PSoC block.
Typical parameters apply to 5V at 25°C and are for
design guidance only. For 5V operation, see Table 105
on page 130.
ranges, 3.3V +/- 10% and -40°C <= T <= 85°C. The
A
Operational Amplifier is a component of both the Analog
Continuous Time PSoC blocks and the Analog Switch
Table 106: 3.3V DC Operational Amplifier Specifications
Symbol
3.3V DC Operational Amplifier Specifications
Input Offset Voltage (Absolute Value)
Minimum
Typical Maximum
Unit
mV
-
7
30
-
Average Input Offset Voltage Drift
-
+24
2
µV/°C
nA
1
-
700
Input Leakage Current
2
.32
.36
.42
pF
Input Capacitance
3
V
- 1.0
.5
-
-
-
VDC
dB
Common Mode Voltage Range
cc
Common Mode Rejection Ratio
Open Loop Gain
80
80
-
-
dB
High Output Voltage Swing (Worst Case Internal Load)
Bias = Low
Bias = Medium
Bias = High
V
V
V
- .4
- .4
- .4
cc
cc
cc
-
-
-
-
-
-
V
V
V
Low Output Voltage Swing (Worst Case Internal Load)
Bias = Low
Bias = Medium
Bias = High
-
-
-
-
-
-
0.1
0.1
0.1
V
V
V
Supply Current (Including Associated AGND Buffer)
Bias = Low
Bias = Medium
Bias = High
-
-
-
80
112
320
200
300
800
µA
µA
µA
Supply Voltage Rejection Ratio
60
-
-
dB
1. The leakage current includes the Analog Continuous Time PSoC block mux and the analog input mux. The leak-
age related to the General Purpose I/O pins is not included here.
2. The Input Capacitance includes the Analog Continuous Time PSoC block mux and the analog input mux. The
capacitance of the General Purpose I/O pins is not included here.
3. The common-mode input voltage range is measured through an analog output buffer. The specification includes
the limitations imposed by the characteristics of the analog output buffer
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131
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
13.2.2
Analog Input Pin with Multiplexer Specifications
Table 107: DC Analog Input Pin with Multiplexer Specifications
Symbol
DC Analog Input Pin with Multiplexer Specifications
Input Leakage (Absolute Value)
Input Capacitance
Minimum
Typical Maximum
Unit
µA
-
0.1
5
8
-
0.5
-
1.7
10
-
pF
Bandwidth
MHz
V
V
Input Voltage Range
0
cc
13.2.3
Analog Input Pin to Switch Cap Block Specifications
Table 108: DC Analog Input Pin to SC Block Specifications
Symbol
DC Analog Input Pin to SC Block Specifications
Effective input resistance = 1/(f x c)
Input Capacitance
Minimum
Typical Maximum
Unit
1
-
-
MΩ
pF
5
-
0.5
-
10
2
Bandwidth
-
kHz
V
100
V
Input Voltage Range
0
-
cc
1. Assumes 2 pF cap selected and 100 kHz sample frequency.
2. This is a sampled input. Recommendation is Fs/Fin > 10 and for Fs = 1 MHz Fin < 100 kHz.
13.2.4
DC Analog Output Buffer Specifications
The following table lists guaranteed maximum and mini-
mum specifications for the voltage and temperature
parameters apply to 5V at 25°C and are for design guid-
ance only. For 3.3V operation, see Table 110 on
page 133.
ranges, 5V +/- 5% and -40°C <= T <= 85°C. Typical
A
Table 109: 5V DC Analog Output Buffer Specifications
Symbol
5V DC Analog Output Buffer Specifications
Input Offset Voltage (Absolute Value)
Average Input Offset Voltage Drift
Minimum
Typical
Maximum
12
Unit
mV
-
3
-
+6
-
-
µV/°C
V
V
- 1.0
Common-Mode Input Voltage Range
.5
cc
Output Resistance
Bias = Low
Bias = High
-
-
1
1
-
-
Ω
Ω
High Output Voltage Swing (Load = 32 ohms to V /2)
cc
.5 x V + 1.3
cc
.5 x V + 1.3
cc
-
-
-
-
V
V
Bias = Low
Bias = High
Low Output Voltage Swing (Load = 32 ohms to V /2)
cc
.5 x V - 1.3
cc
.5 x V - 1.3
cc
-
-
-
-
V
V
Bias = Low
Bias = High
Supply Current Including Bias Cell (No Load)
Bias = Low
Bias = High
-
-
1.1
2.6
5.1
8.8
mA
mA
Supply Voltage Rejection Ratio
80
-
-
dB
132
Document #: 38-12010 CY Rev. *C
May 17, 2005
DC and AC Characteristics
The following table lists guaranteed maximum and mini-
mum specifications for the voltage and temperature
ranges, 3.3V +/- 10% and -40°C <= T <= 85°C. Typical
A
parameters apply to 5V at 25°C and are for design guid-
ance only. For 5V operation, see Table 109 on page 132.
Table 110: 3.3V DC Analog Output Buffer Specifications
Symbol
3.3V DC Analog Output Buffer Specifications
Input Offset Voltage (Absolute Value)
Average Input Offset Voltage Drift
Minimum
Typical
Maximum
12
Unit
mV
-
3
-
+6
-
-
µV/°C
V
V
- 1.0
Common-Mode Input Voltage Range
.5
cc
Output Resistance
Bias = Low
Bias = High
-
-
1
1
-
-
Ω
Ω
High Output Voltage Swing (Load = 32 ohms to V /2)
cc
.5 x V + 1.3
cc
.5 x V + 1.3
cc
-
-
-
-
V
V
Bias = Low
Bias = High
Low Output Voltage Swing (Load = 32 ohms to V /2)
cc
.5 x V - 1.3
cc
.5 x V - 1.3
cc
-
-
-
-
V
V
Bias = Low
Bias = High
Supply Current Including Bias Cell (No Load)
Bias = Low
Bias = High
-
-
0.8
2.0
2.0
4.3
mA
mA
Supply Voltage Rejection Ratio
80
-
-
dB
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133
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
13.2.5
Switch Mode Pump Specifications
Table 111: DC Switch Mode Pump Specifications
Symbol
DC Switch Mode Pump Specifications
Minimum
Typical Maximum
Unit
1
3.07
-
5.15
V
Output Voltage
Available Output Current
V = 1.5 V V = 3.25 V
2
-
-
-
-
mA
mA
i
,
o
8
V = 1.5 V V = 5.0 V
5
i
,
o
Short Circuit Current (V = 3.3 V)
-
12
-
-
mA
V
i
Input Voltage Range (During sustained operation)
Minimum Input Voltage to Start Pump
1.0
1.1
-
3.3
1.2
5
-
-
Output Voltage Tolerance (Over V Range)
%V
i
o
Line Regulation (Over V Range)
%V
o
-
-
-
5
5
-
-
-
i
%V
Load Regulation
o
3
mV
Output Voltage Ripple (Depends on capacitor and load)
25
pp
Transient Response
50% Load Change to 5% error envelope
µs
%V
o
-
-
1
1
-
-
V Over/Undershoot for 50% Load Change
o
4
Efficiency
50
1.3
50
-
-
-
%
35
Switching Frequency
Switching Duty Cycle
-
-
MHz
%
1. Average, neglecting ripple.
2. For implementation, which includes 2 µH inductor, 1 µF capacitor, and Schottkey diode. Performance is signifi-
cantly a function of external components. Specifications guaranteed for inductors with series resistance less than
0.1 W, with a current rating of > 250 mA, a capacitor with less than 1µA leakage at 5V, and Schottkey diode with
less than 0.6V of drop at 50 mA.
3. Configuration of note 2. Load is 5 mA.
4. Configuration of note 2. Load is 5 mA. V is 3.25V.
out
134
Document #: 38-12010 CY Rev. *C
May 17, 2005
DC and AC Characteristics
13.2.6
DC Analog Reference Specifications
The following table lists guaranteed maximum and mini-
mum specifications for the voltage and temperature
ranges, 5V +/- 5% and -40°C <= TA <= 85°C. The guar-
anteed specifications are measured through the Analog
Continuous Time PSoC blocks. The bias levels for
AGND refer to the bias of the Analog Continuous Time
PSoC block. The bias levels for RefHi and RefLo refer to
the Analog Reference Control Register. The limits stated
for AGND include the offset error of the AGND buffer
local to the Analog Continuous Time PSoC block. Typical
parameters apply to 5V at 25C and are for design guid-
ance only. (3.3V replaces 5V for the 3.3V DC Analog
Reference Specifications.)
Table 112: 5V DC Analog Reference Specifications
Symbol
5V DC Analog Reference Specifications
Minimum
Typical
Maximum
Unit
V
1
AGND = Vcc/2
V
/2 - 0.010
V
/2 - 0.004
V /2 + 0.003
cc
CT Block Bias = High
cc
cc
1
AGND = 2*BandGap
2*BG - 0.043 2*BG - 0.010 2*BG + 0.024
V
CT Block Bias = High
1
AGND = P2[4] (P2[4] = Vcc/2)
CT Block Bias = High
P24 - 0.013
-0.034
P24 0.001
0.000
P24 + 0.014
0.034
V
AGND Column to Column Variation (AGND=Vcc/
1
2)
mV
CT Block Bias = High
REFHI = Vcc/2 + BandGap
Ref Control Bias = High
V
/2+BG +
cc
V
/2+BG - 0.140
cc
V
/2+BG - 0.018
V
V
V
cc
0.103
REFHI = 3*BandGap
Ref Control Bias = High
3*BG - 0.112
3*BG - 0.018 3*BG + 0.076
REFHI = 2*BandGap + P2[6] (P2[6] = 1.3V)
Ref Control Bias = High
2*BG+P2[6] - 2*BG+P2[6] - 2*BG+P2[6]+
0.113
0.018
0.077
REFHI = P2[4] + BandGap (P2[4] = Vcc/2)
Ref Control Bias = High
P2[4]+BG -
0.130
P2[4]+BG -
0.016
P2[4]+BG +
0.098
V
V
REFHI = P2[4] + P2[6] (P2[4] = Vcc/2, P2[6] =
1.3V)
Ref Control Bias = High
P2[4]+P2[6] - P2[4]+P2[6] - P2[4]+P2[6]+
0.133 0.016 0.100
REFLO = Vcc/2 – BandGap
Ref Control Bias = High
V
/2-BG - 0.051
cc
V
/2-BG + 0.024
V
/2-BG + 0.098
V
V
cc
cc
REFLO = BandGap
Ref Control Bias = High
BG - 0.082
BG + 0.023
BG + 0.129
REFLO = 2*BandGap - P2[6] (P2[6] = 1.3V)
Ref Control Bias = High
2*BG-P2[6] -
0.084
2*BG-P2[6] + 2*BG-P2[6] +
V
V
V
0.025
0.134
REFLO = P2[4] – BandGap (P2[4] = Vcc/2)
Ref Control Bias = High
P2[4]-BG -
0.056
P2[4]-BG +
0.026
P2[4]-BG +
0.107
REFLO = P2[4]-P2[6] (P2[4] = Vcc/2, P2[6] =
1.3V)
Ref Control Bias = High
P2[4]-P2[6] -
0.057
P24-P26 +
0.026
P2[4]-P2[6] +
0.110
May 17, 2005
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135
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Table 113: 3.3V DC Analog Reference Specifications
Symbol
3.3V DC Analog Reference Specifications
Minimum
Typical
Maximum
Unit
1
AGND = Vcc/2
Vcc/2 - 0.007 Vcc/2 - 0.003 Vcc/2 + 0.002
Not Allowed
V
CT Block Bias = High
1
AGND = 2*BandGap
CT Block Bias = High
AGND = P2[4] (P2[4] = Vcc/2)
CT Block Bias = High
P24 - 0.008
-0.034
P24 + 0.001
0.000
P24 + 0.009
0.034
V
AGND Column to Column Variation (AGND=Vcc/
1
2)
mV
CT Block Bias = High
REFHI = Vcc/2 + BandGap
Ref Control Bias = High
Not Allowed
REFHI = 3*BandGap
Ref Control Bias = High
Not Allowed
Not Allowed
Not Allowed
REFHI = 2*BandGap + P2[6] (P2[6] = 0.5V)
Ref Control Bias = High
REFHI = P2[4] + BandGap (P2[4] = Vcc/2)
Ref Control Bias = High
REFHI = P2[4] + P2[6] (P2[4] = Vcc/2, P2[6] =
0.5V)
P2[4]+P2[6] - P2[4]+P2[6] - P2[4]+P2[6]+
V
Ref Control Bias = High
0.075
0.009
0.057
REFLO = Vcc/2 - BandGap
Ref Control Bias = High
Not Allowed
REFLO = BandGap
Ref Control Bias = High
Not Allowed
Not Allowed
Not Allowed
REFLO = 2*BandGap - P2[6] (P2[6] = 0.5V)
Ref Control Bias = High
REFLO = P2[4] – BandGap (P2[4] = Vcc/2)
Ref Control Bias = High
REFLO = P2[4]-P2[6] (P2[4] = Vcc/2, P2[6] =
0.5V)
P2[4]-P2[6] -
0.048
P24-P26 +
0.022
P2[4]-P2[6] +
0.092
V
Ref Control Bias = High
1. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 2%
13.2.7 DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and mini-
mum specifications include both voltage ranges, 5V +/-
5% and 3.3V +/- 10% and the temperature range -40°C
<= T <= 85°C. Typical parameters apply to 3.3V and 5V
A
at 25°C and are for design guidance only.
Table 114: DC Analog PSoC Block Specifications
Symbol
DC Analog PSoC Block Specifications
Resistor Unit Value (Continuous Time)
Capacitor Unit Value (Switch Cap)
Minimum
Typical Maximum
Unit
kΩ
-
45
70
-
-
-
fF
136
Document #: 38-12010 CY Rev. *C
May 17, 2005
DC and AC Characteristics
13.2.8
DC Programming Specifications
Table 115: DC Programming Specifications
Symbol
DC Programming Specifications
Minimum Typical Maximum
Unit
I
Supply Current During Programming or Verify
Input Low Voltage During Programming or Verify
-
-
5
-
20
0.8
-
mA
V
ccp
V
ilp
V
Input High Voltage During Programming or Verify 2.2
-
V
ihp
Input Current when Applying Vilp to P1[0] or P1[1]
During Programming or Verify
I
-
-
0.2
mA
ilp
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
1
I
-
-
-
-
mA
V
1.5
ihp
V
V
+ 0.75
Output Low Voltage During Programming or Verify
-
olv
ss
cc
Output High Voltage During Programming or
Verify
V
V
- 1.0
V
-
V
ohv
cc
E/W Cycles
per Block
Flash
Flash Endurance (Per Block)
50,000
-
-
enpb
2
Flash
Flash
1,800,000
10
E/W Cycles
Years
Flash Endurance (Total)
ent
Flash Data Retention (After Cycling)
-
dr
1. Driving internal pull-down resistor.
2. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1
blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500
maximum cycles each (and so forth to limit the total number of cycles to 36x50,000 and that no single block ever
sees more than 50,000 cycles).
The CY8C25xxx/26xxx family of PSoC devices uses an adaptive algorithm to enhance endurance over the indus-
trial temperature range (-40°C to +85°C ambient). Any temperature range within a 50°C span between 0°C and
85°C is considered constant with respect to endurance enhancements. For instance, if room temperature (25°C)
is the nominal operating temperature, then the range from 0°C to 50°C can be approximated by the constant value
25 and a temperature sensor is not needed.
For the full industrial range, the user must employ a temperature sensor User Module (FlashTemp) and feed the
result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://
www.cypressmicro.com under Support or Active Design Support for more information.
May 17, 2005
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137
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
13.3 AC Characteristics
Table 116: AC Operating Specifications
Symbol
AC Operating Specifications
Minimum
91.35
Typical
2,400
Maximum
2,460
1,230
Unit
kHz
1,2,3
F
CPU1
CPU Frequency (5 V Nominal)
4,3
F
91.35
1,200
48
kHz
CPU2
CPU Frequency (3.3V Nominal)
Digital PSoC Block Frequency
Digital PSoC Block Frequency
GPIO Operating Frequency
1,5
F
MHz
MHz
MHz
48M
49.2
24.6
2,4
F
24
24M
F
12
GPIO
Internal Main Oscillator Frequency
F
23.4
24
24.6
MHz
IMO
o
o
(0 C to +85 C)
Internal Main Oscillator Frequency Cold
F
22.44
24
32
32
24.6
50
MHz
kHz
kHz
IMOC
o
o
(-40 C to 0 C)
Internal Low Speed Oscillator Frequency
(Non Sleep)
6
F
32K1
15
Internal Low Speed Oscillator Frequency
(Sleep or Halt)
7
F
64
15
32K2
8
9
F
External Crystal Oscillator
PLL Frequency
-
-
-
kHz
MHz
ns
32.768
32K3
F
-
23.986
pll
10
T
f
Output Fall Time
Output Rise Time
PLL Lock Time
-
12
18
10
-
2
10
T
r
-
ns
3
T
0.5
-
ms
pllslew
11
SV
V
Rise Rate at Power Up
-
mV/ms
ms
80
dd
dd
12
T
External Crystal Oscillator Startup to 1%
External Crystal Oscillator Startup to 100 ppm
External Reset Pulse Width
-
100
150
-
500
os
13
T
-
ms
600
-
osacc
T
10
µs
xrst
1. 4.75V < V < 5.25V.
cc
2. Accuracy derived from Internal Main Oscillator with appropriate trim for V range.
cc
o
o
3. 0 C to +85 C.
4. 3.0V < V < 3.6V.
cc
5. See Application Note AN2012 ”Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for infor-
mation on maximum frequency for User Modules.
6. Limits are valid only when not in sleep mode.
7. Limits are valid only when in sleep mode.
8. Accuracy is capacitor and crystal dependent.
9. Is a multiple (x732) of crystal frequency.
10. Load capacitance = 50 pF.
11. To minimum allowable voltage for desired frequency.
12. The crystal oscillator frequency is guaranteed to be within 1% of its final value by the end of the 1s startup timer
period. Timer period may be as short as 640 ms for the case where F
is 50 kHz. Correct operation assumes a
32K1
properly loaded 1uW maximum drive level 32.768 kHz crystal.
13. The crystal oscillator frequency is within 100 ppm of its final value by the end of the T
period. Correct opera-
osacc
o
tion assumes a properly loaded 1 uW maximum drive level 32.768 kHz crystal. 3.0V <= V <= 5.5V, -40 C <= T
cc
A
o
<= 85 C.
138
Document #: 38-12010 CY Rev. *C
May 17, 2005
DC and AC Characteristics
13.3.1
AC Operational Amplifier Specifications
The following table lists guaranteed maximum and mini-
mum specifications for the voltage and temperature
block. The block is configured as an auto zeroed, gain of
0.5, output sampled amplifier. All 32-feedback caps are
on, 16 input caps are used (divide by 2), and the output
steps of 0.625V. Gain bandwidth is based on Analog
Continuous Time PSoC blocks. For 3.3V operation, see
Table 118 on page 140.
ranges, 5V +/- 5% and –40°C <= T <= 85°C. Typical
A
parameters are provided for design guidance only. Typi-
cal parameters apply to 5V and 25°C. Settling times and
slew rates are based on the Analog Switch Cap PSoC
Table 117: 5V AC Operational Amplifier Specifications
Symbol
5V AC Operational Amplifier Specifications
Minimum
Typical Maximum
Unit
µs
µs
µs
Rising Settling Time to 0.1%
Bias = Low
Bias = Medium
Bias = High
-
-
-
-
-
-
2.7
1.4
0.6
Falling Settling Time to 0.1%
Bias = Low
Bias = Medium
-
-
-
-
-
-
1.7
0.9
0.5
µs
µs
µs
Bias = High
Rising Slew Rate (20% to 80%)
Bias = Low
Bias = Medium
0.4
0.7
2.0
-
-
-
-
-
-
V/µs
V/µs
V/µs
Bias = High
Falling Slew Rate (80% to 20%)
Bias = Low
Bias = Medium
0.7
1.7
2.5
-
-
-
-
-
-
V/µs
V/µs
V/µs
Bias = High
Gain Bandwidth Product
Bias = Low
Bias = Medium
Bias = High
1.7
4.6
8.9
-
-
-
-
-
-
MHz
MHz
MHz
May 17, 2005
Document #: 38-12010 CY Rev. *C
139
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Table 118: 3.3V AC Operational Amplifier Specifications
Symbol
3.3V AC Operational Amplifier Specifications
Minimum
Typical Maximum
Unit
µs
µs
µs
Rising Settling Time to 0.1%
Bias = Low
Bias = Medium
Bias = High
-
-
-
-
-
-
3.0
1.6
1.5
Falling Settling Time to 0.1%
Bias = Low
Bias = Medium
-
-
-
-
-
-
2.6
1.7
1.6
µs
µs
µs
Bias = High
Rising Slew Rate (20% to 80%)
Bias = Low
Bias = Medium
0.2
0.3
0.3
-
-
-
-
-
-
V/µs
V/µs
V/µs
Bias = High
Falling Slew Rate (80% to 20%)
Bias = Low
Bias = Medium
0.3
0.3
0.3
-
-
-
-
-
-
V/µs
V/µs
V/µs
Bias = High
Gain Bandwidth Product
Bias = Low
Bias = Medium
Bias = High
1.5
4.4
8.7
-
-
-
-
-
-
MHz
MHz
MHz
140
Document #: 38-12010 CY Rev. *C
May 17, 2005
DC and AC Characteristics
13.3.2
AC Analog Output Buffer Specifications
The following table lists guaranteed maximum and mini-
mum specifications for the voltage and temperature
parameters are provided for design guidance only. Typi-
cal parameters apply to 5V and 25°C. For 3.3V opera-
tion, see Table 120 on page 142.
ranges, 5V +/- 5% and –40°C <= T <= 85°C. Typical
A
Table 119: 5V AC Analog Output Buffer Specifications
Symbol
5V AC Analog Output Buffer Specifications
Minimum
Typical Maximum
Unit
µs
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Bias = Low
Bias = High
-
-
-
-
2.5
2.5
µs
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Bias = Low
Bias = High
-
-
-
-
2.2
2.2
µs
µs
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Bias = Low
Bias = High
.9
.9
-
-
-
-
V/µs
V/µs
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Bias = Low
Bias = High
.9
.9
-
-
-
-
V/µs
V/µs
Small Signal Bandwidth, 20mV , 3dB BW, 100pF Load
pp
1.5
1.5
-
-
-
-
MHz
MHz
Bias = Low
Bias = High
Large Signal Bandwidth, 1V , 3dB BW, 100pF Load
pp
600
600
-
-
-
-
kHz
kHz
Bias = Low
Bias = High
May 17, 2005
Document #: 38-12010 CY Rev. *C
141
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
Table 120: 3.3V AC Analog Output Buffer Specifications
Symbol
3.3V AC Analog Output Buffer Specifications
Minimum
Typical Maximum
Unit
µs
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Bias = Low
Bias = High
-
-
-
-
3.2
3.2
µs
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Bias = Low
Bias = High
-
-
-
-
2.6
2.6
µs
µs
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Bias = Low
Bias = High
.5
.5
-
-
-
-
V/µs
V/µs
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Bias = Low
Bias = High
.5
.5
-
-
-
-
V/µs
V/µs
Small Signal Bandwidth, 20mV , 3dB BW, 100pF Load
pp
1.3
1.3
-
-
-
-
MHz
MHz
Bias = Low
Bias = High
Large Signal Bandwidth, 1V , 3dB BW, 100pF Load
pp
360
360
-
-
-
-
kHz
kHz
Bias = Low
Bias = High
13.3.3
AC Programming Specifications
Table 121: AC Programming Specifications
Symbol
AC Programming Specifications
Rise Time of SCLK
Minimum
Typical
Maximum
Unit
T
1
-
-
-
-
-
20
20
-
ns
rsclk
T
Fall Time of SCLK
1
ns
fsclk
T
Data Set up Time to Rising Edge of SCLK
25
ns
ssclk
T
Data Hold Time from Rising Edge of SCLK 25
-
ns
hsclk
F
Frequency of SCLK
2
-
20
-
MHz
ms
ms
ms
sclk
T
Flash Erase Time (Block)
Flash Erase Time (Full)
Flash Block Write Time
10
40
10
eraseb
T
-
-
erasef
T
2
20
write
142
Document #: 38-12010 CY Rev. *C
May 17, 2005
Packaging Information
14.0 Packaging Information
51-85064-B
Figure 37: 44-Lead Thin Plastic Quad Flat Pack A44
May 17, 2005
Document #: 38-12010 CY Rev. *C
143
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
51-85077 *C
Figure 38: 20-Pin Shrunk Small Outline Package O20
144
Document #: 38-12010 CY Rev. *C
May 17, 2005
Packaging Information
51-85079 *C
Figure 39: 28-Lead (210-Mil) Shrunk Small Outline Package O28
51-85061-C
Figure 40: 48-Lead Shrunk Small Outline Package O48
May 17, 2005
Document #: 38-12010 CY Rev. *C
145
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
51-85011-A
Figure 41: 20-Lead (300-Mil) Molded DIP P5
51-85014 *D
Figure 42: 28-Lead (300-Mil) Molded DIP P21
146
Document #: 38-12010 CY Rev. *C
May 17, 2005
Packaging Information
48-Lead
(600-Mil)
Molded
DIP
P25
51 -8 5020 -A
Figure 43: 48-Lead (600-Mil) Molded DIP P25
51-85024 *B
Figure 44: 20-Lead (300-Mil) Molded SOIC S5
May 17, 2005
Document #: 38-12010 CY Rev. *C
147
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
51-85026 *C
Figure 45: 28-Lead (300-Mil) Molded SOIC S21
8 Lead (300 Mil) PDIP
0.380
0.390
PIN 1 ID
4
1
DIMENSIONS IN INCHES MIN.
MAX.
0.240
0.260
5
8
0.300
0.325
0.100 BSC.
SEATING
PLANE
0.115
0.145
0.180 MAX.
0.008
0.015
0.015 MIN.
0.125
0.140
0°-10°
0.055
0.070
0.430 MAX.
0.014
0.022
Figure 46: 8-Lead (300-Mil) Molded DIP
148
Document #: 38-12010 CY Rev. *C
May 17, 2005
Packaging Information
14.1 Thermal Impedances per Package
Table 122: Thermal Impedances
Typical ΘJA
121 C/W
Package
8 PDIP
20 PDIP
20 SOIC
20 SSOP
28 PDIP
28 SOIC
28 SSOP
48 PDIP
48 SSOP
44 TQFP
107 C/W
80 C/W
116 C/W
68 C/W
72 C/W
95 C/W
70 C/W
69 C/W
58 C/W
May 17, 2005
Document #: 38-12010 CY Rev. *C
149
CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
15.0 Ordering Guide
Table 123: Ordering Guide (Leaded)1
Flash
(KBytes) (Bytes)
RAM
Temperature
Range
Type
Ordering Code
SMP
8 Pin (300 Mil) Molded DIP
20 Pin (300 Mil) Molded DIP
20 Pin (300 Mil) Molded SOIC
20 Pin (210 Mil) SSOP
CY8C25122-24PI
CY8C26233-24PI
CY8C26233-24SI
CY8C26233-24PVI
CY8C26443-24PI
CY8C26443-24SI
CY8C26443-24PVI
4
8
256
256
256
256
256
256
256
256
No
Ind. -40C to +85C
Ind. -40C to +85C
Ind. -40C to +85C
Ind. -40C to +85C
Ind. -40C to +85C
Ind. -40C to +85C
Ind. -40C to +85C
Ind. -40C to +85C
Yes
Yes
Yes
Yes
Yes
Yes
Yes
8
8
28 Pin (300 Mil) Molded DIP
28 Pin (300 Mil) Molded SOIC
28 Pin (210 Mil) SSOP
16
16
16
16
2
48 Pin (600 Mil) Molded DIP
CY8C26643-24PI
48 Pin (300 Mil) SSOP
16
16
256
256
Yes
Yes
Ind. -40C to +85C
Ind. -40C to +85C
CY8C26643-24PVI
CY8C26643-24AI
44 Pin Thin Plastic Quad Flatpack
1. Orders for leaded devices will not be accepted after July 2005.
2. 48-PDIP package not offered Pb-Free.
Table 124: Ordering Guide (Pb-Free Denoted with an “X” in Ordering Code)
Flash
(KBytes) (Bytes)
RAM
Temperature
Range
Type
Ordering Code
SMP
8 Pin (300 Mil) Molded DIP
20 Pin (300 Mil) Molded DIP
20 Pin (300 Mil) Molded SOIC
CY8C25122-24PXI
CY8C26233-24PXI
CY8C26233-24SXI
4
8
8
256
256
256
No
Yes
Yes
Ind. -40C to +85C
Ind. -40C to +85C
Ind. -40C to +85C
20 Pin (300 Mil) Molded SOIC
Tape and Reel
CY8C26233-24SXIT
CY8C26233-24PVXI
CY8C26233-24PVXIT
8
8
8
256
256
256
Yes
Yes
Yes
Ind. -40C to +85C
Ind. -40C to +85C
Ind. -40C to +85C
20 Pin (210 Mil) SSOP
20 Pin (210 Mil) SSOP
Tape and Reel
28 Pin (300 Mil) Molded DIP
28 Pin (300 Mil) Molded SOIC
CY8C26443-24PXI
CY8C26443-24SXI
16
16
256
256
Yes
Yes
Ind. -40C to +85C
Ind. -40C to +85C
28 Pin (300 Mil) Molded SOIC
Tape and Reel
CY8C26443-24SXIT
CY8C26443-24PVXI
CY8C26443-24PVXIT
CY8C26643-24PVXI
CY8C26643-24PVXIT
CY8C26643-24AXI
CY8C26643-24AXIT
16
16
16
16
16
16
16
256
256
256
256
256
256
256
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Ind. -40C to +85C
Ind. -40C to +85C
Ind. -40C to +85C
Ind. -40C to +85C
Ind. -40C to +85C
Ind. -40C to +85C
Ind. -40C to +85C
28 Pin (210 Mil) SSOP
28 Pin (210 Mil) SSOP
Tape and Reel
48 Pin (300 Mil) SSOP
48 Pin (300 Mil) SSOP
Tape and Reel
44 Pin Thin Plastic Quad Flatpack
44 Pin Thin Plastic Quad Flatpack
Tape and Reel
150
Document #: 38-12010 CY Rev. *C
May 17, 2005
Document Revision History
16.0 Document Revision History
Table 125: Document Revision History
Document Title: CY8C25122, CY8C26233, CY8C26443, CY8C26643 Device Data Sheet for Silicon Revision D
Document Number: 38-12010
Revision
ECN #
Issue Date
Origin of Change
Description of Change
CMS Cypress Man-
agement. New Sili-
con Revision.
**
116628
6/17/2002
New document to CY Document Control (Revision
**). Revision 3.20 for CMS customers.
*A
127231
5/22/2003
HMT.
Implementing new error tracking and document
release procedure. Changes in red for Document #:
38-12010 CY Rev. *A CMS Rev. 3.20a. Changes
include:
--Bit 6 of the VLT_CR register is RW. Should be
changed from "RW" to "--."
--Analog Output Buffer Control Register ABF_CR
Read/Write in Bank 1 table was corrected to Write
Only.
--Rewrite of section 10.4 Analog Reference Control .
--AC Char. Spec. table changed .080 to 80 in "Vdd
Rise Rate at Power Up."
On features pg. 2, changed "Up to 10 bit DAC" to "Up
to 8 bit DAC."
--Adding temp. spec. for 24 MHz at beginning of AC/
DC Characteristics section and Absolute Maximum
Value table.
--In AC Operating Spec. table fixed footnote for Out-
put Rise Time minimum.
--In AC Operating Spec. table fixed value for External
Reset Pulse Width.
--Changed uS to us units in tables.
--New intro.
--In the Analog Reference Control Register, ARF_CR,
state 100 for bits 2:0
should be described as "All Analog Off.“
--Rework title pgs.
*B
*C
127231
362598
5/22/2003
See ECN
HMT.
HMT.
Several updates including Thermal Impedances
table, 8 PDIP diagram and company address.
OSC_CR0 register name.
Add Pb-Free table. Add “Not Recommended for New
Designs“ banner. Update package revisions. Fix reg-
ister typo’s.
Distribution: External/Public
Posting: None
May 17, 2005
Document #: 38-12010 CY Rev. *C
151
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