CY8C27143_06 [CYPRESS]
PSoC㈢ Mixed-Signal Array; 的PSoC ™混合信号阵列
| 型号： | CY8C27143_06 |
| 厂家： | 
CYPRESS |
| 描述： | PSoC㈢ Mixed-Signal Array |
| 文件： | 总51页 (文件大小：753K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PSoC® Mixed-Signal Array
Final Data Sheet
CY8C27143, CY8C27243,
CY8C27443, CY8C27543, and CY8C27643
Features
■
Powerful Harvard Architecture Processor
■
■
Precision, Programmable Clocking
■
Additional System Resources
2
❐
❐
❐
❐
❐
M8C Processor Speeds to 24 MHz
8x8 Multiply, 32-Bit Accumulate
Low Power at High Speed
3.0 to 5.25V Operating Voltage
Operating Voltages Down to 1.0V Using On-
Chip Switch Mode Pump (SMP)
❐
❐
❐
❐
Internal 2.5% 24/48 MHz Oscillator
❐
I C™ Slave, Master, and Multi-Master to
400 kHz
24/48 MHz with Optional 32 kHz Crystal
Optional External Oscillator, up to 24 MHz
Internal Oscillator for Watchdog and Sleep
❐
❐
❐
❐
Watchdog and Sleep Timers
User-Configurable Low Voltage Detection
Integrated Supervisory Circuit
On-Chip Precision Voltage Reference
Flexible On-Chip Memory
❐
16K Flash Program Storage 50,000 Erase/
Write Cycles
❐
Industrial Temperature Range: -40°C to +85°C
■
Complete Development Tools
■
Advanced Peripherals (PSoC Blocks)
❐
❐
❐
❐
❐
256 Bytes SRAM Data Storage
In-System Serial Programming (ISSP)
Partial Flash Updates
Flexible Protection Modes
EEPROM Emulation in Flash
❐
Free Development Software
(PSoC Designer™)
❐
12 Rail-to-Rail Analog PSoC Blocks Provide:
❐
Full-Featured, In-Circuit Emulator and
Programmer
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
❐
❐
❐
Full Speed Emulation
Complex Breakpoint Structure
128K Trace Memory
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
8 Digital PSoC Blocks Provide:
■
Programmable Pin Configurations
❐
❐
❐
25 mA Sink on all GPIO
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Up to 2 Full-Duplex UARTs
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
Up to 12 Analog Inputs on GPIO
Four 30 mA Analog Outputs on GPIO
Configurable Interrupt on all GPIO
❐
❐
❐
❐
Complex Peripherals by Combining Blocks
PSoC® Functional Overview
Analog
Drivers
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
PSoC
CORE
The PSoC® family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of conve-
nient pinouts and packages.
System Bus
Global Digital Interconnect
SRAM
Global Analog Interconnect
SROM
Flash 16K
256 Bytes
Sleep and
Watchdog
CPUCore(M8C)
Interrupt
Controller
MultipleClockSources
(IncludesIMO,ILO, PLL, andECO)
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C27x43 family can have up to five IO
ports that connect to the global digital and analog interconnects,
providing access to 8 digital blocks and 12 analog blocks.
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Digital
Block
Array
Analog
Block
Array
Analog
Input
Muxing
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-
ture set. The core includes a CPU, memory, clocks, and config-
urable GPIO (General Purpose IO).
POR and LVD Internal
Voltage
Switch
Mode
Pump
Digital
Clocks
Multiply
2
I C
Decimator
Accum.
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
System Resets
Ref.
SYSTEM RESOURCES
October 26, 2006
© Cypress Semiconductor Corp. 2002 - 2006 — Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
PSoC® Overview
processor. The CPU utilizes an interrupt controller with 17 vec-
tors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Digital peripheral configurations include those listed below.
■ PWMs (8 to 32 bit)
■ PWMs with Dead band (8 to 32 bit)
■ Counters (8 to 32 bit)
Memory encompasses 16K of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2K of EEPROM
emulated using the Flash. Program Flash utilizes four protec-
tion levels on blocks of 64 bytes, allowing customized software
IP protection.
■ Timers (8 to 32 bit)
■ UART 8 bit with selectable parity (up to 2)
■ SPI slave and master (up to 2)
■ I2C slave and multi-master (1 available as a System
Resource)
The PSoC device incorporates flexible internal clock genera-
tors, including a 24 MHz IMO (internal main oscillator) accurate
to 2.5% over temperature and voltage. The 24 MHz IMO can
also be doubled to 48 MHz for use by the digital system. A low
power 32 kHz ILO (internal low speed oscillator) is provided for
the Sleep timer and WDT. If crystal accuracy is desired, the
ECO (32.768 kHz external crystal oscillator) is available for use
as a Real Time Clock (RTC) and can optionally generate a crys-
tal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
■ Cyclical Redundancy Checker/Generator (8 to 32 bit)
■ IrDA (up to 2)
■ Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the con-
straints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the opti-
mum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device Charac-
teristics” on page 3.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfac-
ing. Every pin also has the capability to generate a system inter-
rupt on high level, low level, and change from last read.
The Analog System
The Analog System is composed of 12 configurable blocks,
each comprised of an opamp circuit allowing the creation of
complex analog signal flows. Analog peripherals are very flexi-
ble and can be customized to support specific application
requirements. Some of the more common PSoC analog func-
tions (most available as user modules) are listed below.
The Digital System
The Digital System is composed of 8 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references.
■ Analog-to-digital converters (up to 4, with 6- to 14-bit resolu-
Port 5
Port 3
Port 1
tion, selectable as Incremental, Delta Sigma, and SAR)
Port 4
Port 2
Port 0
■ Filters (2, 4, 6, and 8 pole band-pass, low-pass, and notch)
■ Amplifiers (up to 4, with selectable gain to 48x)
To SystemBus
DigitalClocks
FromCore
ToAnalog
System
■ Instrumentation amplifiers (up to 2, with selectable gain to
93x)
DIGITAL SYSTEM
■ Comparators (up to 4, with 16 selectable thresholds)
■ DACs (up to 4, with 6- to 9-bit resolution)
DigitalPSoCBlockArray
Row 0
4
4
■ Multiplying DACs (up to 4, with 6- to 9-bit resolution)
■ High current output drivers (four with 30 mA drive as a Core
DBB00
DBB10
DBB01
DCB02
DCB12
DCB03
Resource)
■ 1.3V reference (as a System Resource)
■ DTMF Dialer
8
8
8
8
Row 1
4
4
■ Modulators
DBB11
DCB13
■ Correlators
■ Peak detectors
■ Many other topologies possible
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Digital System Block Diagram
October 26, 2006
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CY8C27x43 Final Data Sheet
PSoC® Overview
Analog blocks are provided in columns of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in the figure below.
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems. Addi-
tional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Statements
describing the merits of each system resource are below.
P0[7]
P0[5]
P0[6]
P0[4]
■ Digital clock dividers provide three customizable clock fre-
quencies for use in applications. The clocks can be routed to
both the digital and analog systems. Additional clocks can be
generated using digital PSoC blocks as clock dividers.
P0[3]
P0[1]
P0[2]
P0[0]
■ Multiply accumulate (MAC) provides fast 8-bit multiplier with
P2[6]
P2[4]
32-bit accumulate, to assist in general math and digital filters.
P2[3]
P2[1]
■ The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
P2[2]
P2[0]
■ The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
■ Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
Array Input Configuration
■ An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
■ An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
Block Array
ACB00
ASC10
ASD20
ACB01
ASD11
ASC21
ACB02
ASC12
ASD22
ACB03
ASD13
ASC23
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources
available for specific PSoC device groups.The PSoC device
covered by this data sheet is highlighted below.
Analog Reference
PSoC Device Characteristics
Interface to
Digital System
Re fe r ence
Generators
Ref Hi
Ref Lo
AGND
AGNDIn
Ref In
Bandgap
PSoC Part
Number
up to
64
CY8C29x66
4
16
12
4
4
12
2K
32K
M8C Interface (Address Bus, Data Bus, Etc.)
up to
44
256
Bytes
CY8C27x43
CY8C24x94
CY8C24x23
2
1
1
8
4
4
12
48
12
4
2
2
4
2
2
12
6
16K
16K
4K
Analog System Block Diagram
49
1K
up to
24
256
Bytes
6
up to
24
256
Bytes
CY8C24x23A
CY8C21x34
CY8C21x23
CY8C20x34
1
1
1
0
4
4
4
0
12
28
8
2
0
0
0
2
2
2
0
6
4K
8K
4K
8K
up to
28
512
Bytes
a
4
256
Bytes
a
16
4
up to
28
512
Bytes
b
28
3
a. Limited analog functionality.
b. Two analog blocks and one CapSense.
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CY8C27x43 Final Data Sheet
PSoC® Overview
Getting Started
Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable System-on-
Chip (PSoC) devices. The PSoC Designer IDE and application
runs on Windows NT 4.0, Windows 2000, Windows Millennium
(Me), or Windows XP. (Reference the PSoC Designer Func-
tional Flow diagram below.)
The quickest path to understanding the PSoC silicon is by read-
ing this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an over-
view of the PSoC integrated circuit and presents specific pin,
register, and electrical specifications. For in-depth information,
along with detailed programming information, reference the
PSoC Mixed-Signal Array Technical Reference Manual.
PSoC Designer helps the customer to select an operating con-
figuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest PSoC device data sheets on
the web at http://www.cypress.com/psoc.
Development Kits
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com, click the Online Store shopping cart
icon at the bottom of the web page, and click PSoC (Program-
mable System-on-Chip) to view a current list of available items.
Context
Graphical Designer
PSoC
Sensitive
Interface
Help
Designer
Technical Training
Free PSoC technical training is available for beginners and is
taught by a marketing or application engineer over the phone.
PSoC training classes cover designing, debugging, advanced
analog, as well as application-specific classes covering topics
such as PSoC and the LIN bus. Go to http://www.cypress.com,
click on Design Support located on the left side of the web
page, and select Technical Training for more details.
Importable
Design
Database
PSoC
Configuration
Sheet
Device
Database
PSoC
Designer
Core
Application
Database
Consultants
Manufacturing
Information
File
Engine
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Design
Support located on the left side of the web page, and select
CYPros Consultants.
Project
Database
User
Modules
Library
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.
Emulation
Pod
In-Circuit
Emulator
Device
Programmer
Application Notes
PSoC Designer Subsystems
A long list of application notes will assist you in every aspect of
your design effort. To view the PSoC application notes, go to
the http://www.cypress.com web site and select Application
Notes under the Design Resources list located in the center of
the web page. Application Notes are sorted by date by default.
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CY8C27x43 Final Data Sheet
PSoC® Overview
PSoC Designer Software Subsystems
Device Editor
Debugger
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic configu-
ration allows for changing configurations at run time.
PSoC Designer sets up power-on initialization tables for
selected PSoC block configurations and creates source code
for an application framework. The framework contains software
to operate the selected components and, if the project uses
more than one operating configuration, contains routines to
switch between different sets of PSoC block configurations at
run time. PSoC Designer can print out a configuration sheet for
a given project configuration for use during application pro-
gramming in conjunction with the Device Data Sheet. Once the
framework is generated, the user can add application-specific
code to flesh out the framework. It’s also possible to change the
selected components and regenerate the framework.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
Design Browser
A low cost, high functionality ICE (In-Circuit Emulator) is avail-
able for development support. This hardware has the capability
to program single devices.
The Design Browser allows users to select and import precon-
figured designs into the user’s project. Users can easily browse
a catalog of preconfigured designs to facilitate time-to-design.
Examples provided in the tools include a 300-baud modem, LIN
Bus master and slave, fan controller, and magnetic card reader.
The emulator consists of a base unit that connects to the PC by
way of the parallel or USB port. The base unit is universal and
will operate with all PSoC devices. Emulation pods for each
device family are available separately. The emulation pod takes
the place of the PSoC device in the target board and performs
full speed (24 MHz) operation.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble, com-
pile, link, and build.
Assembler. The macro assembler allows the assembly code
to be merged seamlessly with C code. The link libraries auto-
matically use absolute addressing or can be compiled in relative
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available
that supports Cypress MicroSystems’ PSoC family devices.
Even if you have never worked in the C language before, the
product quickly allows you to create complete C programs for
the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
October 26, 2006
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CY8C27x43 Final Data Sheet
PSoC® Overview
Designing with User Modules
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture
a unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses, and to the IO
pins. Iterative development cycles permit you to adapt the hard-
ware as well as the software. This substantially lowers the risk
that you will have to select a different part to meet the final
design requirements.
Device Editor
Placement
and
Parameter
-ization
User
Module
Selection
Source
Code
Generator
Generate
Application
Application Editor
Source
Code
Editor
To speed the development process, the PSoC Designer Inte-
grated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library con-
tains over 50 common peripherals such as ADCs, DACs Tim-
ers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Project
Manager
Build
Manager
Build
All
Debugger
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters
that allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Mod-
ule configures one or more digital PSoC blocks, one for each 8
bits of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides high-
level functions to control and respond to hardware events at
run-time. The API also provides optional interrupt service rou-
tines that you can adapt as needed.
Event &
Breakpoint
Manager
Interface
to ICE
Storage
Inspector
User Module and Source Code Development Flows
The next step is to write your main program, and any sub-rou-
tines using PSoC Designer’s Application Editor subsystem.
The Application Editor includes a Project Manager that allows
you to open the project source code files (including all gener-
ated code files) from a hierarchal view. The source code editor
provides syntax coloring and advanced edit features for both C
and assembly language. File search capabilities include simple
string searches and recursive “grep-style” patterns. A single
mouse click invokes the Build Manager. It employs a profes-
sional-strength “makefile” system to automatically analyze all
file dependencies and run the compiler and assembler as nec-
essary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in
a console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the set-
ting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by inter-
connecting user modules to each other and the IO pins. At this
stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to developing code for the project, you
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specification and provides the high-level user
module API functions.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger down-
loads the HEX image to the In-Circuit Emulator (ICE) where it
runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
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CY8C27x43 Final Data Sheet
PSoC® Overview
Document Conventions
Table of Contents
For an in depth discussion and more information on your PSoC
device, obtain the PSoC Mixed-Signal Array Technical Refer-
ence Manual on http://www.cypress.com. This document is
organized into the following chapters and sections.
Acronyms Used
The following table lists the acronyms that are used in this doc-
ument.
Acronym
AC
Description
1.
Pin Information ........................................................................................ 8
1.1 Pinouts ........................................................................................... 8
alternating current
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
8-Pin Part Pinout ............................................................ 8
20-Pin Part Pinout .......................................................... 9
28-Pin Part Pinout ........................................................ 10
44-Pin Part Pinout ........................................................ 11
48-Pin Part Pinouts ...................................................... 12
56-Pin Part Pinout ......................................................... 14
ADC
API
analog-to-digital converter
application programming interface
central processing unit
continuous time
CPU
CT
2.
3.
Register Reference ................................................................................ 16
DAC
DC
digital-to-analog converter
direct current
2.1
2.2
Register Conventions ................................................................... 16
Register Mapping Tables ............................................................. 16
ECO
EEPROM
FSR
GPIO
GUI
external crystal oscillator
electrically erasable programmable read-only memory
full scale range
Electrical Specifications ....................................................................... 19
3.1
3.2
3.3
Absolute Maximum Ratings ........................................................ 20
Operating Temperature ............................................................... 20
DC Electrical Characteristics ........................................................ 21
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
3.3.9
DC Chip-Level Specifications ........................................ 21
DC General Purpose IO Specifications ......................... 21
DC Operational Amplifier Specifications ....................... 22
DC Low Power Comparator Specifications ................... 23
DC Analog Output Buffer Specifications ....................... 24
DC Switch Mode Pump Specifications .......................... 25
DC Analog Reference Specifications ............................ 26
DC Analog PSoC Block Specifications .......................... 28
DC POR and LVD Specifications .................................. 28
general purpose IO
graphical user interface
human body model
HBM
ICE
in-circuit emulator
ILO
internal low speed oscillator
internal main oscillator
input/output
IMO
3.3.10 DC Programming Specifications ................................... 29
AC Electrical Characteristics ........................................................ 30
IO
3.4
IPOR
LSb
imprecise power on reset
least-significant bit
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
AC Chip-Level Specifications ........................................ 30
AC General Purpose IO Specifications ......................... 32
AC Operational Amplifier Specifications ........................ 33
AC Low Power Comparator Specifications ................... 35
AC Digital Block Specifications ..................................... 35
AC Analog Output Buffer Specifications ........................ 36
AC External Clock Specifications .................................. 37
AC Programming Specifications .................................... 37
AC I2C Specifications .................................................... 38
LVD
low voltage detect
MSb
PC
most-significant bit
program counter
PLL
phase-locked loop
POR
PPOR
PSoC®
PWM
SC
power on reset
4.
5.
Packaging Information .......................................................................... 39
precision power on reset
Programmable System-on-Chip™
pulse width modulator
switched capacitor
4.1
4.2
4.3
4.4
Packaging Dimensions ................................................................. 39
Thermal Impedances .................................................................. 44
Capacitance on Crystal Pins ....................................................... 44
Solder Reflow Peak Temperature ................................................ 44
Development Tool Selection ................................................................ 45
5.1
Software ....................................................................................... 45
SLIMO
SMP
SRAM
slow IMO
5.1.1
5.1.2
5.1.3
5.1.4
PSoC Designer .............................................................. 45
PSoC Express ............................................................... 45
PSoC Programmer ........................................................ 45
CY3202-C iMAGEcraft C Compiler ............................... 45
switch mode pump
static random access memory
5.2
5.3
Development Kits ......................................................................... 45
5.2.1
5.2.2
CY3215-DK Basic Development Kit .............................. 45
CY3210-ExpressDK Development Kit ........................... 46
Evaluation Tools ........................................................................... 46
Units of Measure
5.3.1
5.3.2
5.3.3
CY3210-MiniProg1 ........................................................ 46
CY3210-PSoCEval1 ...................................................... 46
CY3214-PSoCEvalUSB ................................................ 46
A units of measure table is located in the Electrical Specifica-
tions section. Table 3-1 on page 19 lists all the abbreviations
used to measure the PSoC devices.
5.4
Device Programmers ................................................................... 46
5.4.1
5.4.2
CY3216 Modular Programmer ...................................... 46
CY3207ISSP Serial Programmer (ISSP) ...................... 46
5.5
5.6
5.7
Accessories (Emulation and Programming) ................................. 47
3rd-Party Tools ............................................................................. 47
Build a PSoC Emulator into Your Board ...................................... 47
Numeric Naming
6.
7.
Ordering Information ............................................................................ 48
6.1 Ordering Code Definitions ........................................................... 49
Hexidecimal numbers are represented with all letters in upper-
case with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Sales and Service Information ............................................................. 50
7.1
7.2
Revision History ........................................................................... 50
Copyrights and Code Protection .................................................. 51
October 26, 2006
Document No. 38-12012 Rev. *K
7
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1. Pin Information
This chapter describes, lists, and illustrates the CY8C27x43 PSoC device pins and pinout configurations.
1.1
Pinouts
The CY8C27x43 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
1.1.1
8-Pin Part Pinout
Table 1-1. 8-Pin Part Pinout (PDIP)
Type
CY8C27143 8-Pin PSoC Device
Pin
No.
Pin
Name
Description
Digital Analog
1
2
3
IO
IO
IO
IO
IO
P0[5]
Analog column mux input and column output.
Analog column mux input and column output.
Vdd
A, IO,P0[5]
A,IO, P0[3]
I2CSCL,XTALin,P1[1]
Vss
1
2
3
4
8
7
6
5
P0[4], A,IO
P0[2], A,IO
P0[3]
P1[1]
PDIP
Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*.
P1[0],XTALout,I2CSDA
4
5
Power
Power
Vss
Ground connection.
IO
P1[0]
Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*.
6
7
8
IO
IO
IO
IO
P0[2]
P0[4]
Vdd
Analog column mux input and column output.
Analog column mux input and column output.
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
1. Pin Information
1.1.2
20-Pin Part Pinout
Table 1-2. 20-Pin Part Pinout (SSOP, SOIC)
Type
CY8C27243 20-Pin PSoC Device
Pin
No.
Pin
Name
Description
Digital Analog
1
2
3
4
5
IO
IO
IO
IO
I
P0[7]
P0[5]
P0[3]
P0[1]
SMP
Analog column mux input.
A, I,P0[7]
A,IO, P0[5]
A,IO, P0[3]
A,I, P0[1]
Vdd
20
19
18
17
16
1
2
3
4
5
6
7
8
9
IO
IO
I
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
P0[6], A,I
P0[4], A,IO
P0[2], A,IO
P0[0], A,I
XRES
SSOP
SMP
Power
Switch Mode Pump (SMP) connection to
external components required.
I2CSCL,P1[7]
I2CSDA, P1[5]
P1[3]
SOIC 15
P1[6]
14
13
12
11
6
7
8
9
IO
IO
IO
IO
P1[7]
P1[5]
P1[3]
P1[1]
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA
I2CSCL,XTALin, P1[1]
Vss
10
Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*.
10
11
Power
Vss
Ground connection.
IO
IO
P1[0]
Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*.
12
P1[2]
13
14
15
IO
IO
P1[4]
P1[6]
XRES
Optional External Clock Input (EXTCLK).
Input
Active high external reset with internal pull
down.
16
17
18
19
20
IO
IO
IO
IO
I
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Analog column mux input.
IO
IO
I
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Power
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
1. Pin Information
1.1.3
28-Pin Part Pinout
Table 1-3. 28-Pin Part Pinout (PDIP, SSOP, SOIC)
Type
CY8C27443 28-Pin PSoC Device
Pin
No.
Pin
Name
Description
Digital Analog
1
2
3
4
5
6
7
8
9
IO
IO
IO
IO
IO
IO
IO
IO
I
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
SMP
Analog column mux input.
A, I,P0[7]
A,IO, P0[5]
A,IO, P0[3]
A,I, P0[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Vdd
P0[6], A, I
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IO
IO
I
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
P0[4], A,IO
P0[2], A,IO
P0[0], A, I
P2[6],Ex ternalVRef
P2[4],Ex ternalAGND
P2[2], A, I
P2[7]
P2[5]
PDIP
SSOP
SOIC
A,I, P2[3]
A, I,P2[1]
I
I
Direct switched capacitor block input.
Direct switched capacitor block input.
SMP
P2[0], A, I
XRES
P1[6]
Power
Switch Mode Pump (SMP) connection to
external components required.
I2CSCL,P1[7]
I2CSDA,P1[5]
P1[3]
10
11
12
13
IO
IO
IO
IO
P1[7]
P1[5]
P1[3]
P1[1]
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA
I2CSCL,XTALin,P1[1]
Vss
Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*.
14
15
Power
Vss
Ground connection.
IO
P1[0]
Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*.
16
17
18
19
IO
IO
IO
P1[2]
P1[4]
P1[6]
XRES
Optional External Clock Input (EXTCLK).
Input
Active high external reset with internal pull
down.
20
21
22
23
24
25
26
27
28
IO
IO
IO
IO
IO
IO
IO
IO
I
I
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND).
External Voltage Reference (VRef).
Analog column mux input.
I
IO
IO
I
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Power
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See
the PSoC Mixed-Signal Array Technical Reference Manual for details.
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
1. Pin Information
1.1.4
44-Pin Part Pinout
Table 1-4. 44-Pin Part Pinout (TQFP)
Type
CY8C27543 44-Pin PSoC Device
Pin
No.
Pin
Name
Description
Digital Analog
1
2
3
4
5
6
7
8
IO
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
IO
IO
IO
IO
IO
IO
I
I
Direct switched capacitor block input.
Direct switched capacitor block input.
Power
Switch Mode Pump (SMP) connection to
external components required.
P2[5]
A, I,P2[3]
A, I,P2[1]
P4[7]
1
2
3
4
5
6
33
32
31
30
29
28
27
P2[4],ExternalAGND
P2[2], A,I
9
IO
IO
IO
IO
IO
IO
IO
IO
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
P1[3]
P1[1]
P2[0], A,I
P4[6]
10
11
12
13
14
15
16
P4[4]
P4[2]
P4[0]
P4[5]
TQFP
P4[3]
P4[1]
SMP
P3[7]
P3[5] 10
P3[3] 11
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
7
8
9
XRES
P3[6]
26
25
24
23
P3[4]
P3[2]
Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*.
17
18
Power
Vss
Ground connection.
IO
IO
P1[0]
Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*.
19
P1[2]
20
21
22
23
24
25
26
IO
IO
IO
IO
IO
IO
P1[4]
P1[6]
P3[0]
P3[2]
P3[4]
P3[6]
XRES
Optional External Clock Input (EXTCLK).
Input
Active high external reset with internal pull
down.
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
P4[0]
P4[2]
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
I
I
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND).
External Voltage Reference (VRef).
Analog column mux input.
I
IO
IO
I
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Power
Supply voltage.
IO
IO
IO
IO
IO
I
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
Analog column mux input.
IO
IO
I
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
1. Pin Information
1.1.5
48-Pin Part Pinouts
Table 1-5. 48-Pin Part Pinout (SSOP)
Type
CY8C27643 48-Pin PSoC Device
Pin
No.
Pin
Name
Description
Digital Analog
1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
Analog column mux input.
A, I,P0[7]
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Vdd
A,IO,P0[5]
A,IO,P0[3]
A, I,P0[1]
P2[7]
2
IO
IO
I
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
P0[6], A,I
P0[4],A,IO
P0[2],A,IO
P0[0], A,I
P2[6],ExternalVRef
P2[4],ExternalAGND
P2[2], A,I
P2[0], A,I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
3
4
5
6
3
4
5
P2[5]
6
A, I,P2[3]
A, I,P2[1]
P4[7]
7
8
9
7
I
I
Direct switched capacitor block input.
Direct switched capacitor block input.
8
P4[5] 10
9
P4[3]
P4[1]
SMP
11
10
11
12
13
12
13
14
SSOP
P3[7]
Power
Switch Mode Pump (SMP) connection to
external components required.
P3[5] 15
P3[6]
P3[3]
P3[1]
16
17
P3[4]
P3[2]
14
15
16
17
18
19
20
21
22
23
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
P5[3] 18
P5[1] 19
I2CSCL,P1[7]
P3[0]
P5[2]
P5[0]
P1[6]
20
21
I2CSDA,P1[5]
P1[3]
I2CSCL,XTALin,P1[1]
Vss
22
23
P1[4],EXTCLK
P1[2]
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
24
P1[0],XTALout,I2CSDA
Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*.
24
25
Power
Vss
Ground connection.
IO
P1[0]
Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA.*
26
27
28
29
30
31
32
33
34
35
IO
IO
IO
IO
IO
IO
IO
IO
IO
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P3[0]
P3[2]
P3[4]
P3[6]
XRES
Optional External Clock Input (EXTCLK).
Input
Active high external reset with internal pull
down.
36
37
38
39
40
41
42
43
44
45
46
47
48
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
P4[0]
P4[2]
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
I
I
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND).
External Voltage Reference (VRef).
Analog column mux input.
I
IO
IO
I
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Power
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
October 26, 2006
Document No. 38-12012 Rev. *K
12
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CY8C27x43 Final Data Sheet
1. Pin Information
Table 1-6. 48-Pin Part Pinout (QFN*)
Type
CY8C27643 48-Pin PSoC Device
Pin
No.
Pin
Name
Description
Digital Analog
1
2
3
4
5
6
7
IO
IO
IO
IO
IO
IO
I
I
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
Direct switched capacitor block input.
Direct switched capacitor block input.
Power
Switch Mode Pump (SMP) connection to
external components required.
P2[4],ExternalAGND
P2[2], A,I
A, I,P2[3]
A, I,P2[1]
P4[7]
36
35
34
33
32
31
30
1
2
8
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
3
4
5
6
P2[0], A,I
P4[6]
P4[4]
9
P4[5]
P4[3]
10
11
12
13
14
15
16
17
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
QFN
(Top View)
P4[2]
P4[0]
7
8
9
10
29
28
27
26
25
XRES
P3[6]
P3[4]
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
P3[2]
P3[0]
11
12
Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*.
18
19
Power
Vss
Ground connection.
IO
P1[0]
Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*.
20
21
22
23
24
25
26
27
28
29
IO
IO
IO
IO
IO
IO
IO
IO
IO
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P3[0]
P3[2]
P3[4]
P3[6]
XRES
Optional External Clock Input (EXTCLK).
Input
Active high external reset with internal pull
down.
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
P4[0]
P4[2]
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
I
I
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND).
External Voltage Reference (VRef).
Analog column mux input.
I
IO
IO
I
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Power
Supply voltage.
IO
IO
IO
IO
IO
IO
I
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
Analog column mux input.
IO
IO
I
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
LEGEND: A = Analog, I = Input, and O = Output.
* The QFN package has a center pad that must be connected to ground (Vss).
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
October 26, 2006
Document No. 38-12012 Rev. *K
13
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CY8C27x43 Final Data Sheet
1. Pin Information
1.1.6
56-Pin Part Pinout
The 56-pin SSOP part is for the CY8C27002 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Table 1-7. 56-Pin Part Pinout (SSOP)
Type
CY8C27002 56-Pin PSoC Device
Pin
No.
Pin
Name
Description
Digital Analog
1
NC
No connection.
NC
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
56
55
54
53
1
2
3
4
5
6
Vdd
2
IO
IO
I
I
I
I
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
OCDE
Analog column mux input.
P0[6], AI
P0[4], AIO
3
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
P0[2], AIO
P0[0], AI
4
IO
52
51
P2[6], External VRef
P2[4], External AGND
P2[2], AI
P2[0], AI
P4[6]
5
IO
P2[5]
AI, P2[3]
AI, P2[1]
P4[7]
7
8
9
50
49
48
6
IO
7
IO
10
47
46
45
44
43
42
41
40
39
38
37
36
35
34
8
IO
I
I
Direct switched capacitor block input.
Direct switched capacitor block input.
P4[5]
P4[3]
P4[4]
11
12
13
P4[2]
P4[0]
9
IO
P4[1]
10
11
12
13
14
15
16
IO
OCDE
OCDO
SMP
14
CCLK
HCLK
XRES
P3[6]
SSOP
IO
15
16
IO
I
I
P3[7]
17
IO
P3[5]
P3[3]
P3[4]
P3[2]
P3[0]
P5[2]
18
19
20
OCD
OCD
OCD even data IO.
P3[1]
P5[3]
OCDO OCD odd data output.
21
22
23
P5[1]
P5[0]
P1[6]
Power
SMP
Switch Mode Pump (SMP) connection to
required external components.
I2C SCL, P1[7]
I2C SDA, P1[5]
NC
P1[4], EXTCLK
24
25
33
32
17
18
19
20
IO
IO
IO
IO
P3[7]
P3[5]
P3[3]
P3[1]
P1[2]
P1[3]
SCLK, I2C SCL, XTALIn, P1[1]
Vss
26
27
28
31
30
P1[0], XTALOut, I2C SDA, SDATA
NC
NC
29
21
IO
P5[3]
Not for Production
22
23
24
25
26
27
IO
IO
IO
P5[1]
P1[7]
P1[5]
NC
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
No connection.
IO
IO
P1[3]
P1[1]
Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*.
28
29
30
31
Power
Vdd
NC
Supply voltage.
No connection.
No connection..
NC
IO
P1[0]
Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*.
32
33
34
35
36
37
38
39
40
41
IO
IO
IO
IO
IO
IO
IO
IO
IO
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P3[0]
P3[2]
P3[4]
P3[6]
XRES
Optional External Clock Input (EXTCLK).
Input
Active high external reset with internal pull
down.
42
43
44
45
46
47
OCD
OCD
IO
HCLK
CCLK
P4[0]
P4[2]
P4[4]
P4[6]
OCD high-speed clock output.
OCD CPU clock output.
IO
IO
IO
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
1. Pin Information
Table 1-7. 56-Pin Part Pinout (SSOP)
48
49
50
51
52
53
54
55
56
IO
IO
IO
IO
IO
IO
IO
IO
I
I
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND).
External Voltage Reference (VRef).
Analog column mux input.
I
I
I
I
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Power
Supply voltage.
LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
October 26, 2006
Document No. 38-12012 Rev. *K
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2. Register Reference
This chapter lists the registers of the CY8C27x43 PSoC device. For detailed register information, reference the
PSoC Mixed-Signal Array Technical Reference Manual.
2.1
Register Conventions
2.2
Register Mapping Tables
The register conventions specific to this section are listed in the
following table.
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI
bit is set the user is in Bank 1.
Convention
Description
R
W
L
Read register or bit(s)
Write register or bit(s)
Note In the following register mapping tables, blank fields are
reserved and should not be accessed.
Logical register or bit(s)
Clearable register or bit(s)
Access is bit specific
C
#
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
2. Register Reference
Register Map Bank 0 Table: User Space
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC12CR0
ASC12CR1
ASC12CR2
ASC12CR3
ASD13CR0
ASD13CR1
ASD13CR2
ASD13CR3
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
ASD22CR0
ASD22CR1
ASD22CR2
ASD22CR3
ASC23CR0
ASC23CR1
ASC23CR2
ASC23CR3
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
PRT5GS
PRT5DM2
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
RW
#
RW
#
RW
RW
INT_CLR3
INT_MSK3
RW
RW
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
DBB10DR0
DBB10DR1
DBB10DR2
DBB10CR0
DBB11DR0
DBB11DR1
DBB11DR2
DBB11CR0
DCB12DR0
DCB12DR1
DCB12DR2
DCB12CR0
DCB13DR0
DCB13DR1
DCB13DR2
DCB13CR0
#
AMX_IN
RW
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL_X
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
W
RW
#
ARF_CR
CMP_CR0
ASY_CR
CMP_CR1
RW
#
#
#
W
RW
#
RW
#
W
RW
#
MUL_Y
MUL_DH
MUL_DL
ACC_DR1
ACC_DR0
ACC_DR3
ACC_DR2
#
W
RW
#
#
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
ACB02CR3
ACB02CR0
ACB02CR1
ACB02CR2
ACB03CR3
ACB03CR0
ACB03CR1
ACB03CR2
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
RW
RW
RW
RW
RW
RW
RW
W
RW
#
#
W
RW
#
CPU_F
RL
#
RDI1RI
RDI1SYN
RDI1IS
RDI1LT0
RDI1LT1
RDI1RO0
RDI1RO1
RW
RW
RW
RW
RW
RW
RW
W
RW
#
#
W
RW
#
CPU_SCR1
CPU_SCR0
#
#
Blank fields are Reserved and should not be accessed.
# Access is bit specific.
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
2. Register Reference
Register Map Bank 1 Table: Configuration Space
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
PRT5DM1
PRT5IC0
PRT5IC1
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC12CR0
ASC12CR1
ASC12CR2
ASC12CR3
ASD13CR0
ASD13CR1
ASD13CR2
ASD13CR3
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
ASD22CR0
ASD22CR1
ASD22CR2
ASD22CR3
ASC23CR0
ASC23CR1
ASC23CR2
ASC23CR3
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
RW
RW
RW
RW
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
OSC_GO_EN DD
RW
RW
RW
RW
RW
RW
RW
R
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
DBB00FN
DBB00IN
DBB00OU
RW
RW
RW
CLK_CR0
CLK_CR1
ABF_CR0
AMD_CR0
RW
RW
RW
RW
DBB01FN
DBB01IN
DBB01OU
RW
RW
RW
VLT_CMP
AMD_CR1
ALT_CR0
ALT_CR1
CLK_CR2
RW
RW
RW
RW
DCB02FN
DCB02IN
DCB02OU
RW
RW
RW
IMO_TR
ILO_TR
BDG_TR
ECO_TR
W
W
RW
W
DCB03FN
DCB03IN
DCB03OU
RW
RW
RW
DBB10FN
DBB10IN
DBB10OU
RW
RW
RW
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
ACB02CR3
ACB02CR0
ACB02CR1
ACB02CR2
ACB03CR3
ACB03CR0
ACB03CR1
ACB03CR2
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
RW
RW
RW
RW
RW
RW
RW
DBB11FN
DBB11IN
DBB11OU
RW
RW
RW
CPU_F
RL
DCB12FN
DCB12IN
DCB12OU
RW
RW
RW
RDI1RI
RDI1SYN
RDI1IS
RDI1LT0
RDI1LT1
RDI1RO0
RDI1RO1
RW
RW
RW
RW
RW
RW
RW
DCB13FN
DCB13IN
DCB13OU
RW
RW
RW
CPU_SCR1
CPU_SCR0
#
#
Blank fields are Reserved and should not be accessed.
# Access is bit specific.
October 26, 2006
Document No. 38-12012 Rev. *K
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3. Electrical Specifications
This chapter presents the DC and AC electrical specifications of the CY8C27x43 PSoC device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ T ≤ 85oC and T ≤ 100oC, except where noted. Specifications for devices running at greater
A
J
than 12 MHz are valid for -40oC ≤ T ≤ 70oC and T ≤ 82oC.
A
J
5.25
4.75
3.00
93 kHz
12 MHz
24 MHz
CPUFrequency
Figure 3-1. Voltage versus CPU Frequency
The following table lists the units of measure that are used in this chapter.
Table 3-1: Units of Measure
Symbol
Unit of Measure
Symbol
Unit of Measure
o
degree Celsius
µW
microwatts
C
dB
fF
decibels
mA
ms
mV
nA
ns
milli-ampere
milli-second
milli-volts
femto farad
hertz
Hz
KB
1024 bytes
1024 bits
kilohertz
nanoampere
nanosecond
nanovolts
Kbit
kHz
kΩ
nV
Ω
kilohm
ohm
MHz
MΩ
µA
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
pA
pF
pp
ppm
ps
picoampere
picofarad
peak-to-peak
parts per million
picosecond
µF
µH
µs
sps
σ
samples per second
sigma: one standard deviation
volts
µV
µVrms
microvolts root-mean-square
V
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
3. Electrical Specifications
3.1
Absolute Maximum Ratings
Table 3-2. Absolute Maximum Ratings
Symbol
Description
Min
-55
Typ
Max
+100
Units
Notes
o
o
T
Storage Temperature
25
–
Higher storage temperatures will reduce data
retention time. Recommended storage temper-
STG
C
o
o
ature is +25 C ± 25 C. Extended duration stor-
o
age temperatures above 65 C will degrade
reliability.
T
Ambient Temperature with Power Applied
-40
+85
A
C
Vdd
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
-0.5
–
–
+6.0
V
V
V
V
Vss- 0.5
Vdd + 0.5
IO
DC Voltage Applied to Tri-state
Vss - 0.5
-25
–
–
–
Vdd + 0.5
+50
V
IOZ
I
Maximum Current into any Port Pin
mA
mA
MIO
MAIO
I
Maximum Current into any Port Pin Configured as Analog
Driver
-50
+50
ESD
LU
Electro Static Discharge Voltage
Latch-up Current
2000
–
–
–
–
V
Human Body Model ESD.
200
mA
3.2
Operating Temperature
Table 3-3. Operating Temperature
Symbol
Description
Min
Typ
Max
Units
Notes
o
T
Ambient Temperature
Junction Temperature
-40
–
+85
A
C
C
o
T
-40
–
+100
The temperature rise from ambient to junction is
package specific. See “Thermal Impedances”
on page 44. The user must limit the power con-
sumption to comply with this requirement.
J
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
3. Electrical Specifications
3.3
DC Electrical Characteristics
3.3.1
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-4. DC Chip-Level Specifications
Symbol
Description
Min
3.00
Typ
Max
5.25
Units
Notes
Vdd
Supply Voltage
Supply Current
–
5
V
o
I
–
8
mA
DD
Conditions are Vdd = 5.0V, T = 25 C, CPU = 3
A
MHz, SYSCLK doubler disabled. VC1 = 1.5
MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz.
o
I
Supply Current
–
3.3
6.0
mA
DD3
Conditions are Vdd = 3.3V, T = 25 C, CPU = 3
A
MHz, SYSCLK doubler disabled. VC1 = 1.5
MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz.
I
I
I
Sleep (Mode) Current with POR, LVD, Sleep Timer, and
–
–
–
3
4
4
6.5
25
µA
µA
µA
Conditions are with internal slow speed oscilla-
SB
a
o
o
WDT.
tor, Vdd = 3.3V, -40 C ≤ T ≤ 55 C.
A
Sleep (Mode) Current with POR, LVD, Sleep Timer, and
Conditions are with internal slow speed oscilla-
SBH
SBXTL
a
o
o
WDT at high temperature.
tor, Vdd = 3.3V, 55 C < T ≤ 85 C.
A
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
7.5
Conditions are with properly loaded, 1 µW max,
a
o
and external crystal.
32.768 kHz crystal. Vdd = 3.3V, -40 C ≤ T
≤
A
o
55 C.
I
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
–
5
26
µA
Conditions are with properly loaded, 1 µW max,
SBXTLH
a
o
and external crystal at high temperature.
32.768 kHz crystal. Vdd = 3.3V, 55 C < T ≤ 85
A
o
C.
b
V
V
1.275
1.280
1.300
1.300
1.325
1.320
V
V
Trimmed for appropriate Vdd.
Trimmed for appropriate Vdd.
REF
Reference Voltage (Bandgap) for Silicon A
b
REF
Reference Voltage (Bandgap) for Silicon B
a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions
enabled.
b. Refer to the Ordering Information chapter on page 48.
3.3.2
DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-5. DC GPIO Specifications
Symbol
Description
Min
Typ
5.6
Max
Units
kΩ
Notes
R
Pull up Resistor
4
4
8
8
–
PU
PD
OH
R
Pull down Resistor
High Output Level
5.6
–
kΩ
V
V
Vdd - 1.0
V
IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads,
4 on even port pins (for example, P0[2], P1[4]),
4 on odd port pins (for example, P0[3], P1[5])).
Low Output Level
–
–
0.75
0.8
V
IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads,
4 on even port pins (for example, P0[2], P1[4]),
4 on odd port pins (for example, P0[3], P1[5])).
OL
V
V
V
I
Input Low Level
Input High Level
Input Hysterisis
–
–
V
Vdd = 3.0 to 5.25.
Vdd = 3.0 to 5.25.
IL
IH
H
2.1
–
–
V
60
1
–
mV
nA
pF
pF
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
Capacitive Load on Pins as Output
–
–
Gross tested to 1 µA.
IL
o
C
C
–
3.5
3.5
10
10
IN
Package and pin dependent. Temp = 25 C.
o
–
OUT
Package and pin dependent. Temp = 25 C.
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
3. Electrical Specifications
3.3.3
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at
25°C and are for design guidance only.
Table 3-6. 5V DC Operational Amplifier Specifications
Symbol
Description
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Average Input Offset Voltage Drift
Min
Typ
Max
Units
Notes
V
OSOA
–
–
–
–
1.6
10
8
mV
1.3
1.2
7.0
mV
mV
7.5
o
TCV
I
35.0
OSOA
µV/ C
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
Common Mode Voltage Range
–
–
20
–
pA
Gross tested to 1 µA.
EBOA
o
C
4.5
9.5
pF
V
INOA
Package and pin dependent. Temp = 25 C.
V
0.0
0.5
–
–
Vdd
The common-mode input voltage range is mea-
sured through an analog output buffer. The
specification includes the limitations imposed
by the characteristics of the analog output
buffer.
CMOA
Common Mode Voltage Range (high power or high
opamp bias)
Vdd - 0.5
CMRR
Common Mode Rejection Ratio
Power = Low
–
–
–
–
dB
dB
Specification is applicable at high power. For all
other bias modes (except high power, high
opamp bias), minimum is 60 dB.
OA
60
60
60
Power = Medium
Power = High
G
Open Loop Gain
Specification is applicable at high power. For all
other bias modes (except high power, high
opamp bias), minimum is 60 dB.
OLOA
Power = Low
60
60
80
Power = Medium
Power = High
V
High Output Voltage Swing (internal signals)
Power = Low
OHIGHOA
OLOWOA
SOA
Vdd - 0.2
Vdd - 0.2
Vdd - 0.5
–
–
–
–
–
–
V
V
V
Power = Medium
Power = High
V
Low Output Voltage Swing (internal signals)
Power = Low
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
Power = Medium
Power = High
I
Supply Current (including associated AGND buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
Supply Voltage Rejection Ratio
–
150
300
600
1200
2400
4600
–
200
400
800
1600
3200
6400
–
µA
µA
µA
µA
µA
µA
dB
–
–
–
–
–
PSRR
60
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN
≤ Vdd.
OA
October 26, 2006
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CY8C27x43 Final Data Sheet
3. Electrical Specifications
Table 3-7. 3.3V DC Operational Amplifier Specifications
Symbol
Description
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
High Power is 5 Volts Only
Min
Typ
Max
Units
Notes
V
OSOA
–
–
1.65
10
8
mV
mV
1.32
o
TCV
I
Average Input Offset Voltage Drift
–
7.0
20
4.5
–
35.0
OSOA
µV/ C
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
Common Mode Voltage Range
–
–
pA
Gross tested to 1 µA.
EBOA
o
C
–
9.5
pF
V
INOA
Package and pin dependent. Temp = 25 C.
V
0.2
Vdd - 0.2
The common-mode input voltage range is
measured through an analog output buffer.
The specification includes the limitations
imposed by the characteristics of the analog
output buffer.
CMOA
CMRR
Common Mode Rejection Ratio
Power = Low
–
–
–
–
dB
dB
Specification is applicable at high power. For
all other bias modes (except high power, high
opamp bias), minimum is 60 dB.
OA
50
50
50
Power = Medium
Power = High
G
Open Loop Gain
Specification is applicable at high power. For
all other bias modes (except high power, high
opamp bias), minimum is 60 dB.
OLOA
Power = Low
60
60
80
Power = Medium
Power = High
V
V
High Output Voltage Swing (internal signals)
Power = Low
OHIGHOA
OLOWOA
SOA
Vdd - 0.2
Vdd - 0.2
Vdd - 0.2
–
–
–
–
–
–
V
V
V
Power = Medium
Power = High is 5V only
Low Output Voltage Swing (internal signals)
Power = Low
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
Power = Medium
Power = High
I
Supply Current (including associated AGND buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
Supply Voltage Rejection Ratio
–
150
300
600
1200
2400
4600
80
200
400
800
1600
3200
6400
–
µA
µA
µA
µA
µA
µA
dB
–
–
–
–
–
PSRR
50
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤
VIN ≤ Vdd.
OA
3.3.4
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 3-8. DC Low Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
V
I
Low power comparator (LPC) reference voltage range
0.2
–
–
Vdd - 1
V
REFLPC
LPC supply current
LPC voltage offset
10
40
30
µA
SLPC
V
–
2.5
mV
OSLPC
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
3. Electrical Specifications
3.3.5
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-9. 5V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
mV
Notes
V
Input Offset Voltage (Absolute Value)
–
3
12
–
OSOB
TCV
Average Input Offset Voltage Drift
Common-Mode Input Voltage Range
–
+6
–
µV/°C
OSOB
CMOB
V
0.5
Vdd - 1.0
V
R
Output Resistance
Power = Low
OUTOB
–
–
1
1
–
–
Ω
Ω
Power = High
V
High Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
OHIGHOB
OLOWOB
SOB
0.5 x Vdd + 1.3
0.5 x Vdd + 1.3
–
–
–
–
V
V
Power = High
V
Low Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
Power = High
–
–
–
–
0.5 x Vdd - 1.3
0.5 x Vdd - 1.3
V
V
I
Supply Current Including Bias Cell (No Load)
Power = Low
–
1.1
2.6
64
5.1
8.8
–
mA
mA
dB
Power = High
–
PSRR
Supply Voltage Rejection Ratio
60
OB
Table 3-10. 3.3V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
V
Input Offset Voltage (Absolute Value)
–
3
12
mV
µV/°C
V
OSOB
TCV
Average Input Offset Voltage Drift
Common-Mode Input Voltage Range
–
+6
-
–
OSOB
CMOB
V
0.5
Vdd - 1.0
R
Output Resistance
OUTOB
Power = Low
–
–
1
1
–
–
Ω
Ω
Power = High
V
High Output Voltage Swing (Load = 1k ohms to Vdd/2)
OHIGHOB
OLOWOB
SOB
Power = Low
Power = High
0.5 x Vdd + 1.0
0.5 x Vdd + 1.0
–
–
–
–
V
V
V
Low Output Voltage Swing (Load = 1k ohms to Vdd/2)
Power = Low
Power = High
–
–
–
–
0.5 x Vdd - 1.0
0.5 x Vdd - 1.0
V
V
I
Supply Current Including Bias Cell (No Load)
Power = Low
0.8
2.0
64
2.0
4.3
–
mA
mA
dB
Power = High
–
PSRR
Supply Voltage Rejection Ratio
60
OB
October 26, 2006
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CY8C27x43 Final Data Sheet
3. Electrical Specifications
3.3.6
DC Switch Mode Pump Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-11. DC Switch Mode Pump (SMP) Specifications
Symbol
Description
Min
4.75
Typ
5.0
Max
5.25
Units
Notes
a
V
V
5V
5V Output Voltage
3V Output Voltage
V
V
PUMP
PUMP
PUMP
Configuration of footnote. Average, neglecting
ripple. SMP trip voltage is set to 5.0V.
a
3V
3.00
3.25
3.60
Configuration of footnote. Average, neglecting
ripple. SMP trip voltage is set to 3.25V.
a
I
Available Output Current
Configuration of footnote.
V
V
= 1.5V, V
= 1.8V, V
= 3.25V
= 5.0V
8
5
–
–
–
–
mA
mA
BAT
BAT
PUMP
PUMP
SMP trip voltage is set to 3.25V.
SMP trip voltage is set to 5.0V.
a
V
V
V
5V
Input Voltage Range from Battery
1.8
–
5.0
V
BAT
Configuration of footnote. SMP trip voltage is
set to 5.0V.
a
3V
Input Voltage Range from Battery
1.0
–
3.3
V
BAT
Configuration of footnote. SMP trip voltage is
set to 3.25V.
a
Minimum Input Voltage from Battery to Start Pump
1.1
–
–
5
–
–
V
BATSTART
Configuration of footnote.
a
∆V
∆V
∆V
Line Regulation (over V
Load Regulation
range)
%V
PUMP_Line
PUMP_Load
PUMP_Ripple
BAT
O
O
Configuration of footnote.
V
is the “Vdd Value
O
for PUMP Trip” specified by the VM[2:0] setting
in the DC POR and LVD Specification, Table 3-
17 on page 28.
a
–
5
–
%V
Configuration of footnote.
V
is the “Vdd Value
O
for PUMP Trip” specified by the VM[2:0] setting
in the DC POR and LVD Specification, Table 3-
17 on page 28.
a
Output Voltage Ripple (depends on capacitor/load)
Efficiency
–
100
50
–
–
mVpp
%
Configuration of footnote. Load is 5mA.
a
E
35
3
Configuration of footnote. Load is 5 mA. SMP
trip voltage is set to 3.25V.
F
Switching Frequency
Switching Duty Cycle
–
–
1.3
50
–
–
MHz
%
PUMP
DC
PUMP
a. L1 = 2 µH inductor, C1 = 10 µF capacitor, D1 = Schottky diode. See Figure 3-2.
D1
Vdd
VPUMP
L1
C1
SMP
Vss
+
VBAT
Battery
TM
PSoC
Figure 3-2. Basic Switch Mode Pump Circuit
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
3. Electrical Specifications
3.3.7
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 3-12. Silicon Revision A – 5V DC Analog Reference Specifications
Symbol
Description
Bandgap Voltage Reference
Min
Typ
Max
Units
BG
–
1.274
1.30
1.326
V
V
a
Vdd/2 - 0.030
2 x BG - 0.043
P2[4] - 0.013
BG - 0.009
Vdd/2 - 0.004
2 x BG - 0.010
P2[4]
Vdd/2 + 0.003
2 x BG + 0.024
P2[4] + 0.014
BG + 0.009
AGND = Vdd/2
AGND = 2 x BandGap
a
–
–
–
–
–
V
V
V
V
V
a
AGND = P2[4] (P2[4] = Vdd/2)
a
BG
AGND = BandGap
a
1.6 x BG - 0.018
-0.034
1.6 x BG
0.000
1.6 x BG + 0.018
0.034
AGND = 1.6 x BandGap
a
AGND Block to Block Variation (AGND = Vdd/2)
RefHi = Vdd/2 + BandGap
–
–
–
–
–
–
–
–
–
–
–
V
V
V
V
V
V
V
V
V
V
V
Vdd/2 + BG - 0.140
3 x BG - 0.112
Vdd/2 + BG - 0.018
3 x BG - 0.018
Vdd/2 + BG + 0.103
3 x BG + 0.076
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
2 x BG + P2[6] - 0.113
P2[4] + BG - 0.130
P2[4] + P2[6] - 0.133
3.2 x BG - 0.112
2 x BG + P2[6] - 0.018
P2[4] + BG - 0.016
P2[4] + P2[6] - 0.016
3.2 x BG
2 x BG + P2[6] + 0.077
P2[4] + BG + 0.098
P2[4] + P2[6] + 0.100
3.2 x BG + 0.076
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
RefHi = 3.2 x BandGap
RefLo = Vdd/2 – BandGap
Vdd/2 - BG - 0.051
BG - 0.082
Vdd/2 - BG + 0.024
BG + 0.023
Vdd/2 - BG + 0.098
BG + 0.129
RefLo = BandGap
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
2 x BG - P2[6] - 0.084
P2[4] - BG - 0.056
P2[4] - P2[6] - 0.057
2 x BG - P2[6] + 0.025
P2[4] - BG + 0.026
P2[4] - P2[6] + 0.026
2 x BG - P2[6] + 0.134
P2[4] - BG + 0.107
P2[4] - P2[6] + 0.110
a. AGND tolerance includes the offsets of the local buffer in the PSoC block.
Table 3-13. Silicon Revision B – 5V DC Analog Reference Specifications
Symbol
Description
Bandgap Voltage Reference
Min
Typ
1.30
Max
1.32
Units
BG
–
1.28
V
V
a
Vdd/2 - 0.030
2 x BG - 0.043
P2[4] - 0.011
BG - 0.009
Vdd/2
Vdd/2 + 0.007
AGND = Vdd/2
AGND = 2 x BandGap
a
–
–
–
–
–
2 x BG
P2[4]
2 x BG + 0.024
P2[4] + 0.011
BG + 0.009
1.6 x BG + 0.018
0.034
V
V
V
V
V
a
AGND = P2[4] (P2[4] = Vdd/2)
a
BG
AGND = BandGap
a
1.6 x BG - 0.018
-0.034
1.6 x BG
0.000
AGND = 1.6 x BandGap
a
AGND Block to Block Variation (AGND = Vdd/2)
RefHi = Vdd/2 + BandGap
–
–
–
–
–
–
–
–
–
–
–
V
V
V
V
V
V
V
V
V
V
V
Vdd/2 + BG - 0.1
3 x BG - 0.06
Vdd/2 + BG - 0.01
3 x BG - 0.01
Vdd/2 + BG + 0.1
3 x BG + 0.06
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
2 x BG + P2[6] - 0.06
P2[4] + BG - 0.06
P2[4] + P2[6] - 0.06
3.2 x BG - 0.06
2 x BG + P2[6] - 0.01
P2[4] + BG - 0.01
P2[4] + P2[6] - 0.01
3.2 x BG - 0.01
2 x BG + P2[6] + 0.06
P2[4] + BG + 0.06
P2[4] + P2[6] + 0.06
3.2 x BG + 0.06
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
RefHi = 3.2 x BandGap
RefLo = Vdd/2 – BandGap
Vdd/2 - BG - 0.051
BG - 0.06
Vdd/2 - BG + 0.01
BG + 0.01
Vdd/2 - BG + 0.06
BG + 0.06
RefLo = BandGap
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
2 x BG - P2[6] - 0.04
P2[4] - BG - 0.056
P2[4] - P2[6] - 0.056
2 x BG - P2[6] + 0.01
P2[4] - BG + 0.01
P2[4] - P2[6] + 0.01
2 x BG - P2[6] + 0.04
P2[4] - BG + 0.056
P2[4] - P2[6] + 0.056
a. AGND tolerance includes the offsets of the local buffer in the PSoC block.
October 26, 2006
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CY8C27x43 Final Data Sheet
3. Electrical Specifications
Table 3-14. Silicon Revision A – 3.3V DC Analog Reference Specifications
Symbol
BG
Description
Bandgap Voltage Reference
Min
Typ
Max
Units
1.274
1.30
1.326
V
V
a
–
–
Vdd/2 - 0.027
Vdd/2 - 0.003
Vdd/2 + 0.002
AGND = Vdd/2
AGND = 2 x BandGap
a
Not Allowed
P2[4] - 0.008
BG - 0.009
–
–
AGND = P2[4] (P2[4] = Vdd/2)
P2[4] + 0.001
BG
P2[4] + 0.009
BG + 0.009
V
V
a
AGND = BandGap
a
–
–
1.6 x BG - 0.018
-0.034
1.6 x BG
0.000
1.6 x BG + 0.018
0.034
V
V
AGND = 1.6 x BandGap
a
AGND Block to Block Variation (AGND = Vdd/2)
RefHi = Vdd/2 + BandGap
–
–
–
–
–
–
–
–
–
–
–
Not Allowed
RefHi = 3 x BandGap
Not Allowed
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
Not Allowed
Not Allowed
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
RefHi = 3.2 x BandGap
P2[4] + P2[6] - 0.075
Not Allowed
P2[4] + P2[6] - 0.009
P2[4] + P2[6] + 0.057
V
V
RefLo = Vdd/2 - BandGap
Not Allowed
RefLo = BandGap
Not Allowed
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
Not Allowed
Not Allowed
P2[4] - P2[6] - 0.048
P2[4] - P2[6] + 0.022
P2[4] - P2[6] + 0.092
a. AGND tolerance includes the offsets of the local buffer in the PSoC block.
Note See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.
Table 3-15. Silicon Revision B – 3.3V DC Analog Reference Specifications
Symbol
BG
Description
Bandgap Voltage Reference
Min
Typ
Max
Units
1.28
1.30
1.32
V
V
a
–
–
Vdd/2 - 0.027
Vdd/2
Vdd/2 + 0.005
AGND = Vdd/2
AGND = 2 x BandGap
a
Not Allowed
P2[4] - 0.008
BG - 0.009
–
–
AGND = P2[4] (P2[4] = Vdd/2)
P2[4]
BG
P2[4] + 0.009
BG + 0.009
V
V
a
AGND = BandGap
a
–
–
1.6 x BG - 0.018
-0.034
1.6 x BG
0.000
1.6 x BG + 0.018
0.034
V
AGND = 1.6 x BandGap
a
mV
AGND Block to Block Variation (AGND = Vdd/2)
RefHi = Vdd/2 + BandGap
–
–
–
–
–
–
–
–
–
–
–
Not Allowed
RefHi = 3 x BandGap
Not Allowed
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
Not Allowed
Not Allowed
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
RefHi = 3.2 x BandGap
P2[4] + P2[6] - 0.06
Not Allowed
P2[4] + P2[6] - 0.01
P2[4] + P2[6] + 0.057
V
RefLo = Vdd/2 - BandGap
Not Allowed
RefLo = BandGap
Not Allowed
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
Not Allowed
Not Allowed
P2[4] - P2[6] - 0.048
P2[4] - P2[6] + 0.01
P2[4] - P2[6] + 0.048
V
a. AGND tolerance includes the offsets of the local buffer in the PSoC block.
Note See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.
October 26, 2006
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3. Electrical Specifications
3.3.8
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-16. DC Analog PSoC Block Specifications
Symbol
Description
Min
Typ
12.2
80
Max
Units
kΩ
fF
Notes
R
C
Resistor Unit Value (Continuous Time)
–
–
–
–
CT
SC
Capacitor Unit Value (Switch Cap)
3.3.9
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Mixed-Signal Array Technical
Reference Manual for more information on the VLT_CR register.
Table 3-17. DC POR and LVD Specifications
Symbol
Description
Vdd Value for PPOR Trip (positive ramp)
PORLEV[1:0] = 00b
Min
Typ
Max
Units
Notes
Vdd must be greater than or equal to 2.5V
during startup, reset from the XRES pin, or
reset from Watchdog.
V
V
V
PPOR0R
PPOR1R
PPOR2R
2.91
V
V
V
PORLEV[1:0] = 01b
–
–
4.39
4.55
–
–
PORLEV[1:0] = 10b
Vdd Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 00b
V
V
V
PPOR0
PPOR1
PPOR2
2.82
4.39
4.55
V
V
V
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
PPOR Hysteresis
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
V
V
V
PH0
PH1
PH2
–
–
–
92
0
–
–
–
mV
mV
mV
0
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
V
V
V
V
V
V
V
V
a
2.86
2.96
3.07
3.92
4.39
4.55
4.63
4.72
2.92
3.02
3.13
4.00
4.48
4.64
4.73
4.81
LVD0
LVD1
LVD2
LVD3
LVD4
LVD5
LVD6
LVD7
V
V
V
V
V
V
V
V
V
2.98
3.08
3.20
4.08
4.57
b
4.74
4.82
4.91
Vdd Value for PUMP Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
2.96
3.03
3.18
4.11
4.55
4.63
4.72
4.90
3.02
3.10
3.25
4.19
4.64
4.73
4.82
5.00
3.08
3.16
3.32
4.28
4.74
4.82
4.91
5.10
PUMP0
PUMP1
PUMP2
PUMP3
PUMP4
PUMP5
PUMP6
PUMP7
a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
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3. Electrical Specifications
3.3.10
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-18. DC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
mA
Notes
I
Supply Current During Programming or Verify
–
5
–
–
–
25
0.8
–
DDP
V
Input Low Voltage During Programming or Verify
Input High Voltage During Programming or Verify
–
V
ILP
IHP
V
2.2
–
V
I
I
Input Current when Applying Vilp to P1[0] or P1[1] During
Programming or Verify
0.2
mA
Driving internal pull-down resistor.
Driving internal pull-down resistor.
ILP
Input Current when Applying Vihp to P1[0] or P1[1] During
Programming or Verify
–
–
1.5
mA
IHP
V
V
Output Low Voltage During Programming or Verify
Output High Voltage During Programming or Verify
–
–
–
Vss + 0.75
Vdd
V
V
OLV
Vdd - 1.0
OHV
Flash
Flash
Flash
Flash Endurance (per block)
50,000
1,800,000
10
–
–
–
–
–
–
–
Erase/write cycles per block.
Erase/write cycles.
ENPB
ENT
DR
a
–
Flash Endurance (total)
Flash Data Retention
Years
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of
25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than
50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to
the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
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3. Electrical Specifications
3.4
AC Electrical Characteristics
3.4.1
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-19. AC Chip-Level Specifications
Symbol
IMO
Description
Min
23.4
Typ
Max
Units
MHz
Notes
a
F
F
F
F
Internal Main Oscillator Frequency
24
24
12
48
Trimmed. Utilizing factory trim values.
24.6
a,b
CPU Frequency (5V Nominal)
CPU Frequency (3.3V Nominal)
Digital PSoC Block Frequency
0.93
0.93
0
MHz
MHz
MHz
Trimmed. Utilizing factory trim values.
Trimmed. Utilizing factory trim values.
CPU1
CPU2
48M
24.6
12.3
49.2
b,c
a,b,d
Refer to the AC Digital Block Specifications
below.
b, d
F
F
F
Digital PSoC Block Frequency
Internal Low Speed Oscillator Frequency
External Crystal Oscillator
0
24
32
MHz
kHz
kHz
24M
24.6
64
15
–
32K1
32K2
32.768
–
Accuracy is capacitor and crystal dependent.
50% duty cycle.
F
PLL Frequency
–
23.986
–
MHz
Multiple (x732) of crystal frequency.
PLL
Jitter24M2
24 MHz Period Jitter (PLL)
PLL Lock Time
–
–
–
600
10
ps
T
0.5
ms
PLLSLEW
T
PLL Lock Time for Low Gain Setting
0.5
–
50
ms
PLLSLEWS-
LOW
T
External Crystal Oscillator Startup to 1%
–
–
1700
2800
ms
ms
OS
2620
3800
T
External Crystal Oscillator Startup to 100 ppm
The crystal oscillator frequency is within 100 ppm of its
OSACC
final value by the end of the T
period. Correct
osacc
operation assumes a properly loaded 1 uW maximum
drive level 32.768 kHz crystal. 3.0V ≤ Vdd ≤ 5.5V, -40
o
o
C ≤ T ≤ 85 C.
A
Jitter32k
32 kHz Period Jitter
–
100
–
ns
T
External Reset Pulse Width
10
–
µs
XRST
DC24M
24 MHz Duty Cycle
40
–
50
60
–
%
Step24M
Fout48M
24 MHz Trim Step Size
48 MHz Output Frequency
50
kHz
MHz
a,c
46.8
48.0
Trimmed. Utilizing factory trim values.
49.2
Jitter24M1
24 MHz Period Jitter (IMO)
–
–
600
–
ps
F
T
Maximum frequency of signal on row input or row output.
12.3
–
MHz
MAX
Supply Ramp Time
0
–
µs
RAMP
a. 4.75V < Vdd < 5.25V.
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.
d. See the individual user module data sheets for information on maximum frequencies for user modules.
PLL
Enable
T
24 MHz
PLLSLEW
FPLL
PLL
Gain
0
Figure 3-3. PLL Lock Timing Diagram
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3. Electrical Specifications
PLL
Enable
T
24 MHz
PLLSLEWLOW
FPLL
PLL
1
Gain
Figure 3-4. PLL Lock for Low Gain Setting Timing Diagram
32K
Select
32 kHz
T
OS
F32K2
Figure 3-5. External Crystal Oscillator Startup Timing Diagram
Jitter24M1
F24M
Figure 3-6. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter32k
F32K2
Figure 3-7. 32 kHz Period Jitter (ECO) Timing Diagram
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3. Electrical Specifications
3.4.2
AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-20. AC GPIO Specifications
Symbol
Description
GPIO Operating Frequency
Min
Typ
Max
Units
MHz
Notes
Normal Strong Mode
F
0
–
12
GPIO
TRiseF
TFallF
TRiseS
TFallS
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
3
–
18
18
–
ns
ns
ns
ns
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
2
–
10
10
27
22
–
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
Figure 3-8. GPIO Timing Diagram
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3. Electrical Specifications
3.4.3
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 3-21. 5V AC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
T
Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
ROA
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
3.9
µs
0.72
0.62
µs
µs
T
Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
SOA
Power = Low, Opamp Bias = Low
–
–
–
–
–
–
5.9
µs
µs
µs
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.92
0.72
SR
SR
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
ROA
FOA
0.15
1.7
–
–
–
–
–
–
V/µs
V/µs
V/µs
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
6.5
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
0.01
0.5
–
–
–
–
–
–
V/µs
V/µs
V/µs
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
4.0
BW
Gain Bandwidth Product
OA
Power = Low, Opamp Bias = Low
0.75
3.1
5.4
–
–
–
–
–
–
–
–
MHz
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
MHz
MHz
E
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
100
nV/rt-Hz
NOA
Table 3-22. 3.3V AC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
T
Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
ROA
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
–
–
–
–
3.92
0.72
µs
µs
T
Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
SOA
Power = Low, Opamp Bias = Low
–
–
–
–
5.41
0.72
µs
µs
Power = Medium, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
SR
SR
ROA
FOA
0.31
2.7
–
–
–
–
V/µs
V/µs
Power = Medium, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
0.24
1.8
–
–
–
–
V/µs
V/µs
Power = Medium, Opamp Bias = High
Gain Bandwidth Product
BW
OA
Power = Low, Opamp Bias = Low
0.67
2.8
–
–
–
–
–
MHz
Power = Medium, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
MHz
E
100
nV/rt-Hz
NOA
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3. Electrical Specifications
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
Figure 3-9. Typical AGND Noise with P2[4] Bypass
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequen-
cies, increased power level reduces the noise spectrum level.
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
0.01
0.1
1
10
100
Freq (kHz)
Figure 3-10. Typical Opamp Noise
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3. Electrical Specifications
3.4.4
AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 3-23. AC Low Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
µs
Notes
T
LPC response time
–
–
50
≥ 50 mV overdrive comparator reference set
RLPC
within V
.
REFLPC
3.4.5
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-24. AC Digital Block Specifications
Function
Description
Maximum Block Clocking Frequency (> 4.75V)
Maximum Block Clocking Frequency (< 4.75V)
Capture Pulse Width
Min
Typ
Max
49.2
Units
Notes
4.75V < Vdd < 5.25V.
All
Functions
Timer
24.6
–
3.0V < Vdd < 4.75V.
a
–
ns
50
–
Maximum Frequency, No Capture
Maximum Frequency, With Capture
Enable Pulse Width
–
–
–
49.2
24.6
–
MHz
MHz
ns
4.75V < Vdd < 5.25V.
–
a
Counter
50
–
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
–
–
49.2
24.6
MHz
MHz
4.75V < Vdd < 5.25V.
–
Dead Band Kill Pulse Width:
Asynchronous Restart Mode
20
50
–
–
–
–
ns
ns
a
a
Synchronous Restart Mode
Disable Mode
–
–
ns
50
–
Maximum Frequency
–
–
49.2
49.2
MHz
MHz
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
CRCPRS
Maximum Input Clock Frequency
–
(PRS Mode)
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
Maximum Input Clock Frequency
–
–
–
–
24.6
8.2
MHz
MHz
SPIM
SPIS
Maximum data rate at 4.1 MHz due to 2 x over
clocking.
Maximum Input Clock Frequency
–
–
–
4.1
–
ns
ns
a
Width of SS_ Negated Between Transmissions
50
b
Transmitter
Maximum Input Clock Frequency
–
–
–
–
–
–
16.4
24.6
49.2
MHz
MHz
MHz
Maximum data rate at 2.05 MHz due to 8 x over
clocking.
Silicon A
Silicon B
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
Silicon B Maximum Input Clock Frequency with Vdd ≥
4.75V, 2 Stop Bits
Maximum data rate at 6.15 MHz due to 8 x over
clocking.
b
Receiver
Maximum Input Clock Frequency
–
–
–
–
–
–
16.4
24.6
49.2
MHz
MHz
MHz
Maximum data rate at 2.05 MHz due to 8 x over
clocking.
Silicon A
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
Silicon B
Maximum data rate at 6.15 MHz due to 8 x over
clocking.
Silicon B Maximum Input Clock Frequency with Vdd ≥
4.75V, 2 Stop Bits
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
b. Refer to the Ordering Information chapter on page 48.
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
3. Electrical Specifications
3.4.6
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-25. 5V AC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
T
Rising Settling Time to 0.1%, 1V Step, 100pF Load
ROB
Power = Low
–
–
–
–
2.5
µs
Power = High
2.5
µs
T
Falling Settling Time to 0.1%, 1V Step, 100pF Load
SOB
Power = Low
–
–
–
–
2.2
2.2
µs
µs
Power = High
SR
SR
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
ROB
FOB
Power = Low
0.65
0.65
–
–
–
–
V/µs
V/µs
Power = High
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Power = Low
Power = High
0.65
0.65
–
–
–
–
V/µs
V/µs
BW
BW
Small Signal Bandwidth, 20mV , 3dB BW, 100pF Load
pp
OB
OB
0.8
0.8
–
–
–
–
MHz
MHz
Power = Low
Power = High
Large Signal Bandwidth, 1V , 3dB BW, 100pF Load
pp
300
300
–
–
–
–
kHz
kHz
Power = Low
Power = High
Table 3-26. 3.3V AC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
T
Rising Settling Time to 0.1%, 1V Step, 100pF Load
ROB
Power = Low
–
–
–
–
3.8
3.8
µs
µs
Power = High
T
Falling Settling Time to 0.1%, 1V Step, 100pF Load
SOB
Power = Low
–
–
–
–
2.6
2.6
µs
µs
Power = High
SR
SR
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
ROB
FOB
Power = Low
0.5
0.5
–
–
–
–
V/µs
V/µs
Power = High
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Power = Low
Power = High
0.5
0.5
–
–
–
–
V/µs
V/µs
BW
BW
Small Signal Bandwidth, 20mV , 3dB BW, 100pF Load
pp
OB
OB
0.7
0.7
–
–
–
–
MHz
MHz
Power = Low
Power = High
Large Signal Bandwidth, 1V , 3dB BW, 100pF Load
pp
200
200
–
–
–
–
kHz
kHz
Power = Low
Power = High
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
3. Electrical Specifications
3.4.7
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-27. 5V AC External Clock Specifications
Symbol
Description
Min
0.093
Typ
Max
24.6
Units
MHz
Notes
F
Frequency
–
OSCEXT
–
–
–
High Period
Low Period
20.6
20.6
150
–
–
–
5300
ns
ns
µs
–
–
Power Up IMO to Switch
Table 3-28. 3.3V AC External Clock Specifications
Symbol
OSCEXT
OSCEXT
Description
Min
Typ
Max
Units
Notes
a
F
F
0.093
0.186
–
–
12.3
24.6
MHz
MHz
Frequency with CPU Clock divide by 1
b
Frequency with CPU Clock divide by 2 or greater
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
–
–
–
41.7
41.7
150
–
–
–
5300
ns
ns
µs
–
–
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty per-
cent duty cycle requirement is met.
3.4.8
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-29. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
ns
Notes
T
Rise Time of SCLK
Fall Time of SCLK
1
–
20
20
–
RSCLK
FSCLK
SSCLK
HSCLK
SCLK
T
T
T
F
T
T
T
T
1
–
ns
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
–
8
MHz
ms
ms
ns
Flash Erase Time (Block)
–
10
10
–
–
ERASEB
WRITE
DSCLK
DSCLK3
Flash Block Write Time
–
–
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
–
45
50
Vdd > 3.6
–
–
ns
3.0 ≤ Vdd ≤ 3.6
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
3. Electrical Specifications
2
3.4.9
AC I C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-30. AC Characteristics of the I2C SDA and SCL Pins
Standard Mode
Min Max
100
Fast Mode
Min Max
Symbol
SCLI2C
Description
Units
kHz
Notes
F
T
SCL Clock Frequency
0
0
400
–
Hold Time (repeated) START Condition. After this period, the 4.0
first clock pulse is generated.
–
0.6
µs
HDSTAI2C
T
T
T
T
T
T
T
T
LOW Period of the SCL Clock
4.7
4.0
4.7
0
–
–
–
–
–
–
–
–
1.3
0.6
0.6
0
–
µs
µs
µs
µs
ns
µs
µs
ns
LOWI2C
HIGH Period of the SCL Clock
–
HIGHI2C
SUSTAI2C
HDDATI2C
SUDATI2C
SUSTOI2C
BUFI2C
Set-up Time for a Repeated START Condition
Data Hold Time
–
–
a
Data Set-up Time
250
4.0
4.7
–
–
100
0.6
Set-up Time for STOP Condition
Bus Free Time Between a STOP and START Condition
Pulse Width of spikes are suppressed by the input filter.
–
1.3
0
–
50
SPI2C
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if
the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
SDA
TSPI2C
T
LOWI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
SCL
TSUSTOI2C
TSUSTAI2C
THDDATI2C
THDSTAI2C
THIGHI2C
S
Sr
P
S
Figure 3-11. Definition for Timing for Fast/Standard Mode on the I2C Bus
October 26, 2006
Document No. 38-12012 Rev. *K
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4. Packaging Information
This chapter illustrates the packaging specifications for the CY8C27x43 PSoC device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
4.1
Packaging Dimensions
51-85075 *A
Figure 4-1. 8-Lead (300-Mil) PDIP
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
4. Packaging Information
51-85077 *C
Figure 4-2. 20-Lead (210-Mil) SSOP
51-85024 *C
Figure 4-3. 20-Lead (300-Mil) Molded SOIC
Document No. 38-12012 Rev. *K
October 26, 2006
40
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CY8C27x43 Final Data Sheet
4. Packaging Information
51-85014 *D
Figure 4-4. 28-Lead (300-Mil) Molded DIP
51-85079 *C
Figure 4-5. 28-Lead (210-Mil) SSOP
Document No. 38-12012 Rev. *K
October 26, 2006
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CY8C27x43 Final Data Sheet
4. Packaging Information
51-85026 *D
Figure 4-6. 28-Lead (300-Mil) Molded SOIC
51-85064 *C
Figure 4-7. 44-Lead TQFP
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
4. Packaging Information
51-85061 *C
Figure 4-8. 48-Lead (300-Mil) SSOP
0.08
C
6.90
7.10
1.00 MAX.
0.0ꢀ MAX.
0.20 REF.
X
0.80 MAX.
6.70
6.80
0.23 0.0ꢀ
PIN1 ID
0.20 R.
N
N
1
1
2
2
0.4ꢀ
0.80 DIA.
6.90
7.10
6.70
6.80
ꢀ.4ꢀ
ꢀ.ꢀꢀ
Y
0.30-0.4ꢀ
0.42 0.18
(4X)
0°-12°
0.ꢀ0
ꢀ.4ꢀ
ꢀ.ꢀꢀ
C
SEATING
PLANE
TOP VIEW
SIDE VIEW
BOTTOM VIEW
51-85152 - *B
DIMENSIONS IN mm MIN.
MAX.
Figure 4-9. 48-Lead (7x7 mm) QFN
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
4. Packaging Information
4.2
Thermal Impedances
Table 4-1. Thermal Impedances per Package
Package
8 PDIP
Typical θJA
*
o
120 C/W
o
20 SSOP
20 SOIC
28 PDIP
28 SSOP
28 SOIC
44 TQFP
48 SSOP
48 QFN
116 C/W
o
79 C/W
o
67 C/W
o
95 C/W
o
68 C/W
o
61 C/W
o
69 C/W
o
18 C/W
* T = T + POWER x θJA
J
A
4.3
Capacitance on Crystal Pins
Table 4-2: Typical Package Capacitance on Crystal Pins
Package
8 PDIP
Package Capacitance
2.8 pF
20 SSOP
20 SOIC
28 PDIP
28 SSOP
28 SOIC
44 TQFP
48 SSOP
48 QFN
2.6 pF
2.5 pF
3.5 pF
2.8 pF
2.7 pF
2.6 pF
3.3 pF
2.3 pF
4.4
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 4-3. Solder Reflow Peak Temperature
Silicon A*
Silicon B*
Package
Minimum Peak
Temperature**
Maximum Peak
Temperature
Minimum Peak
Temperature*
Maximum Peak
Temperature
o
o
o
o
8 PDIP
20 SSOP
20 SOIC
28 PDIP
28 SSOP
28 SOIC
44 TQFP
48 SSOP
48 QFN
220 C
240 C
240 C
260 C
o
o
o
o
220 C
240 C
240 C
260 C
o
o
o
o
220 C
240 C
220 C
260 C
o
o
o
o
220 C
240 C
240 C
260 C
o
o
o
o
220 C
240 C
240 C
260 C
o
o
o
o
220 C
240 C
220 C
260 C
o
o
o
o
220 C
240 C
220 C
260 C
o
o
o
o
220 C
240 C
220 C
260 C
o
o
o
o
220 C
240 C
240 C
260 C
*Refer to the Ordering Information chapter on page 48.
**Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-
Pb or 245 ± 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
October 26, 2006
Document No. 38-12012 Rev. *K
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5. Development Tool Selection
This chapter presents the development tools available for all current PSoC device families including the CY8C27x43 family.
5.1
Software
5.2
Development Kits
All development kits can be purchased from the Cypress Online
Store.
5.1.1
PSoC Designer™
At the core of the PSoC development software suite is PSoC
Designer. Utilized by thousands of PSoC developers, this
robust software has been facilitating PSoC designs for half a
decade. PSoC Designer is available free of charge at http://
www.cypress.com under DESIGN RESOURCES >> Software
and Drivers.
5.2.1
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface allows users to run, halt, and single step the processor
and view the content of specific memory locations. Advance
emulation features also supported through PSoC Designer. The
kit includes:
5.1.2
PSoC Express™
■ PSoC Designer Software CD
As the newest addition to the PSoC development software
suite, PSoC Express is the first visual embedded system design
tool that allows a user to create an entire PSoC project and
generate a schematic, BOM, and data sheet without writing a
single line of code. Users work directly with application objects
such as LEDs, switches, sensors, and fans. PSoC Express is
available free of charge at http://www.cypress.com/psocex-
press.
■ ICE-Cube In-Circuit Emulator
■ ICE Flex-Pod for CY8C29x66 Family
■ Cat-5 Adapter
■ Mini-Eval Programming Board
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ iMAGEcraft C Compiler (Registration Required)
■ ISSP Cable
5.1.3
PSoC Programmer
■ USB 2.0 Cable and Blue Cat-5 Cable
■ 2 CY8C29466-24PXI 28-PDIP Chip Samples
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can oper-
ate directly from PSoC Designer or PSoC Express. PSoC Pro-
grammer software is compatible with both PSoC ICE-Cube In-
Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free ofcharge at http://www.cypress.com/psocpro-
grammer.
5.1.4
CY3202-C iMAGEcraft C Compiler
CY3202 is the optional upgrade to PSoC Designer that enables
the iMAGEcraft C compiler. It can be purchased from the
Cypress Online Store. At http://www.cypress.com, click the
Online Store shopping cart icon at the bottom of the web page,
and click PSoC (Programmable System-on-Chip) to view a cur-
rent list of available items.
October 26, 2006
Document No. 38-12012 Rev. *K
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CY8C27x43 Final Data Sheet
5. Development Tool Selection
5.2.2
CY3210-ExpressDK PSoC Express
Development Kit
5.3.3
CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features a develop-
ment board for the CY8C24794-24LFXI PSoC device. Special
features of the board include both USB and capacitive sensing
development and debugging support. This evaluation board
also includes an LCD module, potentiometer, LEDs, an enunci-
ator and plenty of bread boarding space to meet all of your eval-
uation needs. The kit includes:
The CY3210-ExpressDK is for advanced prototyping and devel-
opment with PSoC Express (may be used with ICE-Cube In-Cir-
cuit Emulator). It provides access to I2C buses, voltage
reference, switches, upgradeable modules and more. The kit
includes:
■ PSoC Express Software CD
■ Express Development Board
■ 4 Fan Modules
■ PSoCEvalUSB Board
■ LCD Module
■ MIniProg Programming Unit
■ Mini USB Cable
■ 2 Proto Modules
■ MiniProg In-System Serial Programmer
■ MiniEval PCB Evaluation Board
■ Jumper Wire Kit
■ PSoC Designer and Example Projects CD
■ Getting Started Guide
■ Wire Pack
■ USB 2.0 Cable
■ Serial Cable (DB9)
5.4
Device Programmers
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ 2 CY8C24423A-24PXI 28-PDIP Chip Samples
■ 2 CY8C27443-24PXI 28-PDIP Chip Samples
■ 2 CY8C29466-24PXI 28-PDIP Chip Samples
All device programmers can be purchased from the Cypress
Online Store.
5.4.1
CY3216 Modular Programmer
5.3
Evaluation Tools
The CY3216 Modular Programmer kit features a modular pro-
grammer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
All evaluation tools can be purchased from the Cypress Online
Store.
■ Modular Programmer Base
■ 3 Programming Module Cards
■ MiniProg Programming Unit
■ PSoC Designer Software CD
■ Getting Started Guide
5.3.1
CY3210-MiniProg1
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■ USB 2.0 Cable
■ MiniProg Programming Unit
■ MiniEval Socket Programming and Evaluation Board
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■ PSoC Designer Software CD
5.4.2
CY3207ISSP In-System Serial
Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes pro-
tection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note: CY3207ISSP needs special software and is not compati-
ble with PSoC Programmer. The kit includes:
■ Getting Started Guide
■ USB 2.0 Cable
5.3.2
CY3210-PSoCEval1
■ CY3207 Programmer Unit
■ PSoC ISSP Software CD
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread-
boarding space to meet all of your evaluation needs. The kit
includes:
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ USB 2.0 Cable
■ Evaluation Board with LCD Module
■ MiniProg Programming Unit
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■ PSoC Designer Software CD
■ Getting Started Guide
■ USB 2.0 Cable
October 26, 2006
Document No. 38-12012 Rev. *K
46
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CY8C27x43 Final Data Sheet
5. Development Tool Selection
5.5
Accessories (Emulation and
Programming)
Table 5-1. Emulation and Programming Accessories
a
b
c
Part #
Pin
Package
Flex-Pod Kit
Foot Kit
Adapter
CY8C27143 8 PDIP
-24PXI
CY3250-27XXX CY3250-
8PDIP-FK
CY8C27243 20 SSOP
-24PVXI
CY3250-27XXX CY3250-
20SSOP-FK
CY8C27243 20 SOIC
-24SXI
CY3250-27XXX CY3250-
20SOIC-FK
CY8C27443 28 PDIP
-24PXI
CY3250-27XXX CY3250-
28PDIP-FK
Adapters can be
found at http://
CY8C27443 28 SSOP
-24PVXI
CY3250-27XXX CY3250-
28SSOP-FK www.emula-
tion.com.
CY8C27443 28 SOIC
-24SXI
CY3250-27XXX CY3250-
28SOIC-FK
CY8C27543 44 TQFP
-24AXI
CY3250-27XXX CY3250-
44TQFP-FK
CY8C27643 48 SSOP
-24PVXI
CY3250-27XXX CY3250-
48SSOP-FK
CY8C27643 48 QFN
-24LFXI
CY3250-
27XXXQFN
CY3250-
48QFN-FK
a. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two
flex-pods.
b. Foot kit includes surface mount feet that can be soldered to the target PCB.
c. Programming adapter converts non-DIP package to DIP footprint. Specific
details and ordering information for each of the adapters can be found at
http://www.emulation.com.
5.6
3rd-Party Tools
Several tools have been specially designed by the following
3rd-party vendors to accompany PSoC devices during develop-
ment and production. Specific details for each of these tools can
be found at http://www.cypress.com under DESIGN
RESOURCES >> Evaluation Boards.
5.7
Build a PSoC Emulator into
Your Board
For details on how to emulate your circuit before going to vol-
ume production using an on-chip debug (OCD) non-production
PSoC device, see Application Note “Debugging - Build a PSoC
Emulator into Your Board - AN2323” at http://www.cypress.com/
an2323.
October 26, 2006
Document No. 38-12012 Rev. *K
47
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6. Ordering Information
The following table lists the CY8C27x43 PSoC device’s key package features and ordering codes.
Table 6-1. CY8C27x43 PSoC Device Key Features and Ordering Information
Ordering
Package
Code
CY8C27x43 Silicon B – These parts are lead free and offer the following improvements. The DEC_CR1 register selections are enhanced to allow
any digital block to be the decimator clock source, the ECO EX and ECO EXW bits in the CPU_SCR1 register are readable, and the accuracy of
the analog reference is enhanced (see the Electrical Specifications chapter). All silicon A errata are fixed in silicon B.
8 Pin (300 Mil) DIP
CY8C27143-24PXI
CY8C27243-24PVXI
16K
16K
256
256
No
-40C to +85C
-40C to +85C
8
8
12
12
6
4
8
4
4
No
20 Pin (210 Mil) SSOP
Yes
16
Yes
20 Pin (210 Mil) SSOP
(Tape and Reel)
CY8C27243-24PVXIT
CY8C27243-24SXI
CY8C27243-24SXIT
16K
256
256
256
Yes
Yes
Yes
-40C to +85C
-40C to +85C
-40C to +85C
8
8
8
12
12
12
16
16
16
8
8
8
4
4
4
Yes
Yes
Yes
20 Pin (300 Mil) SOIC
16K
16K
20 Pin 300 Mil) SOIC
(Tape and Reel)
28 Pin (300 Mil) DIP
CY8C27443-24PXI
CY8C27443-24PVXI
16K
16K
16K
256
256
Yes
Yes
-40C to +85C
-40C to +85C
8
8
12
12
24
24
12
12
4
4
Yes
Yes
28 Pin (210 Mil) SSOP
28 Pin (210 Mil) SSOP
(Tape and Reel)
CY8C27443-24PVXIT
CY8C27443-24SXI
CY8C27443-24SXIT
CY8C27543-24AXI
CY8C27543-24AXIT
CY8C27643-24PVXI
CY8C27643-24PVXIT
CY8C27643-24LFXI
CY8C27643-24LFXIT
CY8C27002-24PVXIa
256
256
256
256
256
256
256
256
256
256
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
8
8
8
8
8
8
8
8
8
8
12
12
12
12
12
12
12
12
12
12
24
24
24
40
40
44
44
44
44
44
12
12
12
12
12
12
12
12
12
14
4
4
4
4
4
4
4
4
4
4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
28 Pin (300 Mil) SOIC
16K
16K
28 Pin (300 Mil) SOIC
(Tape and Reel)
44 Pin TQFP
16K
16K
44 Pin TQFP
(Tape and Reel)
48 Pin (300 Mil) SSOP
16K
16K
48 Pin (300 Mil) SSOP
(Tape and Reel)
48 Pin (7x7) QFN
16K
16K
16K
48 Pin (7x7) QFN
(Tape and Reel)
56 Pin OCD SSOP
CY8C27x43 Silicon A – Silicon A is not recommended for new designs.
8 Pin (300 Mil) DIP
CY8C27143-24PI
CY8C27243-24PVI
16K
16K
16K
256
256
No
-40C to +85C
-40C to +85C
8
8
12
12
6
4
8
4
4
No
20 Pin (210 Mil) SSOP
Yes
16
Yes
20 Pin (210 Mil) SSOP
(Tape and Reel)
CY8C27243-24PVIT
CY8C27243-24SI
CY8C27243-24SIT
CY8C27443-24PI
256
256
256
256
Yes
Yes
Yes
Yes
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
8
8
8
8
12
12
12
12
16
16
16
24
8
8
4
4
4
4
Yes
Yes
Yes
Yes
20 Pin (300 Mil) SOIC
16K
16K
20 Pin 300 Mil) SOIC
(Tape and Reel)
8
28 Pin (300 Mil) DIP
16K
12
October 26, 2006
Document No. 38-12012 Rev. *K
48
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CY8C27x43 Final Data Sheet
6. Ordering Information
Table 6-1. CY8C27x43 PSoC Device Key Features and Ordering Information (continued)
Ordering
Package
Code
28 Pin (210 Mil) SSOP
CY8C27443-24PVI
CY8C27443-24PVIT
CY8C27443-24SI
CY8C27443-24SIT
CY8C27543-24AI
CY8C27543-24AIT
CY8C27643-24PVI
CY8C27643-24PVIT
CY8C27643-24LFI
CY8C27643-24LFIT
16K
16K
256
256
256
256
256
256
256
256
256
256
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
8
8
8
8
8
8
8
8
8
8
12
12
12
12
12
12
12
12
12
12
24
24
24
24
40
40
44
44
44
44
12
12
12
12
12
12
12
12
12
12
4
4
4
4
4
4
4
4
4
4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
28 Pin (210 Mil) SSOP
(Tape and Reel)
28 Pin (300 Mil) SOIC
16K
16K
28 Pin (300 Mil) SOIC
(Tape and Reel)
44 Pin TQFP
16K
16K
44 Pin TQFP
(Tape and Reel)
48 Pin (300 Mil) SSOP
16K
16K
48 Pin (300 Mil) SSOP
(Tape and Reel)
48 Pin (7x7) MLF
16K
16K
48 Pin (7x7) MLF
(Tape and Reel)
a. This part may be used for in-circuit debugging. It is NOT available for production
6.1
Ordering Code Definitions
CY 8 C 27 xxx-SPxx
Package Type:
Thermal Rating:
C = Commercial
I = Industrial
PX = PDIP Pb-Free
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
LFX/LKX = QFN Pb-Free
AX = TQFP Pb-Free
E = Extended
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
October 26, 2006
Document No. 38-12012 Rev. *K
49
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7. Sales and Service Information
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134
408.943.2600
Web Sites:
Company Information – http://www.cypress.com
Sales – http://www.cypress.com/aboutus/sales_locations.cfm
Technical Support – http://www.cypress.com/support/login.cfm
7.1
Revision History
Table 7-1. CY8C27x43 Data Sheet Revision History
Document Title:
CY8C27143, CY8C27243, CY8C27443, CY8C27543, and CY8C27643 PSoC Mixed-Signal Array Final Data Sheet
Document Number: 38-12012
Revision
**
ECN #
127087
128780
Issue Date Origin of Change
Description of Change
7/01/2003 New Silicon.
New document (Revision **).
*A
7/29/2003 Engineering and
NWJ.
New electrical spec additions, fix of Core Architecture links, corrections to some text,
tables, drawings, and format.
*B
128992
8/14/2003 NWJ
Interrupt controller table fixed, refinements to Electrical Spec section and Register chap-
ter.
*C
*D
129283
129442
8/28/2003 NWJ
9/09/2003 NWJ
Significant changes to the Electrical Specifications section.
Changes made to Electrical Spec section. Added 20/28-Lead SOIC packages and
pinouts.
*E
*F
*G
130129
130651
131298
10/13/2003 NWJ
10/28/2003 NWJ
11/18/2003 NWJ
Revised document for Silicon Revision A.
Refinements to Electrical Specification section and I2C chapter.
Revisions to GDI, RDI, and Digital Block chapters. Revisions to AC Digital Block Spec
and miscellaneous register changes.
*H
229416
See ECN SFV
New data sheet format and organization. Reference the PSoC Mixed-Signal Array Tech-
nical Reference Manual for additional information. Title change.
*I
247529
355555
See ECN SFV
See ECN HMT
Added Silicon B information to this data sheet.
*J
Add DS standards, update device table, swap 48-pin SSOP 45 and 46, add Reflow Peak
Temp. table. Add new color and logo. Re-add pinout ISSP notation. Add URL to pre-
ferred dimensions for mounting MLF packages. Update Transmitter and Receiver AC
Digital Block Electrical Specifications.
*K
523233
See ECN HMT
Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add new Dev. Tool
section. Add CY8C20x34 to PSoC Device Characteristics table. Add OCD pinout and
package diagram. Add ISSP note to pinout tables. Update package diagram revisions.
Update typical and recommended Storage Temperature per industrial specs. Update CY
branding and QFN convention. Update copyright and trademarks.
Distribution: External Public
Posting: None
October 26, 2006
© CypressSemiconductor Corp. 2002 - 2006 — Document No. 38-12012 Rev. *K
50
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CY8C27x43 Final Data Sheet
7. Sales and Service Information
7.2
Copyrights and Code Protection
Copyrights
© Cypress Semiconductor Corp. 2002-2006. All rights reserved. PSoC Designer™, Programmable System-on-Chip™, and PSoC Express are trademarks and PSoC® is
a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations.
The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other than circuitry
embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products
for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of
Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress
Semiconductor against all charges. Cypress Semiconductor products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety
applications, unless pursuant to an express written agreement with Cypress Semiconductor.
Flash Code Protection
Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices.
Cypress Semiconductor products meet the specifications contained in their particular data sheets. Cypress Semiconductor believes that its family of products is one of the
most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach the
code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor nor any other semiconductor
manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress
Semiconductor are committed to continuously improving the code protection features of our products.
Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress
Semiconductor are committed to continuously improving the code protection features of our products.
October 26, 2006
Document No. 38-12012 Rev. *K
51
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