CY8C27443-24PVI_技术文档

PSoC™ Mixed Signal Array

Final Data Sheet

CY8C27143, CY8C27243,

CY8C27443, CY8C27543, and CY8C27643

Features

■ Powerful Harvard Architecture Processor

■ M8C Processor Speeds to 24 MHz

■ 8x8 Multiply, 32-Bit Accumulate

■ Low Power at High Speed

■ Precision, Programmable Clocking

■ Internal 2.5% 24/48 MHz Oscillator

■ Additional System Resources

■ I²C™ Slave, Master, and Multi-Master to

■ 24/48 MHz with Optional 32 kHz Crystal

■ Optional External Oscillator, up to 24 MHz

■ Internal Oscillator for Watchdog and Sleep

400 kHz

■ Watchdog and Sleep Timers

■ User-Configurable Low Voltage Detection

■ Integrated Supervisory Circuit

■ On-Chip Precision Voltage Reference

■ 3.0 to 5.25 V Operating Voltage

■ Operating Voltages Down to 1.0V Using On-

■ Flexible On-Chip Memory

Chip Switch Mode Pump (SMP)

■ 16K Bytes Flash Program Storage 50,000

■ Industrial Temperature Range: -40°C to +85°C

Erase/Write Cycles

■ Complete Development Tools

■ Advanced Peripherals (PSoC Blocks)

■ 256 Bytes SRAM Data Storage

■ In-System Serial Programming (ISSP™)

■ Partial Flash Updates

■ Flexible Protection Modes

■ EEPROM Emulation in Flash

■ Free Development Software

■ 12 Rail-to-Rail Analog PSoC Blocks Provide:

(PSoC™ Designer)

- Up to 14-Bit ADCs

- Up to 9-Bit DACs

- Programmable Gain Amplifiers

- Programmable Filters and Comparators

■ 8 Digital PSoC Blocks Provide:

■ Full-Featured, In-Circuit Emulator and

Programmer

■ Full Speed Emulation

■ Complex Breakpoint Structure

■ 128K Bytes Trace Memory

■ Programmable Pin Configurations

■ 25 mA Sink on all GPIO

- 8- to 32-Bit Timers, Counters, and PWMs

- CRC and PRS Modules

- Up to 2 Full-Duplex UARTs

- Multiple SPI™ Masters or Slaves

- Connectable to all GPIO Pins

■ Pull up, Pull down, High Z, Strong, or Open

Drain Drive Modes on all GPIO

■ Up to 12 Analog Inputs on GPIO

■ Four 30 mA Analog Outputs on GPIO

■ Configurable Interrupt on all GPIO

■ Complex Peripherals by Combining Blocks

Analog

Drivers

PSoC™ Functional Overview

Port 5 Port 4 Port 3 Port 2 Port 1 Port 0

PSoC

CORE

The PSoC™ family consists of many Mixed Signal Array with

On-Chip Controller devices. These devices are designed to

replace multiple traditional MCU-based system components

with one, low cost single-chip programmable device. PSoC

devices include configurable blocks of analog and digital logic,

as well as programmable interconnects. This architecture

allows the user to create customized peripheral configurations

that match the requirements of each individual application.

Additionally, a fast CPU, Flash program memory, SRAM data

memory, and configurable IO are included in a range of conve-

nient pinouts and packages.

System Bus

Global Digital Interconnect

SRAM

Global Analog Interconnect

SROM

Flash 16K

256 Bytes

Sleep and

Watchdog

CPU Core (M8C)

Interrupt

Controller

Multiple Clock Sources

(Includes IMO, ILO, PLL, and ECO)

The PSoC architecture, as illustrated on the left, is comprised of

four main areas: PSoC Core, Digital System, Analog System,

and System Resources. Configurable global busing allows all

the device resources to be combined into a complete custom

system. The PSoC CY8C27x43 family can have up to five IO

ports that connect to the global digital and analog interconnects,

providing access to 8 digital blocks and 12 analog blocks.

DIGITAL SYSTEM

ANALOG SYSTEM

Analog

Ref

Digital

Block

Array

Analog

Block

Array

(2 Rows,

8 Blocks)

(4 Columns,

12 Blocks)

Analog

Input

Muxing

The PSoC Core

The PSoC Core is a powerful engine that supports a rich fea-

ture set. The core includes a CPU, memory, clocks, and config-

urable GPIO (General Purpose IO).

POR and LVD Internal

Voltage

Switch

Mode

Pump

Digital

Clocks Accum.

Multiply

I²C

Decimator

System Resets

Ref.

The M8C CPU core is a powerful processor with speeds up to

24 MHz, providing a four MIPS 8-bit Harvard architecture micro-

SYSTEM RESOURCES

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CY8C27x43 Final Data Sheet

PSoC™ Overview

processor. The CPU utilizes an interrupt controller with 17 vec-

tors, to simplify programming of real time embedded events.

Program execution is timed and protected using the included

Sleep and Watch Dog Timers (WDT).

Digital peripheral configurations include those listed below.

■ PWMs (8 to 32 bit)

■ PWMs with Dead band (8 to 32 bit)

■ Counters (8 to 32 bit)

Memory encompasses 16 KB of Flash for program storage, 256

bytes of SRAM for data storage, and up to 2 KB of EEPROM

emulated using the Flash. Program Flash utilizes four protec-

tion levels on blocks of 64 bytes, allowing customized software

IP protection.

■ Timers (8 to 32 bit)

■ UART 8 bit with selectable parity (up to 2)

■ SPI master and slave (up to 2)

■ I2C slave and master (1 available as a System Resource)

■ Cyclical Redundancy Checker/Generator (8 to 32 bit)

■ IrDA (up to 2)

The PSoC device incorporates flexible internal clock genera-

tors, including a 24 MHz IMO (internal main oscillator) accurate

to 2.5% over temperature and voltage. The 24 MHz IMO can

also be doubled to 48 MHz for use by the digital system. A low

power 32 kHz ILO (internal low speed oscillator) is provided for

the Sleep timer and WDT. If crystal accuracy is desired, the

ECO (32.768 kHz external crystal oscillator) is available for use

as a Real Time Clock (RTC) and can optionally generate a crys-

tal-accurate 24 MHz system clock using a PLL. The clocks,

together with programmable clock dividers (as a System

Resource), provide the flexibility to integrate almost any timing

requirement into the PSoC device.

■ Pseudo Random Sequence Generators (8 to 32 bit)

The digital blocks can be connected to any GPIO through a

series of global buses that can route any signal to any pin. The

buses also allow for signal multiplexing and for performing logic

operations. This configurability frees your designs from the con-

straints of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of

blocks varies by PSoC device family. This allows you the opti-

mum choice of system resources for your application. Family

resources are shown in the table titled “PSoC Device Charac-

teristics” on page 3.

PSoC GPIOs provide connection to the CPU, digital and analog

resources of the device. Each pin’s drive mode may be selected

from eight options, allowing great flexibility in external interfac-

ing. Every pin also has the capability to generate a system inter-

rupt on high level, low level, and change from last read.

The Analog System

The Analog System is composed of 12 configurable blocks,

each comprised of an opamp circuit allowing the creation of

complex analog signal flows. Analog peripherals are very flexi-

ble and can be customized to support specific application

requirements. Some of the more common PSoC analog func-

tions (most available as user modules) are listed below.

The Digital System

The Digital System is composed of 8 digital PSoC blocks. Each

block is an 8-bit resource that can be used alone or combined

with other blocks to form 8, 16, 24, and 32-bit peripherals, which

are called user module references.

■ Analog-to-digital converters (up to 4, with 6- to 14-bit resolu-

tion, selectable as Incremental, Delta Sigma, and SAR)

Port 5

Port 4

Port 3

Port 2

Port 1

Port 0

■ Filters (2, 4, 6, and 8 pole band-pass, low-pass, and notch)

■ Amplifiers (up to 4, with selectable gain to 48x)

To System Bus

Digital Clocks

From Core

To Analog

System

■ Instrumentation amplifiers (up to 2, with selectable gain to

93x)

■ Comparators (up to 4, with 16 selectable thresholds)

■ DACs (up to 4, with 6- to 9-bit resolution)

DIGITAL SYSTEM

Digital PSoC Block Array

■ Multiplying DACs (up to 4, with 6- to 9-bit resolution)

Row 0

4

■ High current output drivers (four with 30 mA drive as a Core

Resource)

DBB00

DBB01

DCB02

DCB03

4

■ 1.3V reference (as a System Resource)

■ DTMF dialer

8

■ Modulators

Row 1

DBB11 DCB12

■ Correlators

DBB10

DCB13

■ Peak detectors

4

■ Many other topologies possible

GIE[7:0]

GIO[7:0]

GOE[7:0]

GOO[7:0]

Global Digital

Interconnect

Digital System Block Diagram

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CY8C27x43 Final Data Sheet

PSoC™ Overview

Analog blocks are provided in columns of three, which includes

one CT (Continuous Time) and two SC (Switched Capacitor)

blocks, as shown in the figure below.

Additional System Resources

System Resources, some of which have been previously listed,

provide additional capability useful to complete systems. Addi-

tional resources include a multiplier, decimator, switch mode

pump, low voltage detection, and power on reset. Brief state-

ments describing the merits of each system resource are pre-

sented below.

P0[7]

P0[5]

P0[6]

P0[4]

■ Digital clock dividers provide three customizable clock fre-

quencies for use in applications. The clocks can be routed to

both the digital and analog systems. Additional clocks can be

generated using digital PSoC blocks as clock dividers.

P0[3]

P0[1]

P0[2]

P0[0]

P2[6]

P2[4]

■ A multiply accumulate (MAC) provides a fast 8-bit multiplier

with 32-bit accumulate, to assist in both general math as well

as digital filters.

P2[3]

P2[1]

■ The decimator provides a custom hardware filter for digital

signal processing applications including the creation of Delta

Sigma ADCs.

P2[2]

P2[0]

■ The I2C module provides 100 and 400 kHz communication

over two wires. Slave, master, and multi-master modes are

all supported.

■ Low Voltage Detection (LVD) interrupts can signal the appli-

cation of falling voltage levels, while the advanced POR

(Power On Reset) circuit eliminates the need for a system

supervisor.

Array Input Configuration

ACI0[1:0]

ACI1[1:0]

ACI2[1:0]

ACI3[1:0]

■ An internal 1.3V reference provides an absolute reference for

the analog system, including ADCs and DACs.

■ An integrated switch mode pump (SMP) generates normal

operating voltages from a single 1.2V battery cell, providing a

low cost boost converter.

Block Array

ACB00

ASC10

ASD20

ACB01

ASD11

ASC21

ACB02

ASC12

ASD22

ACB03

ASD13

ASC23

PSoC Device Characteristics

Depending on your PSoC device characteristics, the digital and

analog systems can have 16, 8, or 4 digital blocks and 12, 6, or

3 analog blocks. The following table lists the resources

available for specific PSoC device groups. The PSoC device

covered by this data sheet is shown in the second row of the

table.

Analog Reference

Interface to

Digital System

Reference

Generators

RefHi

RefLo

AGND

AGNDIn

RefIn

Bandgap

PSoC Device Characteristics

PSoC Part

Number

M8C Interface (Address Bus, Data Bus, Etc.)

up to

64

Analog System Block Diagram

CY8C29x66

CY8C27x43

CY8C24x23

CY8C24x23A

CY8C22x13

4

2

1

16

8

12

8

4

2

1

4

2

1

12

6

up to

44

up to

24

4

up to

24

4

6

up to

16

4

3

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CY8C27x43 Final Data Sheet

PSoC™ Overview

Getting Started

Development Tools

The Cypress MicroSystems PSoC Designer is a Microsoft^®

Windows-based, integrated development environment for the

Programmable System-on-Chip (PSoC) devices. The PSoC

Designer IDE and application runs on Windows NT 4.0, Win-

dows 2000, Windows Millennium (Me), or Windows XP. (Refer-

ence the PSoC Designer Functional Flow diagram below.)

The quickest path to understanding the PSoC silicon is by read-

ing this data sheet and using the PSoC Designer Integrated

Development Environment (IDE). This data sheet is an over-

view of the PSoC integrated circuit and presents specific pin,

register, and electrical specifications. For in-depth information,

along with detailed programming information, reference the

PSoC™ Mixed Signal Array Technical Reference Manual.

PSoC Designer helps the customer to select an operating con-

figuration for the PSoC, write application code that uses the

PSoC, and debug the application. This system provides design

database management by project, an integrated debugger with

In-Circuit Emulator, in-system programming support, and the

CYASM macro assembler for the CPUs.

For up-to-date Ordering, Packaging, and Electrical Specification

information, reference the latest PSoC device data sheets on

the web at http://www.cypress.com/psoc.

Development Kits

PSoC Designer also supports a high-level C language compiler

developed specifically for the devices in the family.

Development Kits are available from the following distributors:

Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store

at http://www.onfulfillment.com/cypressstore/ contains develop-

ment kits, C compilers, and all accessories for PSoC develop-

ment. Click on PSoC (Programmable System-on-Chip) to view

a current list of available items.

Context

Sensitive

Help

Graphical Designer

PSoC^TM

Interface

Designer

Tele-Training

Free PSoC "Tele-training" is available for beginners and taught

by a live marketing or application engineer over the phone. Five

training classes are available to accelerate the learning curve

including introduction, designing, debugging, advanced design,

advanced analog, as well as application-specific classes cover-

ing topics like PSoC and the LIN bus. For days and times of the

tele-training, see http://www.cypress.com/support/training.cfm.

Importable

Design

Database

PSoC

Configuration

Sheet

Device

Database

Consultants

PSoC^TM

Designer

Core

Application

Database

Certified PSoC Consultants offer everything from technical

assistance to completed PSoC designs. To contact or become a

PSoC Consultant, go to the following Cypress support web site:

http://www.cypress.com/support/cypros.cfm.

Manufacturing

Information

File

Engine

Project

Database

User

Modules

Library

Technical Support

PSoC application engineers take pride in fast and accurate

response. They can be reached with a 4-hour guaranteed

response at http://www.cypress.com/support/login.cfm.

Application Notes

Emulation

Pod

In-Circuit

Emulator

Device

Programmer

A long list of application notes will assist you in every aspect of

your design effort. To locate the PSoC application notes, go to

http://www.cypress.com/design/results.cfm.

PSoC Designer Subsystems

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CY8C27x43 Final Data Sheet

PSoC™ Overview

PSoC Designer Software Subsystems

Device Editor

Debugger

The Device Editor subsystem allows the user to select different

onboard analog and digital components called user modules

using the PSoC blocks. Examples of user modules are ADCs,

DACs, Amplifiers, and Filters.

The PSoC Designer Debugger subsystem provides hardware

in-circuit emulation, allowing the designer to test the program in

a physical system while providing an internal view of the PSoC

device. Debugger commands allow the designer to read and

program and read and write data memory, read and write IO

registers, read and write CPU registers, set and clear break-

points, and provide program run, halt, and step control. The

debugger also allows the designer to create a trace buffer of

registers and memory locations of interest.

The device editor also supports easy development of multiple

configurations and dynamic reconfiguration. Dynamic configu-

ration allows for changing configurations at run time.

PSoC Designer sets up power-on initialization tables for

selected PSoC block configurations and creates source code

for an application framework. The framework contains software

to operate the selected components and, if the project uses

more than one operating configuration, contains routines to

switch between different sets of PSoC block configurations at

run time. PSoC Designer can print out a configuration sheet for

a given project configuration for use during application pro-

gramming in conjunction with the Device Data Sheet. Once the

framework is generated, the user can add application-specific

code to flesh out the framework. It’s also possible to change the

selected components and regenerate the framework.

Online Help System

The online help system displays online, context-sensitive help

for the user. Designed for procedural and quick reference, each

functional subsystem has its own context-sensitive help. This

system also provides tutorials and links to FAQs and an Online

Support Forum to aid the designer in getting started.

Hardware Tools

In-Circuit Emulator

Design Browser

A low cost, high functionality ICE (In-Circuit Emulator) is avail-

able for development support. This hardware has the capability

to program single devices.

The Design Browser allows users to select and import precon-

figured designs into the user’s project. Users can easily browse

a catalog of preconfigured designs to facilitate time-to-design.

Examples provided in the tools include a 300-baud modem, LIN

Bus master and slave, fan controller, and magnetic card reader.

The emulator consists of a base unit that connects to the PC by

way of the parallel or USB port. The base unit is universal and

will operate with all PSoC devices. Emulation pods for each

device family are available separately. The emulation pod takes

the place of the PSoC device in the target board and performs

full speed (24 MHz) operation.

Application Editor

In the Application Editor you can edit your C language and

Assembly language source code. You can also assemble, com-

pile, link, and build.

Assembler. The macro assembler allows the assembly code

to be merged seamlessly with C code. The link libraries auto-

matically use absolute addressing or can be compiled in relative

mode, and linked with other software modules to get absolute

addressing.

C Language Compiler. A C language compiler is available

that supports Cypress MicroSystems’ PSoC family devices.

Even if you have never worked in the C language before, the

product quickly allows you to create complete C programs for

the PSoC family devices.

The embedded, optimizing C compiler provides all the features

of C tailored to the PSoC architecture. It comes complete with

embedded libraries providing port and bus operations, standard

keypad and display support, and extended math functionality.

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CY8C27x43 Final Data Sheet

PSoC™ Overview

Designing with User Modules

The development process for the PSoC device differs from that

of a traditional fixed function microprocessor. The configurable

analog and digital hardware blocks give the PSoC architecture

a unique flexibility that pays dividends in managing specification

change during development and by lowering inventory costs.

These configurable resources, called PSoC Blocks, have the

ability to implement a wide variety of user-selectable functions.

Each block has several registers that determine its function and

connectivity to other blocks, multiplexers, buses, and to the IO

pins. Iterative development cycles permit you to adapt the hard-

ware as well as the software. This substantially lowers the risk

that you will have to select a different part to meet the final

design requirements.

Device Editor

Placement

and

Parameter

-ization

User

Module

Selection

Source

Code

Generator

Generate

Application

Application Editor

Source

Code

Editor

To speed the development process, the PSoC Designer Inte-

grated Development Environment (IDE) provides a library of

pre-built, pre-tested hardware peripheral functions, called “User

Modules.” User modules make selecting and implementing

peripheral devices simple, and come in analog, digital, and

mixed signal varieties. The standard User Module library con-

tains over 50 common peripherals such as ADCs, DACs Tim-

ers, Counters, UARTs, and other not-so common peripherals

such as DTMF Generators and Bi-Quad analog filter sections.

Project

Manager

Build

Manager

Build

All

Debugger

Each user module establishes the basic register settings that

implement the selected function. It also provides parameters

that allow you to tailor its precise configuration to your particular

application. For example, a Pulse Width Modulator User Mod-

ule configures one or more digital PSoC blocks, one for each 8

bits of resolution. The user module parameters permit you to

establish the pulse width and duty cycle. User modules also

provide tested software to cut your development time. The user

module application programming interface (API) provides high-

level functions to control and respond to hardware events at

run-time. The API also provides optional interrupt service rou-

tines that you can adapt as needed.

Event &

Breakpoint

Manager

Interface

to ICE

Storage

Inspector

User Module and Source Code Development Flows

The next step is to write your main program, and any sub-rou-

tines using PSoC Designer’s Application Editor subsystem.

The Application Editor includes a Project Manager that allows

you to open the project source code files (including all gener-

ated code files) from a hierarchal view. The source code editor

provides syntax coloring and advanced edit features for both C

and assembly language. File search capabilities include simple

string searches and recursive “grep-style” patterns. A single

mouse click invokes the Build Manager. It employs a profes-

sional-strength “makefile” system to automatically analyze all

file dependencies and run the compiler and assembler as nec-

essary. Project-level options control optimization strategies

used by the compiler and linker. Syntax errors are displayed in

a console window. Double clicking the error message takes you

directly to the offending line of source code. When all is correct,

the linker builds a HEX file image suitable for programming.

The API functions are documented in user module data sheets

that are viewed directly in the PSoC Designer IDE. These data

sheets explain the internal operation of the user module and

provide performance specifications. Each data sheet describes

the use of each user module parameter and documents the set-

ting of each register controlled by the user module.

The development process starts when you open a new project

and bring up the Device Editor, a graphical user interface (GUI)

for configuring the hardware. You pick the user modules you

need for your project and map them onto the PSoC blocks with

point-and-click simplicity. Next, you build signal chains by inter-

connecting user modules to each other and the IO pins. At this

stage, you also configure the clock source connections and

enter parameter values directly or by selecting values from

drop-down menus. When you are ready to test the hardware

configuration or move on to developing code for the project, you

perform the “Generate Application” step. This causes PSoC

Designer to generate source code that automatically configures

the device to your specification and provides the high-level user

module API functions.

The last step in the development process takes place inside the

PSoC Designer’s Debugger subsystem. The Debugger down-

loads the HEX image to the In-Circuit Emulator (ICE) where it

runs at full speed. Debugger capabilities rival those of systems

costing many times more. In addition to traditional single-step,

run-to-breakpoint and watch-variable features, the Debugger

provides a large trace buffer and allows you define complex

breakpoint events that include monitoring address and data bus

values, memory locations and external signals.

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CY8C27x43 Final Data Sheet

PSoC™ Overview

Document Conventions

Table of Contents

For an in depth discussion and more information on your PSoC

device, obtain the PSoC Mixed Signal Array Technical Refer-

ence Manual. This document encompasses and is organized

into the following chapters and sections.

Acronyms Used

The following table lists the acronyms that are used in this doc-

ument.

Acronym

AC

Description

1.

Pin Information ............................................................. 8

alternating current

1.1 Pinouts ................................................................... 8

1.1.1 8-Pin Part Pinout .................................................8

1.1.2 20-Pin Part Pinout ...............................................9

1.1.3 28-Pin Part Pinout .............................................10

1.1.4 44-Pin Part Pinout .............................................11

1.1.5 48-Pin Part Pinouts ...........................................12

ADC

API

analog-to-digital converter

application programming interface

central processing unit

continuous time

CPU

CT

DAC

DC

digital-to-analog converter

direct current

2.

3.

Register Reference ..................................................... 14

ECO

EEPROM

FSR

GPIO

GUI

external crystal oscillator

electrically erasable programmable read-only memory

full scale range

2.1 Register Conventions ........................................... 14

2.2 Register Mapping Tables ..................................... 14

Electrical Specifications ............................................ 17

general purpose IO

3.1 Absolute Maximum Ratings ................................ 18

3.2 Operating Temperature ....................................... 18

3.3 DC Electrical Characteristics ................................ 19

3.3.1 DC Chip-Level Specifications .............................19

3.3.2 DC General Purpose IO Specifications ..............19

3.3.3 DC Operational Amplifier Specifications ............20

3.3.4 DC Analog Output Buffer Specifications ............22

3.3.5 DC Switch Mode Pump Specifications ...............23

3.3.6 DC Analog Reference Specifications .................24

3.3.7 DC Analog PSoC Block Specifications ...............26

3.3.8 DC POR and LVD Specifications .......................26

3.3.9 DC Programming Specifications ........................27

3.4 AC Electrical Characteristics ................................ 28

3.4.1 AC Chip-Level Specifications .............................28

3.4.2 AC General Purpose IO Specifications ..............30

3.4.3 AC Operational Amplifier Specifications .............31

3.4.4 AC Digital Block Specifications ..........................32

3.4.5 AC Analog Output Buffer Specifications .............33

3.4.6 AC External Clock Specifications .......................34

3.4.7 AC Programming Specifications .........................34

3.4.8 AC I2C Specifications .........................................35

graphical user interface

human body model

HBM

ICE

in-circuit emulator

ILO

internal low speed oscillator

internal main oscillator

input/output

IMO

IO

IPOR

LSb

imprecise power on reset

least-significant bit

LVD

low voltage detect

MSb

PC

most-significant bit

program counter

PLL

phase-locked loop

POR

PPOR

PSoC™

PWM

RAM

SC

power on reset

precision power on reset

Programmable System-on-Chip™

pulse width modulator

random access memory

switched capacitor

4.

Packaging Information ............................................... 36

SLIMO

SMP

slow IMO

switch mode pump

4.1 Packaging Dimensions ......................................... 36

4.2 Thermal Impedances .......................................... 41

4.3 Capacitance on Crystal Pins ............................... 41

Units of Measure

5.

6.

Ordering Information .................................................. 42

5.1 Ordering Code Definitions ................................... 43

A units of measure table is located in the Electrical Specifica-

tions section. Table 3-1 on page 17 lists all the abbreviations

used to measure the PSoC devices.

Sales and Service Information .................................. 44

6.1 Revision History ................................................... 44

6.2 Copyrights and Code Protection .......................... 44

Numeric Naming

Hexidecimal numbers are represented with all letters in upper-

case with an appended lowercase ‘h’ (for example, ‘14h’ or

‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’

prefix, the C coding convention. Binary numbers have an

appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).

Numbers not indicated by an ‘h’ or ‘b’ are decimal.

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Document No. 38-12012 Rev. *I

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1. Pin Information

This chapter describes, lists, and illustrates the CY8C27x43 PSoC device pins and pinout configurations.

1.1

Pinouts

The CY8C27x43 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port

pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.

1.1.1

8-Pin Part Pinout

Table 1-1. 8-Pin Part Pinout (PDIP)

Type

CY8C27143 8-Pin PSoC Device

No.

Name

Description

Digital Analog

1

2

3

4

5

IO

P0[5]

Analog column mux input and column output.

Crystal Input (XTALin), I2C Serial Clock (SCL)

Ground connection.

Vdd

AIO, P0[5]

AIO, P0[3]

1

2

3

4

8

7

6

5

P0[4], AIO

P0[3]

P1[1]

Vss

PDIP

P0[2], AIO

I2C SCL, XTALin, P1[1]

Vss

P1[0], XTALout, I2C SDA

Power

IO

P1[0]

Crystal Output (XTALout), I2C Serial Data

(SDA)

6

7

8

IO

P0[2]

P0[4]

Vdd

Analog column mux input and column output.

Supply voltage.

Power

LEGEND: A = Analog, I = Input, and O = Output.

August 3, 2004

Document No. 38-12012 Rev. *I

8

CY8C27x43 Final Data Sheet

1. Pin Information

1.1.2

20-Pin Part Pinout

Table 1-2. 20-Pin Part Pinout (SSOP, SOIC)

Type

CY8C27243 20-Pin PSoC Device

No.

Name

Description

Digital Analog

1

2

3

4

5

IO

I

P0[7]

P0[5]

P0[3]

P0[1]

SMP

Analog column mux input.

AI, P0[7]

AIO, P0[5]

Vdd

20

19

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

9

IO

I

Analog column mux input and column output.

Analog column mux input.

P0[6], AI

AIO, P0[3]

P0[4], AIO

P0[2], AIO

P0[0], AI

AI, P0[1]

SSOP

SOIC

SMP

Power

Switch Mode Pump (SMP) connection to

external components required.

I2C SCL, P1[7]

I2C SDA, P1[5]

P1[3]

XRES

P1[6]

6

IO

P1[7]

P1[5]

P1[3]

P1[1]

Vss

I2C Serial Clock (SCL)

I2C Serial Data (SDA)

P1[4], EXTCLK

P1[2]

7

I2C SCL, XTALin, P1[1]

Vss

8

P1[0], XTALout, I2C SDA

10

9

Crystal Input (XTALin), I2C Serial Clock (SCL)

Ground connection.

10

11

IO

P1[0]

Crystal Output (XTALout), I2C Serial Data

(SDA)

12

P1[2]

13

14

15

IO

P1[4]

P1[6]

XRES

Optional External Clock Input (EXTCLK)

Input

Active high external reset with internal pull

down.

16

17

18

19

20

IO

I

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

Analog column mux input.

IO

I

Analog column mux input and column output.

Analog column mux input.

Power

Supply voltage.

LEGEND: A = Analog, I = Input, and O = Output.

August 3, 2004

Document No. 38-12012 Rev. *I

9

CY8C27x43 Final Data Sheet

1. Pin Information

1.1.3

28-Pin Part Pinout

Table 1-3. 28-Pin Part Pinout (PDIP, SSOP, SOIC)

Type

CY8C27443 28-Pin PSoC Device

No.

Name

Description

Digital Analog

1

2

3

4

5

6

7

8

9

IO

I

P0[7]

P0[5]

P0[3]

P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

SMP

Analog column mux input.

AI, P0[7]

AIO, P0[5]

AIO, P0[3]

AI, P0[1]

Vdd

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

IO

I

Analog column mux input and column output.

Analog column mux input.

P0[6], AI

P0[4], AIO

P0[2], AIO

P0[0], AI

P2[7]

P2[5]

P2[6], External VRef

P2[4], External AGND

P2[2], AI

PDIP

SSOP

SOIC

AI, P2[3]

I

Direct switched capacitor block input.

AI, P2[1]

SMP

P2[0], AI

Power

Input

Switch Mode Pump (SMP) connection to

external components required.

I2C SCL, P1[7]

I2C SDA, P1[5]

P1[3]

XRES

P1[6]

10

11

12

13

14

15

IO

P1[7]

P1[5]

P1[3]

P1[1]

Vss

I2C Serial Clock (SCL)

I2C Serial Data (SDA)

P1[4], EXTCLK

P1[2]

I2C SCL, XTALin, P1[1]

Vss

P1[0], XTALout, I2C SDA

Crystal Input (XTALin), I2C Serial Clock (SCL)

Ground connection.

IO

P1[0]

Crystal Output (XTALout), I2C Serial Data

(SDA)

16

17

18

19

IO

P1[2]

P1[4]

P1[6]

XRES

Optional External Clock Input (EXTCLK)

Active high external reset with internal pull

down.

20

21

22

23

24

25

26

27

28

IO

I

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

Direct switched capacitor block input.

External Analog Ground (AGND)

External Voltage Reference (VRef)

Analog column mux input.

I

IO

I

Analog column mux input and column output.

Analog column mux input.

Power

Supply voltage.

LEGEND: A = Analog, I = Input, and O = Output.

August 3, 2004

Document No. 38-12012 Rev. *I

10

CY8C27x43 Final Data Sheet

1. Pin Information

1.1.4

44-Pin Part Pinout

Table 1-4. 44-Pin Part Pinout (TQFP)

Type

CY8C27543 44-Pin PSoC Device

No.

Name

Description

Digital Analog

1

2

3

4

5

6

7

8

IO

P2[5]

P2[3]

P2[1]

P4[7]

P4[5]

P4[3]

P4[1]

SMP

IO

I

Direct switched capacitor block input.

Power

Switch Mode Pump (SMP) connection to

external components required.

P2[5]

P2[4], External AGND

P2[2], AI

P2[0], AI

P4[6]

1

2

33

32

31

30

AI, P2[3]

AI, P2[1]

P4[7]

9

IO

P3[7]

P3[5]

P3[3]

P3[1]

P1[7]

P1[5]

P1[3]

P1[1]

Vss

3

4

5

10

11

12

13

14

15

16

17

18

P4[4]

P4[5]

29

28

27

TQFP

P4[2]

6

P4[3]

P4[1]

SMP

P3[7]

P4[0]

7

8

9

10

I2C Serial Clock (SCL)

I2C Serial Data (SDA)

XRES

26

25 P3[6]

24

23 P3[2]

P3[5]

P3[4]

Crystal Input (XTALin), I2C Serial Clock (SCL)

Ground connection.

P3[3] 11

Power

IO

P1[0]

Crystal Output (XTALout), I2C Serial Data

(SDA)

19

P1[2]

20

21

22

23

24

25

26

IO

P1[4]

P1[6]

P3[0]

P3[2]

P3[4]

P3[6]

XRES

Optional External Clock Input (EXTCLK)

Input

Active high external reset with internal pull

down.

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

IO

P4[0]

P4[2]

P4[4]

P4[6]

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

I

Direct switched capacitor block input.

External Analog Ground (AGND)

External Voltage Reference (VRef)

Analog column mux input.

I

IO

I

Analog column mux input and column output.

Analog column mux input.

Power

Supply voltage.

IO

I

P0[7]

P0[5]

P0[3]

P0[1]

P2[7]

Analog column mux input.

IO

I

Analog column mux input and column output.

Analog column mux input.

LEGEND: A = Analog, I = Input, and O = Output.

August 3, 2004

Document No. 38-12012 Rev. *I

11

CY8C27x43 Final Data Sheet

1. Pin Information

1.1.5

48-Pin Part Pinouts

Table 1-5. 48-Pin Part Pinout (SSOP)

Type

CY8C27643 48-Pin PSoC Device

No.

Name

Description

Digital Analog

1

IO

I

P0[7]

P0[5]

P0[3]

P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

P4[7]

P4[5]

P4[3]

P4[1]

SMP

Analog column mux input.

AI, P0[7]

1

2

Vdd

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

AIO, P0[5]

AIO, P0[3]

2

IO

I

Analog column mux input and column output.

Analog column mux input.

P0[6], AI

P0[2], AIO

P0[4], AIO

P0[0], AI

P2[6], External VRef

P2[4], External AGND

P2[2], AI

P2[0], AI

P4[6]

3

4

5

3

AI, P0[1]

P2[7]

4

5

P2[5]

6

7

6

AI, P2[3]

AI, P2[1]

P4[7]

7

I

Direct switched capacitor block input.

8

9

10

8

P4[5]

9

P4[3]

11

12

13

14

15

16

P4[4]

P4[2]

10

11

12

13

P4[1]

SSOP

SMP

P4[0]

P3[7]

XRES

Power

Input

Switch Mode Pump (SMP) connection to

external components required.

P3[5]

P3[6]

P3[3]

P3[1]

P3[4]

14

15

16

17

18

19

20

21

22

23

24

25

IO

P3[7]

P3[5]

P3[3]

P3[1]

P5[3]

P5[1]

P1[7]

P1[5]

P1[3]

P1[1]

Vss

17

18

19

20

21

P3[2]

P5[3]

P5[1]

I2C SCL, P1[7]

P3[0]

P5[2]

P5[0]

P1[6]

I2C SDA, P1[5]

P1[3]

I2C SCL, XTALin, P1[1]

Vss

22

23

24

P1[4], EXTCLK

P1[2]

I2C Serial Clock (SCL)

I2C Serial Data (SDA)

P1[0], XTALout, I2C SDA

Crystal Input (XTALin), I2C Serial Clock (SCL)

Ground connection.

IO

P1[0]

Crystal Output (XTALout), I2C Serial Data

(SDA)

26

27

28

29

30

31

32

33

34

35

IO

P1[2]

P1[4]

P1[6]

P5[0]

P5[2]

P3[0]

P3[2]

P3[4]

P3[6]

XRES

Optional External Clock Input (EXTCLK)

Active high external reset with internal pull

down.

36

37

38

39

40

41

42

43

44

45

46

47

48

IO

P4[0]

P4[2]

P4[4]

P4[6]

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

I

Direct switched capacitor block input.

External Analog Ground (AGND)

External Voltage Reference (VRef)

Analog column mux input.

I

IO

I

Analog column mux input and column output.

Analog column mux input.

Power

Supply voltage.

LEGEND: A = Analog, I = Input, and O = Output.

August 3, 2004

Document No. 38-12012 Rev. *I

12

CY8C27x43 Final Data Sheet

1. Pin Information

Table 1-6. 48-Pin Part Pinout (MLF*)

Type

CY8C27643 48-Pin PSoC Device

No.

Name

Description

Digital Analog

1

2

3

4

5

6

7

IO

I

P2[3]

P2[1]

P4[7]

P4[5]

P4[3]

P4[1]

SMP

Direct switched capacitor block input.

P2[4], External AGND

P2[2], AI

AI, P2[3]

AI, P2[1]

P4[7]

36

35

34

33

32

31

1

2

Power

Input

Switch Mode Pump (SMP) connection to

external components required.

3

4

5

6

P2[0], AI

P4[6]

8

IO

P3[7]

P3[5]

P3[3]

P3[1]

P5[3]

P5[1]

P1[7]

P1[5]

P1[3]

P1[1]

Vss

P4[5]

P4[3]

P4[1]

SMP

P3[7]

P3[5]

P3[3]

P3[1]

P5[3]

9

P4[4]

10

11

12

13

14

15

16

17

18

19

P4[2]

MLF

(Top View)

30

29

28

27

P4[0]

7

8

9

XRES

P3[6]

P3[4]

10

I2C Serial Clock (SCL)

I2C Serial Data (SDA)

26

25

P3[2]

P3[0]

11

12

Crystal Input (XTALin), I2C Serial Clock (SCL)

Ground connection.

IO

P1[0]

Crystal Output (XTALout), I2C Serial Data

(SDA)

20

21

22

23

24

25

26

27

28

29

IO

P1[2]

P1[4]

P1[6]

P5[0]

P5[2]

P3[0]

P3[2]

P3[4]

P3[6]

XRES

Optional External Clock Input (EXTCLK)

Active high external reset with internal pull

down.

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

IO

P4[0]

P4[2]

P4[4]

P4[6]

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

I

Direct switched capacitor block input.

External Analog Ground (AGND)

External Voltage Reference (VRef)

Analog column mux input.

I

IO

I

Analog column mux input and column output.

Analog column mux input.

Power

Supply voltage.

IO

I

P0[7]

P0[5]

P0[3]

P0[1]

P2[7]

P2[5]

Analog column mux input.

IO

I

Analog column mux input and column output.

Analog column mux input.

LEGEND: A = Analog, I = Input, and O = Output.

* The MLF package has a center pad that must be connected to ground (Vss).

August 3, 2004

Document No. 38-12012 Rev. *I

13

2. Register Reference

This chapter lists the registers of the CY8C27x43 PSoC device. For detailed register information, reference the PSoC™ Mixed Sig-

nal Array Technical Reference Manual.

2.1

Register Conventions

2.2

Register Mapping Tables

The register conventions specific to this section are listed in the

following table.

The PSoC device has a total register address space of 512

bytes. The register space is referred to as IO space and is

divided into two banks. The XOI bit in the Flag register (CPU_F)

determines which bank the user is currently in. When the XOI

bit is set the user is in bank 1.

Convention

Description

R

W

L

Read register or bit(s)

Write register or bit(s)

Note In the following register mapping tables, blank fields are

reserved and should not be accessed.

Logical register or bit(s)

Clearable register or bit(s)

Access is bit specific

C

#

August 3, 2004

14

CY8C27x43 Final Data Sheet

2. Register Reference

Register Map Bank 0 Table: User Space

PRT0DR

PRT0IE

PRT0GS

PRT0DM2

PRT1DR

PRT1IE

PRT1GS

PRT1DM2

PRT2DR

PRT2IE

PRT2GS

PRT2DM2

PRT3DR

PRT3IE

PRT3GS

PRT3DM2

PRT4DR

PRT4IE

PRT4GS

PRT4DM2

PRT5DR

PRT5IE

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

ASC10CR0

ASC10CR1

ASC10CR2

ASC10CR3

ASD11CR0

ASD11CR1

ASD11CR2

ASD11CR3

ASC12CR0

ASC12CR1

ASC12CR2

ASC12CR3

ASD13CR0

ASD13CR1

ASD13CR2

ASD13CR3

ASD20CR0

ASD20CR1

ASD20CR2

ASD20CR3

ASC21CR0

ASC21CR1

ASC21CR2

ASC21CR3

ASD22CR0

ASD22CR1

ASD22CR2

ASD22CR3

ASC23CR0

ASC23CR1

ASC23CR2

ASC23CR3

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

PRT5GS

PRT5DM2

I2C_CFG

I2C_SCR

I2C_DR

I2C_MSCR

INT_CLR0

INT_CLR1

RW

#

RW

#

RW

INT_CLR3

INT_MSK3

RW

DBB00DR0

DBB00DR1

DBB00DR2

DBB00CR0

DBB01DR0

DBB01DR1

DBB01DR2

DBB01CR0

DCB02DR0

DCB02DR1

DCB02DR2

DCB02CR0

DCB03DR0

DCB03DR1

DCB03DR2

DCB03CR0

DBB10DR0

DBB10DR1

DBB10DR2

DBB10CR0

DBB11DR0

DBB11DR1

DBB11DR2

DBB11CR0

DCB12DR0

DCB12DR1

DCB12DR2

DCB12CR0

DCB13DR0

DCB13DR1

DCB13DR2

DCB13CR0

#

AMX_IN

RW

INT_MSK0

INT_MSK1

INT_VC

RES_WDT

DEC_DH

DEC_DL

DEC_CR0

DEC_CR1

MUL_X

RW

RC

W

RC

RW

W

R

RW

W

RW

#

ARF_CR

CMP_CR0

ASY_CR

CMP_CR1

RW

#

W

RW

#

RW

#

W

RW

#

MUL_Y

MUL_DH

MUL_DL

ACC_DR1

ACC_DR0

ACC_DR3

ACC_DR2

#

W

RW

#

ACB00CR3

ACB00CR0

ACB00CR1

ACB00CR2

ACB01CR3

ACB01CR0

ACB01CR1

ACB01CR2

ACB02CR3

ACB02CR0

ACB02CR1

ACB02CR2

ACB03CR3

ACB03CR0

ACB03CR1

ACB03CR2

RW

RDI0RI

RDI0SYN

RDI0IS

RDI0LT0

RDIOLT1

RDI0RO0

RDI0RO1

RW

W

RW

#

F1

F2

F3

F4

F5

F6

F7

F8

#

W

RW

#

CPU_F

RL

#

RDI1RI

RDI1SYN

RDI1IS

RDI1LT0

RDI1LT1

RDI1RO0

RDI1RO1

RW

W

RW

#

F9

FA

FB

FC

FD

FE

FF

#

W

RW

#

CPU_SCR1

CPU_SCR0

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

August 3, 2004

Document No. 38-12012 Rev. *I

15

CY8C27x43 Final Data Sheet

2. Register Reference

Register Map Bank 1 Table: Configuration Space

PRT0DM0

PRT0DM1

PRT0IC0

PRT0IC1

PRT1DM0

PRT1DM1

PRT1IC0

PRT1IC1

PRT2DM0

PRT2DM1

PRT2IC0

PRT2IC1

PRT3DM0

PRT3DM1

PRT3IC0

PRT3IC1

PRT4DM0

PRT4DM1

PRT4IC0

PRT4IC1

PRT5DM0

PRT5DM1

PRT5IC0

PRT5IC1

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

ASC10CR0

ASC10CR1

ASC10CR2

ASC10CR3

ASD11CR0

ASD11CR1

ASD11CR2

ASD11CR3

ASC12CR0

ASC12CR1

ASC12CR2

ASC12CR3

ASD13CR0

ASD13CR1

ASD13CR2

ASD13CR3

ASD20CR0

ASD20CR1

ASD20CR2

ASD20CR3

ASC21CR0

ASC21CR1

ASC21CR2

ASC21CR3

ASD22CR0

ASD22CR1

ASD22CR2

ASD22CR3

ASC23CR0

ASC23CR1

ASC23CR2

ASC23CR3

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

GDI_O_IN

GDI_E_IN

GDI_O_OU

GDI_E_OU

RW

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

OSC_GO_EN DD

RW

R

OSC_CR4

OSC_CR3

OSC_CR0

OSC_CR1

OSC_CR2

VLT_CR

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

DBB00FN

DBB00IN

DBB00OU

RW

CLK_CR0

CLK_CR1

ABF_CR0

AMD_CR0

RW

DBB01FN

DBB01IN

DBB01OU

RW

VLT_CMP

AMD_CR1

ALT_CR0

ALT_CR1

CLK_CR2

RW

DCB02FN

DCB02IN

DCB02OU

RW

IMO_TR

ILO_TR

BDG_TR

ECO_TR

W

RW

W

DCB03FN

DCB03IN

DCB03OU

RW

DBB10FN

DBB10IN

DBB10OU

RW

ACB00CR3

ACB00CR0

ACB00CR1

ACB00CR2

ACB01CR3

ACB01CR0

ACB01CR1

ACB01CR2

ACB02CR3

ACB02CR0

ACB02CR1

ACB02CR2

ACB03CR3

ACB03CR0

ACB03CR1

ACB03CR2

RW

RDI0RI

RDI0SYN

RDI0IS

RDI0LT0

RDIOLT1

RDI0RO0

RDI0RO1

RW

DBB11FN

DBB11IN

DBB11OU

RW

CPU_F

RL

DCB12FN

DCB12IN

DCB12OU

RW

RDI1RI

RDI1SYN

RDI1IS

RDI1LT0

RDI1LT1

RDI1RO0

RDI1RO1

RW

DCB13FN

DCB13IN

DCB13OU

RW

CPU_SCR1

CPU_SCR0

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

August 3, 2004

Document No. 38-12012 Rev. *I

16

3. Electrical Specifications

This chapter presents the DC and AC electrical specifications of the CY8C27x43 PSoC device. For the most up to date electrical

specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.

Specifications are valid for -40^oC ≤ T ≤ 85^oC and T ≤ 100^oC, except where noted. Specifications for devices running at greater

A

J

than 12 MHz are valid for -40^oC ≤ T ≤ 70^oC and T ≤ 82^oC.

A

J

5.25

4.75

3.00

93 kHz

12 MHz

24 MHz

CPU Frequency

Figure 3-1. Voltage versus CPU Frequency

The following table lists the units of measure that are used in this chapter.

Table 3-1: Units of Measure

Symbol

Unit of Measure

Symbol

Unit of Measure

^oC

dB

degree Celsius

µW

micro watts

decibels

mA

ms

mV

nA

ns

milli-ampere

milli-second

milli-volts

fF

femto farad

hertz

Hz

KB

1024 bytes

1024 bits

nano ampere

nanosecond

nanovolts

Kbit

kHz

kΩ

kilohertz

nV

Ω

kilohm

ohm

MHz

MΩ

µA

megahertz

megaohm

micro ampere

micro farad

micro henry

microsecond

micro volts

pA

pF

pp

ppm

ps

pico ampere

pico farad

peak-to-peak

parts per million

picosecond

µF

µH

µs

sps

σ

samples per second

sigma: one standard deviation

volts

µV

µVrms

micro volts root-mean-square

V

August 3, 2004

Document No. 38-12012 Rev. *I

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CY8C27x43 Final Data Sheet

3. Electrical Specifications

3.1

Absolute Maximum Ratings

Table 3-2. Absolute Maximum Ratings

Symbol

Description

Min

-55

Typ

Max

+100

Units

^oC

Notes

T_STG

Storage Temperature

–

Higher storage temperatures will reduce data

retention time.

^oC

V

T_A

Ambient Temperature with Power Applied

-40

+85

Vdd

V_IO

Supply Voltage on Vdd Relative to Vss

DC Input Voltage

-0.5

–

+6.0

Vss- 0.5

Vdd + 0.5

V

–

DC Voltage Applied to Tri-state

Vss - 0.5

-25

–

Vdd + 0.5

+50

V

I_MIO

Maximum Current into any Port Pin

mA

I_MAIO

Maximum Current into any Port Pin Configured as Analog

Driver

-50

–

+50

mA

ESD

–

Electro Static Discharge Voltage

Latch-up Current

2000

–

V

Human Body Model ESD

200

mA

3.2

Operating Temperature

Table 3-3. Operating Temperature

Symbol

T_A

T_J

Description

Min

Typ

Max

Units

^oC

Notes

Ambient Temperature

Junction Temperature

-40

–

+85

-40

–

+100

The temperature rise from ambient to junction is

package specific. See “Thermal Impedances”

on page 41. The user must limit the power con-

sumption to comply with this requirement.

August 3, 2004

Document No. 38-12012 Rev. *I

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CY8C27x43 Final Data Sheet

3. Electrical Specifications

3.3

DC Electrical Characteristics

3.3.1

DC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-4. DC Chip-Level Specifications

Symbol

Vdd

Description

Min

3.00

Typ

Max

5.25

Units

Notes

Supply Voltage

Supply Current

–

5

V

Conditions are Vdd = 5.0V, T_A= 25 ^oC, CPU = 3

I_DD

–

8

mA

MHz, 48 MHz = Disabled. VC1 = 1.5 MHz, VC2

= 93.75 kHz, VC3 = 93.75 kHz.

Conditions are Vdd = 3.3V, T_A= 25 ^oC, CPU = 3

I_DD3

Supply Current

–

3.3

6.0

mA

MHz, 48 MHz = Disabled, VC1 = 1.5 MHz, VC2

= 93.75 kHz, VC3 = 93.75 kHz.

I_SB

Sleep (Mode) Current with POR, LVD, Sleep Timer, and

WDT.^a

–

3

4

6.5

25

µA

Conditions are with internal slow speed oscilla-

tor, Vdd = 3.3V, -40 ^oC ≤ T_A≤ 55 ^oC.

I_SBH

Sleep (Mode) Current with POR, LVD, Sleep Timer, and

WDT at high temperature.^a

Conditions are with internal slow speed oscilla-

tor, Vdd = 3.3V, 55 ^oC < T_A≤ 85 ^oC.

I_SBXTL

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,

and external crystal.^a

7.5

Conditions are with properly loaded, 1 µW max,

32.768 kHz crystal. Vdd = 3.3V, -40 ^oC ≤ T_A

55 ^oC.

≤

I_SBXTLH

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,

and external crystal at high temperature.^a

–

5

26

µA

Conditions are with properly loaded, 1 µW max,

32.768 kHz crystal. Vdd = 3.3V, 55 ^oC < T_A≤ 85

^oC.

Reference Voltage (Bandgap) for Silicon A ^b

Reference Voltage (Bandgap) for Silicon B ^b

V_REF

1.275

1.280

1.300

1.325

1.320

V

Trimmed for appropriate Vdd.

a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions

enabled.

b. Refer to the Ordering Information chapter on page 42.

3.3.2

DC General Purpose IO Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-5. DC GPIO Specifications

Symbol

Description

Min

Typ

5.6

Max

Units

kΩ

Notes

R_PU

Pull up Resistor

4

8

–

R_PD

V_OH

Pull down Resistor

High Output Level

5.6

–

kΩ

Vdd - 1.0

V

IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads,

4 on even port pins (for example, P0[2], P1[4]),

4 on odd port pins (for example, P0[3], P1[5])).

V_OL

Low Output Level

–

0.75

0.8

V

IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads,

4 on even port pins (for example, P0[2], P1[4]),

4 on odd port pins (for example, P0[3], P1[5])).

V_IL

Input Low Level

Input High Level

Input Hysterisis

–

V

Vdd = 3.0 to 5.25

V_IH

V_H

2.1

–

V

60

1

–

mV

nA

pF

I_IL

Input Leakage (Absolute Value)

Capacitive Load on Pins as Input

Capacitive Load on Pins as Output

–

Gross tested to 1 µA.

Package and pin dependent. Temp = 25^oC.

C_IN

C_OUT

–

3.5

10

–

August 3, 2004

Document No. 38-12012 Rev. *I

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CY8C27x43 Final Data Sheet

3. Electrical Specifications

3.3.3

DC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC

blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at

25°C and are for design guidance only.

Table 3-6. 5V DC Operational Amplifier Specifications

Symbol

V_OSOA

Description

Input Offset Voltage (absolute value)

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

Average Input Offset Voltage Drift

Min

Typ

Max

Units

Notes

–

1.6

10

8

mV

1.3

1.2

7.0

mV

7.5

µV/^oC

TCV_OSOA

I_EBOA

35.0

Input Leakage Current (Port 0 Analog Pins)

Input Capacitance (Port 0 Analog Pins)

Common Mode Voltage Range

–

20

–

pA

Gross tested to 1 µA.

Package and pin dependent. Temp = 25^oC.

C_INOA

4.5

9.5

pF

V

V_CMOA

0.0

0.5

–

Vdd

The common-mode input voltage range is mea-

sured through an analog output buffer. The

specification includes the limitations imposed

by the characteristics of the analog output

buffer.

Common Mode Voltage Range (high power or high

opamp bias)

Vdd - 0.5

CMRR_OA

Common Mode Rejection Ratio

Power = Low

–

dB

Specification is applicable at high power. For all

other bias modes (except high power, high

opamp bias), minimum is 60 dB.

60

Power = Medium

Power = High

G_OLOA

Open Loop Gain

Specification is applicable at high power. For all

other bias modes (except high power, high

opamp bias), minimum is 60 dB.

Power = Low

60

80

Power = Medium

Power = High

V_OHIGHOA

V_OLOWOA

I_SOA

High Output Voltage Swing (internal signals)

Power = Low

Vdd - 0.2

Vdd - 0.5

–

V

Power = Medium

Power = High

Low Output Voltage Swing (internal signals)

Power = Low

–

0.2

0.5

V

Power = Medium

Power = High

Supply Current (including associated AGND buffer)

Power = Low, Opamp Bias = Low

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = Low

Power = High, Opamp Bias = High

Supply Voltage Rejection Ratio

–

150

300

600

1200

2400

4600

–

200

400

800

1600

3200

6400

–

µA

dB

–

PSRR_OA

60

0V ≤ V_IN≤ (Vdd - 2.25) or

(Vdd - 1.25V) ≤ V_IN≤ Vdd.

August 3, 2004

Document No. 38-12012 Rev. *I

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CY8C27x43 Final Data Sheet

3. Electrical Specifications

Table 3-7. 3.3V DC Operational Amplifier Specifications

Symbol

V_OSOA

Description

Min

Typ

Max

Units

Notes

Input Offset Voltage (absolute value)

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = High

High Power is 5 Volts Only

–

1.65

10

8

mV

1.32

mV

µV/^oC

TCV_OSOA

I_EBOA

Average Input Offset Voltage Drift

Input Leakage Current (Port 0 Analog Pins)

Input Capacitance (Port 0 Analog Pins)

Common Mode Voltage Range

–

7.0

20

4.5

–

35.0

–

pA

Gross tested to 1 µA.

Package and pin dependent. Temp = 25^oC.

C_INOA

–

9.5

pF

V

V_CMOA

0.2

Vdd - 0.2

The common-mode input voltage range is

measured through an analog output buffer.

The specification includes the limitations

imposed by the characteristics of the analog

output buffer.

CMRR_OA

Common Mode Rejection Ratio

Power = Low

–

dB

Specification is applicable at high power. For

all other bias modes (except high power, high

opamp bias), minimum is 60 dB.

50

Power = Medium

Power = High

G_OLOA

Open Loop Gain

Power = Low

Specification is applicable at high power. For

all other bias modes (except high power, high

opamp bias), minimum is 60 dB.

60

80

Power = Medium

Power = High

V_OHIGHOA

V_OLOWOA

I_SOA

High Output Voltage Swing (internal signals)

Power = Low

Vdd - 0.2

–

V

Power = Medium

Power = High is 5V only

Low Output Voltage Swing (internal signals)

Power = Low

–

0.2

V

Power = Medium

Power = High

Supply Current (including associated AGND buffer)

Power = Low, Opamp Bias = Low

–

150

200

µA

Power = Low, Opamp Bias = High

300

400

Power = Medium, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = Low

600

800

1200

2400

4600

1600

3200

6400

Power = High, Opamp Bias = High

PSRR_OA

Supply Voltage Rejection Ratio

50

–

dB

0V ≤ V_IN≤ (Vdd - 2.25) or

(Vdd - 1.25V) ≤ V_IN≤ Vdd.

August 3, 2004

Document No. 38-12012 Rev. *I

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CY8C27x43 Final Data Sheet

3. Electrical Specifications

3.3.4

DC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-8. 5V DC Analog Output Buffer Specifications

Symbol

V_OSOB

Description

Min

Typ

Max

Units

mV

Notes

Input Offset Voltage (Absolute Value)

–

3

12

–

TCV_OSOB

V_CMOB

Average Input Offset Voltage Drift

Common-Mode Input Voltage Range

–

+6

–

µV/°C

0.5

Vdd - 1.0

V

R_OUTOB

Output Resistance

Power = Low

–

1

–

Ω

Power = High

V_OHIGHOB

High Output Voltage Swing (Load = 32 ohms to Vdd/2)

Power = Low

0.5 x Vdd + 1.3

–

V

Power = High

V_OLOWOB

Low Output Voltage Swing (Load = 32 ohms to Vdd/2)

Power = Low

Power = High

–

0.5 x Vdd - 1.3

V

I_SOB

Supply Current Including Bias Cell (No Load)

Power = Low

–

1.1

2.6

–

5.1

8.8

–

mA

dB

Power = High

–

PSRR_OB

Supply Voltage Rejection Ratio

60

Table 3-9. 3.3V DC Analog Output Buffer Specifications

Symbol

V_OSOB

Description

Min

Typ

Max

Units

Notes

Input Offset Voltage (Absolute Value)

–

3

12

mV

µV/°C

V

TCV_OSOB

V_CMOB

Average Input Offset Voltage Drift

Common-Mode Input Voltage Range

–

+6

-

–

0.5

Vdd - 1.0

R_OUTOB

Output Resistance

Power = Low

–

1

–

Ω

Power = High

V_OHIGHOB

High Output Voltage Swing (Load = 1k ohms to Vdd/2)

Power = Low

Power = High

0.5 x Vdd + 1.0

–

V

V_OLOWOB

Low Output Voltage Swing (Load = 1k ohms to Vdd/2)

Power = Low

Power = High

–

0.5 x Vdd - 1.0

V

I_SOB

Supply Current Including Bias Cell (No Load)

Power = Low

0.8

2.0

–

2.0

4.3

–

mA

dB

Power = High

–

PSRR_OB

Supply Voltage Rejection Ratio

60

August 3, 2004

Document No. 38-12012 Rev. *I

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CY8C27x43 Final Data Sheet

3. Electrical Specifications

3.3.5

DC Switch Mode Pump Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-10. DC Switch Mode Pump (SMP) Specifications

Symbol

Description

Min

4.75

Typ

5.0

Max

5.25

Units

Notes

Configuration of footnote ^a. Average, neglecting

ripple. SMP trip voltage is set to 5.0V.

V_PUMP5V

5V Output Voltage

3V Output Voltage

V

Configuration of footnote ^a. Average, neglecting

ripple. SMP trip voltage is set to 3.25V.

V_PUMP3V

I_PUMP

3.00

3.25

3.60

Configuration of footnote ^a

.

Available Output Current

V_BAT= 1.5V, V_PUMP= 3.25V

8

5

–

mA

SMP trip voltage is set to 3.25V.

SMP trip voltage is set to 5.0V.

V_BAT= 1.8V, V_PUMP= 5.0V

Configuration of footnote ^a. SMP trip voltage is

set to 5.0V.

V

_BAT5V

_BAT3V

Input Voltage Range from Battery

1.8

–

5.0

V

Configuration of footnote ^a. SMP trip voltage is

set to 3.25V.

V

Input Voltage Range from Battery

1.0

–

3.3

V

Configuration of footnote ^a

.

V_BATSTART

Minimum Input Voltage from Battery to Start Pump

Line Regulation (over V_BATrange)

1.1

–

5

–

V

Configuration of footnote ^a. V_Ois the “Vdd

∆V_{PUMP_Line}

%V_O

Value for PUMP Trip” specified by the VM[2:0]

setting in the DC POR and LVD Specification,

Table 3-16 on page 26.

Configuration of footnote ^a. V_Ois the “Vdd

∆V_{PUMP_Load}

Load Regulation

–

5

–

%V_O

Value for PUMP Trip” specified by the VM[2:0]

setting in the DC POR and LVD Specification,

Table 3-16 on page 26.

Configuration of footnote ^a. Load is 5mA.

∆V_{PUMP_Ripple}Output Voltage Ripple (depends on capacitor/load)

–

100

50

–

mVpp

%

Configuration of footnote ^a. Load is 5 mA. SMP

trip voltage is set to 3.25V.

E₃

Efficiency

35

F_PUMP

Switching Frequency

Switching Duty Cycle

–

1.3

50

–

MHz

%

DC_PUMP

a. L = 2 µH inductor, C = 10 µF capacitor, D = Schottky diode. See Figure 3-2.

1

D1

Vdd

V_PUMP

L₁

C1

SMP

Vss

+

V_BAT

TM

Battery

PSoC

Figure 3-2. Basic Switch Mode Pump Circuit

August 3, 2004

Document No. 38-12012 Rev. *I

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CY8C27x43 Final Data Sheet

3. Electrical Specifications

3.3.6

DC Analog Reference Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to

the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control

register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.

Reference control power is high.

Table 3-11. Silicon Revision A – 5V DC Analog Reference Specifications

Symbol

Description

Bandgap Voltage Reference

Min

Typ

Max

Units

BG

–

1.274

1.30

1.326

V

AGND = Vdd/2^a

Vdd/2 - 0.030

2 x BG - 0.043

P2[4] - 0.013

BG - 0.009

Vdd/2 - 0.004

2 x BG - 0.010

P2[4]

Vdd/2 + 0.003

2 x BG + 0.024

P2[4] + 0.014

BG + 0.009

AGND = 2 x BandGap^a

AGND = P2[4] (P2[4] = Vdd/2)^a

AGND = BandGap^a

–

V

BG

AGND = 1.6 x BandGap^a

1.6 x BG - 0.018

-0.034

1.6 x BG

0.000

1.6 x BG + 0.018

0.034

AGND Block to Block Variation (AGND = Vdd/2)^a

RefHi = Vdd/2 + BandGap

Vdd/2 + BG - 0.140

3 x BG - 0.112

Vdd/2 + BG - 0.018

3 x BG - 0.018

Vdd/2 + BG + 0.103

3 x BG + 0.076

–

RefHi = 3 x BandGap

V

RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)

RefHi = P2[4] + BandGap (P2[4] = Vdd/2)

RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)

RefHi = 3.2 x BandGap

2 x BG + P2[6] - 0.113

P2[4] + BG - 0.130

P2[4] + P2[6] - 0.133

3.2 x BG - 0.112

2 x BG + P2[6] - 0.018

P2[4] + BG - 0.016

P2[4] + P2[6] - 0.016

3.2 x BG

2 x BG + P2[6] + 0.077

P2[4] + BG + 0.098

P2[4] + P2[6] + 0.100

3.2 x BG + 0.076

RefLo = Vdd/2 – BandGap

Vdd/2 - BG - 0.051

BG - 0.082

Vdd/2 - BG + 0.024

BG + 0.023

Vdd/2 - BG + 0.098

BG + 0.129

–

RefLo = BandGap

V

RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)

RefLo = P2[4] – BandGap (P2[4] = Vdd/2)

RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)

2 x BG - P2[6] - 0.084

P2[4] - BG - 0.056

P2[4] - P2[6] - 0.057

2 x BG - P2[6] + 0.025

P2[4] - BG + 0.026

P2[4] - P2[6] + 0.026

2 x BG - P2[6] + 0.134

P2[4] - BG + 0.107

P2[4] - P2[6] + 0.110

a. AGND tolerance includes the offsets of the local buffer in the PSoC block.

Table 3-12. Silicon Revision B – 5V DC Analog Reference Specifications

Symbol

Description

Bandgap Voltage Reference

Min

Typ

1.30

Max

1.32

Units

BG

–

1.28

V

AGND = Vdd/2^a

Vdd/2 - 0.030

2 x BG - 0.043

P2[4] - 0.011

BG - 0.009

Vdd/2

Vdd/2 + 0.007

AGND = 2 x BandGap^a

AGND = P2[4] (P2[4] = Vdd/2)^a

AGND = BandGap^a

–

2 x BG

P2[4]

2 x BG + 0.024

P2[4] + 0.011

BG + 0.009

1.6 x BG + 0.018

0.034

V

BG

AGND = 1.6 x BandGap^a

1.6 x BG - 0.018

-0.034

1.6 x BG

0.000

AGND Block to Block Variation (AGND = Vdd/2)^a

RefHi = Vdd/2 + BandGap

Vdd/2 + BG - 0.1

3 x BG - 0.06

Vdd/2 + BG - 0.01

3 x BG - 0.01

Vdd/2 + BG + 0.1

3 x BG + 0.06

–

RefHi = 3 x BandGap

V

RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)

RefHi = P2[4] + BandGap (P2[4] = Vdd/2)

RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)

RefHi = 3.2 x BandGap

2 x BG + P2[6] - 0.06

P2[4] + BG - 0.06

P2[4] + P2[6] - 0.06

3.2 x BG - 0.06

2 x BG + P2[6] - 0.01

P2[4] + BG - 0.01

P2[4] + P2[6] - 0.01

3.2 x BG - 0.01

2 x BG + P2[6] + 0.06

P2[4] + BG + 0.06

P2[4] + P2[6] + 0.06

3.2 x BG + 0.06

RefLo = Vdd/2 – BandGap

Vdd/2 - BG - 0.051

BG - 0.06

Vdd/2 - BG + 0.01

BG + 0.01

Vdd/2 - BG + 0.06

BG + 0.06

–

RefLo = BandGap

V

RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)

RefLo = P2[4] – BandGap (P2[4] = Vdd/2)

RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)

2 x BG - P2[6] - 0.04

P2[4] - BG - 0.056

P2[4] - P2[6] - 0.056

2 x BG - P2[6] + 0.01

P2[4] - BG + 0.01

P2[4] - P2[6] + 0.01

2 x BG - P2[6] + 0.04

P2[4] - BG + 0.056

P2[4] - P2[6] + 0.056

a. AGND tolerance includes the offsets of the local buffer in the PSoC block.

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3. Electrical Specifications

Table 3-13. Silicon Revision A – 3.3V DC Analog Reference Specifications

Symbol

BG

Description

Bandgap Voltage Reference

Min

Typ

Max

Units

1.274

1.30

1.326

V

AGND = Vdd/2^a

–

Vdd/2 - 0.027

Vdd/2 - 0.003

Vdd/2 + 0.002

AGND = 2 x BandGap^a

Not Allowed

P2[4] - 0.008

BG - 0.009

–

AGND = P2[4] (P2[4] = Vdd/2)

P2[4] + 0.001

BG

P2[4] + 0.009

BG + 0.009

V

AGND = BandGap^a

AGND = 1.6 x BandGap^a

–

1.6 x BG - 0.018

-0.034

1.6 x BG

0.000

1.6 x BG + 0.018

0.034

V

AGND Block to Block Variation (AGND = Vdd/2)^a

RefHi = Vdd/2 + BandGap

mV

–

Not Allowed

RefHi = 3 x BandGap

Not Allowed

RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)

RefHi = P2[4] + BandGap (P2[4] = Vdd/2)

RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)

RefHi = 3.2 x BandGap

Not Allowed

P2[4] + P2[6] - 0.075

Not Allowed

P2[4] + P2[6] - 0.009

P2[4] + P2[6] + 0.057

V

RefLo = Vdd/2 - BandGap

Not Allowed

RefLo = BandGap

Not Allowed

RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)

RefLo = P2[4] – BandGap (P2[4] = Vdd/2)

RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)

Not Allowed

P2[4] - P2[6] - 0.048

P2[4] - P2[6] + 0.022

P2[4] - P2[6] + 0.092

V

a. AGND tolerance includes the offsets of the local buffer in the PSoC block.

Note See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.

Table 3-14. Silicon Revision B – 3.3V DC Analog Reference Specifications

Symbol

BG

Description

Bandgap Voltage Reference

Min

Typ

Max

Units

1.28

1.30

1.32

V

AGND = Vdd/2^a

–

Vdd/2 - 0.027

Not Allowed

Vdd/2

Vdd/2 + 0.005

AGND = 2 x BandGap^a

–

AGND = P2[4] (P2[4] = Vdd/2)

P2[4] - 0.008

BG - 0.009

P2[4]

BG

P2[4] + 0.009

BG + 0.009

V

AGND = BandGap^a

AGND = 1.6 x BandGap^a

–

1.6 x BG - 0.018

-0.034

1.6 x BG

0.000

1.6 x BG + 0.018

0.034

V

AGND Block to Block Variation (AGND = Vdd/2)^a

RefHi = Vdd/2 + BandGap

mV

–

Not Allowed

RefHi = 3 x BandGap

Not Allowed

RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)

RefHi = P2[4] + BandGap (P2[4] = Vdd/2)

RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)

RefHi = 3.2 x BandGap

Not Allowed

P2[4] + P2[6] - 0.06

Not Allowed

P2[4] + P2[6] - 0.01

P2[4] + P2[6] + 0.057

V

RefLo = Vdd/2 - BandGap

Not Allowed

RefLo = BandGap

Not Allowed

RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)

RefLo = P2[4] – BandGap (P2[4] = Vdd/2)

RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)

Not Allowed

P2[4] - P2[6] - 0.048

P2[4] - P2[6] + 0.01

P2[4] - P2[6] + 0.048

a. AGND tolerance includes the offsets of the local buffer in the PSoC block.

Note See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.

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3. Electrical Specifications

3.3.7

DC Analog PSoC Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-15. DC Analog PSoC Block Specifications

Symbol

R_CT

Description

Min

Typ

12.2

80

Max

Units

kΩ

fF

Notes

Resistor Unit Value (Continuous Time)

–

C_SC

Capacitor Unit Value (Switch Cap)

3.3.8

DC POR and LVD Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Mixed Signal Array Technical

Reference Manual for more information on the VLT_CR register.

Table 3-16. DC POR and LVD Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

Vdd Value for PPOR Trip (positive ramp)

PORLEV[1:0] = 00b

V_PPOR0R

V_PPOR1R

V_PPOR2R

2.91

V

PORLEV[1:0] = 01b

–

4.39

4.55

–

PORLEV[1:0] = 10b

Vdd Value for PPOR Trip (negative ramp)

PORLEV[1:0] = 00b

V_PPOR0

V_PPOR1

V_PPOR2

2.82

4.39

4.55

V

PORLEV[1:0] = 01b

PORLEV[1:0] = 10b

PPOR Hysteresis

PORLEV[1:0] = 00b

PORLEV[1:0] = 01b

PORLEV[1:0] = 10b

V_PH0

V_PH1

V_PH2

–

92

0

–

mV

0

Vdd Value for LVD Trip

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

V_LVD0

V_LVD1

V_LVD2

V_LVD3

V_LVD4

V_LVD5

V_LVD6

V_LVD7

V

2.86

2.96

3.07

3.92

4.39

4.55

4.63

4.72

2.92

3.02

3.13

4.00

4.48

4.64

4.73

4.81

2.98^a

3.08

3.20

4.08

4.57

V

4.74^b

4.82

4.91

Vdd Value for PUMP Trip

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

V_PUMP0

V_PUMP1

V_PUMP2

V_PUMP3

V_PUMP4

V_PUMP5

V_PUMP6

V_PUMP7

V

2.96

3.03

3.18

4.11

4.55

4.63

4.72

4.90

3.02

3.10

3.25

4.19

4.64

4.73

4.82

5.00

3.08

3.16

3.32

4.28

4.74

4.82

4.91

5.10

a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.

b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.

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3. Electrical Specifications

3.3.9

DC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-17. DC Programming Specifications

Symbol

I_DDP

Description

Min

Typ

Max

Units

mA

Notes

Supply Current During Programming or Verify

–

5

–

25

0.8

–

V_ILP

V_IHP

I_ILP

Input Low Voltage During Programming or Verify

Input High Voltage During Programming or Verify

–

V

2.2

–

V

Input Current when Applying Vilp to P1[0] or P1[1] During

Programming or Verify

0.2

mA

Driving internal pull-down resistor.

I_IHP

Input Current when Applying Vihp to P1[0] or P1[1] During

Programming or Verify

–

1.5

mA

V_OLV

V_OHV

Output Low Voltage During Programming or Verify

Output High Voltage During Programming or Verify

–

Vss + 0.75

Vdd

V

Vdd - 1.0

Flash_ENPB

Flash_ENT

Flash_DR

Flash Endurance (per block)

50,000

1,800,000

10

–

Erase/write cycles per block.

Erase/write cycles.

Flash Endurance (total)^a

Flash Data Retention

–

Years

a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of

25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than

50,000 cycles).

For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to

the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

August 3, 2004

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3. Electrical Specifications

3.4

AC Electrical Characteristics

3.4.1

AC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-18. AC Chip-Level Specifications

Symbol

F_IMO

Description

Min

23.4

Typ

Max

24.6^a

Units

MHz

Notes

Internal Main Oscillator Frequency

24

12

48

Trimmed. Utilizing factory trim values.

24.6^a,b

12.3^b,c

49.2^a,b,d

F_CPU1

F_CPU2

F_48M

CPU Frequency (5V Nominal)

CPU Frequency (3.3V Nominal)

Digital PSoC Block Frequency

0.93

0

MHz

Trimmed. Utilizing factory trim values.

Refer to the AC Digital Block Specifications

below.

24.6^{b, d}

64

F_24M

F_32K1

F_32K2

Digital PSoC Block Frequency

Internal Low Speed Oscillator Frequency

External Crystal Oscillator

0

24

32

MHz

kHz

15

–

32.768

–

Accuracy is capacitor and crystal dependent.

50% duty cycle.

F_PLL

PLL Frequency

–

23.986

–

MHz

Multiple (x732) of crystal frequency.

Jitter24M2

T_PLLSLEW

24 MHz Period Jitter (PLL)

PLL Lock Time

–

600

10

ps

0.5

ms

T_PLLSLEWS-PLL Lock Time for Low Gain Setting

LOW

0.5

–

50

ms

T_OS

External Crystal Oscillator Startup to 1%

–

1700

2800

ms

2620

3800

T_OSACC

External Crystal Oscillator Startup to 100 ppm

The crystal oscillator frequency is within 100 ppm of its

final value by the end of the T_osaccperiod. Correct

operation assumes a properly loaded 1 uW maximum

drive level 32.768 kHz crystal. 3.0V ≤ Vdd ≤ 5.5V, -40

^oC ≤ T_A≤ 85 ^oC.

Jitter32k

T_XRST

32 kHz Period Jitter

–

100

–

ns

External Reset Pulse Width

10

–

µs

DC24M

24 MHz Duty Cycle

40

–

50

60

–

%

Step24M

Fout48M

24 MHz Trim Step Size

48 MHz Output Frequency

50

kHz

MHz

49.2^a,c

46.8

48.0

Trimmed. Utilizing factory trim values.

Jitter24M1

F_MAX

24 MHz Period Jitter (IMO)

–

600

–

ps

Maximum frequency of signal on row input or row output.

12.3

–

MHz

T_RAMP

Supply Ramp Time

0

–

µs

a. 4.75V < Vdd < 5.25V.

b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.

c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.

d. See the individual user module data sheets for information on maximum frequencies for user modules.

PLL

Enable

T

24 MHz

PLLSLEW

F_PLL

PLL

Gain

0

Figure 3-3. PLL Lock Timing Diagram

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3. Electrical Specifications

PLL

Enable

T

24 MHz

PLLSLEWLOW

F_PLL

PLL

Gain

1

Figure 3-4. PLL Lock for Low Gain Setting Timing Diagram

32K

Select

32 kHz

T

OS

F_32K2

Figure 3-5. External Crystal Oscillator Startup Timing Diagram

Jitter24M1

F_24M

Figure 3-6. 24 MHz Period Jitter (IMO) Timing Diagram

Jitter32k

F_32K2

Figure 3-7. 32 kHz Period Jitter (ECO) Timing Diagram

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3. Electrical Specifications

3.4.2

AC General Purpose IO Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-19. AC GPIO Specifications

Symbol

F_GPIO

Description

GPIO Operating Frequency

Min

Typ

Max

Units

MHz

Notes

0

–

12

TRiseF

TFallF

TRiseS

TFallS

Rise Time, Normal Strong Mode, Cload = 50 pF

Fall Time, Normal Strong Mode, Cload = 50 pF

Rise Time, Slow Strong Mode, Cload = 50 pF

Fall Time, Slow Strong Mode, Cload = 50 pF

3

–

18

–

ns

Vdd = 4.5 to 5.25V, 10% - 90%

Vdd = 3 to 5.25V, 10% - 90%

2

–

10

27

22

–

90%

GPIO

Output

Voltage

10%

TRiseF

TRiseS

TFallF

TFallS

Figure 3-8. GPIO Timing Diagram

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3. Electrical Specifications

3.4.3

AC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.

Power = High and Opamp Bias = High is not supported at 3.3V.

Table 3-20. 5V AC Operational Amplifier Specifications

Symbol

T_ROA

Description

Min

Typ

Max

Units

Notes

Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF

load, Unity Gain)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

–

3.9

µs

0.72

0.62

µs

T_SOA

Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF

load, Unity Gain)

Power = Low, Opamp Bias = Low

–

5.9

µs

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

0.92

0.72

SR_ROA

SR_FOA

BW_OA

E_NOA

Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)

Power = Low, Opamp Bias = Low

0.15

1.7

–

V/µs

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

6.5

Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)

Power = Low, Opamp Bias = Low

0.01

0.5

–

V/µs

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

4.0

Gain Bandwidth Product

Power = Low, Opamp Bias = Low

0.75

3.1

5.4

–

MHz

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

MHz

Noise at 1 kHz (Power = Medium, Opamp Bias = High)

100

nV/rt-Hz

Table 3-21. 3.3V AC Operational Amplifier Specifications

Symbol

T_ROA

Description

Min

Typ

Max

Units

Notes

Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF

load, Unity Gain)

Power = Low, Opamp Bias = Low

Power = Low, Opamp Bias = High

–

3.92

0.72

µs

T_SOA

Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF

load, Unity Gain)

Power = Low, Opamp Bias = Low

–

5.41

0.72

µs

Power = Medium, Opamp Bias = High

Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)

Power = Low, Opamp Bias = Low

SR_ROA

SR_FOA

BW_OA

E_NOA

0.31

2.7

–

V/µs

Power = Medium, Opamp Bias = High

Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)

Power = Low, Opamp Bias = Low

0.24

1.8

–

V/µs

Power = Medium, Opamp Bias = High

Gain Bandwidth Product

Power = Low, Opamp Bias = Low

0.67

2.8

–

MHz

Power = Medium, Opamp Bias = High

Noise at 1 kHz (Power = Medium, Opamp Bias = High)

–

MHz

100

nV/rt-Hz

August 3, 2004

Document No. 38-12012 Rev. *I

31

CY8C27x43 Final Data Sheet

3. Electrical Specifications

3.4.4

AC Digital Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-22. AC Digital Block Specifications

Function

Description

Maximum Block Clocking Frequency (> 4.75V)

Maximum Block Clocking Frequency (< 4.75V)

Capture Pulse Width

Min

Typ

Max

49.2

Units

Notes

4.75V < Vdd < 5.25V.

All

Functions

Timer

24.6

–

3.0V < Vdd < 4.75V.

50^a

–

ns

Maximum Frequency, No Capture

Maximum Frequency, With Capture

Enable Pulse Width

–

49.2

24.6

–

MHz

ns

4.75V < Vdd < 5.25V.

50^a

–

Counter

Maximum Frequency, No Enable Input

Maximum Frequency, Enable Input

–

49.2

24.6

MHz

4.75V < Vdd < 5.25V.

–

Dead Band Kill Pulse Width:

Asynchronous Restart Mode

20

–

ns

50^a

Synchronous Restart Mode

Disable Mode

50^a

–

ns

Maximum Frequency

–

49.2

MHz

4.75V < Vdd < 5.25V.

CRCPRS

Maximum Input Clock Frequency

–

(PRS Mode)

CRCPRS

(CRC Mode)

Maximum Input Clock Frequency

–

24.6

8.2

MHz

SPIM

SPIS

Maximum data rate at 4.1 MHz due to 2 x over

clocking.

Maximum Input Clock Frequency

–

4.1

–

ns

50^a

Width of SS_ Negated Between Transmissions

Maximum Input Clock Frequency ^b

Silicon A

Transmitter

–

16.4

24.6

MHz

Maximum data rate at 2.05 MHz due to 8 x over

clocking.

Maximum data rate at 3.08 MHz due to 8 x over

clocking.

Silicon B

Maximum Input Clock Frequency ^b

Silicon A

Receiver

–

16.4

24.6

MHz

Maximum data rate at 2.05 MHz due to 8 x over

clocking.

Maximum data rate at 3.08 MHz due to 8 x over

clocking.

Silicon B

a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

b. Refer to the Ordering Information chapter on page 42.

August 3, 2004

Document No. 38-12012 Rev. *I

32

CY8C27x43 Final Data Sheet

3. Electrical Specifications

3.4.5

AC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-23. 5V AC Analog Output Buffer Specifications

Symbol

Description

Rising Settling Time to 0.1%, 1V Step, 100pF Load

Power = Low

Min

Typ

Max

Units

Notes

T_ROB

–

2.5

µs

Power = High

2.5

µs

T_SOB

Falling Settling Time to 0.1%, 1V Step, 100pF Load

Power = Low

–

2.2

µs

Power = High

SR_ROB

SR_FOB

BW_OB

Rising Slew Rate (20% to 80%), 1V Step, 100pF Load

Power = Low

0.65

–

V/µs

Power = High

Falling Slew Rate (80% to 20%), 1V Step, 100pF Load

Power = Low

0.65

–

V/µs

Power = High

Small Signal Bandwidth, 20mV_pp, 3dB BW, 100pF Load

0.8

–

MHz

Power = Low

Power = High

BW_OB

Large Signal Bandwidth, 1V_pp, 3dB BW, 100pF Load

300

–

kHz

Power = Low

Power = High

Table 3-24. 3.3V AC Analog Output Buffer Specifications

Symbol

Description

Rising Settling Time to 0.1%, 1V Step, 100pF Load

Power = Low

Min

Typ

Max

Units

Notes

T_ROB

–

3.8

µs

Power = High

T_SOB

Falling Settling Time to 0.1%, 1V Step, 100pF Load

Power = Low

–

2.6

µs

Power = High

SR_ROB

SR_FOB

BW_OB

Rising Slew Rate (20% to 80%), 1V Step, 100pF Load

Power = Low

0.5

–

V/µs

Power = High

Falling Slew Rate (80% to 20%), 1V Step, 100pF Load

Power = Low

0.5

–

V/µs

Power = High

Small Signal Bandwidth, 20mV_pp, 3dB BW, 100pF Load

0.7

–

MHz

Power = Low

Power = High

BW_OB

Large Signal Bandwidth, 1V_pp, 3dB BW, 100pF Load

200

–

kHz

Power = Low

Power = High

August 3, 2004

Document No. 38-12012 Rev. *I

33

CY8C27x43 Final Data Sheet

3. Electrical Specifications

3.4.6

AC External Clock Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-25. 5V AC External Clock Specifications

Symbol

Description

Min

0.093

Typ

Max

24.6

Units

MHz

Notes

F_OSCEXT

Frequency

–

High Period

Low Period

20.6

150

–

5300

ns

µs

–

Power Up IMO to Switch

Table 3-26. 3.3V AC External Clock Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

Frequency with CPU Clock divide by 1^a

F_OSCEXT

0.093

0.186

–

12.3

24.6

MHz

Frequency with CPU Clock divide by 2 or greater^b

High Period with CPU Clock divide by 1

Low Period with CPU Clock divide by 1

Power Up IMO to Switch

F_OSCEXT

–

41.7

150

–

5300

ns

µs

–

a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.

b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty per-

cent duty cycle requirement is met.

3.4.7

AC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-27. AC Programming Specifications

Symbol

Description

Min

Typ

Max

Units

ns

Notes

T_RSCLK

Rise Time of SCLK

Fall Time of SCLK

1

–

20

–

T_FSCLK

T_SSCLK

T_HSCLK

F_SCLK

1

–

ns

Data Set up Time to Falling Edge of SCLK

Data Hold Time from Falling Edge of SCLK

Frequency of SCLK

40

0

–

ns

–

ns

–

8

MHz

ms

ns

T_ERASEBFlash Erase Time (Block)

–

10

–

T_WRITE

T_DSCLK

Flash Block Write Time

–

Data Out Delay from Falling Edge of SCLK

–

45

50

Vdd > 3.6

T_DSCLK3Data Out Delay from Falling Edge of SCLK

–

ns

3.0 ≤ Vdd ≤ 3.6

August 3, 2004

Document No. 38-12012 Rev. *I

34

CY8C27x43 Final Data Sheet

3. Electrical Specifications

2

3.4.8

AC I C Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 3-28. AC Characteristics of the I²C SDA and SCL Pins

Standard Mode

Min Max

100

Fast Mode

Min Max

Symbol

Description

Units

kHz

Notes

F_SCLI2C

SCL Clock Frequency

0

400

–

T_HDSTAI2CHold Time (repeated) START Condition. After this period, the 4.0

first clock pulse is generated.

–

0.6

µs

T_LOWI2C

T_HIGHI2C

LOW Period of the SCL Clock

HIGH Period of the SCL Clock

4.7

4.0

4.7

0

–

1.3

0.6

0

–

µs

ns

µs

ns

–

T_SUSTAI2CSet-up Time for a Repeated START Condition

T_HDDATI2CData Hold Time

–

100^a

0.6

T_SUDATI2CData Set-up Time

250

4.0

4.7

–

T_SUSTOI2CSet-up Time for STOP Condition

–

T_BUFI2C

T_SPI2C

Bus Free Time Between a STOP and START Condition

Pulse Width of spikes are suppressed by the input filter.

1.3

0

–

50

a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t

≥ 250 ns must then be met. This will automatically be the case if

SU;DAT

the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line

t

+ t

= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

rmax SU;DAT

SDA

T_SPI2C

T_LOWI2C

T_SUDATI2C

T_HDSTAI2C

T_BUFI2C

SCL

T_SUSTOI2C

T_SUSTAI2C

T_HDDATI2C

T_HDSTAI2C

T_HIGHI2C

S

Sr

P

S

Figure 3-9. Definition for Timing for Fast/Standard Mode on the I²C Bus

August 3, 2004

Document No. 38-12012 Rev. *I

35

4. Packaging Information

This chapter illustrates the packaging specifications for the CY8C27x43 PSoC device, along with the thermal impedances for each

package and the typical package capacitance on crystal pins.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of

the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at

http://www.cypress.com/support/link.cfm?mr=poddim.

4.1

Packaging Dimensions

51-85075 - *A

Figure 4-1. 8-Lead (300-Mil) PDIP

August 3, 2004

36

CY8C27x43 Final Data Sheet

4. Packaging Information

51-85077 - *C

Figure 4-2. 20-Lead (210-Mil) SSOP

51-85024 - *B

Figure 4-3. 20-Lead (300-Mil) Molded SOIC

Document No. 38-12012 Rev. *I

August 3, 2004

37

CY8C27x43 Final Data Sheet

4. Packaging Information

51-85014 - *D

Figure 4-4. 28-Lead (300-Mil) Molded DIP

51-85079 - *C

Figure 4-5. 28-Lead (210-Mil) SSOP

Document No. 38-12012 Rev. *I

August 3, 2004

38

CY8C27x43 Final Data Sheet

4. Packaging Information

51-85026 - *C

Figure 4-6. 28-Lead (300-Mil) Molded SOIC

51-85064-B

51-85064 - *B

Figure 4-7. 44-Lead TQFP

August 3, 2004

Document No. 38-12012 Rev. *I

39

CY8C27x43 Final Data Sheet

4. Packaging Information

51-85061 - *C

51-85061-C

Figure 4-8. 48-Lead (300-Mil) SSOP

0.08

C

6.90

7.10

1.00 MAX.

0.0ꢀ MAX.

0.20 REF.

X

0.80 MAX.

6.70

6.80

0.23 0.0ꢀ

PIN1 ID

0.20 R.

N

1

2

0.4ꢀ

0.80 DIA.

6.90

7.10

E-PAD

6.70

6.80

ꢀ.4ꢀ

ꢀ.ꢀꢀ

Y

0.30-0.4ꢀ

0.42 0.18

(4X)

0°-12°

0.ꢀ0

ꢀ.4ꢀ

ꢀ.ꢀꢀ

C

SEATING

PLANE

TOP VIEW

SIDE VIEW

BOTTOM VIEW

E-PAD SIZE PADDLE SIZE

(X, Y MAX.)

51-85152 - *B

DIMENSIONS IN mm MIN.

MAX.

ꢀ 1 X ꢀ 1

ꢀ 3 X ꢀ 3

Figure 4-9. 48-Lead (7x7 mm) MLF

August 3, 2004

Document No. 38-12012 Rev. *I

40

CY8C27x43 Final Data Sheet

4. Packaging Information

4.2

Thermal Impedances

Table 4-1. Thermal Impedances per Package

Package

8 PDIP

Typical θ_JA

*

120 ^oC/W

95 ^oC/W

79 ^oC/W

67 ^oC/W

95 ^oC/W

71 ^oC/W

58 ^oC/W

69 ^oC/W

18 ^oC/W

20 SSOP

20 SOIC

28 PDIP

28 SSOP

28 SOIC

44 TQFP

48 SSOP

48 MLF

* T_J= T_A+ POWER x θ_JA

4.3

Capacitance on Crystal Pins

Table 4-2: Typical Package Capacitance on Crystal Pins

Package

8 PDIP

Package Capacitance

2.8 pF

20 SSOP

20 SOIC

28 PDIP

28 SSOP

28 SOIC

44 TQFP

48 SSOP

48 MLF

2.6 pF

2.5 pF

3.5 pF

2.8 pF

2.7 pF

2.6 pF

3.3 pF

2.3 pF

August 3, 2004

Document No. 38-12012 Rev. *I

41

5. Ordering Information

The following table lists the CY8C27x43 PSoC device family’s key package features and ordering codes.

Table 5-1. CY8C27x43 PSoC Device Family Key Features and Ordering Information

Ordering

Package

Code

CY8C27x43 Silicon B – These parts are lead free and offer the following improvements. The DEC_CR1 register selections are enhanced to allow

any digital block to be the decimator clock source, the ECO EX and ECO EXW bits in the CPU_SCR1 register are readable, and the accuracy of

the analog reference is enhanced (see the Electrical Specifications chapter). All silicon A errata are fixed in silicon B.

8 Pin (300 Mil) DIP

CY8C27143-24PXI

CY8C27243-24PVXI

16

256

No

-40C to +85C

8

12

6

4

8

4

No

20 Pin (210 Mil) SSOP

Yes

16

Yes

20 Pin (210 Mil) SSOP

(Tape and Reel)

CY8C27243-24PVXIT

CY8C27243-24SXI

CY8C27243-24SXIT

16

256

Yes

-40C to +85C

8

12

16

8

4

Yes

20 Pin (300 Mil) SOIC

20 Pin 300 Mil) SOIC

(Tape and Reel)

28 Pin (300 Mil) DIP

CY8C27443-24PXI

CY8C27443-24PVXI

16

256

Yes

-40C to +85C

8

12

24

12

4

Yes

28 Pin (210 Mil) SSOP

(Tape and Reel)

CY8C27443-24PVXIT

CY8C27443-24SXI

CY8C27443-24SXIT

CY8C27543-24AXI

CY8C27543-24AXIT

CY8C27643-24PVXI

CY8C27643-24PVXIT

CY8C27643-24LFXI

CY8C27643-24LFXIT

16

256

Yes

-40C to +85C

8

12

24

40

44

12

4

Yes

28 Pin (300 Mil) SOIC

(Tape and Reel)

44 Pin TQFP

(Tape and Reel)

48 Pin (300 Mil) SSOP

(Tape and Reel)

48 Pin (7x7) MLF

(Tape and Reel)

CY8C27x43 Silicon A – Silicon A is not recommended for new designs.

8 Pin (300 Mil) DIP

CY8C27143-24PI

CY8C27243-24PVI

16

256

No

-40C to +85C

8

12

6

4

8

4

No

20 Pin (210 Mil) SSOP

Yes

16

Yes

20 Pin (210 Mil) SSOP

(Tape and Reel)

CY8C27243-24PVIT

CY8C27243-24SI

CY8C27243-24SIT

16

256

Yes

-40C to +85C

8

12

16

8

4

Yes

20 Pin (300 Mil) SOIC

20 Pin 300 Mil) SOIC

(Tape and Reel)

28 Pin (300 Mil) DIP

CY8C27443-24PI

CY8C27443-24PVI

16

256

Yes

-40C to +85C

8

12

24

12

4

Yes

28 Pin (210 Mil) SSOP

August 3, 2004

Document No. 38-12012 Rev. *I

42

CY8C27x43 Final Data Sheet

5. Ordering Information

Table 5-1. CY8C27x43 PSoC Device Family Key Features and Ordering Information (continued)

Ordering

Package

Code

28 Pin (210 Mil) SSOP

(Tape and Reel)

CY8C27443-24PVIT

CY8C27443-24SI

CY8C27443-24SIT

CY8C27543-24AI

CY8C27543-24AIT

CY8C27643-24PVI

CY8C27643-24PVIT

CY8C27643-24LFI

CY8C27643-24LFIT

16

256

Yes

-40C to +85C

8

12

24

40

44

12

4

Yes

28 Pin (300 Mil) SOIC

(Tape and Reel)

44 Pin TQFP

(Tape and Reel)

48 Pin (300 Mil) SSOP

(Tape and Reel)

48 Pin (7x7) MLF

(Tape and Reel)

5.1

Ordering Code Definitions

CY 8 C 27 xxx-SPxx

Package Type:

P = PDIP

S = SOIC

PV = SSOP

LF = MLF

A = TQFP

Thermal Rating:

C = Commercial

I = Industrial

PX = PDIP Pb Free

SX = SOIC Pb Free

PVX = SSOP Pb Free

LFX = MLF Pb Free

AX = TQFP Pb Free

E = Extended

Speed: 24 MHz

Part Number

Family Code

Technology Code: C = CMOS

Marketing Code: 8 = Cypress MicroSystems

Company ID: CY = Cypress

August 3, 2004

Document No. 38-12012 Rev. *I

43

6. Sales and Service Information

To obtain information about Cypress MicroSystems or PSoC sales and technical support, reference the following information or go to

the section titled “Getting Started” on page 4 in this document.

Cypress MicroSystems

2700 162nd Street SW

Building D

Lynnwood, WA 98037

Phone:

Facsimile:

800.669.0557

425.787.4641

Web Sites:

Company Information – http://www.cypress.com

Sales – http://www.cypress.com/aboutus/sales_locations.cfm

Technical Support – http://www.cypress.com/support/login.cfm

6.1

Revision History

Table 6-1. CY8C27x43 Data Sheet Revision History

Document Title:

CY8C27143, CY8C27243, CY8C27443, CY8C27543, and CY8C27643 PSoC Mixed Signal Array Final Data Sheet

38-12012

Issue Date

Document Number:

Revision

ECN #

Origin of Change

Description of Change

**

127087

128780

7/01/2003

7/29/2003

New Silicon.

New document (Revision **).

*A

Engineering and

NWJ.

New electrical spec additions, fix of Core Architecture links, corrections to some text, tables, draw-

ings, and format.

*B

*C

*D

*E

*F

*G

128992

129283

129442

130129

130651

131298

8/14/2003

8/28/2003

9/09/2003

NWJ

Interrupt controller table fixed, refinements to Electrical Spec section and Register chapter.

Significant changes to the Electrical Specifications section.

Changes made to Electrical Spec section. Added 20/28-Lead SOIC packages and pinouts.

Revised document for Silicon Revision A.

10/13/2003 NWJ

10/28/2003 NWJ

Refinements to Electrical Specification section and I2C chapter.

11/18/2003

See ECN

NWJ

Revisions to GDI, RDI, and Digital Block chapters. Revisions to AC Digital Block Spec and miscella-

neous register changes.

*H

*I

229416

247529

SFV

New data sheet format and organization. Reference the PSoC Mixed Signal Array Technical Refer-

ence Manual for additional information. Title change.

SFV

Added Silicon B information to this data sheet.

Distribution: External Public

Posting: None

6.2

Copyrights and Code Protection

Copyrights

tems, Inc. All other trademarks or registered trademarks referenced herein are property of the respective corporations.

The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for the use of any circuitry other than circuitry

embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSystems does not authorize its products

for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of

Cypress MicroSystems products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress

MicroSystems against all charges. Cypress MicroSystems products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety

applications, unless pursuant to an express written agreement with Cypress MicroSystems.

Flash Code Protection

Note the following details of the Flash code protection features on Cypress MicroSystems devices.

Cypress MicroSystems products meet the specifications contained in their particular Cypress MicroSystems Data Sheets. Cypress MicroSystems believes that its family of

products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress MicroSystems,

that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress MicroSystems nor any

other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."

Cypress MicroSystems is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress Micro-

Systems are committed to continuously improving the code protection features of our products.

August 3, 2004

44


型号：	CY8C27443-24PVI
厂家：	CYPRESS
描述：	PSoC Mixed Signal Array PSoC混合信号阵列
文件：	总44页 (文件大小：543K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C27443-24PVI [CYPRESS]

相关型号：

CY8C27443-24PVIT

CY8C27443-24PVXI

CY8C27443-24PVXIT

CY8C27443-24PXI

CY8C27443-24SI

CY8C27443-24SIT

CY8C27443-24SXI

CY8C27443-24SXIT

CY8C27466

CY8C27466-24PVXI

CY8C27466-24PVXIT

CY8C27466-24PXI