CY8C4146LQS-S263_技术文档

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Programmable System-on-Chip (PSoC)

General Description

PSoC^®4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an

Arm^®Cortex™-M0+ CPU while being AEC-Q100 compliant. It combines programmable and reconfigurable analog and digital blocks

with flexible automatic routing. PSoC 4100S Plus is a member of the PSoC 4 platform architecture. It is a combination of a microcon-

troller with standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class perfor-

mance, programmable general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity.

PSoC 4100S Plus products will be upward compatible with members of the PSoC 4 platform for new applications and design needs.

■ Timing and Pulse-Width Modulation

❐ Eight 16-bit timer/counter/pulse-width modulator (TCPWM)

blocks

Features

■ Automotive Electronics Council (AEC) AEC-Q100 Qualified

❐ Center-aligned, Edge, and Pseudo-random modes

❐ Comparator-based triggering of Kill signals for motor drive

and other high-reliability digital logic applications

■ 32-bit MCU Subsystem

❐ 48-MHz Arm Cortex-M0+ CPU

❐ Up to 128 KB of flash with Read Accelerator

❐ Up to 16 KB of SRAM

❐ Quadrature decoder

■ Clock Sources

❐ 8-channel DMA engine

❐ 4 to 33 MHz external crystal oscillator (ECO)

❐ PLL to generate 48-MHz frequency

❐ 32-kHz Watch Crystal Oscillator (WCO)

❐ ±2% Internal Main Oscillator (IMO)

❐ 32-kHz Internal Low-power Oscillator (ILO)

■ Programmable Analog

❐ Two opamps with reconfigurable high-drive external and

high-bandwidth internal drive and Comparator modes and

ADC input buffering capability. Opamps can operate in Deep

Sleep low-power mode.

❐ 12-bit 1-Msps SAR ADC with differential and single-ended

modes, and Channel Sequencer with signal averaging

■ True Random Number Generator (TRNG)

❐ TRNG generates truly random number for secure key gen-

eration for Cryptography applications

❐ Single-slope 10-bit ADC function provided by a capacitance

sensing block

❐ Two current DACs (IDACs) for general-purpose or capacitive

■ CAN Block

sensing applications on any pin

❐ CAN 2.0B block with support for Time-Triggered CAN

(TTCAN)

❐ Two low-power comparators that operate in Deep Sleep

low-power mode

■ Temperature Range

■ Programmable Digital

❐ Programmable logic blocks allowing Boolean operations to

be performed on port inputs and outputs

❐ Grade-A: –40 °C to +85 °C

❐ Grade-S: –40 °C to +105 °C

❐ Grade-E: –40 °C to +125 °C^[1]

■ Low-Power 1.71 V to 5.5 V Operation

❐ Deep Sleep mode with operational analog and 2.5 A digital

system current

■ Up to 54 Programmable GPIO Pins

❐ 40-pin QFN and 64-pin TQFP packages^[2]

❐ Any GPIO pin can be CapSense, analog, or digital

❐ Drive modes, strengths, and slew rates are programmable

■ Capacitive Sensing

❐ Cypress CapSense Sigma-Delta (CSD) provides

best-in-class signal-to-noise ratio (SNR) (> 5:1) and water

tolerance

❐ Cypress-supplied software component makes capacitive

sensing design easy

■ PSoC Creator Design Environment

❐ Integrated Development Environment (IDE) provides schematic

design entry and build (with analog and digital automatic routing)

❐ Applications Programming Interface (API) component for all

fixed-function and programmable peripherals

❐ Automatic hardware tuning (SmartSense™)

■ Industry-Standard Tool Compatibility

■ LCD Drive Capability

❐ After schematic entry, development can be done with

Arm-based industry-standard development tools

❐ LCD segment drive capability on GPIOs

■ Serial Communication

❐ Five independent run-time reconfigurable Serial Communi-

cation Blocks (SCBs) with re-configurable I²C, SPI, UART

functionality, or LIN Slave functionality

Notes

1. Grade-E specifications (at +125 °C) are preliminary. Contact Cypress for the availability of Grade-E devices.

2. 40-pin QFN package specifications are preliminary. Contact Cypress for the availability of 40-pin QFN package devices.

Cypress Semiconductor Corporation

Document Number: 002-20072 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 4, 2019

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

More Information

Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you

to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article

KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 4:

■ Overview: PSoC Portfolio, PSoC Roadmap

The MiniProg3 device provides an interface for flash

programming and debug.

■ Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP

In addition, PSoC Creator includes a device selection tool.

■ Software User Guide:

❐ A step-by-step guide for using PSoC Creator. The software

user guide shows you how the PSoC Creator build process

works in detail, how to use source control with PSoC Creator,

and much more.

■ Application notes: Cypress offers a large number of PSoC

application notes covering a broad range of topics, from basic

to advanced level. Recommended application notes for getting

started with PSoC 4 are:

❐ AN79953: Getting Started With PSoC 4

❐ AN88619: PSoC 4 Hardware Design Considerations

❐ AN86439: Using PSoC 4 GPIO Pins

■ Component Datasheets:

❐ The flexibility of PSoC allows the creation of new peripherals

(components) long after the device has gone into production.

Component datasheets provide all the information needed to

select and use a particular component, including a functional

description, API documentation, example code, and AC/DC

specifications.

❐ AN57821: Mixed Signal Circuit Board Layout

❐ AN81623: Digital Design Best Practices

❐ AN73854: Introduction To Bootloaders

❐ AN89610: ARM Cortex Code Optimization

■ Online:

❐ AN85951: PSoC^®4 and PSoC Analog Coprocessor

❐ In addition to print documentation, the Cypress PSoC forums

connect you with fellow PSoC users and experts in PSoC

from around the world, 24 hours a day, 7 days a week.

CapSense^®Design Guide

■ Technical Reference Manual (TRM) is in two documents:

❐ Architecture TRM details each PSoC 4 functional block.

❐ Registers TRM describes each of the PSoC 4 registers.

■ Development Kits:

❐ CY8CKIT-041-41XX PSoC 4100S CapSense Pioneer Kit, is

an easy-to-use and inexpensive development platform. This

kit includes connectors for Arduino™ compatible shields.

❐ CY8CKIT-149 PSoC® 4100S Plus Prototyping Kit enables

you to evaluate and develop with Cypress' fourth-generation,

low-power CapSense solution using the PSoC 4100S Plus

devices.

Document Number: 002-20072 Rev. *I

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Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

PSoC Creator

PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design

of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100

pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:

1. Drag and drop component icons to build your hardware

system design in the main design workspace

3. Configure components using the configuration tools

4. Explore the library of 100+ components

5. Review component datasheets

2. Codesign your application firmware with the PSoC hardware,

using the PSoC Creator IDE C compiler

Figure 1. Multiple-Sensor Example Project in PSoC Creator

1

2

3

4

5

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Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Contents

Block Diagram ..................................................................5

Functional Description .....................................................5

Functional Definition ........................................................6

CPU and Memory Subsystem .....................................6

System Resources ......................................................6

Analog Blocks ..............................................................7

Programmable Digital Blocks ......................................7

Fixed Function Digital Blocks ......................................8

GPIO ...........................................................................8

Special Function Peripherals....................................... 9

Pinouts ............................................................................10

Alternate Pin Functions .............................................12

Power ...............................................................................14

Mode 1: 1.8 V to 5.5 V External Supply ....................14

Mode 2: 1.8 V ±5% External Supply ..........................14

Electrical Specifications ................................................15

Absolute Maximum Ratings .......................................15

Device Level Specifications .......................................16

Analog Peripherals ....................................................19

Digital Peripherals .....................................................27

Memory .....................................................................29

System Resources ....................................................30

Ordering Information ......................................................33

Packaging ........................................................................38

Package Diagram ......................................................39

Acronyms ........................................................................41

Document Conventions .................................................43

Units of Measure .......................................................43

Document History Page .................................................44

Sales, Solutions, and Legal Information ......................45

Worldwide Sales and Design Support .......................45

Products ....................................................................45

PSoC® Solutions ......................................................45

Cypress Developer Community .................................45

Technical Support .....................................................45

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Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Block Diagram

Figure 2. Block Diagram

CPU Subsystem

PSoC 4100S

SWD/TC, MTB

Cortex

M0+

SPCIF

Plus

DataWire/

DMA

FLASH

128 KB

SRAM

16 KB

ROM

8 KB

32-bit

48 MHz

FAST MUL

Initiator/MMIO

AHB-Lite

Read Accelerator

SRAM Controller

ROM Controller

NVIC, IRQMUX, MPU

System Resources

Lite

System Interconnect (Single Layer AHB)

Peripheral Interconnect (MMIO)

Power

Sleep Control

WIC

Peripherals

PCLK

POR

REF

PWRSYS

Clock

Clock Control

WDT

Programmable

Analog

ILO

IMO

SAR ADC

(12-bit)

Reset

Reset Control

XRES

Test

TestMode Entry

Digital DFT

Analog DFT

x1

CTBm

2x OpAmp

SARMUX

High Speed I/O Matrix & Smart I/O

Power Modes

Active/Sleep

DeepSleep

Up to 54x GPIOs

I/O Subsystem

■ Robust flash protection

Functional Description

■ Allows customer-proprietary functionality to be implemented in

on-chip programmable blocks

PSoC 4100S Plus devices include extensive support for

programming, testing, debugging, and tracing both hardware

and firmware.

The debug circuits are enabled by default and can be disabled

in firmware. If they are not enabled, the only way to re-enable

them is to erase the entire device, clear flash protection, and

reprogram the device with new firmware that enables debugging.

Thus firmware control of debugging cannot be over-ridden

without erasing the firmware thus providing security.

The Arm Serial-Wire Debug (SWD) interface supports all

programming and debug features of the device.

Complete debug-on-chip functionality enables full-device

debugging in the final system using the standard production

device. It does not require special interfaces, debugging pods,

simulators, or emulators. Only the standard programming

connections are required to fully support debug.

Additionally, all device interfaces can be permanently disabled

(device security) for applications concerned about phishing

attacks due to a maliciously reprogrammed device or attempts to

defeat security by starting and interrupting flash programming

sequences. All programming, debug, and test interfaces are

disabled when maximum device security is enabled. Therefore,

PSoC 4100S Plus, with device security enabled, may not be

returned for failure analysis. This is a trade-off the PSoC 4100S

Plus allows the customer to make.

The PSoC Creator IDE provides fully integrated programming

and debug support for the PSoC 4100S Plus devices. The SWD

interface is fully compatible with industry-standard third-party

tools. PSoC 4100S Plus provides a level of security not possible

with multi-chip application solutions or with microcontrollers. It

has the following advantages:

■ Allows disabling of debug features

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Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

off; wake-up from this mode takes 35 µs. The opamps can

remain operational in Deep Sleep mode.

Functional Definition

CPU and Memory Subsystem

CPU

Clock System

The PSoC 4100S Plus clock system is responsible for providing

clocks to all subsystems that require clocks and for switching

between different clock sources without glitching. In addition, the

clock system ensures that there are no metastable conditions.

The Cortex-M0+ CPU in the PSoC 4100S Plus is part of the

32-bit MCU subsystem, which is optimized for low-power

operation with extensive clock gating. Most instructions are 16

bits in length and the CPU executes a subset of the Thumb-2

instruction set. It includes a nested vectored interrupt controller

(NVIC) block with eight interrupt inputs and also includes a

Wakeup Interrupt Controller (WIC). The WIC can wake the

processor from Deep Sleep mode, allowing power to be switched

off to the main processor when the chip is in Deep Sleep mode.

The clock system for the PSoC 4100S Plus consists of the IMO,

ILO, a 32-kHz Watch Crystal Oscillator (WCO), MHz ECO and

PLL, and provision for an external clock. The WCO block allows

locking the IMO to the 32-kHz oscillator.

Figure 3. PSoC 4100S Plus MCU Clocking Architecture

External Clock

The CPU subsystem includes an 8-channel DMA engine and

also includes a debug interface, the SWD interface, which is a

2-wire form of JTAG. The debug configuration used for

PSoC 4100S Plus has four breakpoint (address) comparators

and two watchpoint (data) comparators.

H

IMO

Divide By

2,4,8

PLL

ECO

Flash

WDC0

16-bits

W CO

ILO

LFCLK

WDC1

16-bits

The PSoC 4100S Plus device has a flash module with a flash

accelerator, tightly coupled to the CPU to improve average

access times from the flash block. The low-power flash block is

designed to deliver two wait-state (WS) access time at 48 MHz.

The flash accelerator delivers 85% of single-cycle SRAM access

performance on average.

WDC2

32-bits

Watchdog Counters(WDC)

WDT

Watchdog Timer(WDT)

Prescaler

SYSCLK

HFCLK

Integer

Dividers

SRAM

12X 16-bit

Fractional

Dividers

16 KB of SRAM are provided with zero wait-state access at

48 MHz.

5X 16.5-bit, 1X 24.5 bit

SROM

The HFCLK signal can be divided down as shown to generate

synchronous clocks for the Analog and Digital peripherals. There

are 18 clock dividers for the PSoC 4100S Plus (six with fractional

divide capability, twelve with integer divide only). The twelve

16-bit integer divide capability allows a lot of flexibility in

generating fine-grained frequency. In addition, there are five

16-bit fractional dividers and one 24-bit fractional divider.

An 8-KB supervisory ROM that contains boot and configuration

routines is provided.

System Resources

Power System

The power system is described in detail in the section Power. It

provides assurance that voltage levels are as required for each

respective mode and either delays mode entry (for example, on

power-on reset (POR)) until voltage levels are as required for

proper functionality, or generates resets (for example, on

brownout detection). PSoC 4100S Plus operates with a single

external supply over the range of either 1.8 V ±5% (externally

regulated) or 1.8 V to 5.5 V (internally regulated) and has three

different power modes, transitions between which are managed

by the power system. PSoC 4100S Plus provides Active, Sleep,

and Deep Sleep low-power modes.

IMO Clock Source

The IMO is the primary source of internal clocking in the

PSoC 4100S Plus. It is trimmed during testing to achieve the

specified accuracy.The IMO default frequency is 24 MHz and it

can be adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO

tolerance with Cypress-provided calibration settings is ±2% over

the entire voltage and temperature range.

ILO Clock Source

The ILO is a very low power, nominally 40-kHz oscillator, which

is primarily used to generate clocks for the watchdog timer

(WDT) and peripheral operation in Deep Sleep mode. ILO-driven

counters can be calibrated to the IMO to improve accuracy.

Cypress provides a software component, which does the

calibration.

All subsystems are operational in Active mode. The CPU

subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep

mode, while all peripherals and interrupts are active with

instantaneous wake-up on a wake-up event. In Deep Sleep

mode, the high-speed clock and associated circuitry is switched

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Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

WCO

Figure 4. SAR ADC

AHB System Bus and Programmable Logic

Interconnect

The PSoC 4100S Plus clock subsystem also implements a

low-frequency (32-kHz watch crystal) oscillator that can be used

for precision timing applications.

SAR Sequencer

Sequencing

and Control

Data and

Status Flags

ECO

POS

SARADC

The PSoC 4100S Plus also implements a 4 to 33 MHz crystal

oscillator.

NEG

WDT

External

Reference and

Bypass

Reference

Selection

A watchdog timer is implemented in the clock block running from

the ILO; this allows watchdog operation during Deep Sleep and

generates a watchdog reset if not serviced before the set timeout

occurs. The watchdog reset is recorded in a Reset Cause

register, which is firmware readable.

(optional)

VDDA

VREF

VDDA/2

Inputs from other Ports

Two Opamps (Continuous-Time Block; CTB)

PSoC 4100S Plus has two opamps with Comparator modes

which allow most common analog functions to be performed

on-chip eliminating external components; PGAs, Voltage

Buffers, Filters, Trans-Impedance Amplifiers, and other functions

can be realized, in some cases with external passives. saving

power, cost, and space. The on-chip opamps are designed with

enough bandwidth to drive the Sample-and-Hold circuit of the

ADC without requiring external buffering.

Reset

PSoC 4100S Plus can be reset from a variety of sources

including a software reset. Reset events are asynchronous and

guarantee reversion to a known state. The reset cause is

recorded in a register, which is sticky through reset and allows

software to determine the cause of the reset. An XRES pin is

reserved for external reset by asserting it active low. The XRES

pin has an internal pull-up resistor that is always enabled.

Low-power Comparators (LPC)

Analog Blocks

PSoC 4100S Plus has a pair of low-power comparators, which

can also operate in Deep Sleep modes. This allows the analog

system blocks to be disabled while retaining the ability to monitor

external voltage levels during low-power modes. The

comparator outputs are normally synchronized to avoid

metastability unless operating in an asynchronous power mode

where the system wake-up circuit is activated by a comparator

switch event. The LPC outputs can be routed to pins.

12-bit SAR ADC

The 12-bit, 1-Msps SAR ADC can operate at a maximum clock

rate of 18 MHz and requires a minimum of 18 clocks at that

frequency to do a 12-bit conversion.

The Sample-and-Hold (S/H) aperture is programmable allowing

the gain bandwidth requirements of the amplifier driving the SAR

inputs, which determine its settling time, to be relaxed if required.

It is possible to provide an external bypass (through a fixed pin

location) for the internal reference amplifier.

Current DACs

PSoC 4100S Plus has two IDACs, which can drive any of the

pins on the chip. These IDACs have programmable current

ranges.

The SAR is connected to a fixed set of pins through an 8-input

sequencer. The sequencer cycles through selected channels

autonomously (sequencer scan) with zero switching overhead

(that is, aggregate sampling bandwidth is equal to 1 Msps

whether it is for a single channel or distributed over several

channels). The sequencer switching is effected through a state

machine or through firmware driven switching. A feature

provided by the sequencer is buffering of each channel to reduce

CPU interrupt service requirements. To accommodate signals

with varying source impedance and frequency, it is possible to

have different sample times programmable for each channel.

Also, signal range specification through a pair of range registers

(low and high range values) is implemented with a corresponding

out-of-range interrupt if the digitized value exceeds the

programmed range; this allows fast detection of out-of-range

values without the necessity of having to wait for a sequencer

scan to be completed and the CPU to read the values and check

for out-of-range values in software.

Analog Multiplexed Buses

PSoC 4100S Plus has two concentric independent buses that go

around the periphery of the chip. These buses (called amux

buses) are connected to firmware-programmable analog

switches that allow the chip's internal resources (IDACs,

comparator) to connect to any pin on the I/O Ports.

Programmable Digital Blocks

Smart I/O Block

The Smart I/O block is a fabric of switches and LUTs that allows

Boolean functions to be performed in signals being routed to the

pins of a GPIO port. The Smart I/O can perform logical opera-

tions on input pins to the chip and on signals going out as

outputs.

The SAR is not available in Deep Sleep mode as it requires a

high-speed clock (up to 18 MHz). The SAR operating range is

1.71 V to 5.5 V.

Document Number: 002-20072 Rev. *I

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Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

SPI Mode: The SPI mode supports full Motorola SPI, TI SSP

(adds a start pulse used to synchronize SPI Codecs), and

National Microwire (half-duplex form of SPI). The SPI block can

use the FIFO.

Fixed Function Digital Blocks

Timer/Counter/PWM (TCPWM) Block

The TCPWM block consists of

a 16-bit counter with

user-programmable period length. There is a capture register to

record the count value at the time of an event (which may be an

I/O event), a period register that is used to either stop or

auto-reload the counter when its count is equal to the period

register, and compare registers to generate compare value

signals that are used as PWM duty cycle outputs. The block also

provides true and complementary outputs with programmable

offset between them to allow use as dead-band programmable

complementary PWM outputs. It also has a Kill input to force

outputs to a predetermined state; for example, this is used in

motor drive systems when an over-current state is indicated and

the PWM driving the FETs needs to be shut off immediately with

no time for software intervention. Each block also incorporates a

Quadrature decoder. There are eight TCPWM blocks in

PSoC 4100S Plus.

LIN Slave Mode: The LIN Slave mode uses the SCB hardware

block and implements a full LIN slave interface. This LIN Slave

is compliant with LIN v1.3, v2.1/2.2, ISO 17987-6, and SAE

J2602-2 specification standards. It is certified by C&S GmbH

based on the standard protocol and data link layer conformance

tests. LIN slave can be operated at baud rates of up to ~20 Kbps

with a maximum of 40-meter cable length. The PSoC Creator

software supports up to two LIN slave interfaces in the PSoC 4

device, providing built-in application programming interfaces

(APIs) based on the LIN specification standard.

CAN

There is one CAN block, which implements CAN 2.0B as defined

in the Bosch specifications and conform to the ISO-11898-1

standard.

Serial Communication Block (SCB)

GPIO

PSoC 4100S Plus has five serial communication blocks, which

can be programmed to have SPI, I C, UART, or LIN Slave

functionality.

PSoC 4100S Plus has up to 54 GPIOs. The GPIO block imple-

ments the following:

2

■ Eight drive modes:

❐ Analog input mode (input and output buffers disabled)

❐ Input only

❐ Weak pull-up with strong pull-down

❐ Strong pull-up with weak pull-down

❐ Open drain with strong pull-down

❐ Open drain with strong pull-up

❐ Strong pull-up with strong pull-down

❐ Weak pull-up with weak pull-down

■ Input threshold select (CMOS or LVTTL).

2

I²C Mode: The hardware I C block implements

a full

multi-master and slave interface (it is capable of multi-master

arbitration). This block is capable of operating at speeds of up to

400 kbps (Fast Mode) and has flexible buffering options to

reduce interrupt overhead and latency for the CPU. It also

2

supports EZI C that creates a mailbox address range in the

2

memory of PSoC 4100S Plus and effectively reduces I C

communication to reading from and writing to an array in

memory. In addition, the block supports an 8-deep FIFO for

receive and transmit which, by increasing the time given for the

CPU to read data, greatly reduces the need for clock stretching

caused by the CPU not having read data on time.

■ Individual control of input and output buffer enabling/disabling

in addition to the drive strength modes

2

The I C peripheral is compatible with the I C Standard-mode and

■ Selectable slew rates for dV/dt related noise control to improve

EMI

2

Fast-mode devices as defined in the NXP I C-bus specification

and user manual (UM10204). The I C bus I/O is implemented

2

The pins are organized in logical entities called ports, which are

8-bit in width (less for Ports 5 and 6). During power-on and reset,

the blocks are forced to the disable state so as not to crowbar

any inputs and/or cause excess turn-on current. A multiplexing

network known as a high-speed I/O matrix is used to multiplex

between various signals that may connect to an I/O pin.

with GPIO in open-drain modes.

2

PSoC 4100S Plus is not completely compliant with the I C spec

in the following respect:

■ GPIO cells are not over-voltage tolerant and, therefore, cannot

be hot-swapped or powered up independently of the rest of the

2

I C system.

Data output and pin state registers store, respectively, the values

to be driven on the pins and the states of the pins themselves.

UART Mode: This is a full-feature UART operating at up to

1 Mbps. It supports automotive single-wire interface (LIN),

infrared interface (IrDA), and SmartCard (ISO7816) protocols, all

of which are minor variants of the basic UART protocol. In

addition, it supports the 9-bit multiprocessor mode that allows

addressing of peripherals connected over common RX and TX

lines. Common UART functions such as parity error, break

detect, and frame error are supported. An 8-deep FIFO allows

much greater CPU service latencies to be tolerated.

Every I/O pin can generate an interrupt if so enabled and each

I/O port has an interrupt request (IRQ) and interrupt service

routine (ISR) vector associated with it.

Document Number: 002-20072 Rev. *I

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Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

ranges for improved sensitivity and flexibility. It can also use an

external reference voltage. It has a full-wave CSD mode that

alternates sensing to VDDA and ground to null out power-supply

related noise.

Special Function Peripherals

CapSense

CapSense is supported in the PSoC 4100S Plus through a

CapSense Sigma-Delta (CSD) block that can be connected to

any pins through an analog multiplex bus via analog switches.

CapSense function can thus be provided on any available pin or

group of pins in a system under software control. A PSoC

Creator component is provided for the CapSense block to make

it easy for the user.

LCD Segment Drive

PSoC 4100S Plus has an LCD controller, which can drive up to

4 commons and up to 50 segments. It uses full digital methods

to drive the LCD segments requiring no generation of internal

LCD voltages. The two methods used are referred to as Digital

Correlation and PWM. Digital Correlation pertains to modulating

the frequency and drive levels of the common and segment

signals to generate the highest RMS voltage across a segment

to light it up or to keep the RMS signal to zero. This method is

good for STN displays but may result in reduced contrast with TN

(cheaper) displays. PWM pertains to driving the panel with PWM

signals to effectively use the capacitance of the panel to provide

the integration of the modulated pulse-width to generate the

desired LCD voltage. This method results in higher power

consumption but can result in better results when driving TN

displays. LCD operation is supported during Deep Sleep

refreshing a small display buffer (4 bits; one 32-bit register per

port).

Shield voltage can be driven on another analog multiplex bus to

provide water-tolerance capability. Water tolerance is provided

by driving the shield electrode in phase with the sense electrode

to keep the shield capacitance from attenuating the sensed

input. Proximity sensing can also be implemented.

The CapSense block has two IDACs, which can be used for

general purposes if CapSense is not being used (both IDACs are

available in that case) or if CapSense is used without water

tolerance (one IDAC is available).

The CapSense block also provides a 10-bit Slope ADC function

which can be used in conjunction with the CapSense function.

The CapSense block is an advanced, low-noise, programmable

block with programmable voltage references and current source

Document Number: 002-20072 Rev. *I

Page 9 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Pinouts

Table 1. Pin List for PSoC 4100S Plus for the 40-pin QFN and 64-pin TQFP Packages

40-pin QFN 64-pin TQFP

64-pin TQFP

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

1

Name

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

XRES

VCCD

VSSD

VDD

VSSA

P1.0

P1.1

P1.2

P1.3

P1.4

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

1

Name

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

XRES

VCCD

VSSD

VDDD

P5.0

P5.1

P5.2

P5.3

P5.5

VDDA

VSSA

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

8

Name

P2.6

9

P2.7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

VSSD

No Connect (NC)

P6.0

P6.1

P6.2

P6.4

P6.5

VSSD

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

P1.7/VREF

P2.3

P2.4

P2.5

P2.6

P2.7

P6.0

P6.1

P6.2

VSSD

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

P4.0

P4.1

P4.2

P4.3

VDDD

P4.0

2

P4.1

3

P4.2

4

P4.3

5

P4.4

6

P4.5

7

P4.6

8

P4.7

9

2

P5.6

10

11

12

13

14

15

16

17

18

19

20

21

3

P5.7

4

P7.0

5

P7.1

6

7

Document Number: 002-20072 Rev. *I

Page 10 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Descriptions of the Power pins are as follows:

VDDD: Power supply for the digital section.

VDDA: Power supply for the analog section.

VSSD, VSSA: Ground pins for the digital and analog sections respectively.

VCCD: Regulated digital supply (1.8 V ±5%)

VDD: Power supply to all sections of the chip

VSS: Ground for all sections of the chip

GPIOs: 54

Document Number: 002-20072 Rev. *I

Page 11 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Mode 1: 1.8 V to 5.5 V External Supply

Power

In this mode, PSoC 4100S Plus is powered by an external power

supply that can be anywhere in the range of 1.8 to 5.5 V. This

range is also designed for battery-powered operation. For

example, the chip can be powered from a battery system that

starts at 3.5 V and works down to 1.8 V. In this mode, the internal

regulator of PSoC 4100S Plus supplies the internal logic and its

The following power system diagram shows the set of power

supply pins as implemented for the PSoC 4100S Plus. The

system has one regulator in Active mode for the digital circuitry.

There is no analog regulator; the analog circuits run directly from

the V input.

DD

output is connected to the V

bypassed to ground via an external capacitor (0.1 µF; X5R

pin. The V

pin must be

Figure 5. Power Supply Connections

CCD

ceramic or better) and must not be connected to anything else.

VDDA

VDDD

Mode 2: 1.8 V ±5% External Supply

VDDD

VSSD

Analog

Domain

Digital

Domain

In this mode, PSoC 4100S Plus is powered by an external power

supply that must be within the range of 1.71 to 1.89 V; note that

this range needs to include the power supply ripple too. In this

mode, the VDD and VCCD pins are shorted together and

bypassed. The internal regulator can be disabled in the firmware.

VSSA

Bypass capacitors must be used from VDDD to ground. The

typical practice for systems in this frequency range is to use a

capacitor in the 1-µF range, in parallel with a smaller capacitor

(0.1 µF, for example). Note that these are simply rules of thumb

and that, for critical applications, the PCB layout, lead induc-

tance, and the bypass capacitor parasitic should be simulated to

design and obtain optimal bypassing.

VCCD

1.8 Volt

Regulator

An example of a bypass scheme is shown in the following

diagram.

There are two distinct modes of operation. In Mode 1, the supply

voltage range is 1.8 V to 5.5 V (unregulated externally; internal

regulator operational). In Mode 2, the supply range is1.8 V ±5%

(externally regulated; 1.71 to 1.89, internal regulator bypassed).

Figure 6. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active

Power supply bypass connections example

1.8 V to 5.5 V

0.1 µF

1.8 V to 5.5 V

V_DDA

V_DDD

1 µF

0.1 µF

V_CCD

PSoC 4100S Premium

0.1F

V_SS

Document Number: 002-20072 Rev. *I

Page 14 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Electrical Specifications

Absolute Maximum Ratings

[3]

Table 3. Absolute Maximum Ratings

Spec ID#

SID1

Parameter

Description

Min

–0.5

Typ

–

Max

6

Unit

Details/Conditions

V

Digital supply relative to V

V

–

DDD_ABS

CCD_ABS

SS

SID2

V

Direct digital core voltage input

relative to V

–

1.95

SS

SID3

SID4

SID5

V

GPIO voltage

–0.5

–25

–

V

+ 0.5

DD

–

GPIO_ABS

I

Maximum current per GPIO

25

mA

V

GPIO injection current, Max for

–0.5

0.5

Current injected per pin

GPIO_injection

V

> V

, and Min for V < V

DDD IL SS

IH

BID44

BID45

BID46

ESD_HBM Electrostatic discharge human

body model

2200

500

–

ESD_CDM Electrostatic discharge charged

device model

LU

Pin current for latch-up

–140

140

mA

Note

3. Usage above the absolute maximum conditions listed in Table 3 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended

periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature

Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.

Document Number: 002-20072 Rev. *I

Page 15 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Device Level Specifications

All specifications are valid for –40 °C  TA  85 °C for Grade-A devices, –40 °C  TA  105 °C for Grade-S devices, and –40 °C  TA

[4]

 125 °C for Grade-E devices . Specifications are valid for 1.71 V to 5.5 V, except where noted.

Table 4. DC Specifications

Typical values measured at V = 3.3 V and 25 °C.

DD

Spec ID#

SID53

Parameter

Description

Min

1.8

Typ

–

Max

5.5

Unit

Details/Conditions

V

Power supply input voltage

V

Internally regulated supply

DD

SID255

V

1.71

–

1.89

Internally unregulated

supply

(V

= V

)

CCD

DDD

DDA

SID54

SID55

SID56

V

Output voltage (for core logic)

External regulator voltage bypass

Power supply bypass capacitor

–

1.8

0.1

1

–

CCD

C

µF X5R ceramic or better

EFC

EXC

X5R ceramic or better

Active Mode, V_DD= 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C.

SID10

SID16

SID19

I

Execute from flash; CPU at

6 MHz

–

1.8

3.0

5.4

2.7

mA Max is at 125 °C and 5.5 V

Max is at 125 °C and 5.5 V

DD5

DD8

DD11

Execute from flash; CPU at

24 MHz

4.75

6.85

Execute from flash; CPU at

48 MHz

Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)

2

SID22

I

I C wakeup WDT, and

Comparators on

–

1.1

1.5

1.8

2.1

mA 6 MHZ. Max is at 125 °C

and 5.5 V

DD17

2

SID25

I

I C wakeup, WDT, and

12 MHZ. Max is at 125 °C

and 5.5 V

DD20

Comparators on

Sleep Mode, V_DDD= 1.71 V to 1.89 V (Regulator bypassed)

2

SID28

I

I C wakeup, WDT, and

Comparators on

–

1.1

1.5

1.8

2.1

mA 6 MHz. Max is at 125 °C

and 1.89 V.

DD23

2

SID28A

I

I C wakeup, WDT, and

12 MHz. Max is at 125 °C

and 1.89 V.

DD23A

Comparators on

Deep Sleep Mode, V_DD= 1.8 V to 3.6 V (Regulator on)

2

SID30

SID31

I

I C wakeup and WDT on

–

2.5

40

µA T = –40 °C to 60 °C

DD25

DD26

2

I C wakeup and WDT on

125

Max is at 3.6 V and 125 °C

Deep Sleep Mode, V_DD= 3.6 V to 5.5 V (Regulator on)

2

SID33

SID34

I

I C wakeup and WDT on

–

2.5

40

µA T = –40 °C to 60 °C

DD28

DD29

2

I C wakeup and WDT on

125

Max is at 5.5 V and 125 °C

Deep Sleep Mode, V_DD= V_CCD= 1.71 V to 1.89 V (Regulator bypassed)

2

SID36

SID37

I

I C wakeup and WDT on

–

2.5

60

µA T = –40 °C to 60 °C

DD31

DD32

2

I C wakeup and WDT on

180

Max is at 125 °C and 1.89

V.

XRES Current

SID307

I

Supply current while XRES

asserted

–

2

5

mA

–

DD_XR

Note

4. Grade-E specifications (at +125 °C) are preliminary. Contact Cypress for the availability of Grade-E devices.

Document Number: 002-20072 Rev. *I

Page 16 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Table 5. AC Specifications

Spec ID# Parameter

SID48

Description

CPU frequency

Min

DC

–

Typ

–

Max

48

–

Unit

Details/Conditions

F

MHz 1.71 V 5.5

CPU

DD

SID49

SID50

T

Wakeup from Sleep mode

0

µs

–

SLEEP

Wakeup from Deep Sleep mode

–

35

–

DEEPSLEEP

GPIO

Table 6. GPIO DC Specifications

Spec ID#

SID57

Parameter

Description

Min

Typ

–

Max

Unit

Details/Conditions

[6]

V

Input voltage high threshold

Input voltage low threshold

0.7 V

–

V

CMOS Input

IH

IL

IH

IL

IH

IL

DDD

SID58

V

–

0.3 V

CMOS Input

DDD

[6]

SID241

SID242

SID243

SID244

SID59

LVTTL input, V

< 2.7 V

 2.7 V

0.7 V

–

DDD

–

2.0

–

0.3 V

DDD

–

0.8

–

Output voltage high level

V

– 0.6

– 0.5

–

I

= 4 mA at 3 V V

= 1 mA at 1.8 V

OH

DDD

OH

DDD

SID60

–

OH

V

DDD

SID61

V

Output voltage low level

–

0.6

I

V

= 4 mA at 1.8 V

OL

DDD

SID62

SID62A

SID63

SID64

SID65

V

Output voltage low level

Pull-up resistor

–

0.6

0.4

8.5

2

I

= 10 mA at 3 V V

OL

DDD

= 3 mA at 3 V V

DDD

R

3.5

–

5.6

–

kΩ

–

PULLUP

Pull-down resistor

PULLDOWN

I

Input leakage current (absolute

value)

nA 25 °C, V

= 3.0 V

DDD

IL

SID66

C

V

Input capacitance

–

40

–

7

–

pF

–

IN

[7]

SID67

SID68

Input hysteresis LVTTL

Input hysteresis CMOS

25

mV

V

 2.7 V

DDD

HYSTTL

[7]

V

0.05 × V

200

< 4.5 V

> 4.5 V

HYSCMOS

DDD

DD

[7]

SID68A

–

HYSCMOS5

V5

[7]

SID69

I

Current through protection diode

–

100

200

µA

–

DIODE

to V /V

DD SS

[7]

SID69A

I

Maximum total source or sink

chip current

mA

TOT_GPIO

Notes

5. Guaranteed by characterization.

6. must not exceed V + 0.2 V.

7. Guaranteed by characterization.

V

IH

DDD

Document Number: 002-20072 Rev. *I

Page 17 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Table 7. GPIO AC Specifications

(Guaranteed by Characterization)

Spec ID#

SID70

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

T

Rise time in fast strong mode

2

–

12

ns 3.3 V V

,

DDD

Cload = 25 pF

RISEF

SID71

SID72

SID73

SID74

SID75

T

F

Fall time in fast strong mode

Rise time in slow strong mode

Fall time in slow strong mode

2

10

–

12

60

3.3 V V

Cload = 25 pF

,

DDD

FALLF

–

3.3 V V

Cload = 25 pF

,

DDD

RISES

60

3.3 V V

Cload = 25 pF

,

DDD

FALLS

GPIO F

Fast strong mode

; 3.3 V  V

5.5 V

33

MHz 90/10%, 25 pF load,

60/40 duty cycle

GPIOUT1

GPIOUT2

OUT

DDD

GPIO F

1.71 V V

Fast strong mode

;

–

16.7

90/10%, 25 pF load,

60/40 duty cycle

OUT

3.3 V

DDD

SID76

F

GPIO F ; 3.3 V V

5.5 V

–

7

90/10%, 25 pF load,

60/40 duty cycle

GPIOUT3

GPIOUT4

OUT

DDD

Slow strong mode

SID245

GPIO F

;

3.5

90/10%, 25 pF load,

60/40 duty cycle

OUT

1.71 V V

3.3 V

DDD

Slow strong mode.

GPIO input operating frequency;

1.71 V V 5.5 V

SID246

F

–

48

90/10% V

IO

GPIOIN

DDD

XRES

Table 8. XRES DC Specifications

Spec ID#

SID77

Parameter

Description

Input voltage high threshold

Input voltage low threshold

Pull-up resistor

Min

Typ

–

Max

–

Unit

Details/Conditions

V

0.7 × V

V

CMOS Input

IH

IL

DDD

SID78

SID79

SID80

SID81

V

–

0.3  V

DDD

R

C

60

–

7

–

kΩ

pF

–

PULLUP

IN

Input capacitance

[8]

V

Input voltage hysteresis

100

mV Typical hysteresis is

HYSXRES

200 mV for V > 4.5 V

DD

SID82

I

Current through protection diode

–

100

µA

–

DIODE

to V /V

DD SS

Table 9. XRES AC Specifications

Spec ID#

Parameter

Description

Reset pulse width

Wake-up time from reset release

Min

Typ

Max

Unit Details/Conditions

[8]

SID83

T

1

–

µs

–

RESETWIDTH

RESETWAKE

[8]

BID194

2.7

ms

Note

8. Guaranteed by characterization.

Document Number: 002-20072 Rev. *I

Page 18 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Analog Peripherals

CTBm Opamp

Table 10. CTBm Opamp Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

I

Opamp block current, External

load

DD

SID269

SID270

SID271

I

power = hi

–

1100

550

150

1850

950

µA

–

DD_HI

power = med

power = lo

DD_MED

DD_LOW

350

G

Load = 20 pF, 0.1 mA

BW

V

= 2.7 V

DDA

SID272

SID273

SID274

power = hi

power = med

power = lo

6

3

–

1

–

MHz Input and output are

0.2 V to V -0.2 V

BW_HI

BW_MED

BW_LO

DDA

Input and output are

0.2 V to V -0.2 V

DDA

Input and output are

0.2 V to V -0.2 V

DDA

I

V

= 2.7 V, 500 mV from rail

OUT_MAX

DDA

SID275

SID276

SID277

power = hi

power = mid

power = lo

10

–

5

–

mA

Output is 0.5 V to V

-0.5 V

OUT_MAX_HI

DDA

I

Output is 0.5 V to V

-0.5 V

OUT_MAX_MID

OUT_MAX_LO

Output is 0.5 V to V

-0.5 V

I

V

= 1.71 V, 500 mV from rail

OUT

DDA

SID278

power = hi

4

–

Output is 0.5 V to V

-0.5 V

OUT_MAX_HI

DDA

power = mid

Output is 0.5 V to

SID279

SID280

I

4

–

OUT_MAX_MID

OUT_MAX_LO

V

-0.5 V

DDA

power = lo

2

Output is 0.5 V to

V

-0.5 V

DDA

I

Opamp block current Internal

Load

DD_Int

–

SID269_I

SID270_I

SID271_I

I

power = hi

power = med

power = lo

1500

1700

µA

DD_HI_Int

700

–

900

–

DD_MED_Int

DD_LOW_Int

–

G

V

= 2.7 V

BW

DDA

SID272_I

power = hi

8

MHz Output is 0.25 V to

BW_HI_Int

V

-0.25 V

DDA

General opamp specs for both

internal and external modes

–

SID281

SID282

V

Charge-pump on, V

= 2.7 V

–0.05

V

-0.2

V

IN

DDA

-0.2

CM

OUT

DDA

V

= 2.7 V

DDA

Document Number: 002-20072 Rev. *I

Page 19 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Table 10. CTBm Opamp Specifications (continued)

Spec ID#

SID283

SID284

SID285

SID286

SID288

Parameter

Description

power = hi, Iload=10 mA

power = hi, Iload=1 mA

power = med, Iload=1 mA

power = lo, Iload=0.1 mA

Offset voltage, trimmed

Min

0.5

Typ

Max

Units

Details/Conditions

–

V

-0.5

V

OUT_1

OUT_2

OUT_3

OUT_4

OS_TR

DDA

–

0.2

-0.2

0.2

–1.0

1.0

mV

High mode, input 0 V

to V -0.2 V

0.5

1

DDA

–

SID288A

SID288B

V

Offset voltage, trimmed

Medium mode, input

0 V to V -0.2 V

OS_TR

DDA

Low mode, input 0 V to

-0.2 V

2

V

DDA

SID290

V

Offset voltage drift, trimmed

DC

–10

–

10

–

µV/°C High mode

µV/°C Medium mode

Low mode

3

10

80

OS_DR_TR

SID290A

SID290B

SID291

–

CMRR

70

dB

Input is 0 V to

-0.2 V, Output is

V

DDA

0.2 V to V

-0.2 V

DDA

–

SID292

PSRR

At 1 kHz, 10-mV ripple

70

85

V

= 3.6 V,

DDD

high-power mode,

input is 0.2 V to

V

-0.2 V

DDA

Noise

VN2

–

SID294

SID295

Input-referred, 1 kHz, power = Hi

72

28

nV/rtHz 3

Input and output are at

0.2 V to V -0.2 V

VN3

Input-referred, 10 kHz, power =

Hi

DDA

–

SID296

VN4

Input-referred, 100 kHz, power =

Hi

15

–

Input and output are at

0.2 V to V

-0.2 V

DDA

–

SID297

SID298

C

Stable up to max. load.

Performance specs at 50 pF.

125

–

pF

LOAD

–

SLEW_RATE Cload = 50 pF, Power = High,

= 2.7 V

6

–

V/µs

V

DDA

–

SID299

T_OP_WAKE From disable to enable, no

external RC dominating

25

–

µs

SID299A

OL_GAIN

COMP_MODE Comparator mode; 50 mV drive,

=T (approx.)

Open Loop Gain

90

dB

T

rise fall

–

SID300

SID301

SID302

SID303

TPD1

Response time; power = hi

Response time; power = med

Response time; power = lo

Hysteresis

150

500

2500

10

ns

Input is 0.2 V to V

– 0.2 V

DDA

TPD2

Input is 0.2 V to V

– 0.2 V

TPD3

Input is 0.2 V to V

– 0.2 V

–

VHYST_OP

mV

Document Number: 002-20072 Rev. *I

Page 20 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Table 10. CTBm Opamp Specifications (continued)

Spec ID#

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

–

SID304

WUP_CTB

Wake-up time from Enabled to

Usable

25

µs

Deep Sleep

Mode

Mode 2 is lowest current range.

Mode 1 has higher GBW.

–

SID_DS_1

SID_DS_2

SID_DS_3

SID_DS_4

SID_DS_5

SID_DS_6

SID_DS_7

I

Mode 1, High current

Mode 1, Medium current

Mode 1, Low current

Mode 2, High current

Mode 2, Medium current

Mode 2, Low current

Mode 1, High current

1400

700

200

120

60

µA

25 °C

DD_HI_M1

DD_MED_M1

DD_LOW_M1

DD_HI_M2

DD_MED_M2

DD_LOW_M2

15

G

4

MHz 20-pF load, no DC

load 0.2 V to

BW_HI_M1

V

– 0.2 V

DDA

–

SID_DS_8

SID_DS_9

Mode 1, Medium current

Mode 1, Low current

Mode 2, High current

Mode 2, Medium current

Mode 2, Low current

2

20-pF load, no DC

load 0.2 V to

BW_MED_M1

BW_LOW_M1

BW_HI_M2

V

– 0.2 V

DDA

0.5

0.2

0.1

20-pF load, no DC

load 0.2 V to

V

– 0.2 V

DDA

SID_DS_10 G

SID_DS_11 G

SID_DS_12 G

20-pF load, no DC

load 0.2 V to

V

– 0.2 V

DDA

20-pF load, no DC

load 0.2 V to

BW_MED_M2

BW_Low_M2

V

– 0.2 V

DDA

20-pF load, no DC

load 0.2 V to V

–

DDA

0.2 V

–

SID_DS_13 V

SID_DS_14 V

SID_DS_15 V

SID_DS_16 V

SID_DS_17 V

SID_DS_18 V

Mode 1, High current

Mode 1, Medium current

Mode 1, Low current

Mode 2, High current

Mode 2, Medium current

Mode 2, Low current

5

mV

With trim 25 °C, 0.2 V

to V – 0.2 V

OS_HI_M1

DDA

With trim 25 °C, 0.2 V

to V – 0.2 V

OS_MED_M1

OS_LOW_M2

OS_HI_M2

DDA

With trim 25 °C, 0.2 V

to V – 0.2 V

DDA

With trim 25 °C, 0.2V

to V – 0.2 V

DDA

With trim 25 °C, 0.2 V

to V – 0.2 V

OS_MED_M2

OS_LOW_M2

DDA

With trim 25 °C, 0.2 V

to V

– 0.2 V

DDA

Document Number: 002-20072 Rev. *I

Page 21 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Table 10. CTBm Opamp Specifications (continued)

Spec ID#

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

–

SID_DS_19 I

Mode 1, High current

10

mA

Output is 0.5 V to

OUT_HI_M1

V

– 0.5 V

DDA

–

SID_DS_20 I

SID_DS_21 I

Mode 1, Medium current

Mode 1, Low current

10

4

Output is 0.5 V to

– 0.5 V

OUT_MED_M1

OUT_LOW_M1

V

DDA

Output is 0.5 V to

V

– 0.5 V

DDA

–

SID_DS_22 I

SID_DS_23 I

SID_DS_24 I

Mode 2, High current

Mode 2, Medium current

Mode 2, Low current

1

OUT_HI_M2

OU_MED_M2

OU_LOW_M2

–

0.5

Comparator

Table 11. Comparator DC Specifications

Spec ID#

SID84

Parameter

Description

Min

Typ

–

Max

Units

Details/Conditions

V

Input offset voltage, Factory trim

Input offset voltage, Custom trim

Hysteresis when enabled

–

0

±10

±4

mV

–

OFFSET1

OFFSET2

HYST

SID85

SID86

SID87

V

–

10

–

35

Input common mode voltage in

normal mode

V

-0.1

V

Modes 1 and 2

ICM1

DDD

SID247

V

Input common mode voltage in

low power mode

0

–

V

DDD

–

ICM2

ICM3

SID247A

Input common mode voltage in

ultra low power mode

V

-1.15

V

≥ 2.2 V at –40 °C

DDD

SID88

C

Common mode rejection ratio

Block current, normal mode

Block current, low power mode

50

42

–

dB

µA

V

–

≥ 2.7V

≤ 2.7V

MRR

DDD

SID88A

SID89

–

DDD

I

400

100

6

CMP1

CMP2

CMP3

SID248

SID259

–

Block current in ultra low-power

mode

–

V

≥ 2.2 V at –40 °C

DDD

SID90

Z

DC Input impedance of

comparator

35

–

MΩ

–

CMP

Table 12. Comparator AC Specifications

Spec ID#

SID91

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

TRESP1

Response time, normal mode,

50 mV overdrive

–

38

110

ns

–

V

SID258

SID92

TRESP2

TRESP3

Response time, low power mode,

50 mV overdrive

–

70

200

15

Response time, ultra-low power

mode, 200 mV overdrive

2.3

µs

≥ 2.2 V at –40 °C

DDD

Note

9. Guaranteed by characterization.

Document Number: 002-20072 Rev. *I

Page 22 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Temperature Sensor

Table 13. Temperature Sensor Specifications

Spec ID#

SID93

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

TSENSACC Temperature sensor accuracy

–5

±1

5

°C –40 to +125 °C

SAR ADC

Table 14. SAR ADC Specifications

Spec ID# Parameter

SAR ADC DC Specifications

Description

Min

Typ

Max

Unit

Details/Conditions

SID94

SID95

A_RES

Resolution

–

12

16

bits

–

A_CHNLS_S Number of channels - single

ended

SID96

A-CHNKS_D Number of channels - differential

–

4

Diff inputs use

neighboring I/O

SID97

SID98

SID99

A-MONO

Monotonicity

–

±0.1

2

Yes

A_GAINERR Gain error

%

With external reference

A_OFFSET

Input offset voltage

mV Measured with 1 V

reference

SID100

SID101

A_ISAR

A_VINS

Current consumption

–

1

mA

V

–

Input voltage range - single

ended

V

SS

DDA

SID102

SID103

SID104

SID260

A_VIND

Input voltage range - differential

Input resistance

V

–

V

KΩ

pF

V

–

SS

DDA

A_INRES

A_INCAP

VREFSAR

–

2.2

10

Input capacitance

–

Trimmed internal reference to

SAR

1.188

1.2

1.212

SAR ADC AC Specifications

SID106

SID107

SID108

SID109

A_PSRR

A_CMRR

A_SAMP

A_SNR

Power supply rejection ratio

Common mode rejection ratio

Sample rate

70

66

–

1

–

dB

–

dB Measured at 1 V

Msps –

Signal-to-noise and distortion

ratio (SINAD)

65

dB

F

= 10 kHz

IN

SID110

SID111

A_BW

A_INL

Input bandwidth without aliasing

–

A_samp/2 kHz

–

Integral non linearity. V = 1.71

–1.7

2

LSB V

= 1 to V

DD

REF

to 5.5, 1 Msps

SID111A

SID111B

SID112

A_INL

Integral non linearity. V

to 3.6, 1 Msps

= 1.71

–1.5

–1

–

1.7

2.2

2

= 1.71 to V

DD

DDD

A_INL

Integral non linearity. V = 1.71

= 1 to V

DD

to 5.5, 500 ksps

A_DNL

A_THD

Differential non linearity.

V

= 1.71 to 5.5, 1 Msps

DD

SID112A

SID112B

Differential non linearity.

= 1.71 to 3.6, 1 Msps

–1

= 1.71 to V

DD

V

DD

Differential non linearity.

= 1.71 to 5.5, 500 ksps

–1

2.2

= 1 to V

DD

V

DD

–

SID113

SID261

Total harmonic distortion

–65

100

dB Fin = 10 kHz

ksps 12-bit resolution

FSARINTREF SAR operating speed without

external reference bypass

Document Number: 002-20072 Rev. *I

Page 23 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

CSD and IDAC

Table 15. CSD and IDAC Specifications

Spec ID#

Parameter

Description

Min Typ

Max

Unit

Details/Conditions

SYS.PER#3

VDD_RIPPLE

Max allowed ripple on power

supply, DC to 10 MHz

–

±50

mV

V

> 2 V (with ripple),

DD

25 °C T ,

A

Sensitivity = 0.1 pF

SYS.PER#16 VDD_RIPPLE_1.8 Max allowed ripple on power

supply, DC to 10 MHz

–

±25

mV

V

> 1.75V (with ripple),

DD

25 °C T ,

A

Parasitic Capacitance (C )

P

< 20 pF,

Sensitivity ≥ 0.4 pF

SID.CSD.BLK ICSD

Maximum block current

–

4000

µA Maximum block current for

both IDACs in dynamic

(switching) mode including

comparators, buffer, and

reference generator

SID.CSD#15

V

Voltage reference for CSD and

Comparator

0.6 1.2

0.6

V

- 0.6

V

- 0.06 or 4.4,

DDA

REF

DDA

whichever is lower

SID.CSD#15A VREF_EXT

External Voltage reference for

CSD and Comparator

- 0.6

V

- 0.06 or 4.4,

DDA

whichever is lower

SID.CSD#16

SID.CSD#17

SID308

IDAC1IDD

IDAC2IDD

VCSD

IDAC1 (7-bits) block current

IDAC2 (7-bits) block current

Voltage range of operation

–

1750

µA

V

–

1750

5.5

–

1.71

0.6

1.8 V ±5% or 1.8 V to 5.5 V

SID308A

VCOMPIDAC

Voltage compliance range of

IDAC

V

–0.6

V

- 0.06 or 4.4,

DDA

whichever is lower

SID309

SID310

IDAC1DNL

IDAC1INL

DNL

INL

–1

–2

–

1

2

LSB –

LSB INL is ±5.5 LSB for

V

< 2 V

DDA

SID311

SID312

IDAC2DNL

IDAC2INL

DNL

INL

–1

–2

–

1

2

LSB –

LSB INL is ±5.5 LSB for

< 2 V

V

DDA

SID313

SNR

Ratio of counts of finger to noise.

Guaranteed by characterization

5

–

Ratio Capacitance range of 5 to

35 pF, 0.1-pF sensitivity.

All use cases. V

> 2 V.

DDA

SID314

IDAC1CRT1

IDAC1CRT2

IDAC1CRT3

IDAC1CRT12

IDAC1CRT22

IDAC1CRT32

IDAC2CRT1

IDAC2CRT2

IDAC2CRT3

IDAC2CRT12

Output currentof IDAC1(7 bits)in 4.2

low range

–

5.4

41

µA LSB = 37.5 nA typ

µA LSB = 300 nA typ

µA LSB = 2.4 µA typ

µA LSB = 75 nA typ

µA LSB = 600 nA typ.

µA LSB = 4.8 µA typ

µA LSB = 37.5 nA typ

µA LSB = 300 nA typ

µA LSB = 2.4 µA typ

µA LSB = 75 nA typ

SID314A

SID314B

SID314C

SID314D

SID314E

SID315

Output current of IDAC1(7 bits) in 34

medium range

Output current of IDAC1(7 bits) in 275

high range

330

10.5

82

Outputcurrentof IDAC1(7 bits)in

low range, 2X mode

8

Output current of IDAC1(7 bits) in 69

medium range, 2X mode

Output current of IDAC1(7 bits) in 540

high range, 2X mode

660

5.4

Output currentof IDAC2(7 bits)in 4.2

low range

SID315A

SID315B

SID315C

Output currentof IDAC2(7 bits)in 34

medium range

41

Output currentof IDAC2(7 bits)in 275

high range

330

10.5

Outputcurrentof IDAC2(7 bits)in

low range, 2X mode

8

Document Number: 002-20072 Rev. *I

Page 24 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Table 15. CSD and IDAC Specifications (continued)

Spec ID#

SID315D

Parameter

Description

Min Typ

Max

Unit

Details/Conditions

IDAC2CRT22

Output current of IDAC2(7 bits) in 69

medium range, 2X mode

–

82

µA LSB = 600 nA typ

µA LSB = 4.8 µA typ

µA LSB = 37.5 nA typ

µA LSB = 300 nA typ

µA LSB = 2.4 µA typ

SID315E

SID315F

SID315G

SID315H

SID320

IDAC2CRT32

IDAC3CRT13

IDAC3CRT23

IDAC3CRT33

IDACOFFSET

Output current of IDAC2(7 bits) in 540

high range, 2X mode

660

10.5

82

Output current of IDAC in 8-bit

mode in low range

8

69

540

–

Output current of IDAC in 8-bit

mode in medium range

Output current of IDAC in 8-bit

mode in high range

660

1

All zeroes input

LSB Polarity set by Source or

Sink. Offset is 2 LSBs for

37.5 nA/LSB mode

SID321

SID322

IDACGAIN

Full-scale error less offset

–

±10

9.2

%

–

IDACMISMATCH1 Mismatch between IDAC1 and

IDAC2 in Low mode

LSB LSB = 37.5 nA typ

LSB LSB = 300 nA typ

LSB LSB = 2.4 µA typ

SID322A

SID322B

SID323

SID324

SID325

IDACMISMATCH2 Mismatch between IDAC1 and

IDAC2 in Medium mode

–

5.6

6.8

5

IDACMISMATCH3 Mismatch between IDAC1 and

IDAC2 in High mode

IDACSET8

IDACSET7

CMOD

Settling time to 0.5 LSB for 8-bit

IDAC

–

µs Full-scale transition. No

external load

Settling time to 0.5 LSB for 7-bit

IDAC

–

5

µs Full-scale transition. No

external load

External modulator capacitor.

2.2

–

nF 5-V rating, X7R or NP0 cap

Document Number: 002-20072 Rev. *I

Page 25 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

10-bit CapSense ADC

Table 16. 10-bit CapSense ADC Specifications

Spec ID#

Parameter

A_RES

Description

Resolution

Min

Typ

Max

Unit

Details/Conditions

SIDA94

–

10

bits Auto-zeroing is required

every millisecond

SIDA95

A_CHNLS_S Number of channels - single

ended

–

16

Defined by AMUX Bus

SIDA97

SIDA98

A-MONO

Monotonicity

–

Yes

%

–

A_GAINERR Gain error

±3

In V

V

(2.4 V) mode with

bypass capacitance of

REF

DDA

10 µF

SIDA99

A_OFFSET

A_VINS

Input offset voltage

–

±18

mV In V

(2.4 V) mode with

REF

bypass capacitance of

V

DDA

10 µF

SIDA101

Input voltage range - single

ended

V

–

SSA

DDA

SIDA103

SIDA104

SIDA106

A_INRES

A_INCAP

A_PSRR

Input resistance

–

2.2

20

60

–

KΩ

pF

–

Input capacitance

Power supply rejection ratio

dB In V

(2.4 V) mode with

REF

V

bypass capacitance of

DDA

10 µF

SIDA107

SIDA108

A_TACQ

Sample acquisition time

–

1

–

µs

–

A_CONV8

Conversion time for 8-bit

resolution at conversion rate =

Fhclk/(2^(N+2)).

21.3

µs Does not include acquisition

time. Equivalent to 44.8 ksps

including acquisition time.

Clock frequency = 48 MHz.

SIDA108A A_CONV10

Conversion time for 10-bit

resolution at conversion rate =

Fhclk/(2^(N+2)).

–

85.3

–

µs Does not include acquisition

time. Equivalent to 11.6 ksps

including acquisition time.

Clock frequency = 48 MHz.

SIDA109

A_SND

Signal-to-noise and Distortion

ratio (SINAD)

61

dB With 10-Hz input sine wave,

external 2.4-V reference,

V

(2.4 V) mode

REF

SIDA110

SIDA111

SIDA112

A_BW

A_INL

A_DNL

Input bandwidth without aliasing

Integral Non Linearity. 1 ksps

Differential Non Linearity. 1 ksps

–

22.4

2

KHz 8-bit resolution

LSB V

–

= 2.4 V or greater

REF

1

Document Number: 002-20072 Rev. *I

Page 26 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Digital Peripherals

Timer Counter Pulse-Width Modulator (TCPWM)

Table 17. TCPWM Specifications

Spec ID

SID.TCPWM.1

Parameter

ITCPWM1

Description

Block current consumption at

3 MHz

Block current consumption at

12 MHz

Block current consumption at

48 MHz

Operating frequency

Min

–

Typ

–

Max

45

Units Details/Conditions

All modes (TCPWM)

μA

SID.TCPWM.2

ITCPWM2

–

155

650

Fc

SID.TCPWM.2A ITCPWM3

SID.TCPWM.3

TCPWM

MHz

ns

Fc max = CLK_SYS

Maximum = 48 MHz

FREQ

[10]

SID.TCPWM.4

SID.TCPWM.5

TPWM

Input trigger pulse width

2/Fc

–

For all trigger events

ENEXT

EXT

TPWM

Output trigger pulse widths

Minimum possible width

of Overflow, Underflow,

and CC (Counter equals

Compare value) outputs

SID.TCPWM.5A TC

Resolution of counter

PWM resolution

1/Fc

–

Minimum time between

successive counts

RES

SID.TCPWM.5B PWM

Minimum pulse width of

PWM Output

RES

SID.TCPWM.5C

Q

Quadrature inputs resolution

Minimum pulse width

between Quadrature

phase inputs

RES

I²C

[10]

Table 18. Fixed I²C DC Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

–

SID149

I

Block current consumption at

100 kHz

–

1

50

135

310

–

µA

I2C1

–

SID150

SID151

SID152

Block current consumption at

400 kHz

–

I2C2

I2C3

I2C4

Block current consumption at

1 Mbps

2

I C enabled in Deep Sleep mode

[11]

Table 19. Fixed I²C AC Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

–

SID153

F

Bit rate

–

1

Msps

I2C1

Note

10. Guaranteed by characterization.

Document Number: 002-20072 Rev. *I

Page 27 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

SPI

[11]

Table 20. SPI DC Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

SID163

ISPI1

Block current consumption at

1 Mbps

–

360

µA

–

SID164

SID165

ISPI2

ISPI3

Block current consumption at

4 Mbps

–

560

600

Block current consumption at

8 Mbps

[11]

Table 21. SPI AC Specifications

Spec ID#

Parameter

FSPI

Description

Min

Typ

Max

Unit Details/Conditions

SID166

SPI Operating frequency

(Master; 6X Oversampling)

–

8

MHz –

Fixed SPI Master Mode AC Specifications

SID167

SID168

SID169

TDMO

MOSI Valid after SClock driving

edge

–

20

0

–

15

–

ns

–

TDSI

MISO Valid before SClock

capturing edge

Full clock, late MISO

sampling

THMO

Previous MOSI data hold time

–

Referred to Slave

capturing edge

Fixed SPI Slave Mode AC Specifications

SID170

SID171

SID171A

TDMI

MOSI Valid before Sclock

Capturing edge

40

–

42 + (3 × Tcpu)

48

–

TDSO

MISO Valid after Sclock driving

edge

T

= 1/F

CPU CPU

TDSO_EXT

THSO

MISO Valid after Sclock driving

edge in Ext. Clk mode

–

SID172

Previous MISO data hold time

0

–

SID172A

TSSELSSCK SSEL Valid to first SCK Valid

edge

100

UART

[11]

Table 22. UART DC Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

SID160

I

Block current consumption at

100 Kbps

–

55

µA

–

UART1

SID161

Block current consumption at

1000 Kbps

–

312

µA

–

UART2

[11]

Table 23. UART AC Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

SID162

F

Bit rate

–

1

Mbps –

UART

Note

11. Guaranteed by characterization.

Document Number: 002-20072 Rev. *I

Page 28 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

LCD Direct Drive

[12]

Table 24. LCD Direct Drive DC Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

SID154

I

Operating current in low power

mode

–

5

–

µA 16  4 small segment

LCDLOW

disp. at 50 Hz

SID155

C

LCD capacitance per

segment/common driver

–

500

5000

pF

–

LCDCAP

SID156

SID157

LCD

I

Long-term segment offset

–

20

2

–

mV

–

OFFSET

LCD system operating current

Vbias = 5 V

mA 32  4 segments at

LCDOP1

50 Hz 25 °C

SID158

I

LCD system operating current

Vbias = 3.3 V

–

2

–

32  4 segments at

50 Hz 25 °C

LCDOP2

[12]

Table 25. LCD Direct Drive AC Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

SID159

F

LCD frame rate

10

50

150

Hz

–

LCD

Memory

Flash

Table 26. Flash DC Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

SID173

V

Erase and program voltage

1.71

–

5.5

V

PE

Table 27. Flash AC Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

ms

[13]

SID174

T

Row (block) write time (erase and

program)

–

20

Row (block) = 256 bytes

ROWWRITE

[13]

ROWERASE

SID175

SID176

SID178

T

F

Row erase time

–

16

4

–

[13]

Row program time after erase

Bulk erase time (64 KB)

Total device program time

Flash endurance

ROWPROGRAM

[13]

–

35

7

BULKERASE

[12]

[13]

SID180

–

Seconds –

DEVPROG

[12]

SID181

100K

20

–

Cycles

Years

–

END

RET

[12]

SID182

Flash retention. T  55 °C,

100K P/E cycles

–

A

[12]

SID182A

SID182B

–

Flash retention. T  85 °C,

10

–

A

10K P/E cycles

[12]

Flash retention. T  105 °C,

A

10K P/E cycles,  three years at

T ≥ 85 °C

A

SID256

SID257

TWS48

TWS24

Number of Wait states at 48 MHz

2

1

–

CPU execution from

Flash

Number of Wait states at 24 MHz

CPU execution from

Flash

Notes

12. Guaranteed by characterization.

13. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied

on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.

Make certain that these are not inadvertently activated.

Document Number: 002-20072 Rev. *I

Page 29 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

System Resources

Power-on Reset (POR)

Table 28. Power On Reset (PRES)

Spec ID#

Parameter

Description

Min

1

Typ

–

Max

67

Unit Details/Conditions

SID.CLK#6 SR_POWER_UP Power supply slew rate

V/ms At power-up

[14]

SID185

SID186

V

Rising trip voltage

Falling trip voltage

0.80

0.70

–

1.5

1.4

V

–

RISEIPOR

FALLIPOR

[14]

–

Brown-out Detect (BOD)

Table 29. Brown-out Detect (BOD) for V_CCD

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

[14]

SID190

V

BOD trip voltage in active and

sleep modes

1.48

–

1.62

V

–

FALLPPOR

[14]

SID192

V

BOD trip voltage in Deep Sleep

1.11

–

1.5

–

FALLDPSLP

SWD Interface

Table 30. SWD Interface Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

SID213

F_SWDCLK1

3.3 V  V  5.5 V

–

14

MHz SWDCLK ≤ 1/3 CPU

clock frequency

DD

SID214

F_SWDCLK2

1.71 V  V  3.3 V

–

7

SWDCLK ≤ 1/3 CPU

clock frequency

DD

[14]

SID215

T_SWDI_SETUP T = 1/f SWDCLK

T_SWDI_HOLD T = 1/f SWDCLK

T_SWDO_VALID T = 1/f SWDCLK

T_SWDO_HOLD T = 1/f SWDCLK

0.25 × T

–

ns

–

[14]

SID216

0.25 × T

–

0.5 × T

–

[14]

SID217

–

1

[14]

SID217A

Internal Main Oscillator

Table 31. IMO DC Specifications

(Guaranteed by Design)

Spec ID#

Parameter

IMO1

Description

Min

Typ

Max

Unit

Details/Conditions

SID218

I

IMO operating current at 48 MHz

–

250

µA

–

SID219

IMO operating current at 24 MHz

180

µA

IMO2

Table 32. IMO AC Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

SID223

F

Frequency variation at 24, 32,

and 48 MHz (trimmed)

–

±2

%

–

IMOTOL1

SID333

IMO

All IMO settings

–

±0.25

%

IMO variation in

WCO-locked DPLL

mode

WCO

SID226

SID228

T

IMO startup time

–

7

–

µs

ps

–

STARTIMO

RMS jitter at 24 MHz

145

JITRMSIMO2

Notes

14. Guaranteed by characterization.

15. Guaranteed by design.

Document Number: 002-20072 Rev. *I

Page 30 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Internal Low-Speed Oscillator

Table 33. ILO DC Specifications

(Guaranteed by Design)

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

SID231

I

ILO operating current

–

0.3

1.05

µA

–

ILO1

Table 34. ILO AC Specifications

Spec ID#

Parameter

Description

ILO startup time

Min

–

Typ

–

Max

2

Unit

ms

[16]

SID234

T

–

STARTILO1

ILODUTY

[16]

SID236

T

F

ILO duty cycle

40

20

50

40

60

80

%

SID237

ILO frequency range

kHz

ILOTRIM1

Watch Crystal Oscillator (WCO)

Table 35. WCO Specifications

Spec ID#

SID398

SID399

SID400

SID401

SID402

SID403

SID404

SID405

Parameter

FWCO

FTOL

ESR

Description

Crystal frequency

Min

–

Typ

Max

–

Unit

Details/Conditions

32.768

kHz

–

Frequency tolerance

Equivalent series resistance

Drive Level

–

50

–

250

–

ppm With 20-ppm crystal

–

kΩ

µW

ms

pF

–

PD

–

1

TSTART

CL

Startup time

–

500

12.5

–

Crystal Load Capacitance

Crystal Shunt Capacitance

6

–

C0

–

1.35

–

pF

IWCO1

Operating Current (high power

mode)

–

8

µA

–

External Clock

Table 36. External Clock Specifications

Spec ID#

Parameter

ExtClkFreq External clock input frequency

ExtClkDuty Duty cycle; measured at V

Description

Min

0

Typ

–

Max

48

Unit

Details/Conditions

[17]

SID305

MHz –

[17]

SID306

45

–

55

%

–

DD/2

Notes

16. Guaranteed by design.

17. Guaranteed by characterization.

Document Number: 002-20072 Rev. *I

Page 31 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

External Crystal Oscillator and PLL

Table 37. External Crystal Oscillator (ECO) Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

–

[18]

IECO1

External clock input frequency

–

1.5

mA

SID316

[18]

FECO

Crystal frequency range

4

–

33

MHz

SID317

Table 38. PLL Specifications

Spec ID#

SID410

SID411

SID412

SID413

Parameter

IDD_PLL_48

IDD_PLL_24

Fpllin

Description

In = 3 MHz, Out = 48 MHz

In = 3 MHz, Out = 24 MHz

PLL input frequency

Min

–

Typ

530

300

–

Max

610

405

48

Unit

µA

Details/Conditions

–

µA

1

MHz

Fpllint

PLL intermediate frequency;

prescaler out

1

–

3

–

SID414

SID415

Fpllvco

Divvco

VCO output frequency before

post-divide

22.5

1

–

104

8

MHz

VCO Output post-divider range;

PLL output frequency is

Fpplvco/Divvco

–

SID416

SID417

Plllocktime

Jperiod_1

Lock time at startup

–

250

150

200

µs

ps

Period jitter for VCO ≥ 67 MHz

Period jitter for VCO ≤ 67 MHz

Guaranteed by design

SID416A Jperiod_2

System Clock

Table 39. Block Specs

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

[18]

SID262

T

System clock source switching

time

3

–

4

Periods –

CLKSWITCH

Smart I/O

Table 40. Smart I/O Pass-through Time (Delay in Bypass Mode)

Spec ID#

Parameter

Description

Min

Typ

Max

1.6

Unit Details/Conditions

SID252

PRG_BYPASS Max delay added by Smart I/O in

bypass mode

–

ns

–

CAN

Table 41. CAN Specifications

Spec ID#

SID420

Parameter

IDD_CAN

CAN_bits

Description

Block current consumption

CAN Bit rate

Min

Typ

Max

Unit

µA

Mbps Min 8-MHz clock

Details/Conditions

–

200

1

SID421

Note

18. Guaranteed by characterization.

Document Number: 002-20072 Rev. *I

Page 32 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Ordering Information

[19, 20]

Table 42 lists the marketing part numbers (MPNs) for the PSoC 4100S Plus devices

.

Table 42. Ordering Information

4126 CY8C4126LQA-S453

4127 CY8C4127LQA-S443

CY8C4127LQA-S453

4146 CY8C4146LQA-S243

CY8C4146LQA-S253

CY8C4146LQA-S263

CY8C4146LQA-S273

CY8C4146LQA-S453

4147 CY8C4147LQA-S243

CY8C4147LQA-S253

CY8C4147LQA-S263

CY8C4147LQA-S273

CY8C4147LQA-S283

CY8C4147LQA-S293

CY8C4147LQA-S443

CY8C4147LQA-S453

CY8C4147LQA-S463

CY8C4147LQA-S473

4126 CY8C4126AZA-S455

4127 CY8C4127AZA-S445

CY8C4127AZA-S455

4146 CY8C4146AZA-S245

CY8C4146AZA-S255

CY8C4146AZA-S265

CY8C4146AZA-S275

CY8C4146AZA-S455

4147 CY8C4147AZA-S245

CY8C4147AZA-S255

CY8C4147AZA-S265

CY8C4147AZA-S275

CY8C4147AZA-S285

CY8C4147AZA-S295

24

64

8



-

2



2



2



2



X



X



806 Ksps

2

8

4

5

X

24



1



1



1

34

54

X



X



24 128 16

X



806 Ksps

48

64

8

1000 Ksps

806 Ksps



X



X



X



48 128 16



X



X



X



X



X



X



24

64

8

24 128 16

806 Ksps



X



806 Ksps



48

64

8

1000 Ksps



X



X



X



48 128 16



X



X



X



X



Notes

19. Contact Cypress for the availability of Grade-E devices.

20. Contact Cypress for the availability of 40-pin QFN package devices.

Document Number: 002-20072 Rev. *I

Page 33 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Table 42. Ordering Information (continued)

4147 CY8C4147AZA-S445

CY8C4147AZA-S455

48 128 16



2



2



2



2



X



X



1000 Ksps

806 Ksps

2

8

5

4

X

24



1



1



1



1

54

34



X



X



X

CY8C4147AZA-S465



CY8C4147AZA-S475

X



4126 CY8C4126LQS-S453

4127 CY8C4127LQS-S443

CY8C4127LQS-S453

4146 CY8C4146LQS-S243

CY8C4146LQS-S253

CY8C4146LQS-S263

CY8C4146LQS-S273

CY8C4146LQS-S453

4147 CY8C4147LQS-S243

CY8C4147LQS-S253

CY8C4147LQS-S263

CY8C4147LQS-S273

CY8C4147LQS-S283

CY8C4147LQS-S293

CY8C4147LQS-S443

CY8C4147LQS-S453

CY8C4147LQS-S463

CY8C4147LQS-S473

4126 CY8C4126LQE-S453

4127 CY8C4127LQE-S443

CY8C4127LQE-S453

4146 CY8C4146LQE-S243

CY8C4146LQE-S253

CY8C4146LQE-S263

CY8C4146LQE-S273

CY8C4146LQE-S453

4147 CY8C4147LQE-S243

CY8C4147LQE-S253

CY8C4147LQE-S263

CY8C4147LQE-S273

CY8C4147LQE-S283

24

64

8

X



24 128 16

806 Ksps

X



806 Ksps

48

64

8

1000 Ksps

806 Ksps



X



X



X



48 128 16



X



X



X



X



X



X



24

64

8

24 128 16

806 Ksps



X



806 Ksps



48

64

8

1000 Ksps



X



X



X



48 128 16



X



X



X



Document Number: 002-20072 Rev. *I

Page 34 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Table 42. Ordering Information (continued)

CY8C4147LQE-S293

CY8C4147LQE-S443

CY8C4147LQE-S453

CY8C4147LQE-S463

CY8C4147LQE-S473

48 128 16



2



2



2



2



X



X



1000 Ksps

806 Ksps

2

8

4

5

X

24

1



1



1



1



34

54

X



X



4147

X



X



4126 CY8C4126AZS-S455

4127 CY8C4127AZS-S445

CY8C4127AZS-S455

24

64

8

X



24 128 16

806 Ksps



X



806 Ksps



4146 CY8C4146AZS-S245

CY8C4146AZS-S255

48

64

8

1000 Ksps

806 Ksps



X



CY8C4146AZS-S265

X



CY8C4146AZS-S275

X



CY8C4146AZS-S455



4147 CY8C4147AZS-S245

CY8C4147AZS-S255

48 128 16



X



CY8C4147AZS-S265

X



CY8C4147AZS-S275

X



CY8C4147AZS-S285



CY8C4147AZS-S295

X



CY8C4147AZS-S445



CY8C4147AZS-S455

X



CY8C4147AZS-S465



CY8C4147AZS-S475

X



4126 CY8C4126AZE-S455

4127 CY8C4127AZE-S445

CY8C4127AZE-S455

24

64

8

X

24 128 16

806 Ksps



X



806 Ksps



4146 CY8C4146AZE-S245

CY8C4146AZE-S255

48

64

8

1000 Ksps



X



CY8C4146AZE-S265

X



CY8C4146AZE-S275

X



CY8C4146AZE-S455



4147 CY8C4147AZE-S245

CY8C4147AZE-S255

48 128 16



X



CY8C4147AZE-S265

X



CY8C4147AZE-S275

X



Document Number: 002-20072 Rev. *I

Page 35 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Table 42. Ordering Information (continued)

4147 CY8C4147AZE-S285

CY8C4147AZE-S295

CY8C4147AZE-S445

CY8C4147AZE-S455

CY8C4147AZE-S465

CY8C4147AZE-S475

48 128 16



2



X



X

1000 Ksps

2

8

5

X

24

1



1

54



X



X



X

The nomenclature used in the preceding table is based on the following part numbering convention:

Field

Description

Cypress Prefix

Architecture

Family

Values

Meaning

CY8C

4

A

B

4

1

2

PSoC 4

4100 Family

24 MHz

CPU Speed

4

48 MHz

16 KB

32 KB

64 KB

128 KB

C

Flash Capacity

4

5

6

7

DE

F

Package Code

AZ

TQFP (0.5-mm pitch)

QFN

LQ

Temperature Range

A

Automotive (AEC-Q100: –40 °C to +85 °C)

Automotive (AEC-Q100: –40 °C to +105 °C)

Automotive (AEC-Q100: –40 °C to +125 °C)

PSoC 4 S-Series

S

E

S

Silicon Family

S

M

L

PSoC 4 M-Series

PSoC 4 L-Series

BL

PSoC 4 BLE-Series

XYZ

Attributes Code

000-999

Code of feature set in the specific family

Document Number: 002-20072 Rev. *I

Page 36 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

The following is an example of a part number:

Example

CY8C 4 A B C DE F –S XYZ

Cypress Prefix

Architecture

Family within Architecture

CPU Speed

4: PSoC4

2: 4100Family

4: 48 MHz

Flash Capacity

Package Code

5: 32KB

AZ: TQFP

A, S, E: Automotive

Temperature Range

Silicon Family

Attributes Code

Document Number: 002-20072 Rev. *I

Page 37 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Packaging

The PSoC 4100S Plus will be offered in 40-QFN and 64-TQFP packages.

Table 43 provides the package dimensions and Cypress drawing numbers.

Table 43. Package List

Spec ID#

BID27

Package

64-pin TQFP

40-pin QFN

Description

Package Dwg

10 × 10 × 1.6-mm height with 0.5-mm pitch

51-85051

BID27A

6 × 6 × 0.6-mm height with 0.5-mm pitch with wettable flanks

002-25105

Table 44. Package Thermal Characteristics

Parameter

Description

Package

Conditions

Min

–40

Typ

25

Max

85

Unit

TA

Operating ambient

temperature

For A-grade devices

For S-grade devices

For E-grade devices

For A-grade devices

°C

–

25

105

125

25

TJ

Operating junction

temperature

–40

–

100

115

140

–

For S-grade devices

For E-grade devices

–

TJA

TJC

Package θ_JA

Package θ_JC

64-pin TQFP (0.5-mm pitch)

40-pin QFN

–

46

2.8

10

2.8

°C/Watt

–

64-pin TQFP (0.5-mm pitch)

40-pin QFN

–

Table 45. Solder Reflow Peak Temperature

Package

Maximum Peak Temperature

260 °C

Maximum Time at Peak Temperature

All

30 seconds

Table 46. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020

Package

MSL

All

MSL 3

Document Number: 002-20072 Rev. *I

Page 38 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Package Diagram

Figure 7. 64-pin TQFP (10 × 10 × 1.4 mm) Package Outline, 51-85051

51-85051 *D

Document Number: 002-20072 Rev. *I

Page 39 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Figure 8. 40-pin QFN (6 × 6 × 0.6 mm (4.6 × 4.6 mm E-Pad (Sawn))) Package Outline, 002-25105

002-25105 *A

Document Number: 002-20072 Rev. *I

Page 40 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Table 47. Acronyms Used in this Document (continued)

Acronyms

Acronym

FS

Description

Table 47. Acronyms Used in this Document

full-speed

Acronym

abus

Description

general-purpose input/output, applies to a PSoC

GPIO

analog local bus

ADC

analog-to-digital converter

analog global

HVI

IC

high-voltage interrupt, see also LVI, LVD

integrated circuit

AG

AMBA (advanced microcontroller bus

architecture) high-performance bus, an ARM data

transfer bus

IDAC

IDE

current DAC, see also DAC, VDAC

integrated development environment

AHB

ALU

Inter-Integrated Circuit, a communications

protocol

2

arithmetic logic unit

I C, or IIC

AMUXBUS analog multiplexer bus

IIR

infinite impulse response, see also FIR

internal low-speed oscillator, see also IMO

internal main oscillator, see also ILO

integral nonlinearity, see also DNL

input/output, see also GPIO, DIO, SIO, USBIO

initial power-on reset

API

application programming interface

ILO

APSR

application program status register

advanced RISC machine, a CPU architecture

automatic thump mode

IMO

INL

®

ARM

ATM

BW

I/O

bandwidth

IPOR

IPSR

IRQ

ITM

LCD

Controller Area Network, a communications

protocol

CAN

interrupt program status register

interrupt request

CMRR

CPU

common-mode rejection ratio

central processing unit

instrumentation trace macrocell

liquid crystal display

cyclic redundancy check, an error-checking

protocol

CRC

Local Interconnect Network, a communications

protocol.

LIN

DAC

DFB

digital-to-analog converter, see also IDAC, VDAC

digital filter block

LR

link register

LUT

LVD

lookup table

digital input/output, GPIO with only digital capabil-

ities, no analog. See GPIO.

DIO

low-voltage detect, see also LVI

low-voltage interrupt, see also HVI

low-voltage transistor-transistor logic

multiply-accumulate

DMIPS

DMA

DNL

DNU

DR

Dhrystone million instructions per second

direct memory access, see also TD

differential nonlinearity, see also INL

do not use

LVI

LVTTL

MAC

MCU

MISO

NC

microcontroller unit

port write data registers

master-in slave-out

DSI

digital system interconnect

data watchpoint and trace

error correcting code

no connect

DWT

ECC

ECO

NMI

nonmaskable interrupt

non-return-to-zero

NRZ

NVIC

NVL

opamp

PAL

external crystal oscillator

nested vectored interrupt controller

nonvolatile latch, see also WOL

operational amplifier

electrically erasable programmable read-only

memory

EEPROM

EMI

electromagnetic interference

external memory interface

end of conversion

programmable array logic, see also PLD

program counter

EMIF

EOC

EOF

EPSR

ESD

ETM

FIR

PC

PCB

PGA

PHUB

PHY

PICU

PLA

printed circuit board

end of frame

programmable gain amplifier

peripheral hub

execution program status register

electrostatic discharge

physical layer

embedded trace macrocell

finite impulse response, see also IIR

flash patch and breakpoint

port interrupt control unit

programmable logic array

FPB

Document Number: 002-20072 Rev. *I

Page 41 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Table 47. Acronyms Used in this Document (continued)

Acronym

PLD

Description

programmable logic device, see also PAL

phase-locked loop

Acronym

Description

Universal Serial Bus

USB

PLL

USB input/output, PSoC pins used to connect to a

USB port

USBIO

PMDD

POR

package material declaration data sheet

power-on reset

VDAC

WDT

voltage DAC, see also DAC, IDAC

watchdog timer

PRES

PRS

precise power-on reset

WOL

write once latch, see also NVL

watchdog timer reset

external reset I/O pin

crystal

pseudo random sequence

port read data register

WRES

XRES

XTAL

PS

®

PSoC

Programmable System-on-Chip™

power supply rejection ratio

pulse-width modulator

PSRR

PWM

RAM

RISC

RMS

RTC

RTL

random-access memory

reduced-instruction-set computing

root-mean-square

real-time clock

register transfer language

remote transmission request

receive

RTR

RX

SAR

SC/CT

SCL

successive approximation register

switched capacitor/continuous time

2

I C serial clock

2

SDA

S/H

I C serial data

sample and hold

SINAD

signal to noise and distortion ratio

special input/output, GPIO with advanced

features. See GPIO.

SIO

SOC

SOF

start of conversion

start of frame

Serial Peripheral Interface, a communications

protocol

SPI

SR

slew rate

SRAM

SRES

SWD

SWV

TD

static random access memory

software reset

serial wire debug, a test protocol

single-wire viewer

transaction descriptor, see also DMA

total harmonic distortion

transimpedance amplifier

technical reference manual

transistor-transistor logic

transmit

THD

TIA

TRM

TTL

TX

Universal Asynchronous Transmitter Receiver, a

communications protocol

UART

UDB

universal digital block

Document Number: 002-20072 Rev. *I

Page 42 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Document Conventions

Units of Measure

Table 48. Units of Measure

Symbol

°C

Unit of Measure

degrees Celsius

decibel

dB

fF

femto farad

hertz

Hz

KB

kbps

Khr

kHz

k

1024 bytes

kilobits per second

kilohour

kilohertz

kilo ohm

ksps

LSB

Mbps

MHz

M

Msps

µA

kilosamples per second

least significant bit

megabits per second

megahertz

mega-ohm

megasamples per second

microampere

microfarad

µF

µH

microhenry

microsecond

microvolt

µs

µV

µW

mA

ms

mV

nA

microwatt

milliampere

millisecond

millivolt

nanoampere

nanosecond

nanovolt

ns

nV



ohm

pF

picofarad

ppm

ps

parts per million

picosecond

second

s

sps

sqrtHz

V

samples per second

square root of hertz

volt

Document Number: 002-20072 Rev. *I

Page 43 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Document History Page

Description Title: Automotive PSoC^®4: PSoC 4100S Plus Datasheet Programmable System-on-Chip (PSoC)

Document Number: 002-20072

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

*G

*H

6566447

6597972

SNPR

05/03/2019 Changed status from Preliminary to Final.

06/21/2019 Added 40-pin QFN package related information in all instances across the

document.

Updated Pinouts:

Updated Table 1.

Updated Ordering Information:

Updated part numbers.

Added Note 20 and referred the same note in description above table.

Updated Packaging:

Added spec 002-25105 *A.

Updated to new template.

*I

6613804

SNPR

07/04/2019 Updated Pinouts:

Updated Table 1 (Fixed typo).

Updated to new template.

Document Number: 002-20072 Rev. *I

Page 44 of 45

Automotive PSoC^®4:

PSoC 4100S Plus Datasheet

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

®

Arm Cortex Microcontrollers

Automotive

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU

Cypress Developer Community

Clocks & Buffers

Interface

Technical Support

Internet of Things

Memory

cypress.com/support

cypress.com/memory

cypress.com/mcu

Microcontrollers

PSoC

cypress.com/psoc

Power Management ICs

Touch Sensing

USB Controllers

Wireless Connectivity

cypress.com/pmic

cypress.com/touch

cypress.com/usb

cypress.com/wireless

firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress

reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property

rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants

you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce

the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or

indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by

Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the

Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing

device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such

as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING

CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, "Security

Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In

addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted

by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or

circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the

responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device"

means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other

medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk

Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of

a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from

and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress

product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)

Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to

use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-20072 Rev. *I

Revised July 4, 2019

Page 45 of 45


型号：	CY8C4146LQS-S263
厂家：	CYPRESS
描述：	Multifunction Peripheral,
文件：	总45页 (文件大小：864K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C4146LQS-S263 [CYPRESS]

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