CY93C16-SXIT [CYPRESS]

EEPROM, 16KX8, Serial, CMOS, PDSO8, LEAD FREE, SOIC-8;


型号：	CY93C16-SXIT
厂家：	CYPRESS
描述：	EEPROM, 16KX8, Serial, CMOS, PDSO8, LEAD FREE, SOIC-8 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件：	总16页 (文件大小：646K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY93C01/02/04/08/16

1 Kbit, 2 Kbit, 4 Kbit, 8 Kbit, and 16 Kbit

(x8 or x16) MicroWire Serial EEPROM

Features

Functional Description

■ Continuous voltage operation

❐ V_CC= 1.65V to 5.5V

The CY93C01/02/04/08/16 provides 1K, 2K, 4K, 8K, and 16K

bits of serial Electrically Erasable and Programmable Read Only

Memory (EEPROM). The memory is organized as x16 when the

ORG pin is connected to V_CCand as x8 when it is tied to ground.

The device is optimized for use in many industrial applications,

where low power and low voltage operations are essential. The

CY93C01/02/04/08/16 is available in space saving 8-Pin SOIC,

and 8-Pin TSSOP packages. The CY93C01/02/04/08/16 is

■ Internally organized as x8 or x16

■ Industry standard three wire serial interface

■ Schmitt trigger, filtered inputs for noise suppression

■ Programming instructions that work on byte, word, or entire

enabled through the Chip Select pin (CS), and accessed through

a three wire serial interface consisting of Data Input (DI), Data

Output (DO), and Serial Clock (SK). On receiving a read

instruction at DI, the address is decoded and the data is clocked

out serially on the data output pin DO. The write cycle is

completely self timed and no separate erase cycle is required

before write. The write cycle is enabled only when the part is in

the erase or write enable state. When CS is brought high

following the initiation of a write cycle, the DO pin outputs the

Ready/Busy status of the part. The CY93C01/02/04/08/16 is

available in a 1.65V to 5.5V version.

memory

■ Sequential read operation

■ 4 MHz clock rate (5V) compatibility

■ Self timed write cycle (5 ms max)

■ Ready/Busy signal during programming

■ Industrial temperature range

■ High reliability

❐ Endurance: 1 million write cycles

❐ Data retention: 100 years

■ RoHS compliant 8-Pin SOIC and 8-Pin TSSOP packages

■ Pb-free and RoHS compliant

Logic Block Diagram

V_CC

ORG

CY93CXX

V_SS

Cypress Semiconductor Corporation

Document #: 001-15635 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 05, 2009

[+] Feedback

CY93C01/02/04/08/16

Pinouts

Figure 1. Pin Diagram: 8-Pin SOIC/TSSOP Package

Top View

(not to scale)

ORG

GND

Table 1. Pin Definition - 8-SOIC/TSSOP

8-SOIC

Pin Name

8-TSSOP

Pin Number

I/O Type

Description

Pin Number

Input

Output

Input

Chip Select

Serial Clock

Serial Data Input

Serial Data Output

Ground

Internal Organization^[1]

No Connect^[2]

GND

ORG

V_CC

Input

Power Supply

Notes

1. When the ORG is connected to Vcc, the x16 organization is selected. When it is connected to ground, the x8 organization is selected. If the ORG pin is left unconnected

and the application does not load the input beyond the capability of the internal 1Meg ohm pull up, then the x16 organization is selected.

2. The NC pin does not contribute to the normal operation of the device. The pin may be left unconnected or may be connected to Vcc or GND. Direct connection of NC

to GND is recommended for lowest standby power consumption.

Document #: 001-15635 Rev. *C

Page 2 of 16

[+] Feedback

CY93C01/02/04/08/16

Write

Device Operating Features

The Write (WRITE) instruction contains 8 or 16 bits of data to be

written into the specified memory location. The self timed

programming cycle t_WCstarts after the last bit of data is received

at serial data input pin DI. The DO pin outputs the Ready/Busy

status of the part if CS is brought high after being kept low for a

minimum of 100 ns (t_CE). A logic ‘0’ at DO indicates that

programming is still in progress. A logic ‘1’ indicates that the

memory location at the specified address is written with the data

pattern contained in the instruction and the part is ready for

further instructions. A Ready/Busy status is not obtained if the

CS is brought high after the end of the self timed programming

Internal Device Reset

To prevent inadvertent write operations during power up, a

Power On Reset (POR) circuit is included.

During power up and power down, the device must not be

selected (that is, the Chip Select Input (CS) must be driven low)

until the supply voltage reaches the operating voltage V_CC

During power up (the phase during which V_CCis lower than the

minimum V_CC, but increases continuously), the device does not

respond to any instruction until V_CChas reached the POR

threshold voltage (this threshold is lower than the minimum V_CC

operating voltage defined in DC Electrical Characteristics on

page 9). After V_CChas passed the POR threshold, the device is

reset.

cycle t_WC

An internal power on data protection mechanism in the CY93C02

inhibits the device when the supply is too low.

Erase

Before selecting the memory and issuing instructions to it, a valid

and stable V_CCvoltage is applied. This voltage must remain

stable and valid until the end of transmission of the instruction

and, for a write instruction, until the completion of the internal

write cycle (t_WC).

The Erase (ERASE) instruction programs all bits in the specified

memory location to the logical ‘1’ state. The self timed erase

cycle starts after the ERASE instruction and address are

decoded. The DO pin outputs the Ready/Busy status of the part

if CS is brought high after being kept low for a minimum of 100

ns (t_CE). A logic ‘1’ at pin DO indicates that the selected memory

location is erased, and the part is ready for another instruction.

During power down (the phase during which V_CCdecreases

continuously), as soon as V_CCdrops from the normal operating

voltage below the POR threshold voltage, the device stops

responding to any instruction sent to it.

Erase/Write Enable (EWEN)

Active and Standby Power Modes

To assure data integrity, the part automatically goes into the

Erase/Write Disable (EWDS) state when power is first applied.

An Erase/Write Enable (EWEN) instruction must be executed

first before any programming instruction is carried out. Note that

in the EWEN state, programming remains enabled until an

EWDS instruction is executed or V_CCpower is removed from the

part.

When Chip Select (CS) is high, the device is selected and in the

active power mode. It consumes I_CC, as specified in

DC Electrical Characteristics on page 9. When Chip Select (CS)

is low, the device is deselected.

If no erase or write cycle is in progress when Chip Select goes

low, the device enters the standby power mode and the power

consumption drops to I_SB1

Erase All (ERAL)

The Erase All (ERAL) instruction programs every bit in the

memory array to the logic ‘1’ state and is primarily used for

testing purposes. The DO pin outputs the Ready/Busy status of

the part if CS is brought high after being kept low for a minimum

of 100 ns (t_CE).

Device Operations

The CY93C02 is accessed through a simple and versatile three

wire serial communication interface. Device operation is

controlled by seven instructions issued by the host processor. A

valid instruction starts with a rising edge of CS and consists of a

Start Bit (logic ‘1’) followed by the appropriate op-code and the

desired memory address location.

Write All (WRAL)

The Write All (WRAL) instruction programs all memory locations

with the data patterns specified in the instruction. The DO pin

outputs the Ready/Busy status of the part if CS is brought high

after being kept low for a minimum of 100 ns (t_CE).

Read

The Read (READ) instruction contains the address code for the

memory location to be read. After the instruction and address are

decoded, data from the selected memory location is available at

the serial output pin DO. Output data changes are synchronized

with the rising edges of serial clock SK. Note that a dummy bit

(logic ‘0’) precedes the 8-bit or 16-bit data output string. The

CY93C02 supports sequential read operations. The device

automatically increments the internal address pointer and clocks

out the next memory location as long as CS is held high. In this

case, the dummy bit (logic ‘0’) is not clocked out between

memory locations, therefore enabling a continuous stream of

data to be read.

Erase/Write Disable (EWDS)

To protect against accidental data disturbance, the Erase/Write

Disable (EWDS) instruction disables all programming modes

and is executed after all programming operations. The operation

of the READ instruction is independent of both the EWEN and

EWDS instructions and is executed at any time.

Document #: 001-15635 Rev. *C

Page 3 of 16

[+] Feedback

CY93C01/02/04/08/16

Table 2. Instruction Set for CY93C01 ^[3]

Instruction Start Bit Opcode

Address

Data

Comments

x16

READ

ERASE

WRITE

EWEN

EWDS

ERAL

A6–A0

A5–A0

Read Address AN–A0

Clear Address AN–A0

A5–A0

D7–D0

D15–D0

Write Address AN–A0

Write Enable

11XXXXX

00XXXXX

10XXXXX

01XXXXX

11XXXX

00XXXX

10XXXX

01XXXX

Write Disable

Clear All Address

Write All Address

WRAL

D7–D0

Table 3. Instruction Set for CY93C02 and CY93C04 ^[3]

Address

Data

Instruction Start Bit Opcode

Comments

x16

READ

ERASE

WRITE

EWEN

EWDS

ERAL

A8^[4]–A0

A7^[5]–A0

Read Address AN–A0

Clear Address AN–A0

Write Address AN–A0

Write Enable

D7–D0

D15–D0

11XXXXXXX

00XXXXXXX

10XXXXXXX

01XXXXXXX

11XXXXXX

00XXXXXX

10XXXXXX

01XXXXXX

Write Disable

Clear All Address

Write All Address

WRAL

D7–D0

D15–D0

Table 4. Instruction Set for CY93C08 and CY93C16 ^[3]

Address

Data

Instruction Start Bit Opcode

Comments

x16

READ

ERASE

WRITE

EWEN

EWDS

ERAL

A10^[6]–A0

A9^[7]–A0

Read Address AN–A0

Clear Address AN–A0

Write Address AN–A0

Write Enable

D7–D0

D15–D0

11XXXXXXXXX 11XXXXXXXX

00XXXXXXXXX 00XXXXXXXX

10XXXXXXXXX 10XXXXXXXX

01XXXXXXXXX 01XXXXXXXX

Write Disable

Clear All Address

Write All Address

WRAL

D7–D0

D15–D0

Notes

3. X = Do not care bit.

4. Address bit A8 is not decoded by CY93C02.

5. Address bit A7 is not decoded by CY93C02.

6. Address bit A10 is not decoded by CY93C08.

7. Address bit A9 is not decoded by CY93C08.

Document #: 001-15635 Rev. *C

Page 4 of 16

[+] Feedback

CY93C01/02/04/08/16

circuit current from flowing when the last address bit (A0) clashes

with the first data bit on Serial Data Output (DO).

Ready/Busy Status

While the Write or Erase cycle is underway, for a WRITE,

ERASE, WRAL or ERAL instruction, the Busy signal (DO=0) is

returned whenever Chip Select input (CS) is driven high. In this

state, the CY93C02 ignores any data on the bus. When the write

cycle is completed, and Chip Select input (CS) is driven high, the

Ready signal (DO=1) indicates that the CY93C02 is ready to

receive the next instruction. Serial Data Output (DO) remains set

to 1 until the Chip Select Input (CS) is brought low or until a new

start bit is decoded.

Clock Pulse Counter

In a noisy environment, the number of pulses received on Serial

Clock (SK) may be greater than the number delivered by the

master (the microcontroller). This leads to a misalignment of the

instruction of one or more bits, as shown in Figure 8 on page 8,

and may lead to the writing of erroneous data at an erroneous

address. To combat this problem, the CY93C02 has an on-chip

counter that counts the clock pulses from the start bit until the

falling edge of the Chip Select input (CS). If the number of clock

pulses received is not the number expected, the WRITE,

ERASE, ERAL, or WRAL instruction is aborted and the contents

of the memory are not modified.

Common I/O Operation

Serial Data Output (DO) and Serial Data Input (DI) are connected

together, through a current limiting resistor, to form a common,

single wire data bus. Some precautions must be taken when

operating the memory in this way, mostly to prevent a short

Figure 2. Read Instruction Timing

Figure 3. Erase Enable/Disable Instruction Timing

Document #: 001-15635 Rev. *C

Page 5 of 16

[+] Feedback

CY93C01/02/04/08/16

Figure 4. Write Instruction Timing

tCS

t_CE

tHZCE

tLZCE

tWC

Figure 5. Write All Instruction Timing

tCE

tHZCE

tLZCE

tWC

Document #: 001-15635 Rev. *C

Page 6 of 16

[+] Feedback

CY93C01/02/04/08/16

Figure 6. Erase Instruction Timing

tCE

tHZCE

tLZCE

tWC

Figure 7. Erase All Instruction Timing

tCE

tHZCE

tLZCE

tWC

Document #: 001-15635 Rev. *C

Page 7 of 16

[+] Feedback

CY93C01/02/04/08/16

Figure 8. Write Sequence with One Clock Glitch

Document #: 001-15635 Rev. *C

Page 8 of 16

[+] Feedback

CY93C01/02/04/08/16

Package power dissipation

capability (T_A= 25°C).................................................... 1.0W

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Surface mount lead soldering

Temperature (3 Seconds)..................+260°C for 10 seconds

Output short circuit current^[8]....................................... 50 mA

Storage temperature .................................. –65°C to +150°C

Ambient temperature with

power applied............................................. –55°C to +125°C

Static discharge voltage........................................... > 2001V

(per MIL-STD-883, Method 3015)

Supply voltage on V_CCrelative to GND..........–1.0V to +6.0V

Latch up current .................................................... > 200 mA

DC voltage applied to outputs

in high-Z state........................................ –0.5V to V_CC+ 1.0V

Operating Range

Range

Industrial

Ambient Temperature

V_CC

Input voltage.......................................... –0.5V to V_CC+ 0.5V

–40°C to +85°C

1.65V to 5.5V

Transient voltage (<20 ns) on

any pin to ground potential.................... –1.0V to V_CC+ 2.0V

DC Electrical Characteristics

Over the Operating Range (V_CC= 1.65V to 5.5V)

Parameter

V_CC1

Description

Supply Voltage

Test Conditions

V_CC= 1.65V, CS = V_CC

Min

Max

Unit

1.65

5.5

I_SB1

I_SB2

I_SB3

I_CC1

I_CC2

I_LI

Standby Current

μA

Standby Current

V_CC= 2.7V, CS = V_CC

V_CC= 5.5V, CS = V_CC

V_CC= 5.5V at 4 MHz

V_CC= 5.5V

1.1

Standby Current

1.2

Supply Current (Read)

Supply Current (Write)

Input Leakage Current

Output Leakage Current

Input LOW Voltage

V_IN= V_CCor V_SS

I_LO

V_IN= V_CCor V_SS

V_IL

1.65V < V_CC< 2.7V

2.7V < V_CC< 5.5V

1.65V < V_CC< 5.5V

I_OL= 2.1 mA, 2.7 < V_CC< 5.5V

–0.6 ^[9]

0.3 V_CC

0.8

V_CC+ 0.5 ^[9]

V_IH

Input HIGH Voltage

Output LOW Voltage

0.7 V_CC

V_OL

0.4

0.2

I_OL= 0.15 mA, 1.65 < V_CC< 2.7V

V_OH

Output HIGH Voltage

I_OH= -0.1 mA, 1.65 < V_CC< 2.7V

I_OH= -0.4 mA, 2.7 < V_CC< 5.5V

V_CC– 0.2

2.4

Capacitance

In the following table, the capacitance parameters are listed. ^[10]

Parameter

C_IN

Description

Input Capacitance

Test Conditions

T_A= 25°C, f = 1 MHz,

_CC= 1.65V

Max

Unit

C_OUT

Output Pin Capacitance

Thermal Resistance

In the following table, the thermal resistance parameters are listed. ^[10]

Parameter

Description

Test Conditions

8-SOIC 8-TSSOP

Unit

Θ_JA

Thermal Resistance

(Junction to Ambient)

Test conditions follow standard test methods and

procedures for measuring thermal impedance, per EIA

/ JESD51.

120.83

119.31

°C/W

Θ_JC

Thermal Resistance

(Junction to Case)

90.31

82.77

°C/W

Notes

8. Outputs shorted for only one second. Only one output shorted at a time.

9. This parameter is characterized but not tested.

10. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Document #: 001-15635 Rev. *C

Page 9 of 16

[+] Feedback

CY93C01/02/04/08/16

Reliability Characteristics

In the following table, the reliability characteristics parameters are listed. ^[10]

Parameter

Description

Endurance

Test Method

JEDEC Standard A117

JEDEC Standard A103

JEDEC Standard 78

Min

1 Million

100

Unit

Cycles

Years

N_END

T_DR

Data Rentention

Latch Up

I_LTH

100 + I_CC

Figure 9. AC Test Loads and Waveforms

OUTPUT

Parameters

1.65V - 2.7V

2.7V - 5.5V

1.8K

Unit

C_L

1.8K

1.3K

ohm

1.3K

100

Figure 10. AC Input/Output Reference Waveforms

V_IHT

V_ILT

V_HT

V_LT

V_HT

V_LT

OUTPUT

REFERENCE POINTS

INPUT

AC test inputs are driven at V_IHT(0.9V_CC) for a logic ‘1’ and V_ILT(0.1V_CC) for a logic ‘0’. Measurement reference points for inputs and

outputs are V_LT(V_CC/2 - 0.1V) and V_HT(V_CC/2 + 0.1V). Input rise and fall times (10%–90%) are <3.3 ns.

Document #: 001-15635 Rev. *C

Page 10 of 16

[+] Feedback

CY93C01/02/04/08/16

AC Switching Characteristics

Over the Operating Range (V_CC= 1.65V–5.5V)

4 MHz

3 Mhz

2 Mhz

1 Mhz

Cypress

Alt

Description

Clock Frequency

Unit

Parameter Parameter

Min Max

Min

Max

Min Max Min Max

f_SK

100

MHz

t_CL

t_SKLO

t_SKHI

t_CS

Clock Pulse Width Low

Clock Pulse Width High

Minimum CS Low Time

Output Valid

130

200

400

t_CH

t_CE

t_LZCE

t_CES

t_CEH

t_SD

t_SV

130

200

400

t_CSS

t_CSH

t_DIS

t_DIH

t_PD1

t_PD0

t_HZ

CS Setup Time

CS Hold Time

Data In Setup Time

Data In Hold Time

Output Delay to 1

Output Delay to 0

CS to Data Out in High Impedance

Write Cycle Time

100

t_HD

t_CO2

t_CO1

t_HZCE

t_WC

t_F

100

130

150

200

150

400

150

t_WP

t_F

Input Fall Time

t_R

Input Rise Time

Figure 11. Synchronous Data Timing

tCEH

tCL

tCH

tHD

tSD

tCES

tCO1, tCO2

tSD

tCE

Document #: 001-15635 Rev. *C

Page 11 of 16

[+] Feedback

CY93C01/02/04/08/16

Part Numbering Nomenclature

CY93 C 01 - SX

I T

Option:

T = Tape & Reel

Blank = Std.

Temperature:

I = Industrial (–40 to 85°C)

X = Pb-Free

Package:

S = SOIC

Z = TSSOP

Density:

01 = 1 Kb

02 = 2 Kb

04 = 4 Kb

08 = 8 Kb

16 = 16 Kb

Voltage:

C = 1.65V - 5.5V

93 =MicroWire Interface

Cypress

Ordering Information

Package

Diagram

Operating

Range

Density

Ordering Code

Package Type

1 Kbit

CY93C01-SXI

CY93C01-SXIT

CY93C01-ZXI

CY93C01-ZXIT

CY93C02-SXI

CY93C02-SXIT

CY93C02-ZXI

CY93C02-ZXIT

CY93C04-SXI

CY93C04-SXIT

CY93C04-ZXI

CY93C04-ZXIT

CY93C08-SXI

CY93C08-SXIT

CY93C08-ZXI

CY93C08-ZXIT

CY93C16-SXI

CY93C16-SXIT

CY93C16-ZXI

CY93C16-ZXIT

51-85066 8-Pin SOIC

Industrial

8-Pin SOIC (Tape & Reel)

51-85093 8-Pin TSSOP

8-Pin TSSOP (Tape & Reel)

51-85066 8-Pin SOIC

8-Pin SOIC (Tape & Reel)

51-85093 8-Pin TSSOP

8-Pin TSSOP (Tape & Reel)

51-85066 8-Pin SOIC

8-Pin SOIC (Tape & Reel)

51-85093 8-Pin TSSOP

8-Pin TSSOP (Tape & Reel)

51-85066 8-Pin SOIC

8-Pin SOIC (Tape & Reel)

51-85093 8-Pin TSSOP

8-Pin TSSOP (Tape & Reel)

51-85066 8-Pin SOIC

8-Pin SOIC (Tape & Reel)

51-85093 8-Pin TSSOP

8-Pin TSSOP (Tape & Reel)

2 Kbit

4 Kbit

8 Kbit

16 Kbit

Above table contains Preliminary information. Please contact your local Cypress sales representative for availability of these parts.

Document #: 001-15635 Rev. *C

Page 12 of 16

[+] Feedback

CY93C01/02/04/08/16

Package Diagrams

Figure 12. 8-Pin (150-Mil) SOIC, 51-85066

PIN 1 ID

1. DIMENSIONS IN INCHES[MM] MIN.

MAX.

2. PIN 1 ID IS OPTIONAL,

ROUND ON SINGLE LEADFRAME

0.150[3.810]

0.157[3.987]

RECTANGULAR ON MATRIX LEADFRAME

3. REFERENCE JEDEC MS-012

4. PACKAGE WEIGHT 0.07gms

0.230[5.842]

0.244[6.197]

PART #

S08.15 STANDARD PKG.

SZ08.15 LEAD FREE PKG.

0.189[4.800]

0.196[4.978]

0.010[0.254]

0.016[0.406]

X 45°

SEATING PLANE

0.061[1.549]

0.068[1.727]

0.004[0.102]

0.050[1.270]

BSC

0.0075[0.190]

0.0098[0.249]

0.004[0.102]

0.0098[0.249]

0°~8°

0.016[0.406]

0.035[0.889]

0.0138[0.350]

0.0192[0.487]

51-85066-*C

Document #: 001-15635 Rev. *C

Page 13 of 16

[+] Feedback

CY93C01/02/04/08/16

Package Diagrams (continued)

Figure 13. 8-Pin (4.4 mm) TSSOP, 51-85093

51-85093-*A

Document #: 001-15635 Rev. *C

Page 14 of 16

[+] Feedback

CY93C01/02/04/08/16

Document History Page

Document Title: CY93C01/02/04/08/16, 1 Kbit, 2 Kbit, 4 Kbit, 8 Kbit, and 16 Kbit (x8 or x16) MicroWire Serial EEPROM

Document Number: 001-15635

Revision

ECN No.

Orig. of

Change

Submission

Date

Description of Change

1069220

2522135

UHA

See ECN

06/27/08

New Data Sheet

GVCH/PYRS

Added Pb-Free and RoHS Compliant information in Features

Removed PDIP package

Removed Automotive Temperature range

Changed Supply voltage on V_CCrelative to GND max value from 5.0V to

6.0V

Corrected Typo of Vcc max value from 5.0V to 5.5V

Added AC test load values for different parameters

Table 10: Updated AC Switching Characteristics

Table 8: Added Thermal Resistance values for 8-TSSOP packages

Table 9: Changed T_DRvalue from 20 to 100 years

Updated Part Numbering Nomenclature and Ordering Information

2611873

2656511

VKN/PYRS

VKN/AESA

11/24/08

02/09/09

Updated Part numbering nomenclature

Updated Ordering information table

Changed part# from CY93C46/56/66/76/86 to CY93C01/02/04/08/16

Converted from preliminary to final

Included V_ILspec of 0.8V for the V_CCrange between 2.7V to 5.5V

Updated V_IHtest conditions

Added footnote #9

Updated V_OLand V_OHtest conditions

On page 10, Specified V_CCrange for AC test load conditions

On page 10, corrected AC measurement reference points from V_ITand

_OTto V_LTand V_HTrespectively

Changed V_LTlevel from 0.3V_CCto V_CC/2 - 0.1V

Changed V_HTlevel from 0.7V_CCto V_CC/2 + 0.1V

Document #: 001-15635 Rev. *C

Page 15 of 16

[+] Feedback

CY93C01/02/04/08/16

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at cypress.com/sales.

Products

PSoC

PSoC Solutions

General

psoc.cypress.com

clocks.cypress.com

wireless.cypress.com

memory.cypress.com

image.cypress.com

psoc.cypress.com/solutions

psoc.cypress.com/low-power

psoc.cypress.com/precision-analog

psoc.cypress.com/lcd-drive

psoc.cypress.com/can

Clocks & Buffers

Wireless

Low Power/Low Voltage

Precision Analog

LCD Drive

Memories

Image Sensors

CAN 2.0b

USB

psoc.cypress.com/usb

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used

for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use

as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support

systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 001-15635 Rev. *C

Revised February 05, 2009

Page 16 of 16

All products and company names mentioned in this document may be the trademarks of their respective holders.

[+] Feedback

CY93C16-SXIT [CYPRESS]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E