CYD04S18V18 [CYPRESS]
18-Mb/9-Mb/4-Mb x36/x18 FullFlex⑩ Dual-Ports; 18 -MB / 9 -MB / 4 -MB X36 / X18 FullFlex⑩双端口
| 型号： | CYD04S18V18 |
| 厂家： | 
CYPRESS |
| 描述： | 18-Mb/9-Mb/4-Mb x36/x18 FullFlex⑩ Dual-Ports |
| 文件： | 总2页 (文件大小：64K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CONFIDENTIAL
CYDxxS36V18
CYDxxS18V18
ERRATA DOCUMENT
Errata Revision: **
March 15, 2006
Errata Document for CYDxxS36V18/CYDxxS18V18 18-Mb/9-Mb/4-Mb x36/x18 FullFlex™ Dual-Ports
This document describes the errata for the 18Mb/9Mb/4Mb x36/x18 FullFlex™ Dual-Ports (CYDxxS36V18/CYDxxS18V18).
Details include errata trigger conditions, available workarounds, and silicon revision applicability. This document should be used
to compare to the data sheet for this device to fully describe the device functionality. Please contact your local Cypress Sales
Representative if you have further questions.
Part Numbers Affected
Part Number
CYD18S36V18
CYD09S36V18
CYD04S36V18
CYD18S18V18
CYD09S18V18
CYD04S18V18
Package
Device Characteristics
All speed grades
All speed grades
All speed grades
All speed grades
All speed grades
All speed grades
Product Status
Sampling
Sampling
Sampling
Sampling
Sampling
Sampling
256-Ball FBGA
256-Ball FBGA
256-Ball FBGA
256-Ball FBGA
256-Ball FBGA
256-Ball FBGA
18-Mb/9-Mb/4-Mb x36/x18 FullFlex Dual-Ports Errata Summary
The ZQ0 and ZQ1 pins on both ports (left and right) are internally shorted in the 256-Ball FBGA package substrate design. This
creates an error in the Variable Impedance Matching (VIM) feature on the FullFlex Dual-Ports, as the effective output driver
impedance is halved when both resistors are populated. The workaround is to remove the resistors on ZQ1L and ZQ1R for the
affected devices.
Variable Impedance Matching (VIM)
• PROBLEM DEFINITION
The 256-Ball FBGA package substrate design has the ZQ0L pin shorted to ZQ1L and ZQ0R shorted to ZQ1R. The ZQ1L and
ZQ1R pins are not internally connected to the die for the affected devices; therefore, when resistors are connected to these
pins to ground, the effective output driver impedance for each port is halved.
• PARAMETERS AFFECTED
Effective output driver impedance controlled by the VIM circuitry.
• TRIGGER CONDITION(S)
If the designer populates resistors for both ZQ0 and ZQ1, the short between ZQ0 and ZQ1 halves the effective impedance
seen by the VIM calibrating circuitry.
• SCOPE OF IMPACT
Output driver impedance is halved, as the two VIM calibrating resistors are in parallel to ground.
• WORKAROUND
Remove ZQ1L and ZQ1R VIM resistors. Disconnecting these two resistors and leaving the pins open allow the calibrating
circuitry to set the correct output driver impedance.
• FIX STATUS
The date for the substrate design fix is TBD.
References
1. Document # 38-06072, FullFlex Synchronous DDR Dual-Port SRAM
2. Document # 38-06082, FullFlex Synchronous SDR Dual-Port SRAM
Cypress Semiconductor Corporation
Document #: 001-07077 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 28, 2006
CONFIDENTIAL
ERRATA DOCUMENT
CYDxxS36V18
CYDxxS18V18
Document History Page
Document Title: Errata Document for CYDxxS36V18/CYDxxS18V18 18-Mb/9-Mb/4-Mb x36/x18 FullFlex™ Dual-Ports
Document Number: 001-07077
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
435564
See ECN
YDT
Original release of spec
Document #: 001-07077 Rev. **
Page 2 of 2
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