CYDD18S72V18-200BBXC [CYPRESS]
Dual-Port SRAM, 256KX72, 9ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-484;
| 型号： | CYDD18S72V18-200BBXC |
| 厂家： | 
CYPRESS |
| 描述： | Dual-Port SRAM, 256KX72, 9ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-484 静态存储器 |
| 文件： | 总48页 (文件大小：1053K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
FullFlex™ Synchronous
DDR Dual-Port SRAM
— Selectable LVTTL (3.3V), Extended HSTL
(1.4V–1.9V), 1.8V LVCMOS, or 2.5V LVCMOS I/O on
each port
Features
• True dual-ported memory allows simultaneous access
to the shared array from each port
— Burst counters for sequential memory access
— Mailbox with interrupt flags for message passing
— Dual Chip Enables for easy depth expansion
• Synchronous pipelined operation with selectable
Double Data Rate (DDR) or Single Data Rate (SDR)
operation on each port
— DDR SRAM interface (data transferred at 400 Mbps)
Functional Description
@ 200 MHz
The FullFlex Dual-Port SRAM families consist of 4-Mbit,
9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual-port static
RAMs that are high-speed, low-power 1.8V/1.5V CMOS. Two
ports are provided, allowing the array to be accessed simulta-
neously. Simultaneous access to a location triggers determin-
istic access control. For FullFlex72, these ports can operate
independently in DDR mode with 36-bit bus widths or in SDR
mode with 72-bit bus widths. For FullFlex36 and FullFlex18,
the ports operate in DDR mode only. Each port can be
independently configured for two pipeline stages for SDR
mode or 2.5 stages in DDR mode. Each port can also be
configured to operate in pipeline or flow-through mode in SDR
mode.
Advanced features include built-in deterministic access
control to manage address collisions during simultaneous
access to the same memory location, variable impedance
Matching (VIM) to improve data transmission by matching the
output driver impedance to the line impedance, and echo
clocks to improve data transfer.
— SDR interface at 250 MHz
— Up to 36-Gb/s bandwidth (250 MHz * 72 bit * 2 ports)
• Selectable pipeline or flow-through mode
• Selectable 1.5V or 1.8V core power supply
• Commercial and Industrial temperature ranges
• IEEE 1149.1 JTAG boundary scan
• Available in 484-ball PBGA Packages and 256-ball
FBGA Packages
• FullFlex72 family
— 36 Mbit: 512K x 72 (CYDD36S72V18)
— 18 Mbit: 256K x 72 (CYDD18S72V18)
— 9 Mbit: 128K x 72 (CYDD09S72V18)
— 4 Mbit: 64K x 72 (CYDD04S72V18)
• FullFlex36 family
— 36 Mbit: 512K x 72 (CYDD36S36V18)
— 18 Mbit: 256K x 72 (CYDD18S36V18)
— 9 Mbit: 128K x 72 (CYDD09S36V18)
— 4 Mbit: 64K x 72 (CYDD04S36V18)
• FullFlex18 family
— 36 Mbit: 1M x 36 (CYDD36S18V18)
— 18 Mbit: 512K x 36 (CYDD18S18V18)
— 9 Mbit: 256K x 36 (CYDD09S18V18)
— 4 Mbit: 128K x 36 (CYDD04S18V18)
To reduce the static power consumption, chip enables can be
used to power down the internal circuitry. The number of
cycles of latency before a change in CE0 or CE1 will enable
or disable the databus matches the number of cycles of read
latency selected for the device. In order for a valid write or read
to occur, both chip enable inputs on a port must be active.
Each port contains an optional burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally.
Additional features of this device include a mask register and
a
mirror register to control counter increments and
• Built-in deterministic access control to manage
wrap-around, counter-interrupt (CNTINT) flags to notify that
the counter will reach the maximum value on the next clock
cycle, readback of the burst-counter internal address, mask
register address, and BUSY address on the address lines,
retransmit functionality, mailbox interrupt flags for message
passing, JTAG for boundary scan, and asynchronous Master
Reset (MRST). The logic block diagram in Figure 1 displays
these features.
address collisions
— Deterministic flag output upon collision detection
— Collision detection on back-to-back clock cycles
— First Busy Address readback
• Advanced features for improved high-speed data
transfer and flexibility
— Variable impedance Matching (VIM)
— Echo clocks
The FullFlex72 DDR family of devices is offered in a 484-ball
plastic BGA package. The FullFlex36 and FullFlex18 DDR
only families of devices are offered in a 256-ball fine pitch BGA
package.
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Document #: 38-06072 Rev. *E
Revised October 11, 2005
PRELIMINARY
FullFlex
FTSEL
CQEN
L
FTSEL
CQEN
L
R
R
CONFIG Block
CONFIG Block
PORTSTD[1:0]
PORTSTD[1:0]
L
R
DQ [71:0]
R
DQ[71:0]
L
BE [7:0]
R
BE [7:0]
L
CE0
CE0
R
L
L
IO
Control
IO
Control
CE1
CE1
R
OE
R
OE
L
R/W
R/W
R
R
L
L
CQ0
CQ0
CQ0
CQ0
L
R
CQ1
CQ1
L
R
CQ1
CQ1
L
R
VC_SEL
Dual Ported Array
Collision Detection
Logic
BUSY
BUSY
L
R
A [19:0]
A [19:0]
L
L
R
R
CNT/MSK
CNT/MSK
ADS
ADS
R
L
CNTEN
CNTEN
R
L
Address &
Counter Logic
Address &
Counter Logic
CNTRST
CNTRST
L
R
RET
L
RET
R
CNTINT
L
CNTINT
R
C
L
C
R
C
L
C
R
WRP
L
WRP
R
TRST
TMS
TDI
Mailboxes
INT
INT
R
L
JTAG
TDO
TCK
READY
L
MRST
RESET
LOGIC
LowSPD
READY
R
L
LowSPD
ZQ0
ZQ1
R
L
L
ZQ0
ZQ1
R
R
Figure 1. Block Diagram[1,2,3]
Notes:
1. The CYDD36S18V18 device has 20 address bits. The CYDD36S36V18, CYDD36S72V18, and the CYDD18S18V18 devices have 19 address bits. The
CYDD18S72V18, CYDD18S36V18, and the CYDD09S18V18 devices have 18 address bits. The CYDD09S72V18, CYDD04S18V18, and the CYDD09S36V18
devices have 17 address bits. The CYDD04S36V18 and the CYDD04S72V18 devices have 16 address bits.
2. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines.
3. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte
enables.
Document #: 38-06072 Rev. *E
Page 2 of 48
FullFlex
PRELIMINARY
Document #: 38-06072 Rev. *E
Page 3 of 48
PRELIMINARY
FullFlex
FullFlex36 DDR 484-ball BGA Pinout (Top View)[8]
20 21 22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
NC DQ34 DQ32 DQ30 DQ27 NC
NC
NC DQ24 DQ21 DQ18 DQ18 DQ21 DQ24 NC
NC
NC DQ27 DQ30 DQ32 DQ34 NC
A
B
C
L
L
L
L
L
L
L
R
R
R
R
R
R
R
NC DQ35 DQ33 DQ31 DQ28 NC
LNC
NC
NC
NC DQ25 DQ22 DQ19 DQ19 DQ22 DQ25 NC
NC
NC
NC DQ28 DQ31 DQ33 DQ35 NC
L
L
L
L
L
L
R
R
R
R
R
R
R
NC
NC VSS VSS DQ29 NC
L
NC DQ26 DQ23 DQ20 DQ20 DQ23 DQ26 NC
NC DQ29 VSS VSS NC
R
NC
NC
L
L
L
R
R
R
[
NC
NC VSS VSS VSS CQ1L CQ1L
LOW PORT ZQ0L BUSY CNTI PORT NC CQ1R CQ1R VSS VSS VSS NC
4]
DDR
ONL
SPDL STD0
L
L
NTL STD1
L
D
E
F
NC
NC
NC VDDI VSS VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI NC VSS VDDI NC
OL OL OL OL OL OL OR OR OR OR OR
NC
NC
NC CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R NC
OL OL OL OL OL RE RE RE RE OR OR OR OR OR
A0L A1L RETL BE2L VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI BE2R RETR A1R A0R
OL OL OR OR
G
H
J
L
R
A2L A3L WRP NC VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI NC WRP A3R A2R
OL OL OR OR
L
R
A4L A5L READ BE3L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE3R READ A5R A4R
YL OL OL OR OR YR
[
A6L A7L ZQ1L NC VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VDDI NC ZQ1R A7R A6R
4]
[4]
K
L
RE
RE
OR
A8L A9L
CL
OEL VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER CR A9R A8R
RE RE
A10L A11L CL
NC VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL NC
RE RE
CR A11R A10R
M
N
A12L A13L ADSL BE1L VDDI VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL BE1R ADSR A13R A12R
OL RE RE
A14L A15L CNT NC VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI NC CNT A15R A14R
MSKL
OL
OL
OR
OR
MSK
R
P
R
T
A16L A17L CNTE BE0L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R A16R
NL OL OL OR OR NR
A18L NC CNTR INTL VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI INTR CNTR NC A18R
STL OL OL OR OR STR
L
R
NC
NC
NC
NC R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR NC
NL OL OL OL OL OL RE RE RE RE OR OR OR OR OR NR
NC
NC
NC
U
V
NC FTSE VDDI NC VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI FTSE NC
LL OL OL OL OL OL OR OR OR OR OR OR LR
NC VSS MRST VSS CQ0L CQ0L VC_S PORT CNTI BUSY ZQ0R PORT LOW DDR CQ0R CQ0R VSS TDI TDO NC
[4]
EL STD1 NTR
R
R
STD0 SPDR ONR
R
W
Y
NC
NC VSS VSS DQ11 NC
L
NC
NC
NC
NC DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R NC
NC DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R NC
NC DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R NC
NC
NC
NC
NC DQ11 TMS TCK NC
R
NC
NC DQ17 DQ15 DQ13 DQ10 NC
NC DQ10 DQ13 DQ15 DQ17 NC
AA
L
L
L
L
R
R
R
R
NC DQ16 DQ14 DQ12 DQ9L NC
NC DQ9R DQ12 DQ14 DQ16 NC
AB
L
L
L
R
R
R
Note:
8. Use this pinout only for device CYDD36S36V18 of the FullFlex36 famiy.
Document #: 38-06072 Rev. *E
Page 4 of 48
PRELIMINARY
FullFlex™ Synchronous
DDR Dual-Port SRAM
FullFlex18 DDR 484-ball BGA Pinout (Top View)
20 21 22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
NC
NC
NC
NC
NC
NC
NC
NC DQ15 DQ12 DQ9L DQ9R DQ12 DQ15 NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A
B
C
L
L
R
R
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC DQ16 DQ13 DQ10 DQ10 DQ13 DQ16 NC
NC
NC
NC
NC
NC
NC
NC
NC
L
L
L
R
R
R
NC VSS VSS NC
NC DQ17 DQ14 DQ11 DQ11 DQ14 DQ17 NC
NC VSS VSS NC
L
L
L
R
R
R
[
NC VSS VSS VSS CQ1L CQ1L
LOW PORT ZQ0L BUSY CNTI PORT NC CQ1R CQ1R VSS VSS VSS NC
4]
DDR
ONL
SPDL STD0
L
L
NTL STD1
L
D
E
F
NC
NC
NC VDDI VSS VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI NC VSS VDDI NC
OL OL OL OL OL OL OR OR OR OR OR
NC
NC
NC CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R NC
OL OL OL OL OL RE RE RE RE OR OR OR OR OR
A0L A1L RETL BE1L VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI BE1R RETR A1R A0R
OL OL OR OR
G
H
J
L
R
A2L A3L WRP NC VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI NC WRP A3R A2R
OL OL OR OR
L
R
A4L A5L READ NC VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI NC READ A5R A4R
YL OL OL OR OR YR
[
A6L A7L ZQ1L NC VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VDDI NC ZQ1R A7R A6R
4]
[4]
K
L
RE
RE
OR
A8L A9L
CL
OEL VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER CR A9R A8R
RE RE
A10L A11L CL
NC VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL NC
RE RE
CR A11R A10R
M
N
A12L A13L ADSL NC VDDI VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL NC ADSR A13R A12R
OL RE RE
A14L A15L CNT NC VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI NC CNT A15R A14R
MSKL
OL
OL
OR
OR
MSK
R
P
R
T
A16L A17L CNTE BE0L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R A16R
NL OL OL OR OR NR
A18L A19L CNTR INTL VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI INTR CNTR A19R A18R
STL OL OL OR OR STR
L
R
A20L NC R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR NC A20R
NL OL OL OL OL OL RE RE RE RE OR OR OR OR OR NR
U
V
NC
NC FTSE VDDI NC VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI FTSE NC
LL OL OL OL OL OL OR OR OR OR OR OR LR
NC
NC
NC VSS MRST VSS CQ0L CQ0L VC_S PORT CNTI BUSY ZQ0R PORT LOW DDR CQ0R CQ0R VSS TDI TDO NC
NC
[4]
EL STD1 NTR
R
R
STD0 SPDR ONR
R
W
Y
NC
NC
NC
NC VSS VSS NC
NC
NC
NC
NC
NC
NC
NC DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R NC
NC DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R NC
NC DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R NC
NC
NC
NC
NC
NC
NC
NC TMS TCK NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AA
AB
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Document #: 38-06072 Rev. *E
Revised October 11, 2005
PRELIMINARY
FullFlex
FullFlex36 DDR 256 Ball BGA (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ32L DQ30L DQ28L DQ26L DQ24L DQ22L DQ20L DQ18L DQ18R DQ20R DQ22R DQ24R DQ26R DQ28R DQ30R DQ32R
A
B
C
D
E
F
DQ33L DQ31L DQ29L DQ27L DQ25L DQ23L DQ21L DQ19L DQ19R DQ21R DQ23R DQ25R DQ27R DQ29R DQ31R DQ33R
[4]
DQ34L DQ35L
RETL
WRPL
CE0L
INTL
CQ1L
CQ1L VC_SEL TRST
MRST ZQ0R
VTTL VSS
CQ1R
CQ1R
INTR
VREF
CE1R
RETR DQ35R DQ34R
A0L
A2L
A1L
A3L
VREF VDDIOL LOWSP
DL
VSS
VTTL
LOWSP VDDIO
DR
WRPR
CE0R
A1R
A3R
A0R
A2R
R
CE1L VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIO VDDIO VDDIO
R
R
R
A4L
A5L
CNINTL BE3L VDDIOL VDDIOL
[4]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
R
BE3R CNINTR
BE2R BUSYR
A5R
A4R
A6L
A7L
BUSYL
BE2L
ZQ0L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
R
A7R
A6R
G
H
J
A8L
A9L
CL
VTTL VCORE
VCORE VTTL
CR
CR
A9R
A8R
A10L
A12L
A14L
A11L
A13L
A15L
CL
PORTS VCORE
TD1L
VCORE PORTS
TD1R
A11R
A13R
A15R
A10R
A12R
A14R
OEL
BE1L VDDIOL
VDDIO
R
BE1R
OER
ADSR
K
L
ADSL
BE0L VDDIOL
VDDIO VDDIO
BE0R
R
R
[10]
[9]
[9]
[10]
A16L
A17L
NC
RWL
CQENL VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIO VDDIO VDDIO CQENR RWR
A17R
NC
A16R
NC
M
N
P
R
T
R
R
R
[4]
[4]
NC
CNTMS VREF PORTS READY ZQ1L
VTTL
TMS
VTTL ZQ1R
READY PORTS VREF CNTMS
KL
TD0L
L
R
TD0R
KR
DQ16L DQ17L CNTEN CNTRS CQ0L
CQ0L
TCK
TDO
DQ1R
DQ0R
TDI
CQ0R
CQ0R CNTRS CNTEN DQ17R DQ16R
TR
L
TL
R
DQ15L DQ13L DQ11L
DQ9L
DQ7L
DQ6L
DQ5L
DQ4L
DQ3L
DQ2L
DQ1L
DQ0L
DQ3R
DQ2R
DQ5R
DQ4R
DQ7R
DQ9R DQ11R DQ13R DQ15R
DQ14L DQ12L DQ10L
DQ8L
DQ6R
DQ8R DQ10R DQ12R DQ14R
Notes:
9. Leave this ball unconnected for CYDD09S36V18 and CYDD04S36V18.
10. Leave this ball unconnected for CYDD04S36V18.
Document #: 38-06072 Rev. *E
Page 6 of 48
PRELIMINARY
FullFlex
FullFlex18 DDR 256 Ball BGA (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
NC
NC
DQ17L DQ16L DQ13L DQ12L
DQ9L
DQ9R DQ12R DQ13R DQ16R DQ17R
NC
NC
NC
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
DQ15L DQ14L DQ11L DQ10L DQ10R DQ11R DQ14R DQ15R
[4]
NC
NC
RETR
WRPR
CE0R
CNINTR
BUSYR
CR
NC
NC
NC
NC
RETL
INTL
CQ1L
CQ1L VC_SEL TRST
MRST ZQ0R
VTTL VSS
CQ1R
CQ1R
INTR
A0L
A2L
A4L
A6L
A8L
A10L
A12L
A14L
A1L
A3L
A5L
A7L
A9L
A11L
A13L
A15L
WRPL
VREF VDDIOL LOWSP
DL
VSS
VTTL
LOWSP VDDIOR VREF
DR
A1R
A3R
A5R
A7R
A9R
A11R
A13R
A15R
A0R
A2R
A4R
A6R
A8R
A10R
A12R
A14R
A16R
CE0L
CE1L VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CE1R
CNINTL
NC
NC
VDDIOL VDDIOL
[4]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VDDIOR
VSS VDDIOR
NC
NC
BUSYL
ZQ0L
VSS
VSS
VSS
VSS
VSS
G
H
J
CL
VTTL VCORE
VSS
VSS
VCORE VTTL
CL
PORTST VCORE
D1L
VCORE PORTST
D1R
CR
OEL
BE1L VDDIOL
VSS VDDIOR BE1R
OER
K
L
ADSL
BE0L VDDIOL
VSS VDDIOR VDDIOR BE0R
ADSR
[12]
[12]
A16L A17L
[11]
RWL
CQENL VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CQENR RWR A17R
M
N
P
R
T
[4]
[4]
[11]
A18L
NC
NC
NC
NC
NC
CNTMS VREF PORTST READYL ZQ1L
VTTL
TMS
VTTL ZQ1R
READY PORTST VREF CNTMS
NC
A18R
KL
D0L
R
D0R
KR
CNTENL CNTRST CQ0L
L
CQ0L
DQ5L
DQ4L
TCK
TDO
DQ1R
DQ0R
TDI
CQ0R
CQ0R CNTRST CNTEN
NC
NC
NC
NC
NC
NC
R
R
NC
NC
NC
DQ6L
DQ2L
DQ3L
DQ1L
DQ0L
DQ2R
DQ3R
DQ5R
DQ4R
DQ6R
DQ7R
NC
NC
NC
NC
DQ8L
DQ7L
DQ8R
NC
Note:
11. Leave this ball unconnected for CYDD09S18V18 and CYDD04S18V18.
12. Leave this ball unconnected for CYDD04S18V18.
Table 1. Selection Guide
-200[13,14,16,17
]
-250[13,15,17]
250
-167[13,14]
167
Unit
MHz
ns
fMAX
200
3.3
0.50
TBD
TBD
SDR Max. Access Time (Clock to Data)
DDR Max. Access Time (Clock to Data)
Typical Operating Current ICC
2.64
0.50
TBD
TBD
4.0
0.50
ns
TBD
TBD
mA
mA
Typical Standby Current for ISB3 (Both Ports CMOS Level)
Notes:
13. SDR mode with two pipeline stages.
14. DDR mode with 2.5 pipeline stages.
15. In SDR mode, these parameters apply for the 1.8V LVCMOS and HSTL.
16. In DDR mode, these parameters apply for the 1.8V LVCMOS and HSTL.
17. There is a speed bin drop for a 1.5V Core voltage.
18. These parameters apply for the 1.5V Core voltage only.
Document #: 38-06072 Rev. *E
Page 7 of 48
PRELIMINARY
FullFlex
Pin Definitions
Left Port
A[20:0]L
DQ0L–DQ71L
BE0L–BE7L
Right Port
A[20:0]R
DQ0R–DQ71R
BE0R–BE7R
Description
Address Inputs.[1]
Data Bus Input/Output.[2]
Byte Select Inputs.[3] Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
BUSYL
C/CL
BUSYR
C/CR
Port Busy Output. When there is an address match and both chip enables are active for
both ports, an external BUSY signal is asserted on the fifth clock cycle from when the collision
occurs.
Clock Signal.[19] Maximum clock input rate is fMAX. Tie C to VSS when operating in SDR
mode.
CE0L
CE0R
Active LOW Chip Enable Input.
CE1L
CE1R
Active HIGH Chip Enable Input.
CQENL
CQ0L, CQ0L
CQENR
CQ0R, CQ0R
Echo Clock Enable Input. Assert HIGH to enable echo clocking on respective port.
Echo Clock Signal Output for DQ[35:0] for FullFlex72 devices. Echo Clock Signal Output
for DQ[17:0] for FullFlex36 devices. Echo Clock Signal Output for DQ[8:0] for FullFlex18
devices.
CQ1L, CQ1L
CQ1R, CQ1R
Echo Clock Signal Output for DQ[71:36] for FullFlex72 devices. Echo Clock Signal
Output for DQ[35:18] for FullFlex36 devices. Echo Clock Signal Output for DQ[17:9] for
FullFlex18 devices.
DDRONL
ZQ<1:0>L
DDRONR
ZQ<1:0>R
DDR Enable Input. Assert HIGH to enable DDR clocking on respective port.
VIM Output Impedance Matching Input. To use, connect a calibrating resistor between ZQ
and ground. The resistor must be five times larger than the intended line impedance driven
by the dual-port. Assert HIGH to disable Variable Impedance Matching.
OEL
INTL
OER
INTR
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ
data pins during Read operations.
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The
upper two memory locations can be used for message passing. INTL is asserted LOW when
the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a
port is deasserted HIGH when it reads the contents of its mailbox.
LowSPDL
LowSPDR
Port Low Speed Select Input. Assert this pin LOW to disable the DLL. For operation at less
than 100 MHz, assert this pin LOW.
PORTSTD[1:0]L PORTSTD[1:0]R Port Clock/Address/Control/Data/Echo Clock/ I/O Standard Select Input. Assert these
[20]
[20]
pins LOW/LOW for LVTTL, LOW/HIGH for HSTL, HIGH/LOW for 2.5V LVCMOS, and
HIGH/HIGH for 1.8V LVCMOS, respectively. Connect these pins to a VTTL supply.
R/WL
R/WR
Read/Write Enable Input. Assert this pin LOW to Write to, or HIGH to Read from the
dual-port memory array.
READYL
READYR
Port DLL Ready Output. This signal will be asserted LOW when the DLL and Variable
Impedance Matching circuits have completed calibration. This is a wired OR capable output.
CNT/MSKL
ADSL
CNTENL
CNTRSTL
CNTINTL
CNT/MSKR
ADSR
CNTENR
CNTRSTR
CNTINTR
Port Counter/Mask Select Input. Counter control input.
Port Counter Address Load Strobe Input. Counter control input.
Port Counter Enable Input. Counter control input.
Port Counter Reset Input. Counter control input.
Port Counter Interrupt Output. This pin is asserted LOW one cycle before the unmasked
portion of the counter is incremented to all “1s”.
WRPL
WRPR
RETR
Port Counter Wrap Input. When the burst counter reaches the maximum count, on the next
counter increment WRP can be set LOW to load the unmasked counter bits to 0 or set HIGH
to load the counter with the value stored in the mirror register.
RETL
Port Counter Retransmit Input. Assert this pin LOW to reload the initial address for
repeated access to the same segment of memory.
Notes:
19. C and C are complimentary for DDR operation.
20. Pins D14 and W9 of the FullFlex72 have an internal pull-down resistor.
Document #: 38-06072 Rev. *E
Page 8 of 48
PRELIMINARY
FullFlex
Pin Definitions (continued)
Left Port
VREFL
VDDIOL
FTSELL
Right Port
VREFR
VDDIOR
FTSELR
Description
Port External HSTL I/O Reference Input.
Port Data I/O Power Supply.
Port Flow-Through Mode Select Input. Assert this pin LOW to select Flow-Through mode.
Assert this pin HIGH to select Pipeline mode. Selection for SDR only.
MRST
Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting
MRST LOW performs all of the reset functions as described in the text. A MRST operation
is required at power-up. This pin must be driven by VDDIO referenced levels.
VC_SEL
TMS
Core Power Supply Select. Assert this pin LOW to select 1.8V Core operation. Assert this
pin HIGH to select 1.5V Core operation. This pin must be driven by VTTL referenced levels.
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK. Operation for LVTTL or 2.5V LVCMOS.
TDI
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers.
Operation for LVTTL or 2.5V LVCMOS.
TRST
TCK
JTAG Reset Input. Operation for LVTTL or 2.5V LVCMOS.
JTAG Test Clock Input. Operation for LVTTL or 2.5V LVCMOS.
TDO
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP. Operation for LVTTL
or 2.5V LVCMOS.
VSS
VCORE
VTTL
Ground Inputs.
Device Core Power Supply.
LVTTL Power Supply.
Selectable I/O Standard
Clocking
The FullFlex families of devices also offer the option of
choosing one of four port standards for the device. Each port
can independently select standards from single-ended HSTL
class I, single-ended LVTTL, 2.5V LVCMOS, or 1.8V
LVCMOS. The selection of the standard is determined by the
PORTSTD pins for each port. These pins must be connected
to a VTTL power supply. This will determine the input clock,
address, control, data, and Echo clock standard for each port
as shown in Table 2.
Separate clocks synchronize the operations on each port.
Each port has two clock inputs C and C. In SDR mode only the
C input clock is used and C should be tied to VSS. In this
mode, all the transactions on the address, control, and data
will be on the C rising edge. In DDR mode, both C and C will
be used and these signals are complementary. In this mode,
all transactions on the address and control, except for the byte
enables, will occur on the C rising edge. Transactions on the
data input, output, and byte enables will be on the C and C
rising edges.
Table 2. Port Standard Selection
Double Data Rate (DDR)
PORTSTD1
VSS
PORTSTD0
VSS
I/O Standard
LVTTL
In DDR mode with a x36 bus width, the input data is sampled
on both edges of the input clock. During a write, on the rising
edge of C, the first 36 bits (DQ[71:36]) will be latched into a
register. On the rising edge of C, the next 36 bits (DQ[35:0])
will be latched into a register. During a read, the first 36 bits
are driven out first on the rising edge of C. The next 36 bits will
be driven out on the rising edge of C. The internal bus width of
the FullFlex72 family is still x72. All counter operation is based
upon the x72 word width. The DDR option is set on a per port
basis by the configuration of the DDRON pin. Table 4 shows
the data assignment for SDR and DDR configuration. The
column on the right (Data Pin Name) shows the pins on which
data is presented on the data lines.
VSS
VTTL
HSTL
VTTL
VTTL
VSS
VTTL
2.5V LVCMOS
1.8V LVCMOS
Operating mode with different IO standards combined with
different core power supply will result in different maximum
speed as shown in Table 3.
Document #: 38-06072 Rev. *E
Page 9 of 48
PRELIMINARY
FullFlex
Table 3. Operating Mode vs. Speed, I/O Standard and Pipeline Stages
Operating Mode Maximum Speed (MHz) Core Voltage (V)
I/O Standard
Latency Cycles
SDR
SDR
SDR
250
200
200
1.8
1.8
1.5
HSTL/1.8V LVCMOS
LVTTL/2.5V LVCMOS
HSTL/LVTTL/2.5V LVCMOS/1.8V
LVCMOS
2
2
2
DDR
DDR
200
167
1.8
1.5
HSTL/1.8V LVCMOS
2.5
2.5
HSTL/LVTTL/2.5V LVCMOS/1.8V
LVCMOS
Table 4. Data Pin Assignment for SDR and DDR Configuration
x72 SDR Mode
x36 DDR Mode
BE Pin Name for BE Pin Name for
Related Rising Edge
Related Rising Edge Data Pin
DDR
BE[3]
BE[3]
BE[3]
BE[3]
BE[3]
BE[3]
BE[3]
BE[3]
BE[3]
BE[3]
BE[3]
BE[3]
BE[3]
BE[3]
BE[3]
BE[3]
BE[3]
BE[3]
BE[2]
BE[2]
BE[2]
BE[2]
BE[2]
BE[2]
BE[2]
BE[2]
BE[2]
BE[2]
BE[2]
BE[2]
BE[2]
BE[2]
SDR
BE[7]
BE[3]
BE[7]
BE[3]
BE[7]
BE[3]
BE[7]
BE[3]
BE[7]
BE[3]
BE[7]
BE[3]
BE[7]
BE[3]
BE[7]
BE[3]
BE[7]
BE[3]
BE[6]
BE[2]
BE[6]
BE[2]
BE[6]
BE[2]
BE[6]
BE[2]
BE[6]
BE[2]
BE[6]
BE[2]
BE[6]
BE[2]
Data Pin Name
DQ[71]
DQ[35]
DQ[70]
DQ[34]
DQ[69]
DQ[33]
DQ[68]
DQ[32]
DQ[67]
DQ[31]
DQ[66]
DQ[30]
DQ[65]
DQ[29]
DQ[64]
DQ[28]
DQ[63]
DQ[27]
DQ[62]
DQ[26]
DQ[61]
DQ[25]
DQ[60]
DQ[24]
DQ[59]
DQ[23]
DQ[58]
DQ[22]
DQ[57]
DQ[21]
DQ[56]
DQ[20]
Clock for Write
Clock for Read
Name
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
DQ[35]
DQ[34]
DQ[33]
DQ[32]
DQ[31]
DQ[30]
DQ[29]
DQ[28]
DQ[27]
DQ[26]
DQ[25]
DQ[24]
DQ[23]
DQ[22]
DQ[21]
DQ[20]
Document #: 38-06072 Rev. *E
Page 10 of 48
PRELIMINARY
FullFlex
Table 4. Data Pin Assignment for SDR and DDR Configuration (continued)
x72 SDR Mode
x36 DDR Mode
BE Pin Name for BE Pin Name for
Related Rising Edge
Related Rising Edge Data Pin
DDR
BE[2]
BE[2]
BE[2]
BE[2]
BE[1]
BE[1]
BE[1]
BE[1]
BE[1]
BE[1]
BE[1]
BE[1]
BE[1]
BE[1]
BE[1]
BE[1]
BE[1]
BE[1]
BE[1]
BE[1]
BE[1]
BE[1]
BE[0]
BE[0]
BE[0]
BE[0]
BE[0]
BE[0]
BE[0]
BE[0]
BE[0]
BE[0]
BE[0]
BE[0]
BE[0]
BE[0]
BE[0]
BE[0]
BE[0]
BE[0]
SDR
BE[6]
BE[2]
BE[6]
BE[2]
BE[5]
BE[1]
BE[5]
BE[1]
BE[5]
BE[1]
BE[5]
BE[1]
BE[5]
BE[1]
BE[5]
BE[1]
BE[5]
BE[1]
BE[5]
BE[1]
BE[5]
BE[1]
BE[4]
BE[0]
BE[4]
BE[0]
BE[4]
BE[0]
BE[4]
BE[0]
BE[4]
BE[0]
BE[4]
BE[0]
BE[4]
BE[0]
BE[4]
BE[0]
BE[4]
BE[0]
Data Pin Name
DQ[55]
DQ[19]
DQ[54]
DQ[18]
DQ[53]
DQ[17]
DQ[52]
DQ[16]
DQ[51]
DQ[15]
DQ[50]
DQ[14]
DQ[49]
DQ[13]
DQ[48]
DQ[12]
DQ[47]
DQ[11]
DQ[46]
DQ[10]
DQ[45]
DQ[9]
Clock for Write
Clock for Read
Name
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
DQ[19]
DQ[18]
DQ[17]
DQ[16]
DQ[15]
DQ[14]
DQ[13]
DQ[12]
DQ[11]
DQ[10]
DQ[9]
DQ[8]
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
DQ[44]
DQ[8]
DQ[43]
DQ[7]
DQ[42]
DQ[6]
DQ[41]
DQ[5]
DQ[40]
DQ[4]
DQ[39]
DQ[3]
DQ[38]
DQ[2]
DQ[37]
DQ[1]
DQ[36]
DQ[0]
Document #: 38-06072 Rev. *E
Page 11 of 48
PRELIMINARY
FullFlex
Selectable Pipeline/Flow-Through Mode
If both ports are accessing the same location at the same time
and only one port is doing a write, if tCCS is met, then the data
being written to and read from the address is valid data. For
example, if the right port is reading and the left port is writing
and the left ports clock meets tCCS, then the data being read
from the address by the right port will be the old data. In the
same case, if the right ports clock meets tCCS, then the data
being read out of the address from the right port will be the new
data. In the above case, if tCCS is violated by the either ports
clock with respect to the other port and the right port gets the
external BUSY flag, the data from the right port is corrupted.
Table 5 shows the tCCS timing that must be met to guarantee
the data.
To meet data rate and throughput requirements, the FullFlex
families offer selectable pipeline or flow-through mode.
Flow-through mode is only supported in the FullFlex72
devices when the port is configured in SDR mode. Echo clocks
are not supported in flow-through mode and the DLL must be
disabled.
Flow-Through mode is selected by the FTSEL pin. Strapping
this pin HIGH selects pipeline mode. Strapping this pin LOW
selects flow-through mode.
DLL
The FullFlex families of devices have an on-chip DLL.
Enabling the DLL reduces the clock to data valid time allowing
more setup time for the receiving device. For operation at or
below 100 MHz, the DLL must be disabled. This is selectable
by strapping LowSPD LOW. For information on DLL lock and
reset time, please see the Master Reset section below.
Table 6 shows that in the case of the left port writing and the
right port reading, when an external BUSY flag is asserted on
the right port, the data read out of the device will not be
guaranteed.
The value in the busy address register can be read back to the
address lines. The required input control signals for this
function are shown in Table 9. The value in the busy address
register will be read out to the address lines tCA after the same
amount of latency as a data read operation in SDR mode. In
DDR mode, the address latency is only 2 cycles instead of 2.5
which is the data latency. After an initial address match, the
address under contention is saved in the busy address
register. All following address matches cause the BUSY flag
to be generated, however, none of the addresses are saved
into the busy address register. Once a busy readback is
performed, the address of the first match which happens at
least two clock cycles after the busy readback, is saved into
the busy address register.
Echo Clocking
As the speed of data increases, on-board delays caused by
parasitics make providing accurate clock trees extremely
difficult. To counter this problem, the FullFlex families incor-
porate Echo Clocks. Echo Clocks are enabled on a per port
basis. The dual-port receives input clocks (C and C for DDR
mode, C for SDR mode) that are used to clock in the address
and control signals for a read operation. The dual-port
retransmits the input clocks relative to the data output. The
buffered clocks are provided on the CQ1, CQ1, CQ0, and CQ0
outputs. Each port has two pairs of Echo clocks. Each clock is
associated with half the data bits. The output clock will match
the corresponding ports I/O configuration.
To enable Echo clock outputs, tie CQEN HIGH. To disable
Echo clock outputs, tie CQEN LOW.
Input Clock
Data Out
Echo Clock
Figure 2. SDR Echo Clock Delay
Input Clock
Input Clock
Data Out
Echo Clock
Echo Clock
Figure 3. DDR Echo Clock Delay
Deterministic Access Control
Deterministic Access Control is provided for ease of design.
The circuitry detects when both ports are accessing the same
location and provides an external BUSY flag to the port on
which data may be corrupted. The collision detection logic
saves the address in conflict (Busy Address) to a readable
register. In the case of multiple collisions, the first Busy
address will be written to the Busy Address register.
Document #: 38-06072 Rev. *E
Page 12 of 48
PRELIMINARY
FullFlex
Table 5. tCCS Timing for All Operating Modes
Port A – Early Arriving Port Port B – Late Arriving Port
tCCS C/C Rise to Opposite C/C Rise Set-up Time
for Non-corrupt Data
Mode
SDR
SDR
DDR
DDR
Active Edge
Mode
SDR
DDR
SDR
DDR
Active Edge
Unit
ns
ns
ns
ns
C
C
C
C
C
C
C
C
tCYC(min) – 1
tCYC(min) – 1
0.55 * tCYC + tCYC(min) – 1
0.55 * tCYC + tCYC(min) – 1
Table 6. Deterministic Access Control Winning Port
Clock Timing
Left Port
Read
Right Port Left Clock
Right Clock
BUSYL
BUSYR
Description
Read
X
X
H
H
H
H
H
H
H
H
H
H
L
H
L
L
L
H
H
H
H
H
L
No Collision
Write
Read
>tCCS
0
<tCCS
0
Read OLD Data
Read NEW Data
Read OLD Data
>tCCS
0
Data Not Guaranteed
Read NEW Data
Data Not Guaranteed
Read NEW Data
Read OLD Data
Read NEW Data
Data Not Guaranteed
Read OLD Data
Data Not Guaranteed
Array Data Corrupted
Array Stores Right Port Data
Array Stores Left Port Data
0
<tCCS
H
L
Read
Write
Write
Write
>tCCS
0
<tCCS
0
>tCCS
0
H
H
H
H
H
H
L
0
<tCCS
0
0
>–tCCS & <tCCS
>tCCS
0
H
L
>tCCS
Variable Impedance Matching (VIM)
Table 7. Variable Impedance Matching Parameters
Parameter
RQ Value
Output Impedance
Reset Time
Min. Max.
Unit
Tolerance
±2%
±15%
N/A
Each port contains a Variable Impedance Matching circuit to
set the impedance of the I/O driver to match the impedance of
the on board traces. The impedance is set for all outputs
except JTAG and is done on a per port basis. To take
advantage of the VIM feature, connect a calibrating resistor
(RQ) that is five times the value of the intended line impedance
from the ZQ pin to VSS. The output impedance is then
adjusted to account for drifts in supply voltage and temper-
ature every 1024 clock cycles. If a port’s clock is suspended,
the VIM circuit will retain its last setting until the clock is
restarted where it will then resume periodic adjustment. In the
case of a significant change in device temperature or supply
voltage, the recalibration period is multiples of 1024 clock
cycles. A Master Reset will initialize the VIM circuitry. Table 7
shows the VIM parameters and Table 8 describes the VIM
operation modes.
100
275
Ω
20
55
Ω
N/A 1024 Cycles
N/A 1024 Cycles
Update Time
N/A
Table 8. Variable Impedance Matching Operation
RQ Connection Output Configuration
100 –275
Ω
Ω
to Output Driver Impedance = RQ/5 ± 15% at
Vout = VDDIO/2
VSS
ZQ to VDDIO
VIM Disabled. Rout < 20
Ω
at Vout =
VDDIO/2
Address Counter and Mask Register Operations[1]
In order to disable VIM, the ZQ pin must be connected to
VDDIO of the relative supply for the I/Os before a Master
Reset.
Each port of the FullFlex families contains a programmable
burst address counter. The burst counter contains four
registers: a counter register, a mask register, a mirror register,
and a busy address register.
The counter register contains the address used to access the
RAM array. It is changed only by the master reset (MRST),
Counter Reset, Counter Load, Retransmit, and Counter
Increment operations.
Document #: 38-06072 Rev. *E
Page 13 of 48
PRELIMINARY
FullFlex
The mask register value affects the Counter Increment and
Counter Load Operation[1]
Counter Reset operations by preventing the corresponding
bits of the counter register from changing. It also affects the
counter interrupt output (CNTINT). The mask register is only
changed by Mask Reset, Mask Load, and MRST. The Mask
Load operation loads the value of the address bus into the
mask register. The mask register defines the counting range
of the counter register. It divides the counter register into two
or three consecutive regions. Zero or more “0s” define the
masked region and one or more “1s” define the unmasked
portion of the counter register. The counter register may only
be divided into up to three regions. The region containing the
least significant bits must be no more than two bits. Bits one
and zero may be “10” respectively, masking the least signif-
icant counter bit and causing the counter to increment by two
instead of one. If bits one and zero are “00”, the two least
significant bits are masked and the counter will increment by
four instead of one. For example, in the case of a 256Kx72
configuration, a mask register value of 003FC divides the
mask register into three regions. With bit 0 being the least
significant bit and bit 17 being the most significant bit, the two
least significant bits are masked, the next eight bits are
unmasked, and the remaining bits are masked.
The mirror register is used to reload the counter register on
retransmit operations (see “retransmit” below) and wrap
functions (see “counter increment” below). The last value
loaded into the counter register is stored in the mirror register.
The mirror register is only changed by master reset (MRST),
Counter Reset, and Counter Load.
Table 9 summarizes the operations of these registers and the
required input control signals. All signals except MRST are
synchronized to the ports clock.
The address counter and mirror registers are both loaded with
the address value presented on the address lines. This value
ranges from 0 to FFFFF.
Mask Load Operation[1]
The mask register is loaded with the address value presented
on the address bus. This value ranges from 0 to FFFFF though
not all values permit correct increment operations. Permitted
values are in the form of 2n–1, 2n–2, or 2n–4. The counter
register can only be segmented in up to three regions. From
the most significant bit to the least significant bit, permitted
values have zero or more “0s”, one or more “1s”, and the least
significant two bits can be “11”, “10”, or “00”. Thus FFFFE,
7FFFF, and 03FFC are permitted values but 2FFFF, 03FFA,
and 7FFE4 are not.
Counter Readback Operation
The internal value of the counter register can be read out on
the address lines. The address will be valid tCA after the
selected number of latency cycles configured by FTSEL. This
is the same as data in SDR mode and one half cycle earlier
than data latency for DDR mode. The data bus (DQ) is
tri-stated on the cycle that the address is presented on the
address lines. Figure 4 shows a block diagram of the
operation.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. The address will be valid tCA after the selected
number of latency cycles configured by FTSEL. For pipelined
SDR and DDR mode this is two cycles. The data bus (DQ) is
tri-stated on the cycle that the address is presented on the
address lines. Figure 4 shows a block diagram of the
operation.
Table 9. Burst Counter and Mask Register Control Operation (Any Port) [21,22]
C
MRST CNTRST CNT/MSK CNTEN ADS RET
Operation
Description
X
L
X
X
X
X
X
Master Reset
Reset address counter to all 0s, mask register
to all 1s, and BUSY address to all 0’s.
H
L
H
X
X
X
Counter Reset
Reset counter and mirror unmasked portion to
all 0s.
H
H
L
L
X
L
X
L
X
X
Mask Reset
Reset mask register to all 1s.
H
H
Counter Load
Load burst counter and mirror with external
address value presented on address lines.
H
H
L
L
L
X
Mask Load
Retransmit
Load mask register with value presented on the
address lines.
H
H
H
H
H
H
L
L
H
H
L
Load counter with value in the mirror register
Internally increment address counter value.
H
Counter
Increment
H
H
H
H
H
H
H
H
L
H
H
H
H
L
L
H
H
H
Counter Hold
Constantly hold the address value for multiple
clock cycles.
Counter
Read out counter internal value on address
Readback
lines.
Mask Readback Read out mask register value on address lines.
Notes:
21. X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
22. Counter operation and mask register operation is independent of chip enables.
Document #: 38-06072 Rev. *E
Page 14 of 48
PRELIMINARY
Table 9. Burst Counter and Mask Register Control Operation (Any Port) (continued)[21,22]
FullFlex
C
MRST CNTRST CNT/MSK CNTEN ADS RET
Operation
Description
H
H
L
H
H
L
Busy Address
Read out first busy address after last busy
Readback
address readback
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
X
L
Reserved
Reserved
Reserved
Reserved
Reserved
L
H
L
H
L
H
H
H
L
Counter Reset Operation
Hold Operation
All unmasked bits of the counter are reset to “0”. All masked
bits remain unchanged. The new burst counter value is loaded
into the mirror registers. A mask reset followed by a counter
reset will reset the counter and mirror registers to 00000.
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are
needed, or when address is available a few cycles ahead of
data in a shared bus interface.
Mask Reset Operation
Retransmit
The mask register is reset to all “1s”, which unmasks every bit
of the burst counter.
Retransmit allows repeated access to the same block of
memory without the need to reload the initial address. An
internal mirror register stores the address counter value last
loaded. When the burst counter reaches its maximum value
set by the mask register, it wraps back to the initial value stored
in the mirror register as long as WRP is deasserted. The
unmasked counter bits will be loaded with “0” if WRP is
asserted. If the counter is configured to continuously be in
increment mode, it increments once again to the maximum
value and wraps back to the value initially stored in the mirror
register as long as WRP is deasserted. While RET is asserted
low, the counter will continue to wrap back to the value in the
mirror register independent of the state of WRP.
Increment Operation[1]
Once the address counter is initially loaded with an external
address, the counter can internally increment the address
value and address the entire memory array. Only the
unmasked bits of the counter register are incremented. In
order for a counter bit to change, the corresponding bit in the
mask register must be “1”. If the two least significant bits of the
mask register are “11”, the burst counter will increment by one.
If the two least significant bits are “10”, the burst counter will
increment by two, and if they are “00”, the burst counter will
increment by four. If all unmasked counter bits are incre-
mented to “1” and WRP is deasserted, the next increment will
wrap the counter back to the initially loaded value. The cycle
before an increment will result in the unmasked counter bits
being “1s”, a counter interrupt flag (CNTINT) is asserted if the
counter is continuously incrementing. The next increment will
cause the counter to reach its maximum value and the second
increment will return the counter register to its initial value
which was stored in the mirror register when WRP is
deasserted. When WRP is asserted, the second increment
after CNTINT is asserted will load the unmasked counter bits
with “0”. The example shown in Figure 5 shows an example of
the CYDD36S18V18 device with the mask register loaded with
a mask value of 0007F unmasking the seven least significant
bits. Setting the mask register to this value allows the counter
to access the entire memory space. The address counter is
then loaded with an initial value of 00005 assuming WRP is
deasserted. The base address bits (in this case, the seventh
address through the twentieth address) do not increment once
the counter is configured for increment operation. The counter
address will start at address 00005 and will increment its
internal address value until it reaches the mask register value
of 0007F. The counter wraps around the memory block to
location 00005 at the next count. CNTINT is issued when the
counter reaches the maximum –1 count.
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW one clock
cycle before an increment operation that results in the
unmasked portion of the counter register being all “1s”. It is
deasserted by counter reset, counter load, mask reset, mask
load, counter increment, re-transmit, and MRST.
Counting by Two
When the two least significant bits of the mask register are
“10,” the counter increments by two.
Counting by Four
When the two least significant bits of the mask register are
“00,” the counter increments by four.
Mailbox Interrupts
The upper two memory locations can be used for message
passing and permit communications between ports. Table 10
shows the interrupt operation for both ports. The highest
memory location is the mailbox for the right port and the
maximum address–1 is the mailbox for the left port.
When one port Writes to the other ports mailbox, the INT flag
of the port that the mailbox belongs to is asserted LOW. The
INT flag remains asserted until the mailbox location is read by
the other port. When a port reads it’s mailbox, the INT flag is
Document #: 38-06072 Rev. *E
Page 15 of 48
PRELIMINARY
FullFlex
deasserted HIGH after one cycle of latency with respect to the
input clock of the port to which the mailbox belongs and is
independent of OE.
LOW. A valid Read of the FFFFF location by the right port will
reset INTR HIGH after one cycle of latency with respect to the
right port’s clock. At least one byte enable has to be activated
to set or reset the mailbox interrupt.
Table 10 shows that in order to set the INTR flag, a Write
operation by the left port to address FFFFF will assert INTR
CNT/MSK
CNTEN
Decode
Logic
A
CNTRST
RET
MRST
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
Address
Decode
RAM
Array
C
Load/Increment
21
21
From
Address
Lines
Mirror
Counter
To Readback
and Address
Decode
1
0
1
0
From
Increment
Logic
Mask
21
Wrap
Register
21
21
21
From
Mask
From
Counter
Bit 0
and 1
+1
+2
+4
Wrap
Wrap
To
1
0
Detect
21
1
0
Counter
Figure 4. Counter, Mask, and Mirror Logic Block Diagram[1]
Document #: 38-06072 Rev. *E
Page 16 of 48
PRELIMINARY
FullFlex
CNTINT
H
Example:
Load
Counter-Mask
0
0
0s
1
1
1
1
1
1
1
0
Register = 00007F
219 218
26 25 24 23 22 21 20
Unmasked Address
27
Masked Address
Mask
Register
LSB
Load
Address
H
L
X
X
Xs
Xs
Xs
0
0
0
0
1
0
1
X
Counter = 000005
219 218
26 25 24 23 22 21 20
Address
Counter
LSB
27
27
27
Max
Address
Value
X
X
1
1
1
1
1 1
1
X
219 218
26 25 24 23 22 21 20
Max + 1
Address
Value
H
X
X
0
0
0
0
1
0
1
X
219 218
26 25 24 23 22 21 20
Figure 5. Programmable Counter-Mask Register Operation[1,26]
Table 10.Interrupt Operation Example [1, 22, 23, 24, 25]
Left Port
A0L–19L
Right Port
A0R–19R
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
R/WL
CEL
L
INTL
X
R/WR
CER
X
INTR
L
H
X
X
L
X
X
H
Max. Address
X
H
L
X
X
X
L
X
X
X
L
H
L
L
X
Max. Address
Max. Address–1
X
Reset Left INTL Flag
Max. Address–1
X
Master Reset
connected together. For faster pull-down of the signal, connect
a 250-Ohm resistor to VSS. If the DLL and VIM circuits are
disabled for a port, the port will be operational within five clock
cycles. However, the READY will be asserted within 160 clock
cycles.
The FullFlex family of dual-ports undergo a complete reset by
asserting MRST. MRST must be connected to VDDIO. The
MRST can be asserted asynchronously to the clocks and must
remain asserted for at least tRS. Once asserted MRST
deasserts READY, initializes the internal burst counters,
internal mirror registers, and internal Busy Addresses to zero,
and initializes the internal mask register to all “1s”. All mailbox
interrupts (INT), Busy Address Outputs (BUSY), and burst
counter interrupts (CNTINT) are deasserted upon master
reset. Releasing MRST also signifies that the power supplies
and all port clocks are stable. This begins calibration of the
DLL and VIM circuits. READY will be asserted within 1024
clock cycles. READY is a wired OR capable output with a
strong pull-up and weak pull-down. Up to four outputs may be
IEEE 1149.1 Serial Boundary Scan (JTAG)
The FullFlex families incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP operates
using JEDEC-standard 3.3V or 2.5V I/O logic levels depending
on the VTTL power supply. It is composed of four input
connections and one output connection required by the test
logic defined by the standard.
Notes:
23. CE is internal signal. CE = LOW if CE = LOW and CE = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the C and
0
1
can be deasserted after that. Data will be out after the following C edge and will be tri-stated after the next C edge.
24. OE is “Don’t Care” for mailbox operation.
25. At least one of BE0, BE1, BE2, BE3, BE4, BE5, BE6, or BE7 must be LOW.
26. The “X” in this diagram represents the counter upper bits.
Document #: 38-06072 Rev. *E
Page 17 of 48
PRELIMINARY
FullFlex
Table 11.Identification Register Definitions
Table 12.Scan Registers Sizes
Register Name
Instruction
Bypass
Identification
Boundary Scan
Part Number
CYDD36S72V18
CYDD36S36V18
CYDD36S18V18
CYDD18S72V18
CYDD18S36V18
CYDD18S18V18
CYDD09S72V18
CYDD09S36V18
CYDD09S18V18
CYDD04S72V18
CYDD04S36V18
CYDD04S18V18
Configuration
512Kx72
512Kx72
1024Kx36
256Kx72
256Kx72
512Kx36
128Kx72
128Kx72
256Kx36
64Kx72
Value
Bit Size
0C040069h
0C041069h
0C042069h
0C043069h
0C044069h
0C045069h
0C046069h
0C047069h
0C048069h
0C049069h
0C04A069h
0C04B069h
4
1
32
n[27]
64Kx72
128Kx36
Table 13.Instruction Identification Codes
Instruction Code
EXTEST
Description
0000
1111
1011
0111
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
BYPASS
IDCODE
HIGHZ
Places the BYR between TDI and TDO.
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
Places BYR between TDI and TDO. Forces all FullFlex72 and FullFlex36 output drivers
to a High-Z state.
CLAMP
0100
Controls boundary to 1/0. Places BYR between TDI and TDO.
SAMPLE/PRELOAD 1000
Captures the input/output ring contents. Places BSR between TDI and TDO.
RESERVED
All other codes Other combinations are reserved. Do not use other than the above.
Note:
27. Details of the boundary scan length can be found in the BSDL file for the device.
Document #: 38-06072 Rev. *E
Page 18 of 48
PRELIMINARY
FullFlex
Maximum Ratings
Operating Range
(Above which the useful life may be impaired. For user guide-
Range
Commercial
Ambient Temperature
VCORE
lines, not tested.)
0°C to +70°C
1.8V
±
100 mV
Storage Temperature ................................ –65°C to + 150°C
1.5V
±
80 mV
Ambient Temperature with
Industrial
–40°C to +85°C
1.8V
±
100 mV
80 mV
Power Applied............................................–55°C to + 125°C
1.5V
±
Supply Voltage to Ground Potential.............. –0.5V to + 4.1V
Power Supply Requirements
DC Voltage Applied to
Min.
Typ.
3.3V
2.5V
1.5V
1.8V
3.3V
2.5V
Max.
3.6V
2.7V
1.9V
1.9V
3.6V
2.7V
0.95V
Outputs in High-Z State......................–0.5V to VCORE + 0.5V
LVTTL VDDIO
2.5V LVCMOS VDDIO
HSTL VDDIO
1.8V LVCMOS VDDIO
3.3V VTTL
3.0V
2.3V
1.4V
1.7V
3.0V
2.3V
0.68V
DC Input Voltage............................... –0.5V to VCORE + 0.5V
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage...........................................> 2200V
(JEDEC JESD8-6, JESD8-B)
Latch-up Current.....................................................> 200 mA
2.5V VTTL
HSTL VREF
0.75V
Electrical Characteristics Over the Operating Range
-250[15,17]
-200[16,17]
Parameter
VOH
Description
Configuration
Min.
Typ. Max.
Min.
Typ. Max. Unit
Output HIGH Voltage
LVTTL
2.4[28]
2.4[28]
V
(VCORE = Min., IOH = –8 mA)
(VCORE = Min., IOH = –4 mA) HSTL (DC)[29] VDDIO – 0.4[28]
(VCORE = Min., IOH = –4 mA) HSTL (AC)[29] VDDIO – 0.5[28]
VDDIO – 0.4[28]
VDDIO – 0.5[28]
1.7[28]
V
V
V
V
(VCORE = Min., IOH = –6 mA) 2.5V LVCMOS
(VCORE = Min., IOH = –4 mA) 1.8V LVCMOS
1.7[28]
1.6[28]
1.6[28]
VOL
Output HIGH Voltage
LVTTL
0.4[28]
0.4[28]
V
(VCORE = Min., IOL = 8 mA)
(VCORE = Min., IOL = 4 mA)
(VCORE = Min., IOL = 4 mA)
(VCORE = Min., IOL = 6 mA) 2.5V LVCMOS
(VCORE = Min., IOL = 4 mA) 1.8V LVCMOS
Input HIGH Voltage
Input LOW Voltage
HSTL (DC)
HSTL (AC)
0.4[28]
0.5[28]
0.7[28]
0.2[28]
VDDIO
+ 0.3
VDDIO
+ 0.3
0.4[28]
0.5[28]
0.7[28]
0.2[28]
VDDIO
+ 0.3
VDDIO
+ 0.3
V
V
V
V
V
VIH
LVTTL
2
2
HSTL (DC)
VREF + 0.1
VREF + 0.1
V
HSTL (AC)
2.5V LVCMOS
1.8V LVCMOS
LVTTL
VREF + 0.2
1.7
VREF + 0.2
1.7
V
V
V
V
V
1.26
–0.3
–0.3
1.26
–0.3
–0.3
VIL
0.8
VREF –
0.1
0.8
VREF
– 0.1
HSTL (DC)
HSTL (AC)
VREF –
0.2
VREF
– 0.2
V
2.5V LVCMOS
1.8V LVCMOS
0.7
0.36
0.7
0.36
V
V
Notes:
28. These parameters are met with VIM disabled.
29. The (DC) specifications are measured under steady state conditions. The (AC) specifications are measured while switching at speed.
Document #: 38-06072 Rev. *E
Page 19 of 48
PRELIMINARY
FullFlex
Electrical Characteristics Over the Operating Range (continued)
-250[15,17]
-200[16,17]
Parameter
Description
Configuration
Min.
Typ. Max.
Min.
Typ. Max. Unit
READY
Output HIGH Voltage
LVTTL
2.7[28]
2.7[28]
V
VOH
(VCORE = Min., IOH = –24 mA)
(VCORE = Min., IOH = –12 mA) HSTL (DC)[29] VDDIO – 0.4[28]
(VCORE = Min., IOH = –12 mA) HSTL (AC)[29] VDDIO – 0.5[28]
VDDIO – 0.4[28]
VDDIO – 0.5[28]
2.0[28]
V
V
V
V
(VCORE = Min., IOH = –15 mA) 2.5V LVCMOS
(VCORE = Min., IOH = –12 mA) 1.8V LVCMOS VDDIO – 0.45[28]
2.0[28]
VDDIO –
0.45[28]
READY
VOL
Output HIGH Voltage
LVTTL
0.4[28]
0.4[28]
V
(VCORE = Min., IOL = 0.12 mA)
(VCORE = Min., IOL = 0.12 mA) HSTL (DC)
(VCORE = Min., IOL = 0.12 mA) HSTL (AC)
(VCORE = Min., IOL = 0.15 mA) 2.5V LVCMOS
(VCORE = Min., IOL = 0.08 mA) 1.8V LVCMOS
Output Leakage Current
Input Leakage Current
Input Leakage Current TDI,
TMS, MRST, TRST, TCK
0.4[28]
0.5[28]
0.7[28]
0.2[28]
10
0.4[28]
0.5[28]
0.7[28]
0.2[28]
10
V
V
V
V
A
A
A
IOZ
IIX1
IIX2
–10
–10
–300
–10
–10
–300
µ
µ
µ
10
10
10
10
IIX3
Input Leakage Current
PORTSTD, DDRON,
VC_SEL
–10
300
–10
300
µ
A
ICC
Operating Current
512Kx72
1024Kx36
256Kx72
512Kx36
128Kx72
256Kx36
64Kx72
128Kx36
512Kx72
1024Kx36
256Kx72
512Kx36
128Kx72
256Kx36
64Kx72
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
(VCORE = Max.,IOUT = 0 mA)
Outputs Disabled
ISB1
Standby Current
(Both Ports TTL Level)
CEL and CER VIH,
f = fMAX
128Kx36
Document #: 38-06072 Rev. *E
Page 20 of 48
PRELIMINARY
FullFlex
Electrical Characteristics Over the Operating Range (continued)
-250[15,17]
Typ. Max.
-200[16,17]
Parameter
Description
Configuration
512Kx72
1024Kx36
256Kx72
512Kx36
128Kx72
256Kx36
64Kx72
Min.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Min.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Typ. Max. Unit
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
ISB2
Standby Current
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
(One Port TTL Level)
CEL | CER VIH,
f = fMAX
128Kx36
512Kx72
1024Kx36
256Kx72
512Kx36
128Kx72
256Kx36
64Kx72
ISB3
Standby Current
(Both Ports CMOS Level)
CEL and CER VCORE
0.2V, f = 0
–
128Kx36
512Kx72
1024Kx36
256Kx72
512Kx36
128Kx72
256Kx36
64Kx72
ISB4
Standby Current
(One Port CMOS Level)
CEL | CER VIH,
f = fMAX
128Kx36
Document #: 38-06072 Rev. *E
Page 21 of 48
PRELIMINARY
FullFlex
Electrical Characteristics Over the Operating Range (continued)
-167
Typ.
Parameter
VOH
Description
Configuration
Min.
Max.
Unit
V
Output HIGH Voltage
LVTTL
2.4[28]
(VCORE = Min., IOH = –8 mA)
(VCORE = Min., IOH = –4 mA)
(VCORE = Min., IOH = –4 mA)
(VCORE = Min., IOH = –6 mA)
(VCORE = Min., IOH = –4 mA)
HSTL (DC)
HSTL (AC)
2.5V LVCMOS
1.8V LVCMOS
LVTTL
VDDIO – 0.4[28]
VDDIO – 0.5[28]
1.7[28]
V
V
V
V
V
1.6[28]
VOL
Output HIGH Voltage
0.4[28]
(VCORE = Min., IOL = 8 mA)
(VCORE = Min., IOL = 4 mA)
(VCORE = Min., IOL = 4 mA)
(VCORE = Min., IOL = 6 mA)
(VCORE = Min., IOL = 4 mA)
Input HIGH Voltage
HSTL (DC)
HSTL (AC)
2.5V LVCMOS
1.8V LVCMOS
LVTTL
HSTL (DC)
HSTL (AC)
2.5V LVCMOS
1.8V LVCMOS
LVTTL
HSTL (DC)
HSTL (AC)
2.5V LVCMOS
1.8V LVCMOS
LVTTL
0.4[28]
0.5[28]
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0.7[28]
0.2[28]
VIH
2
VREF + 0.1
VREF + 0.2
1.7
VDDIO + 0.3
VDDIO + 0.3
1.26
–0.3
–0.3
VIL
Input LOW Voltage
0.8
VREF – 0.1
VREF – 0.2
0.7
0.36
2.7[28]
READY VOH
Output HIGH Voltage
(VCORE = Min., IOH = –24 mA)
(VCORE = Min., IOH = –12 mA)
(VCORE = Min., IOH = –12 mA)
(VCORE = Min., IOH = –15 mA)
(VCORE = Min., IOH = –12 mA)
HSTL (DC)[29]
HSTL (AC)[29]
2.5V LVCMOS
1.8V LVCMOS
LVTTL
VDDIO – 0.4[28]
VDDIO – 0.5[28]
2.0[28]
V
V
V
V
V
VDDIO – 0.45[28]
READY VOL
Output HIGH Voltage
0.4[28]
(VCORE = Min., IOL = 0.12 mA)
(VCORE = Min., IOL = 0.12 mA)
(VCORE = Min.,IOL = 0.12 mA)
(VCORE = Min., IOL = 0.15 mA)
(VCORE = Min., IOL = 0.08 mA)
Output Leakage Current
Input Leakage Current
Input Leakage Current TDI,
TMS, MRST, TRST, TCK
HSTL (DC)
HSTL (AC)
2.5V LVCMOS
1.8V LVCMOS
0.4[28]
0.5[28]
0.7[28]
0.2[28]
10
V
V
V
V
A
A
A
IOZ
IIX1
IIX2
–10
–10
–300
µ
µ
µ
10
10
IIX3
Input Leakage Current
PORTSTD, DDRON,
VC_SEL
–10
300
µ
A
Document #: 38-06072 Rev. *E
Page 22 of 48
PRELIMINARY
FullFlex
Electrical Characteristics Over the Operating Range (continued) (continued)
-167
Typ.
Parameter
ICC
Description
Configuration
512Kx72
1024Kx36
256Kx72
512Kx36
128Kx72
256Kx36
64Kx72
128Kx36
512Kx72
1024Kx36
256Kx72
512Kx36
128Kx72
256Kx36
64Kx72
128Kx36
512Kx72
1024Kx36
256Kx72
512Kx36
128Kx72
256Kx36
64Kx72
128Kx36
512Kx72
1024Kx36
256Kx72
512Kx36
128Kx72
256Kx36
64Kx72
Min.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Max.
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Operating Current
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
(VCORE = Max.,IOUT = 0 mA)
Outputs Disabled
ISB1
ISB2
ISB3
ISB4
Standby Current
(Both Ports TTL Level)
CEL and CER VIH, f = fMAX
Standby Current
(One Port TTL Level)
CEL | CER VIH, f = fMAX
Standby Current
(Both Ports CMOS Level)
CEL and CER VCORE – 0.2V,
f = 0
128Kx36
512Kx72
1024Kx36
256Kx72
512Kx36
128Kx72
256Kx36
64Kx72
Standby Current
(One Port CMOS Level)
CEL | CER VIH, f = fMAX
128Kx36
Document #: 38-06072 Rev. *E
Page 23 of 48
PRELIMINARY
FullFlex
Table 14.Capacitance
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
10
12
Unit
pF
pF
[30]
CIN
TA = 25°C, f = 1MHz,
V
DD = 3V[32]
[30, 31]
COUT
AC Test Load and Waveforms
V R E F = 0V
V R E F
50 O hm
5 0 O hm
O u tput
T est P oint
R = 250 O hm
C = 10pF
V T H
R E A D Y Z Q
D evice und er
te st
R Q = 25 0 O h m
V T H = 1.5V for LV T T L
V T H = 5 0% V D D IO for 2.5V C M O S
V T H = 5 0% V D D IO for 1.8V C M O S
Figure 6. Output Test Load for LVTTL/CMOS
V
=
E F
0 . 7 5 V
5 0 O h m
R
V
R
E F
5 0 O h m
O u t p u t
T e s t P o in t
V T H
R = 2 5 0 O h m
R E A D Y
Z Q
C = 0 p F f o r D D R
C = 1 0 p F f o r S D R
D e v ic e u n d e r
t e s t
R Q = 2 5 0 O h m
V T H
= 5 0 % V D D I O
Figure 7. Output Test Load for HSTL
Notes:
30. Capacitance for the 36M x18 device is 20 pF, capacitance for all other 36M or x18 devices is 12 pF.
31. C also references to C
.
I/O
out
32. Input and Output switch from 0V to 3V or from 3V to 0V.
Document #: 38-06072 Rev. *E
Page 24 of 48
PRELIMINARY
FullFlex
Switching Characteristics Over the Operating Range
Table 15.DDR Mode with 2.5 Pipeline Stages and DLL Enabled (LOWSPD-HIGH)[36]
-200[16,17,34]
-167[17]
Parameter
fMAX
tCYC
tCH
tCL
tCHCH
tSD
Description
Maximum Operating Frequency
C/C Clock Cycle Time
C/C Clock HIGH Time
C/C Clock LOW Time
C/C Clock Rise to C/C Clock Rise
Data Input Set-up Time to C/C Rise
Data Input Hold Time after C/C Rise
Byte enable Set-up Time to C/C Rise
Byte enable Hold Time after C/C Rise
Address & Control Input except BE Set-up Time to C Rise
Address & Control Input except BE Hold Time after C Rise
Output Enable to Data Valid
OE to Low Z
OE to High Z
C/C Rise to DQ Valid
DQ Output Hold after C/C Rise
C/C Rise to CQ/CQ Rise
Echo Clock (CQ/CQ) High to Output Valid, SC = LOW
Echo Clock (CQ/CQ) High to Output Hold, SC = LOW
C Rise to DQ Output High Z
C Rise to DQ Output Low Z
C Rise to Address Readback Valid
Address Output Hold after C Rise
C Rise to Address Output High Z
C Rise to Address Output Low Z
C Rise to CNTINT Low
Min.
159
5.00
2.00
2.00
Max.
200
6.3
Min.
127
6.00
2.40
2.40
Max.
167
7.88
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.20
2.70
0.40[35]
0.40[35]
0.40[35]
0.40[35]
1.50
0.50[35]
0.50[35]
0.50[35]
0.50[35]
1.70
tHD
tSBE
tHBE
tSAC
tHAC
tOE
0.50
0.60
4.40[35]
5.00[35]
[33]
tOLZ
1.00
1.00
tOHZ
1.00[35] 4.40[35] 1.00[35] 5.00[35]
[33]
tCD
tDC
tCCQ
tCQHQV
0.50[35]
0.60[35]
–0.50
–0.50
–0.60
–0.60
0.50
0.35[35]
0.60
0.40[35]
tCQHQX
–0.35
–0.50
–0.40
–0.60
[33]
tCKHZ
tCKLZ
0.50[35]
5.00
0.60[35]
6.00
[33]
tCA
tAC
tCKHZA
1.00
1.00
1.00
1.00
1.00
0.50
0.50
1.00
1.00
1.00
1.00
1.00
1.00
0.50
0.50
1.00
[33]
5.00
6.00
[33]
tCKLZA
tSCINT
tRCINT
tSINT
tRINT
tBSY
3.30
3.30
7.00
7.00
3.30
4.00
4.00
8.00
8.00
4.00
C Rise to CNTINT High
C Rise to INT Low
C Rise to INT High
C Rise to BUSY Valid
Notes:
33. Parameters specified with the load capacitance in Figure 6 and Figure 7.
34. These parameters apply for the HSTL and 1.8V LVCMOS standards.
35. For the x18 devices, add 200 ps to this parameter in the table above.
36. Test conditions assume a signal transition time of 2 V/ns
Document #: 38-06072 Rev. *E
Page 25 of 48
PRELIMINARY
FullFlex
Table 16.SDR Mode with DLL Enabled (LOWSPD-HIGH) [36]
-250[15,17]
-200[15,17]
-167[17]
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max. Unit
fMAX (PIPELINED)
Maximum Operating Frequency for
100
250
100
200
100
167
MHz
Pipelined Mode
fMAX
Maximum Operating Frequency for
Flow-through Mode
100
77
66.7
MHz
(FLOW-THROUGH)
tCYC (PIPELINED)
C Clock Cycle Time for Pipelined mode
4.00
10.00
10.00
5.00
13.00
10.00
6.00
15.00
10.00
ns
ns
tCYC
C Clock Cycle Time for Flow-through
(FLOW-THROUGH)
mode
tCKD
tCHCH
tSD
tHD
tSAC
C Clock Duty Time
45
N/A
1.20[35]
0.50[35]
1.20
55
45
N/A
1.50[35]
0.50[35]
1.50
55
45
N/A
1.70[35]
0.50[35]
1.70
55
%
ns
ns
ns
ns
C/C Clock Rise to C/C Clock Rise
Data Input Set-up Time to C Rise
Data Input Hold Time after C Rise
Address & Control Input Set-up Time to C
Rise
tHAC
Address & Control Input Hold Time after
C Rise
Output Enable to Data Valid
OE to Low Z
0.50
0.50
0.60
ns
tOE
tOLZ
3.40[35]
4.40[35]
5.00[35] ns
ns
[33]
1.00
1.00
1.00
1.00[35] 3.40 [35] 1.00[35] 4.40[35] 1.00[35] 5.00[35] ns
[33]
tOHZ
OE to High Z
tCD1
tCD2
tCA1
tCA2
C Rise to DQ Valid for Flow-through Mode
7.20
2.6 [35]
7.20
9.00
3.30[35]
9.00
11.00
ns
(LowSPD = 1)
C Rise to DQ Valid for Pipelined Mode
(LowSPD = 1)
4.00[35] ns
C Rise to Address Readback Valid for
11.00
6.00
ns
ns
Flow-through Mode
C Rise to Address Readback Valid for
Pipelined Mode
4.00
5.00
tDC
tCCQ
tCQHQV
tCQHQX
tCKHZ1
DQ Output Hold after C Rise
C Rise to CQ Rise
Echo Clock (CQ) High to Output Valid
Echo Clock (CQ) High to Output Hold
1.00
1.00
1.00
1.00
1.00
1.00
ns
ns
2.64
3.30
4.00
0.70[35]
0.76[35]
0.80[35] ns
ns
–0.66
1.00
–0.72
1.00
–0.76
1.00
[33]
C Rise to DQ Output High Z in
7.20
9.00
11.00
ns
Flow-through Mode
[33]
tCKLZ1
C Rise to DQ Output Low Z in
Flow-Through Mode
1.00
1.00
1.00
ns
[33]
tCKHZ2
C Rise to DQ Output High Z in
1.00[35] 2.64 [35] 1.00[35] 3.30[35] 1.00[35] 4.00[35]
Flow-through Mode
[33]
tCKLZ2
C Rise to DQ Output Low Z in
Flow-Through Mode
1.00
1.00
1.00
tAC
tCKHZA1
Address Output Hold after C Rise
1.00
1.00
1.00
1.00
1.00
1.00
ns
ns
[33]
C Rise to Address Output High Z for
7.20
4.00
9.00
5.00
11.00
6.00
flow-through mode
[33]
tCKHZA2
C Rise to Address Output High Z for
pipelined mode
C Rise to Address Output Low Z
C Rise to CNTINT Low
1.00
1.00
1.00
ns
[33]
tCKLZA
tSCINT
tRCINT
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
ns
ns
ns
2.64
2.64
3.30
3.30
4.00
4.00
C Rise to CNTINT High
Document #: 38-06072 Rev. *E
Page 26 of 48
PRELIMINARY
Table 16.SDR Mode with DLL Enabled (LOWSPD-HIGH) (continued)[36]
FullFlex
-250[15,17]
-200[15,17]
-167[17]
Parameter
tSINT
tRINT
tBSY
Description
C Rise to INT Low
C Rise to INT High
Min.
0.50
0.50
1.00
Max.
6.00
6.00
2.64
Min.
Max.
7.00
7.00
3.30
Min.
0.50
0.50
1.00
Max. Unit
0.50
0.50
1.00
8.00
8.00
4.00
ns
ns
ns
C Rise to BUSY Valid
Table 17.SDR Mode with DLL Disabled (LOWSPD-LOW)[36]
-100
Parameter
Description
Min.
Max.
Unit
fMAX (PIPELINED)
fMAX (FLOW-THROUGH)
tCYC (PIPELINED)
tCYC (FLOW-THROUGH)
tCKD
tCHCH
tSD
Maximum Operating Frequency for Pipelined mode
Maximum Operating Frequency for Flow-through mode
C Clock Cycle Time for Pipelined mode
C Clock Cycle Time for Flow-through mode
C Clock Duty Time
C/C Clock Rise to C/C Clock Rise
Data Input Set-up Time to C Rise
Data Input Hold Time after C Rise
Address & Control Input Set-up Time to C Rise
Address & Control Input Hold Time after C Rise
Output Enable to Data Valid
100
55.6
10.00
MHz
MHz
ns
ns
%
7.00
18.00
45
55
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.80[35]
0.50[35]
1.80
tHD
tSAC
tHAC
tOE
0.70
5.50[35]
[33]
tOLZ
OE to Low Z
OE to High Z
1.00
1.00[35]
tOHZ
5.50[35]
13.00
6.00[35]
13.00
7.50
[33]
tCD1
tCD2
tCA1
tCA2
C Rise to DQ Valid for Flow-through Mode (LowSPD = 0)
C Rise to DQ Valid for Pipelined Mode (LowSPD = 0)
C Rise to Address Readback Valid for Flow-through Mode
C Rise to Address Readback Valid for Pipelined Mode
DQ Output Hold after C Rise
tDC
1.00
1.00
tCCQ
tCQHQV
tCQHQX
C Rise to CQ Rise
6.00
0.90[35]
Echo Clock (CQ) High to Output Valid
Echo Clock (CQ) High to Output Hold
C Rise to DQ Output High Z in Flow-through Mode
C Rise to DQ Output Low Z in Flow-Through Mode
C Rise to DQ Output High Z in Flow-through Mode
C Rise to DQ Output Low Z in Flow-Through Mode
Address Output Hold after C Rise
C Rise to Address Output High Z for flow-through mode
C Rise to Address Output High Z for pipelined mode
C Rise to Address Output Low Z
–0.90
1.00
1.00
1.00[35]
1.00
1.00
1.00
1.00
1.00
1.00
1.00
0.50
0.50
1.00
[33]
tCKHZ1
tCKLZ1
tCKHZ2
tCKLZ2
13.00
[33]
6.00[35]
[33]
[33]
tAC
tCKHZA1
tCKHZA2
tCKLZA
ns
ns
ns
ns
ns
ns
ns
ns
ns
[33]
13.00
7.50
[33]
[33]
tSCINT
tRCINT
tSINT
tRINT
tBSY
C Rise to CNTINT Low
C Rise to CNTINT High
C Rise to INT Low
C Rise to INT High
4.50
4.50
8.50
8.50
4.50
C Rise to BUSY Valid
Document #: 38-06072 Rev. *E
Page 27 of 48
PRELIMINARY
FullFlex
Table 18.Master Reset Timing
-250[15,17]
-200[16,17]
-167
Max.
Parameter
tPUP
tRS
Description
Power-up Time
Min.
Max.
Min.
Max.
Min.
Unit
ms
cycles
cycles
ns
1
5
5
1
5
5
1
5
5
Master Reset Pulse Width
Master Reset Recovery Time
Master Reset to Outputs Inactive/Hi-Z
Master Reset Release to Port Ready
C Rise to Port Ready
tRSR
tRSF
tRDY
10
1024
8
10
1024
9.5
10
1024
11
[37]
[38]
cycles
ns
tCORDY
Table 19.JTAG Timing
-250[15,17]
-200[16,17]
-167[17]
Parameter
Description
JTAG TAP Controller Frequency
TCK Cycle Time
TCK High Time
Min.
Max.
20
Min.
Max.
20
Min.
Max.
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fJTAG
tTCYC
tTH
50
20
20
10
10
10
10
50
20
20
10
10
10
10
50
20
20
10
10
10
10
tTL
TCK Low Time
tTMSS
tTMSH
tTDIS
tTDIH
tTDOV
tTDOX
tJXZ
TMS Set-up to TCK Rise
TMS Hold to TCK Rise
TDI Set-up to TCK Rise
TDI Hold to TCK Rise
TCK Low to TDO Valid
TCK Low to TDO Invalid
TCK Low to TDO hi-Z
TCK Low to TDO Active
10
10
10
0
0
0
15
15
15
15
15
15
tJZX
Notes:
37. READY is a wired OR capable output with a weak pull-down. For a decreased falling delay, connect a 250 Ohm resistor to VSS.
38. Add this propagation delay after t
for all Master Reset Operations
RDY
Document #: 38-06072 Rev. *E
Page 28 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
READ Cycle for Pipelined Mode, DDRON = LOW
t
CYC
C
t
t
HAC
SAC
R/W
A
A
A
A
A
A
A
n+6
n
n+1
x
n+2
n
n+3
n+4
n+5
A
2 pipeline stages
DQ
DQ
DQ
DQ
DQ
DQ
DQ
n+4
x-1
n+1
n+2
n+3
DQ
t
DC
t
CD
WRITE Cycle for Pipelined and Flow-Through Modes, DDRON = LOW
t
CYC
C
R/W
A
A
A
A
A
A
A
n+6
n
n+1
n+2
n+3
n+4
n+5
A
2 pipeline stages
DQ
DQ
DQ
DQ
DQ
DQ
DQ
n+5
n+6
DQ
n
n+1
n+3
n+4
n+2
tSD tHD
Document #: 38-06072 Rev. *E
Page 30 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
READ with Address Counter Advance for Pipelined Mode, DDRON = LOW
t
CYC
C
A
A
n
Internal
Address
A
A
n+1
A
A
n
n+2
n+3
ADS
CNTEN
DQ
DQ
DQ
DQ
DQ
n+1
x-1
x
n
DQ
DQ
n+3
n+2
READ with Address Counter Advance for Flow-Through Mode, DDRON = LOW
tCYC
C
tSAC tHAC
A
An
ADS
CNTEN
DQ
tSAC tHAC
tCD1
DQx
DQn
DQn + 1
DQn + 2
DQn + 3
DQn + 4
tDC
READ EXTERNAL ADDRESS
READ WITH COUNTER
COUNTER HOLD
READ W ITH COUNTER
Document #: 38-06072 Rev. *E
Page 31 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
Mailbox Interrupt Output, DDRON = LOW
tCYC
C
L
AL
AMAX
R/WL
DQL
INTR
tSINT
tRINT
CR
AMAX
AR
R/WR
DQR
DQMAX
Document #: 38-06072 Rev. *E
Page 32 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
Port-to-Port WRITE–READ for Pipelined Mode, DDRON = LOW
t
CYC
Left Port
C
L
A
A
L
n
R/W
DQ
L
DQ
L
n
Right Port
t
CCS
C
R
t
CYC
A
A
R
n
R/W
R
t
t
SAC HAC
DQ
DQ
R
n
t
t
DC
CD2
Chip Enable READ for Pipelined Mode, DDRON = LOW
t
CYC
C
CE0
CE1
R/W
A
t
t
SAC HAC
A
A
A
A
A
A
A
n+6
n
n+1
n+2
n+3
n+4
n+5
DQ
DQ
DQ
n+3
n
t
t
CKLZ2
t
CKHZ2
CD2
Document #: 38-06072 Rev. *E
Page 33 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
OE Controlled WRITE for Pipelined Mode, DDRON = LOW
t
CYC
C
A
A
A
A
A
A
A
A
n+3
x+1
x+2
x+3
n
n+1
n+2
R/W
OE
t
OHZ
DQ
x+1
DQ
DQ
DQ
DQ
DQ
DQ
n+3
x-1
x
n
n+1
n+2
DQ
OE Controlled WRITE for Flow-Through Mode, DDRON = LOW
t
CYC
C
A
A
A
A
A
A
A
A
n+3
x+1
x+2
x+3
n
n+1
n+2
R/W
OE
tOHZ
DQ
x+2
DQ
DQ
DQ
DQ
DQ
DQ
n+3
DQ
x
x+1
n
n+1
n+2
Document #: 38-06072 Rev. *E
Page 34 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
Byte-Enable READ for Pipelined Mode, DDRON = LOW
tCYC
C
A
A
A
A
n
n+1
n+2
n+3
A
R/W
BE7
BE6
BE5
BE4
BE3
BE2
BE1
BE0
tCKLZ2
tCKHZ2
DQn+1(63:71)
DQ
63:71
DQn+1(54:62)
DQ
DQ
DQ
54:62
DQn+2(45:53)
DQn+2(36:44)
45:53
36:44
DQn+1(27:35)
DQ
DQ
27:35
DQn+2(18:26)
18:26
DQn+3(9:17)
DQ
DQ
9:17
0:8
DQn+3(0:8)
Document #: 38-06072 Rev. *E
Page 35 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
Port-to-Port WRITE-to-READ for Flow-Through Mode, DDRON = LOW
CL
R/WL
tSAC
tHAC
tHD
NO MATCH
AL
MATCH
tSD
VALID
DQL
tCCS
`
CR
tCD1
R/WR
tHAC
tSAC
NO MATCH
AR
MATCH
tCD1
DQR
VALID
VALID
tDC
tDC
Busy Address Readback for Pipelined and Flow-Through Modes, DDRON = LOW[39]
t
CYC
~
~
C
Internal
Address
Amatch+2
Amatch+3
Amatch+4
~
~
BUSY
CNTEN
~
~
ADS
External
Address
Amatch
tAC
tCA
Note:
39. A
is the matching address which will be reported on the address bus of the losing port. The counter operation selected for reporting the address is “Busy
match
Address Readback.”
Document #: 38-06072 Rev. *E
Page 36 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
Read Cycle for Flow-Through Mode, DDRON = LOW
tCYC
C
CE0
CE1
tSAC tHAC
BEn
R/W
tSAC
tHAC
A
An
An + 1
An + 2
An + 3
tCKHZ1
tCD1
tDC
DQ
DQn
DQn + 1
DQn + 2
tCKLZ1
tDC
tOLZ
tOHZ
OE
tOE
READ-to-WRITE for Pipelined Mode, DDRON = LOW (OE = VIL)[40, 41, 42]
tCYC
tCL
C
tCH
A
A
x
A
A
n+2
A
n
n+1
tSAC tHAC
tSAC tHAC
R/W
DQ
DQ
DQ
DQ
x
DQ
x-2
x-1
DQ
n+2
DQ
n+1
n
tDC
tCD2
tCKHZ2
tSD tHD
Notes:
40. When OE = V , the last read operation is allowed to complete before the DQ bus is tri-stated and the user is allowed to drive write data.
IL
41. Two dummy writes should be issued to accomplish bus turnaround. The third instruction is the first valid write.
42. Chip enable or all byte enables should be held inactive during the two dummy writes to avoid data corruption.
Document #: 38-06072 Rev. *E
Page 37 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
READ-to-WRITE for Pipelined Mode, DDRON = LOW (OE Controlled)[43, 44]
tCYC
C
A
A
A
A
A
A
A
n+3
x
x+1
x+2
n
n+1
n+2
A
tSAC tHAC
R/W
OE
DQ
tOHZ
tSD tHD
DQ
DQ
x
DQ
DQ
DQ
DQ
DQ
n+3
x-2
x-1
n
n+1
n+2
READ-to-WRITE-to-READ for DDR, DDRON = HIGH[40,41,45,46]
tCH tCL
C
tCYC
C
tSAC
tCHCH tCHCH
tHAC
A
A
A
n+2
A
x
n
A
n+1
tSAC tHAC
R/W
DQ
tCKHZ
DQn[1] DQn[0]
DQx-2[0]
DQ [0]
DQ [0]
n+2
DQ [1]
DQ [0]
n+1
DQ [1]
x-1
x
DQ [0]
x
x-1
DQ [1]
DQ [1]
n+1
n+2
DQ [1]
n+2
tCD
tDC
tSD tHD
Notes:
43. OE should be deasserted and t
allowed to elapse before the first write operation is issued.
OHZ
44. Any write scheduled to complete after OE is deasserted will be preempted.
45. The address should be held constant during the two dummy writes and first valid write to avoid data corruption.
46. D[1] / Q [1] contains data [71:36]; D[0] / Q[0] contains data [35:0].
Document #: 38-06072 Rev. *E
Page 38 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
Read-to-Write-to-Read for Flow-Through Mode, DDRON = LOW (OE = LOW)
tCYC
C
tSAC tHAC
CE0
CE1
BEn
tSAC
tHAC
R/W
A
An
An + 1
An + 2
An + 2
An + 3
An + 4
tSD
tHD
DQIN
DQn + 2
tCD1
tCD1
tCD1
tCD1
DQn
tDC
DQOUT
DQn + 1
DQn + 3
tCKHZ1
tCKLZ1
tDC
READ
NOP
WRITE
READ
Document #: 38-06072 Rev. *E
Page 39 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
Read-to-Write-to-Read for Flow-Through Mode, DDRON = LOW (OE Controlled)
tCYC
C
tHAC
tSAC
CE0
CE1
BEn
tHAC
tSAC
R/W
A
An
An + 1
An + 2
tHD
An + 3
An + 4
An + 5
tSD
DQIN
DQn + 2
DQn + 3
tOE
tCD1
tCD1
tDC
tCD1
DQOUT
DQn
DQn + 4
tDC
tCKLZ1
tOHZ
OE
READ
WRITE
READ
Document #: 38-06072 Rev. *E
Page 40 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow-Through Modes, Clock Timing Violates tCCS. (Flag Both
Ports)
Port A
C
A
R/W
BUSY
C
tBSY
tBSY
< tCCS
Port B
A
R/W
tBSY
tBSY
BUSY
BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow-Through Modes, Clock Timing Meets tCCS. (Flag Losing
Port)
Losing Port
C
A
R/W
tccs
tBSY
BUSY
tBSY
Winning Port
C
A
Match
R/W
BUSY
Document #: 38-06072 Rev. *E
Page 41 of 48
PRELIMINARY
FullFlex
Switching Waveforms (continued)
Read with Echo Clock for Pipelined and Flow-Through Modes (CQEN = HIGH)
C
t
t
HAC
SAC
R/W
A
A
A
A
A
A
A
A
n
n+1
n+2
n+3
n+4
n+5
n+6
CQ0
CQ0
CQ1
t
CCQ
CQ1
DQ
t
CQHQX
t
CQHQV
DQ
DQ
DQ
DQ
DQ
n+4
DQ
DQ
x
n
n+1
n+2
n+3
x-1
Document #: 38-06072 Rev. *E
Page 42 of 48
PRELIMINARY
FullFlex
Ordering Information
512K
×
72 (36 Mbit) 1.8V Synchronous CYDD36S72V18 Dual-Port SRAM (SDR and DDR I/O)
Speed
Package
Operating
Range
(MHz)
Ordering Code
Name
BY484
BY484
BY484
BY484
Package Type
200 CYDD36S72V18-200BBC
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
CYDD36S72V18-200BBI
167 CYDD36S72V18-167BBC
CYDD36S72V18-167BBi
256K
×
72 (18 Mbit) 1.8V Synchronous CYDD18S72V18 Dual-Port SRAM (SDR and DDR I/O)
Package
Speed
Operating
Range
(MHz)
Ordering Code
Name
BY484
BY484
BY484
BY484
BY484
Package Type
250 CYDD18S72V18-250BBC
200 CYDD18S72V18-200BBC
CYDD18S72V18-200BBI
167 CYDD18S72V18-167BBC
CYDD18S72V18-167BBI
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
128K
×
72 (9 Mbit) 1.8V Synchronous CYDD09S72V18 Dual-Port SRAM (SDR and DDR I/O)
Package
Speed
Operating
Range
(MHz)
Ordering Code
Name
BY484
BY484
BY484
BY484
Package Type
200 CYDD09S72V18-200BBC
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
CYDD09S72V18-200BBI
167 CYDD09S72V18-167BBC
CYDD09S72V18-167BBI
64K
× 72 (4 Mbit) 1.8V Synchronous CYDD04S72V18 Dual-Port SRAM (SDR and DDR I/O)
Speed
Package
Operating
Range
(MHz)
Ordering Code
Name
Package Type
250 CYDD04S72V18-250BBC
200 CYDD04S72V18-200BBC
CYDD04S72V18-200BBI
167 CYDD04S72V18-167BBC
CYDD04S72V18-167BBI
BY484
BY484
BY484
BY484
BY484
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
1024K
×
36 (36 Mbit) 1.8V Synchronous CYDD36S36V18 Dual-Port SRAM (DDR only I/O)
Package
Speed
Operating
Range
(MHz)
Ordering Code
Name
BY484
BY484
BY484
Package Type
200 CYDD36S36V18-200BBC
167 CYDD36S36V18-167BBC
CYDD36S36V18-167BBI
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
512K
×
36 (18 Mbit) 1.8V Synchronous CYDD18S36V18 Dual-Port SRAM (DDR only I/O)
Package
Speed
Operating
Range
(MHz)
Ordering Code
Name
Package Type
200 CYDD18S36V18-200BBC BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial
167 CYDD18S36V18-167BBC BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial
CYDD18S36V18-167BBI BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Industrial
Document #: 38-06072 Rev. *E
Page 43 of 48
PRELIMINARY
FullFlex
Ordering Information (continued)
256K
×
36 (9 Mbit) 1.8V Synchronous CYDD09S36V18 Dual-Port SRAM (DDR only I/O)
Speed
Package
Operating
Range
(MHz)
Ordering Code
Name
BB256
BB256
BB256
Package Type
200 CYDD09S36V18-200BBC
167 CYDD09S36V18-167BBC
CYDD09S36V18-167BBI
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial
128K
×
36 (4 Mbit) 1.8V Synchronous CYDD04S36V18 Dual-Port SRAM (DDR only I/O)
Package
Speed
Operating
Range
(MHz)
Ordering Code
Name
BB256
BB256
BB256
Package Type
200 CYDD04S36V18-200BBC
167 CYDD04S36V18-167BBC
CYDD04S36V18-167BBI
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial
2048K
×
18 (36 Mbit) 1.8V Synchronous CYDD36S18V18 Dual-Port SRAM (DDR only I/O)
Package
Speed
Operating
Range
(MHz)
Ordering Code
Name
BY484
BY484
BY484
Package Type
200 CYDD36S18V18-200BBC
167 CYDD36S18V18-167BBC
CYDD36S18V18-167BBI
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Commercial
484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (PBGA) Industrial
1024K
×
18 (18 Mbit) 1.8V Synchronous CYDD18S18V18 Dual-Port SRAM (DDR only I/O)
Package
Speed
Operating
Range
(MHz)
Ordering Code
Name
Package Type
200 CYDD18S18V18-200BBC BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial
167 CYDD18S18V18-167BBC BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Commercial
CYDD18S18V18-167BBI BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (FBGA) Industrial
512K
×
18 (9 Mbit) 1.8V Synchronous CYDD09S18V18 Dual-Port SRAM (DDR only I/O)
Package
Speed
Operating
Range
(MHz)
Ordering Code
Name
BB256
BB256
BB256
Package Type
200 CYDD09S18V18-200BBC
167 CYDD09S18V18-167BBC
CYDD09S18V18-167BBI
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial
256K
×
18 (4 Mbit) 1.8V Synchronous CYDD04S18V18 Dual-Port SRAM (DDR only I/O)
Package
Speed
Operating
Range
(MHz)
Ordering Code
Name
BB256
BB256
BB256
Package Type
200 CYDD04S18V18-200BBC
167 CYDD04S18V18-167BBC
CYDD04S18V18-167BBI
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Commercial
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (FBGA) Industrial
Document #: 38-06072 Rev. *E
Page 44 of 48
PRELIMINARY
FullFlex
Package Diagrams
256-Ball FBGA (17 x 17 mm) BB256
TOP VIEW
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
Ø0.45 0.05(256X)ꢀCPꢁD DEVICES (37K & 39K)
PIN 1 CORNER
+0.10
Ø0.50 (256X)ꢀAꢁꢁ OTHER DEVICES
ꢀ0.05
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
J
G
H
J
K
ꢁ
K
ꢁ
M
N
P
R
T
M
N
P
R
T
1.00
B
7.50
15.00
A
17.00 0.10
A
SEATING PꢁANE
0.20(4X)
A1
C
REFERENCE JEDEC MOꢀ192
A1 0.36 0.56
1.40 MAX. 1.70 MAX.
51-85108-*F
A
Document #: 38-06072 Rev. *E
Page 45 of 48
PRELIMINARY
FullFlex
Package Diagrams (continued)
256 FBGA (19 x 19 x 1.7 mm) BW256C
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
Ø0.50 (256 X)
1
3
PIN A1 CORNER
13
13
1
9
11
15
15
11
9
8
5
5
3
7
7
12
14
16
16
14
12
2
6
10
10
6
2
4
8
4
A
B
C
D
E
A
B
C
D
E
F
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
T
M
N
P
R
T
1.00 (REF)
-B-
15.00 (REF)
19.00 +/- 0.10
-A-
0.15(4X)
Package Weight - 1.1 grams
Jedec Outline - Design Guide 4.14
-C-
SEATING PLANE
001-00915-*A
Document #: 38-06072 Rev. *E
Page 46 of 48
PRELIMINARY
FullFlex
Package Diagrams (continued)
484-ball PBGA (23 mm x 23 mm x 2.03 mm) BY484
Ø0.50~Ø0.70(484X)
PIN #1 CORNER
9
1
11
7
3
1
3
5
7
9
13
5
11
13 15 17 19
10 12 14 16 18
21
20 22
21
17 15
19
2
4
6
8
22 20 18 16 14 12 10
8
6
4
2
Ø1.00(3X) REF.
A
B
A
B
C
C
D
E
D
E
F
F
G
H
J
G
H
J
K
K
L
L
M
N
P
M
N
P
R
R
T
T
U
V
U
V
W
Y
W
Y
AA
AB
AA
AB
1.00
-B-
21.00
3.20*45°(4x)
20.00 REF.
-A-
23.00 0.20
0.20(4X)
30° TYP.
Package Weight - 2.0 grams
Jedec Outline - Design Guide 4.14
-C-
SEATING PLANE
51-85218-**
FullFlex is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are
trademarks of their respective holders.
Document #: 38-06072 Rev. *E
Page 47 of 48
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
FullFlex
Document History Page
Document Title: FullFlex™ Synchronous DDR Dual-Port SRAM
Document Number: 38-06072
Issue
Date
274729 See ECN
Orig. of
Change
SPN
REV.
**
ECN NO.
Description of Change
New data sheet
*A
294239 See ECN
SPN
Updated VIM section
Added notes 7
Added timing for 100 MHz with DLL Disabled
Removed tPS
*B
*C
301331 See ECN
318834 See ECN
SPN
SPN
Added note 19
Updates Selectable I/O Standard Section
Updated Block Diagram
Updated 484 pinouts, changed pins D11, W12, K3, K20
Added note 4 - Leaving pin NC disables VIM
Updated 256 pinout, changed pins C10, G5, N7, N10
Added note 18, 19, 20, 21
Updated parameters in table 16
Updated note 1
*D
386692 See ECN
SPN
Updated ordering information
Added statement about no echo clocks for flow-through mode
Updated electrical characteristics
Added note 27 (timing for x18 devices)
Updated address readback latency to 2 cycles for DDR mode
Updated DDR timing numbers for tCD, tDC, tCCQ, tCQHQV, tCQHQX, tCKHZ, tCKLZ
Updated input edge rate
Removed -133 speed bin electrical characteristics and timing columns
Updated Table 5 on collision detection to be the same as the one found in the EROS
Added description of busy readback in collision detection section
Changed dummy write descriptions
Updated PORTSTD[1:0] connection details
Updated ZQ pins connection details
Updated address count notes
Updated note 17, BO to BEO
Added power supply requirements to MRST and VC_SEL
Updated 484 ball package
Changed name from FLEX72-E, FLEX36-E, AND FLEX18-E to FullFlex72,
FullFlex36, and FullFlex18
*E
401662 See ECN
KGH
Updated READY description to include Wired OR note
Updated master reset to include wired OR note for READY
Updated electrical characteristics to include IOH and IOL values
Updated electrical characteristics to include READY
Added IIX3
Updated maximum input capacitance
Added note 29
Updated Pin Definitions for CQ0, CQ0, CQ1, and CQ1
Changed voltage name from VDDQ to VDDIO
Changed voltage name from VDD to VCORE
Updated the Package Type for the CYDXXS36V18 parts
Updated the Package Type for the CYDXXS18V18 parts
Included the Package Diagram for the 256-Ball FBGA (19 x 19 mm) BW256
Included an OE Controlled Write for Flow-Through Mode Switching Waveform
Included a Read with Echo Clock Switching Waveform
Included a Unit column for Table 5
Removed Switching Characteristic tCA from chart
Included tOHZ in Switching Waveform OE Controlled Write for Pipelined Mode
Included tCKLZ2 in Waveform Read-to-Write-to-Read for Flow-Through Mode
Updated AC Test Load and Waveforms
Included FullFlex36 DDR 484-ball BGA Pinout (Top View)
Included FullFlex18 DDR 484-ball BGA Pinout (Top View)Included Timing
Parameter tCORDY
Document #: 38-06072 Rev. *E
Page 48 of 48
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