CYDD36S36V18-167BGXC

FullFlex

FullFlex™ Synchronous

DDR Dual-Port SRAM

— Selectable LVTTL (3.3V), Extended HSTL

(1.4V–1.9V), 1.8V LVCMOS, or 2.5V LVCMOS I/O on

each port

Features

• True dual-ported memory allows simultaneous access

to the shared array from each port

— Burst counters for sequential memory access

— Mailbox with interrupt flags for message passing

— Dual Chip Enables for easy depth expansion

• Synchronous pipelined operation with selectable

Double Data Rate (DDR) or Single Data Rate (SDR)

operation on each port

— DDR interface at 200 MHz

Functional Description

— SDR interface at 250 MHz

The FullFlex™ Dual-Port SRAM families consist of 4-Mbit,

9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual-port static

RAMs that are high-speed, low-power 1.8V/1.5V CMOS. Two

ports are provided, allowing the array to be accessed simulta-

neously. Simultaneous access to a location triggers determin-

istic access control. For FullFlex72, these ports can operate

independently in DDR mode with 36-bit bus widths or in SDR

mode with 72-bit bus widths. For FullFlex36 and FullFlex18,

the ports operate in DDR mode only. Each port can be

independently configured for two pipelined stages for SDR

mode or 2.5 stages in DDR mode. Each port can also be

configured to operate in pipelined or flow-through mode in

SDR mode.

— Up to 36-Gb/s bandwidth (250 MHz * 72 bit * 2 ports)

• Selectable pipelined or flow-through mode

• 1.5V or 1.8V core power supply

• Commercial and Industrial temperature ranges

• IEEE 1149.1 JTAG boundary scan

• Available in 484-ball PBGA Packages and 256-ball

FBGA Packages

• FullFlex72 family

— 18 Mbit: 256K x 36 x 2 DDR or 256K x 72 SDR

(CYDD18S72V18)

Advanced features include built-in deterministic access

control to manage address collisions during simultaneous

access to the same memory location, Variable Impedance

Matching (VIM) to improve data transmission by matching the

output driver impedance to the line impedance, and echo

clocks to improve data transfer.

— 9 Mbit: 128K x 36 x 2 DDR or 128K x 72 SDR

(CYDD09S72V18)

— 4 Mbit: 64K x 36 x 2 DDR or 64 x 72 SDR

(CYDD04S72V18)

• FullFlex36 family

To reduce the static power consumption, chip enables can be

used to power down the internal circuitry. The number of

cycles of latency before a change in CE0 or CE1 will enable

or disable the databus matches the number of cycles of read

latency selected for the device. In order for a valid write or read

to occur, both chip enable inputs on a port must be active.

— 36 Mbit: 512K x 36 x 2 DDR (CYDD36S36V18)

— 18 Mbit: 256K x 36 x 2 DDR (CYDD18S36V18)

— 9 Mbit: 128K x 36 x 2 DDR (CYDD09S36V18)

— 4 Mbit: 64K x 36 x 2 DDR (CYDD04S36V18)

• FullFlex18 family

Each port contains an optional burst counter on the input

address register. After externally loading the counter with the

initial address, the counter will increment the address inter-

nally.

— 36 Mbit: 1M x 18 x 2 DDR (CYDD36S18V18)

— 18 Mbit: 512K x 18 x 2 DDR (CYDD18S18V18)

— 9 Mbit: 256K x 18 x 2 DDR (CYDD09S18V18)

— 4 Mbit: 128K x 18 x 2 DDR (CYDD04S18V18)

Additional features of this device include a mask register and

a

mirror register to control counter increments and

• Built-in deterministic access control to manage

address collisions

wrap-around. The counter-interrupt (CNTINT) flags notify the

host that the counter will reach maximum count value on the

next clock cycle. The host can read the burst-counter internal

address, mask register address, and busy address on the

address lines. The host can also load the counter with the

address stored in the mirror register by utilizing the retransmit

functionality. Mailbox interrupt flags can be used for message

passing, and JTAG boundary scan and asynchronous Master

Reset (MRST) are also available. The logic block diagram in

Figure 1 displays these features.

— Deterministic flag output upon collision detection

— Collision detection on back-to-back clock cycles

— First Busy Address readback

• Advanced features for improved high-speed data

transfer and flexibility

— Variable Impedance Matching (VIM)

— Echo clocks

The FullFlex72 DDR family of devices is offered in a 484-ball

plastic BGA package. The FullFlex36 and FullFlex18 DDR

only families of devices are offered in both 484-ball and

256-ball fine pitch BGA packages.

Cypress Semiconductor Corporation

Document #: 38-06072 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 21, 2006

FullFlex

FTSEL

CQEN

L

R

CQEN

L

R

CONFIG Block

PORTSTD[1:0]

L

R

DDRON

R

L

DQ [71:0]

R

DQ[71:0]

BE [7:0]

L

BE [7:0]

R

L

CE0

CE1

CE0

R

L

IO

Control

IO

Control

CE1

R

L

OE

R

L

R/W

R

L

CQ0

L

R

CQ0

CQ1

L

R

CQ1

L

R

Dual Ported Array

Collision Detection

Logic

BUSY

L

R

A [19:0]

L

R

CNT/MSK

L

R

ADS

L

R

CNTEN

R

L

Address &

Counter Logic

Address &

Counter Logic

CNTRST

RET

R

L

R

RET

L

CNTINT

L

CNTINT

R

C

L

R

C

L

C

R

WRP

L

WRP

R

TRST

TMS

TDI

Mailboxes

INT

R

L

JTAG

TDO

TCK

READY

L

MRST

READY

LowSPD

RESET

LOGIC

LowSPD

L

R

ZQ0

ZQ1

R

L

ZQ0

ZQ1

R

Figure 1. Block Diagram^[1,2,3]

Notes:

1. The CYDD36S18V18 device has 20 address bits. The CYDD36S36V18, and the CYDD18S18V18 devices have 19 address bits. The CYDD18S72V18,

CYDD18S36V18, and the CYDD09S18V18 devices have 18 address bits. The CYDD09S72V18, CYDD04S18V18, and the CYDD09S36V18 devices have 17

address bits. The CYDD04S36V18 and the CYDD04S72V18 devices have 16 address bits.

2. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines.

3. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte

enables.

Document #: 38-06072 Rev. *I

Page 2 of 53

FullFlex

FullFlex72 SDR/DDR 484-ball BGA Pinout (Top View)

20 21 22

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

DNU DQ34 DQ32 DQ30 DQ27 DQ60 DQ57 DQ54 DQ24 DQ21 DQ18 DQ18 DQ21 DQ24 DQ54 DQ57 DQ60 DQ27 DQ30 DQ32 DQ34 DNU

A

B

C

L

R

DQ63 DQ35 DQ33 DQ31 DQ28 DQ61 DQ58 DQ55 DQ25 DQ22 DQ19 DQ19 DQ22 DQ25 DQ55 DQ58 DQ61 DQ28 DQ31 DQ33 DQ35 DQ63

L

R

DQ65 DQ64 VSS VSS DQ29 DQ62 DQ59 DQ56 DQ26 DQ23 DQ20 DQ20 DQ23 DQ26 DQ56 DQ59 DQ62 DQ29 VSS VSS DQ64 DQ65

L

R

DQ67 DQ66 VSS VSS VSS CQ1L CQ1L DDR LOW PORT ZQ0L BUSY CNTI PORT DNU CQ1R CQ1R VSS VSS VSS DQ66 DQ67

[4]

L

ONL SPDL STD0

L

NTL STD1

L

R

D

E

F

DQ69 DQ68 VDDI VSS VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI DNU VSS VDDI DQ68 DQ69

OL OL OL OL OL OL OR OR OR OR OR

L

R

DQ71 DQ70 CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R DQ70 DQ71

OL OL OL OL OL RE RE RE RE OR OR OR OR OR

L

R

A0L A1L RETL BE2L VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI BE2R RETR A1R A0R

OL OL OR OR

G

H

J

L

R

A2L A3L WRP BE6L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE6R WRP A3R A2R

OL OL OR OR

L

R

A4L A5L READ BE3L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE3R READ A5R A4R

YL OL OL OR OR YR

A6L A7L ZQ1L BE7L VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VDDI BE7R ZQ1R A7R A6R

[4]

K

L

RE

OR

A8L A9L

CL

OEL VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER CR A9R A8R

RE RE

A10L A11L CL BE5L VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL BE5R CR A11R A10R

RE RE

M

N

A12L A13L ADSL BE1L VDDI VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL BE1R ADSR A13R A12R

OL RE RE

A14L A15L CNT/ BE4L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE4R CNT/ A15R A14R

MSKL

OL

OR

MSK

R

P

R

T

A16L A17L CNTE BE0L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R A16R

[7]

[6]

[7]

NL

OL

OR

NR

A18L DNU CNTR INTL VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI INTR CNTR DNU A18R

[5]

STL

OL

L

R

OR

STR

DQ53 DQ52 R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR DQ52 DQ53

U

V

L

NL OL OL OL OL OL RE RE RE RE OR OR OR OR OR NR

R

DQ51 DQ50 FTSE VDDI DNU VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI FTSE DQ50 DQ51

LL OL OL OL OL OL OR OR OR OR OR OR LR

L

R

DQ49 DQ48 VSS MRST VSS CQ0L CQ0L DNU PORT CNTI BUSY ZQ0R PORT LOW DDR CQ0R CQ0R VSS TDI TDO DQ48 DQ49

[4]

L

STD1 NTR

R

STD0 SPDR ONR

R

W

Y

DQ47 DQ46 VSS VSS DQ11 DQ44 DQ41 DQ38 DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ38 DQ41 DQ44 DQ11 TMS TCK DQ46 DQ47

L

R

DQ45 DQ17 DQ15 DQ13 DQ10 DQ43 DQ40 DQ37 DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ37 DQ40 DQ43 DQ10 DQ13 DQ15 DQ17 DQ45

AA

AB

L

R

DNU DQ16 DQ14 DQ12 DQ9L DQ42 DQ39 DQ36 DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ36 DQ39 DQ42 DQ9R DQ12 DQ14 DQ16 DNU

L

R

Notes:

4. Leaving this pin DNU disables VIM

5. Leave this ball unconnected for CYDD18S72V18, CYDD09S72V18 and CYDD04S72V18.

6. Leave this ball unconnected for CYDD09S72V18 and CYDD04S72V18

7. Leave this ball unconnected for CYDD04S72V18

Document #: 38-06072 Rev. *I

Page 3 of 53

FullFlex

FullFlex36 DDR 484-ball BGA Pinout (Top View)^[8]

20 21 22

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

DNU DNU DNU DNU DNU DQ33 DQ30 DQ27 DQ24 DQ21 DQ18 DQ18 DQ21 DQ24 DQ27 DQ30 DQ33 DNU DNU DNU DNU DNU

A

B

C

L

R

DNU DNU DNU DNU DNU DQ34 DQ31 DQ28 DQ25 DQ22 DQ19 DQ19 DQ22 DQ25 DQ28 DQ31 DQ34 DNU DNU DNU DNU DNU

L

R

DNU DNU VSS VSS DNU DQ35 DQ32 DQ29 DQ26 DQ23 DQ20 DQ20 DQ23 DQ26 DQ29 DQ32 DQ35 DNU VSS VSS DNU DNU

L

R

DNU DNU VSS VSS VSS CQ1L CQ1L VDDI LOW PORT ZQ0L BUSY CNTI PORT DNU CQ1R CQ1R VSS VSS VSS DNU DNU

[4]

OL SPDL STD0

L

NTL STD1

L

D

E

F

DNU DNU VDDI VSS VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI DNU VSS VDDI DNU DNU

OL OL OR OR OR OR OL OL OL OL OR

DNU DNU CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R DNU DNU

OL OL OR OR OR RE RE RE RE OL OL OL OR OR

A0L A1L RETL BE2L VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI BE2R RETR A1R A0R

OL OL OR OR

G

H

J

L

R

A2L A3L WRP BE3L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE3R WRP A3R A2R

OL OL OR OR

L

R

A4L A5L READ DNU VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI DNU READ A5R A4R

YL OL OL OR OR YR

A6L A7L ZQ1L DNU VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VDDI DNU ZQ1R A7R A6R

[4]

K

L

RE

OR

A8L A9L

CL

OEL VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER CR A9R A8R

RE RE

A10L A11L CL DNU VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL DNU CR A11R A10R

RE RE

M

N

A12L A13L ADSL DNU VDDI VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL DNU ADSR A13R A12R

OL RE RE

A14L A15L CNT/ BE1L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE1R CNT/ A15R A14R

MSKL

OL

OR

MSK

R

P

R

T

A16L A17L CNTE BE0L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R A16R

NL OL OL OR OR NR

A18L DNU CNTR INTL VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI INTR CNTR DNU A18R

STL OL OL OR OR STR

L

R

DNU DNU R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR DNU DNU

NL OL OL OR OR OR RE RE RE RE OL OL OL OR OR NR

U

V

DNU DNU VDDI VDDI DNU VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI VDDI DNU DNU

OL OL OR OR OR OR OL OL OL OL OR OR OR

DNU DNU VSS MRST VSS CQ0L CQ0L DNU PORT CNTI BUSY ZQ0R PORT LOW VDDI CQ0R CQ0R VSS TDI TDO DNU DNU

[4]

STD1 NTR

R

STD0 SPDR OR

R

W

Y

DNU DNU VSS VSS DNU DQ17 DQ14 DQ11 DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ11 DQ14 DQ17 DNU TMS TCK DNU DNU

L

R

DNU DNU DNU DNU DNU DQ16 DQ13 DQ10 DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ10 DQ13 DQ16 DNU DNU DNU DNU DNU

AA

AB

L

R

DNU DNU DNU DNU DNU DQ15 DQ12 DQ9L DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ9R DQ12 DQ15 DNU DNU DNU DNU DNU

L

R

Note:

8. Use this pinout only for device CYDD36S36V18 of the FullFlex36 family.

Document #: 38-06072 Rev. *I

Page 4 of 53

FullFlex

FullFlex18 DDR 484-ball BGA Pinout (Top View)^[9]

20 21 22

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

DNU DNU DNU DNU DNU DNU DNU DNU DQ15 DQ12 DQ9L DQ9R DQ12 DQ15 DNU DNU DNU DNU DNU DNU DNU DNU

A

B

C

L

R

DNU DNU DNU DNU DNU DNU DNU DNU DQ16 DQ13 DQ10 DQ10 DQ13 DQ16 DNU DNU DNU DNU DNU DNU DNU DNU

L

R

DNU DNU VSS VSS DNU DNU DNU DNU DQ17 DQ14 DQ11 DQ11 DQ14 DQ17 DNU DNU DNU DNU VSS VSS DNU DNU

L

R

DNU DNU VSS VSS VSS CQ1L CQ1L VDDI LOW PORT ZQ0L BUSY CNTI PORT DNU CQ1R CQ1R VSS VSS VSS DNU DNU

[4]

OL SPDL STD0

L

NTL STD1

L

D

E

F

DNU DNU VDDI VSS VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI DNU VSS VDDI DNU DNU

OL OL OR OR OR OR OL OL OL OL OR

DNU DNU CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R DNU DNU

OL OL OR OR OR RE RE RE RE OL OL OL OR OR

A0L A1L RETL BE1L VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI BE1R RETR A1R A0R

OL OL OR OR

G

H

J

L

R

A2L A3L WRP DNU VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI DNU WRP A3R A2R

OL OL OR OR

L

R

A4L A5L READ DNU VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI DNU READ A5R A4R

YL OL OL OR OR YR

A6L A7L ZQ1L DNU VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VDDI DNU ZQ1R A7R A6R

[4]

K

L

RE

OR

A8L A9L

CL

OEL VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER CR A9R A8R

RE RE

A10L A11L CL DNU VTTL VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL DNU CR A11R A10R

RE RE

M

N

A12L A13L ADSL DNU VDDI VCO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL DNU ADSR A13R A12R

OL RE RE

A14L A15L CNT/ DNU VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI DNU CNT/ A15R A14R

MSKL

OL

OR

MSK

R

P

R

T

A16L A17L CNTE BE0L VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R A16R

NL OL OL OR OR NR

A18L A19L CNTR INTL VDDI VDDI VREF VSS VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI INTR CNTR A19R A18R

STL OL OL OR OR STR

L

R

DNU DNU R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR DNU DNU

NL OL OL OR OR OR RE RE RE RE OL OL OL OR OR NR

U

V

DNU DNU VDDI VDDI DNU VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI VDDI DNU DNU

OL OL OR OR OR OR OL OL OL OL OR OR OR

DNU DNU VSS MRST VSS CQ0L CQ0L DNU PORT CNTI BUSY ZQ0R PORT LOW VDDI CQ0R CQ0R VSS TDI TDO DNU DNU

[4]

STD1 NTR

R

STD0 SPDR OR

R

W

Y

DNU DNU VSS VSS DNU DNU DNU DNU DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DNU DNU DNU DNU TMS TCK DNU DNU

DNU DNU DNU DNU DNU DNU DNU DNU DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DNU DNU DNU DNU DNU DNU DNU DNU

DNU DNU DNU DNU DNU DNU DNU DNU DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DNU DNU DNU DNU DNU DNU DNU DNU

AA

AB

Note:

9. Use this pinout only for device CYDD36S18V18 of the FullFlex18 family.

Document #: 38-06072 Rev. *I

Page 5 of 53

FullFlex

FullFlex36 DDR 256 Ball BGA (Top View)

10 11

1

2

3

4

5

6

7

8

9

12

13

14

15

16

DQ32L DQ30L DQ28L DQ26L DQ24L DQ22L DQ20L DQ18L DQ18R DQ20R DQ22R DQ24R DQ26R DQ28R DQ30R DQ32R

A

B

C

D

E

F

DQ33L DQ31L DQ29L DQ27L DQ25L DQ23L DQ21L DQ19L DQ19R DQ21R DQ23R DQ25R DQ27R DQ29R DQ31R DQ33R

[4]

DQ34L DQ35L

RETL

INTL

CQ1L

DNU

TRST

MRST ZQ0R

CQ1R

INTR

RETR

DQ35R DQ34R

A0L

A2L

A1L

A3L

WRPL VREFL VDDIOL LOWSP

DL

VSS

VTTL

VTTL VSS

LOWSP VDDIO VREFR WRPR

DR

A1R

A3R

A0R

A2R

R

CE0L

CE1L VDDIOL VDDIOL VDDIOL VCORE VCOR VDDIO VDDIO VDDIO

CE1R

CE0R

E

R

A4L

A5L

CNTINTL BE3L VDDIOL VDDIOL

[4]

VSS

VDDIO

R

BE3R CNTINT

R

A5R

A4R

A6L

A7L

BUSYL

BE2L ZQ0L

VSS

VDDIO

R

BE2R

BUSYR

A7R

A6R

G

H

J

A8L

A9L

CL

VTTL VCORE

VCORE VTTL

CR

A9R

A8R

A10L

A12L

A14L

A11L

A13L

A15L

CL

PORTS VCORE

TD1L

VCORE PORTS

TD1R

CR

A11R

A13R

A15R

A10R

A12R

A14R

OEL

BE1L VDDIOL

VDDIO

R

BE1R

OER

ADSR

K

L

ADSL

BE0L VDDIOL

VDDIO VDDIO

R

BE0R

R

[11]

[10]

[11]

A16L

A17L

DNU

R/WL

CQENL VDDIOL VDDIOL VDDIOL VCORE VCOR VDDIO VDDIO VDDIO CQENR

R/WR A17R

DNU

A16R

DNU

M

N

P

R

T

E

R

[4]

DNU

CNT/MS VREFL PORTS READY ZQ1L

KL

VTTL

TMS

VTTL ZQ1R

READY PORTS VREFR CNT/MS

TD0L

L

R

TD0R

KR

DQ16L DQ17L CNTENL CNTRS CQ0L

TL

CQ0L

TCK

TDO

DQ1R

DQ0R

TDI

CQ0R

CQ0R CNTRS CNTENR DQ17R DQ16R

TR

DQ15L DQ13L DQ11L

DQ9L

DQ7L

DQ5L

DQ4L

DQ3L

DQ2L

DQ1L

DQ0L

DQ3R

DQ2R

DQ5R

DQ4R

DQ7R

DQ9R

DQ11R DQ13R DQ15R

DQ14L DQ12L DQ10L

DQ8L

DQ6L

DQ6R

DQ8R

DQ10R DQ12R DQ14R

Notes:

10. Leave this ball unconnected for CYDD09S36V18 and CYDD04S36V18.

11. Leave this ball unconnected for CYDD04S36V18.

Document #: 38-06072 Rev. *I

Page 6 of 53

FullFlex

FullFlex18 DDR 256 Ball BGA (Top View)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

DNU

DQ17L DQ16L DQ13L DQ12L

DQ9L

DQ9R DQ12R DQ13R DQ16R DQ17R

DNU

A

B

C

D

E

F

DNU

A0L

DNU

A1L

DNU

INTL

DQ15L DQ14L DQ11L DQ10L DQ10R DQ11R DQ14R DQ15R

[4]

DNU

INTR

DNU

A1R

A3R

DNU

A0R

RETL

CQ1L

DNU

TRST

MRST ZQ0R

CQ1R

RETR

WRPL VREFL VDDIOL LOWSP

DL

VSS

VTTL

VTTL VSS

LOWSP VDDIOR VREFR WRPR

DR

A2L

A3L

CE0L

CE1L VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CE1R

CE0R

A2R

A4L

A5L

CNTINTL DNU VDDIOL VDDIOL

[4]

VSS

VSS VDDIOR DNU CNTINTR A5R

A4R

A6L

A7L

BUSYL

DNU

ZQ0L

VSS

VSS VDDIOR DNU

BUSYR

CR

A7R

A9R

A6R

G

H

J

A8L

A9L

CL

VTTL VCORE

VSS

VCORE VTTL

A8R

A10L

A12L

A14L

A11L

A13L

A15L

CL

PORTST VCORE

D1L

VCORE PORTST

D1R

CR

A11R

A13R

A15R

A10R

A12R

A14R

A16R

OEL

BE1L VDDIOL

VSS VDDIOR BE1R

OER

ADSR

K

L

ADSL

BE0L VDDIOL

VSS VDDIOR VDDIOR BE0R

[13]

A16L A17L

[12]

R/WL

CQENL VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CQENR R/WR A17R

M

N

P

R

T

[4]

[12]

A18L

DNU

CNT/MS VREFL PORTST READYL ZQ1L

KL

VTTL

TMS

VTTL ZQ1R

READY PORTST VREFR CNT/MS

DNU A18R

D0L

R

D0R

KR

DNU

DNU CNTENL CNTRST CQ0L

L

CQ0L

DQ5L

DQ4L

TCK

TDO

DQ1R

DQ0R

TDI

CQ0R

CQ0R CNTRST CNTENR DNU

R

DNU

DQ6L

DQ2L

DQ3L

DQ1L

DQ0L

DQ2R

DQ3R

DQ5R

DQ4R

DQ6R

DNU

DQ8L

DQ7L

DQ7R

DQ8R

DNU

Table 1. Selection Guide

–200

250

–167

200

Unit

[14]

SDR f_MAX

MHz

ns

[15]

DDR f_MAX

200

167

SDR Max. Access Time (Clock to Data)

DDR Max. Access Time (Clock to Data)

Typical Operating Current I_CC

2.64

3.3

0.50

0.60

ns

800^[16]

210^[16]]

700^[16]

210^[16]

mA

Typical Standby Current for I_SB3(Both Ports CMOS Level)

Notes:

12. Leave this ball unconnected for CYDD09S18V18 and CYDD04S18V18.

13. Leave this ball unconnected for CYDD04S18V18.

14. SDR mode with two pipelined stages.

15. DDR mode with 2.5 pipelined stages.

16. For 18-Mbit x36x2 DDR commercial configuration only, please refer to the electrical characteristics section for complete information.

Document #: 38-06072 Rev. *I

Page 7 of 53

FullFlex

Pin Definitions

Left Port

Right Port

A[19:0]_R

DQ[71:0]_R

Description

A[19:0]_L

DQ[71:0]_L

BE[7:0]_L

Address Inputs.^[1]

Data Bus Input/Output.^[2]

BE[7:0]_R

Byte Select Inputs.^[3]Asserting these signals enables Read and Write operations to the

corresponding bytes of the memory array.

BUSY_L

C/C_L

BUSY_R

Port Busy Output. When there is an address match and both chip enables are active for

both ports, an external BUSY signal is asserted on the fifth clock cycle from when the collision

occurs.

Clock Signal.^[18]Maximum clock input rate is f_MAX. Tie C to VSS when operating in SDR

C/C_R

mode.

CE0_L

CE0_R

Active LOW Chip Enable Input.

CE1_L

CE1_R

Active HIGH Chip Enable Input.

CQEN_L

CQ0_L

CQEN_R

CQ0_R

Echo Clock Enable Input. Assert HIGH to enable echo clocking on respective port.

Echo Clock Signal Output for DQ[35:0] for FullFlex72 devices. Echo Clock Signal Output

for DQ[17:0] for FullFlex36 devices. Echo Clock Signal Output for DQ[8:0] for FullFlex18

devices.

CQ0_L

CQ1_L

CQ0_R

CQ1_R

Inverted Echo Clock Signal Output for DQ[35:0] for FullFlex72 devices. Inverted Echo

Clock Signal Output for DQ[17:0] for FullFlex36 devices. Inverted Echo Clock Signal Output

for DQ[8:0] for FullFlex18 devices.

Echo Clock Signal Output for DQ[71:36] for FullFlex72 devices. Echo Clock Signal

Output for DQ[35:18] for FullFlex36 devices. Echo Clock Signal Output for DQ[17:9] for

FullFlex18 devices.

Inverted Echo Clock Signal Output for DQ[71:36] for FullFlex72 devices. Inverted Echo

Clock Signal Output for DQ[35:18] for FullFlex36 devices. Inverted Echo Clock Signal Output

for DQ[17:9] forFullFlex18 devices.

[17]

DDRON_L

ZQ[1:0]_L

DDRON_R

ZQ[1:0]_R

DDR Enable Input. Assert HIGH to enable DDR clocking on respective port.

VIM Output Impedance Matching Input. To use, connect a calibrating resistor between ZQ

and ground. The resistor must be five times larger than the intended line impedance driven

by the dual-port. Assert HIGH or leave DNU to disable Variable Impedance Matching.

OE_L

INT_L

OE_R

INT_R

Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ

data pins during Read operations.

Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The

upper two memory locations can be used for message passing. INT_Lis asserted LOW when

the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a

port is deasserted HIGH when it reads the contents of its mailbox.

LowSPD_L

LowSPD_R

Port Low Speed Select Input. Assert this pin LOW to disable the DLL. For operation at less

than 100 MHz, assert this pin LOW.

PORTSTD[1:0]_LPORTSTD[1:0]_RPort Clock/Address/Control/Data/Echo Clock/I/O Standard Select Input. Assert these

[19]

pins LOW/LOW for LVTTL, LOW/HIGH for HSTL, HIGH/LOW for 2.5V LVCMOS, and

HIGH/HIGH for 1.8V LVCMOS, respectively. These pins must be driven by VTTL referenced

levels.

R/W_L

R/W_R

Read/Write Enable Input. Assert this pin LOW to Write to, or HIGH to Read from the

dual-port memory array.

READY_L

READY_R

Port DLL Ready Output. This signal will be asserted LOW when the DLL and Variable

Impedance Matching circuits have completed calibration. This is a wired OR capable output.

CNT/MSK_L

ADS_L

CNT/MSK_R

ADS_R

Port Counter/Mask Select Input. Counter control input.

Port Counter Address Load Strobe Input. Counter control input.

Port Counter Enable Input. Counter control input.

CNTEN_L

CNTEN_R

Notes:

17. DDRON and DDRON needs to tie to the same voltage level for FullFlex36 and FullFlex18 Family.

L

R

18. C and C are complimentary for DDR operation.

19. PORTSTD[1:0] and PORTSTD[1:0] have internal pull-down resistors.

L

R

Document #: 38-06072 Rev. *I

Page 8 of 53

FullFlex

Pin Definitions (continued)

Left Port

CNTRST_L

Right Port

CNTRST_R

Description

Port Counter Reset Input. Counter control input.

CNTINT_L

CNTINT_R

Port Counter Interrupt Output. This pin is asserted LOW one cycle before the unmasked

portion of the counter is incremented to all “1s”.

WRP_L

WRP_R

Port Counter Wrap Input. When the burst counter reaches the maximum count, on the next

counter increment WRP can be set LOW to load the unmasked counter bits to 0 or set HIGH

to load the counter with the value stored in the mirror register.

RET_L

RET_R

Port Counter Retransmit Input. Assert this pin LOW to reload the initial address for

repeated access to the same segment of memory.

VREF_L

VREF_R

VDDIO_R

FTSEL_R

Port External HSTL I/O Reference Input. This pin is left DNU when HSTL is not used.

Port Data I/O Power Supply.

VDDIO_L

FTSEL_L

Port Flow-through Mode Select Input. Assert this pin LOW to select Flow-through mode.

Assert this pin HIGH to select Pipelined mode. Selection for SDR only.

MRST

Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting

MRST LOW performs all of the reset functions as described in the text. A MRST operation

is required at power-up. This pin must be driven by VDDIO_Lreferenced levels.

TMS

TDI

JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State

machine transitions occur on the rising edge of TCK. Operation for LVTTL or 2.5V LVCMOS.

JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers.

Operation for LVTTL or 2.5V LVCMOS.

TRST

TCK

JTAG Reset Input. Operation for LVTTL or 2.5V LVCMOS.

JTAG Test Clock Input. Operation for LVTTL or 2.5V LVCMOS.

TDO

JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally

three-stated except when captured data is shifted out of the JTAG TAP. Operation for LVTTL

or 2.5V LVCMOS.

VSS

VCORE

VTTL

Ground Inputs.

Device Core Power Supply.

LVTTL Power Supply.

Selectable I/O Standard

Clocking

The FullFlex device families also offer the option of choosing

one of four port standards for the device. Each port can

independently select standards from single-ended HSTL class

I, single-ended LVTTL, 2.5V LVCMOS, or 1.8V LVCMOS. The

selection of the standard is determined by the PORTSTD pins

for each port. These pins must be connected to a VTTL power

supply. This will determine the input clock, address, control,

data, and Echo clock standard for each port as shown in

Table 2. Please note that only 1.8V LVCMOS and HSTL are

supported for 4-Mbit, 9-Mbit, 18-Mbit devices running at

250MHz SDR, and for 36-Mbit devices running at 200 MHz

SDR.

Separate clocks synchronize the operations on each port.

Each port has two clock inputs C and C. In SDR mode only the

C input clock is used and C should be tied to VSS. In this

mode, all the transactions on the address, control, and data

will be on the C rising edge. In DDR mode, both C and C will

be used and these signals are complementary. In this mode,

all transactions on the address and control, except for the byte

enables, will occur on the C rising edge. Transactions on the

data input, output, and byte enables will be on the C and C

rising edges.

Double Data Rate (DDR)

In DDR mode with a x36 bus width, the input data is sampled

on both edges of the input clock. During a write, on the rising

edge of C, the first 36 bits (DQ[71:36]) will be latched into a

register. On the rising edge of C, the next 36 bits (DQ[35:0])

will be latched into a register. During a read, the first 36 bits

are driven out first on the rising edge of C. The next 36 bits will

be driven out on the rising edge of C. The internal bus width of

the FullFlex72 family is still x72. All counter operation is based

upon the x72 word width. The DDR option is set on a per port

basis by the configuration of the DDRON pin. Table 3 shows

the data assignment for SDR and DDR configuration. The

column on the right (Data Pin Name) shows the pins on which

data is presented on the data lines.

Table 2. Port Standard Selection

PORTSTD1

VSS

PORTSTD0

VSS

I/O Standard

LVTTL

VSS

VTTL

HSTL

VTTL

VSS

2.5V LVCMOS

1.8V LVCMOS

VTTL

Document #: 38-06072 Rev. *I

Page 9 of 53

FullFlex

Table 3. Data Pin Assignment for SDR and DDR Configuration

x72 SDR Mode

x36 DDR Mode

BE Pin Name for BE Pin Name for

Related Rising Edge

Related Rising Edge Data Pin

DDR

BE[3]

BE[2]

BE[1]

SDR

BE[7]

BE[3]

BE[7]

BE[3]

BE[7]

BE[3]

BE[7]

BE[3]

BE[7]

BE[3]

BE[7]

BE[3]

BE[7]

BE[3]

BE[7]

BE[3]

BE[7]

BE[3]

BE[6]

BE[2]

BE[6]

BE[2]

BE[6]

BE[2]

BE[6]

BE[2]

BE[6]

BE[2]

BE[6]

BE[2]

BE[6]

BE[2]

BE[6]

BE[2]

BE[6]

BE[2]

BE[5]

BE[1]

BE[5]

BE[1]

Data Pin Name

DQ[71]

DQ[35]

DQ[70]

DQ[34]

DQ[69]

DQ[33]

DQ[68]

DQ[32]

DQ[67]

DQ[31]

DQ[66]

DQ[30]

DQ[65]

DQ[29]

DQ[64]

DQ[28]

DQ[63]

DQ[27]

DQ[62]

DQ[26]

DQ[61]

DQ[25]

DQ[60]

DQ[24]

DQ[59]

DQ[23]

DQ[58]

DQ[22]

DQ[57]

DQ[21]

DQ[56]

DQ[20]

DQ[55]

DQ[19]

DQ[54]

DQ[18]

DQ[53]

DQ[17]

DQ[52]

DQ[16]

Clock for Write

Clock for Read

Name

C

DQ[35]

DQ[34]

DQ[33]

DQ[32]

DQ[31]

DQ[30]

DQ[29]

DQ[28]

DQ[27]

DQ[26]

DQ[25]

DQ[24]

DQ[23]

DQ[22]

DQ[21]

DQ[20]

DQ[19]

DQ[18]

DQ[17]

DQ[16]

Document #: 38-06072 Rev. *I

Page 10 of 53

FullFlex

Table 3. Data Pin Assignment for SDR and DDR Configuration (continued)

x72 SDR Mode

x36 DDR Mode

BE Pin Name for BE Pin Name for

Related Rising Edge

Related Rising Edge Data Pin

DDR

BE[1]

BE[0]

SDR

BE[5]

BE[1]

BE[5]

BE[1]

BE[5]

BE[1]

BE[5]

BE[1]

BE[5]

BE[1]

BE[5]

BE[1]

BE[5]

BE[1]

BE[4]

BE[0]

BE[4]

BE[0]

BE[4]

BE[0]

BE[4]

BE[0]

BE[4]

BE[0]

BE[4]

BE[0]

BE[4]

BE[0]

BE[4]

BE[0]

BE[4]

BE[0]

Data Pin Name

DQ[51]

DQ[15]

DQ[50]

DQ[14]

DQ[49]

DQ[13]

DQ[48]

DQ[12]

DQ[47]

DQ[11]

DQ[46]

DQ[10]

DQ[45]

DQ[9]

Clock for Write

Clock for Read

Name

C

DQ[15]

DQ[14]

DQ[13]

DQ[12]

DQ[11]

DQ[10]

DQ[9]

DQ[8]

DQ[7]

DQ[6]

DQ[5]

DQ[4]

DQ[3]

DQ[2]

DQ[1]

DQ[0]

DQ[44]

DQ[8]

DQ[43]

DQ[7]

DQ[42]

DQ[6]

DQ[41]

DQ[5]

DQ[40]

DQ[4]

DQ[39]

DQ[3]

DQ[38]

DQ[2]

DQ[37]

DQ[1]

DQ[36]

DQ[0]

Selectable Pipelined/Flow-through Mode

DLL

To meet data rate and throughput requirements, the FullFlex

families offer selectable pipelined or flow-through mode.

Flow-through mode is only supported in the FullFlex72

devices when the port is configured in SDR mode. Echo clocks

are not supported in flow-through mode and the DLL must be

disabled.

The FullFlex families of devices have an on-chip DLL.

Enabling the DLL reduces the clock to data valid (t_CD) time

allowing more setup time for the receiving device. For

operation at or below 100 MHz, the DLL must be disabled. This

is selectable by strapping LowSPD LOW.

Whenever the operating frequency is altered beyond the Clock

Input Cycle to Cycle Jitter spec, the DLL is required to be reset

followed by 1024 clocks before any valid operation.

Flow-through mode is selected by the FTSEL pin. Strapping

this pin HIGH selects pipelined mode. Strapping this pin LOW

selects flow-through mode.

LowSPD pins can be used to reset the DLL(s) for a single port

independent of all other circuitry. MRST can be used to reset

Document #: 38-06072 Rev. *I

Page 11 of 53

FullFlex

all DLLs on the chip, for information on DLL lock and reset

time, please see the Master Reset section below.

Deterministic Access Control

Deterministic Access Control is provided for ease of design.

The circuitry detects when both ports are accessing the same

location and provides an external BUSY flag to the port on

which data may be corrupted. The collision detection logic

saves the address in conflict (Busy Address) to a readable

register. In the case of multiple collisions, the first Busy

address will be written to the Busy Address register.

Echo Clocking

As the speed of data increases, on-board delays caused by

parasitics make providing accurate clock trees extremely

difficult. To counter this problem, the FullFlex families incor-

porate Echo Clocks. Echo Clocks are enabled on a per port

basis. The dual-port receives input clocks (C and C for DDR

mode, C for SDR mode) that are used to clock in the address

and control signals for a read operation. The dual-port

retransmits the input clocks relative to the data output. The

buffered clocks are provided on the CQ1, CQ1, CQ0, and CQ0

outputs. Each port has two pairs of Echo clocks. Each clock is

associated with half the data bits. The output clock will match

the corresponding ports I/O configuration.

If both ports are accessing the same location at the same time

and only one port is doing a write, if t_CCSis met, then the data

being written to and read from the address is valid data. For

example, if the right port is reading and the left port is writing

and the left ports clock meets t_CCS, then the data being read

from the address by the right port will be the old data. In the

same case, if the right ports clock meets t_CCS, then the data

being read out of the address from the right port will be the new

data. In the above case, if t_CCSis violated by the either ports

clock with respect to the other port and the right port gets the

external BUSY flag, the data from the right port is corrupted.

Table 4 shows the t_CCStiming that must be met to guarantee

the data.

To enable Echo clock outputs, tie CQEN HIGH. To disable

Echo clock outputs, tie CQEN LOW.

Input Clock

Data Out

Table 5 shows that in the case of the left port writing and the

right port reading, when an external BUSY flag is asserted on

the right port, the data read out of the device will not be

guaranteed.

Echo Clock

The value in the busy address register can be read back to the

address lines. The required input control signals for this

function are shown in Table 8. The value in the busy address

register will be read out to the address lines t_CAafter the same

amount of latency as a data read operation in SDR mode. In

DDR mode, the address latency is only 2 cycles instead of 2.5

which is the data latency. After an initial address match, the

address under contention is saved in the busy address

register. All following address matches cause the BUSY flag

to be generated, however, none of the addresses are saved

into the busy address register. Once a busy readback is

performed, the address of the first match which happens at

least two clock cycles after the busy readback is saved into the

busy address register.

Figure 2. SDR Echo Clock Delay

Input Clock

Data Out

Echo Clock

Figure 3. DDR Echo Clock Delay

Document #: 38-06072 Rev. *I

Page 12 of 53

FullFlex

Table 4. t_CCSTiming for All Operating Modes

Port A – Early Arriving Port Port B – Late Arriving Port

t_CCSC/C Rise to Opposite C/C Rise Set-up Time

for Non-corrupt Data

Mode

SDR

DDR

Active Edge

Mode

SDR

DDR

SDR

DDR

Active Edge

Unit

ns

C

t_CYC(min)– 0.5

ns

0.55 * t_CYC+ t_CYC(min)– 1

ns

Table 5. Deterministic Access Control Winning Port

Clock Timing

Left Port

Read

Right Port Left Clock

Right Clock

BUSY_L

BUSY_R

Description

Read

X

0

H

L

H

L

No Collision

Write

>t_CCS

0

Read OLD Data

>t_CCS

0

Read NEW Data

Read OLD Data

<t_CCS

Data Not Guaranteed

Read NEW Data

Data Not Guaranteed

Read NEW Data

Read OLD Data

0

<t_CCS

H

L

Read

Write

>t_CCS

0

>t_CCS

0

H

L

<t_CCS

Read NEW Data

Data Not Guaranteed

Read OLD Data

0

<t_CCS

H

L

Data Not Guaranteed

Array Data Corrupted

0

>–t_CCS& <t_CCS

L

>t_CCS

0

L

H

L

Array Stores Right Port Data

Array Stores Left Port Data

>t_CCS

H

Variable Impedance Matching (VIM)

Table 6. Variable Impedance Matching Parameters

Parameter

RQ Value

Min. Max.

Unit

Ω

Tolerance

±2%

Each port contains a Variable Impedance Matching circuit to

set the impedance of the I/O driver to match the impedance of

the on-board traces. The impedance is set for all outputs

except JTAG and is done on a per port basis. To take

advantage of the VIM feature, connect a calibrating resistor

(RQ) that is five times the value of the intended line impedance

from the ZQ pin to VSS. The output impedance is then

adjusted to account for drifts in supply voltage and temper-

ature every 1024 clock cycles. If a port’s clock is suspended,

the VIM circuit will retain its last setting until the clock is

restarted. On restart, it will then resume periodic adjustment.

In the case of a significant change in device temperature or

supply voltage, recalibration will happen every 1024 clock

cycles. A Master Reset will initialize the VIM circuitry. Table 6

shows the VIM parameters and Table 7 describes the VIM

operation modes.

100

20

275

55

Output Impedance

Reset Time

Ω

±15%

N/A

N/A 1024 Cycles

Update Time

N/A

Table 7. Variable Impedance Matching Operation

RQ Connection Output Configuration

100Ω–275Ω to Output Driver Impedance = RQ/5 ± 15% at

VSS

Vout = VDDIO/2

ZQ to VDDIO

VIM Disabled. Rout < 20Ω at Vout =

VDDIO/2

Address Counter and Mask Register Operations^[1]

In order to disable VIM, the ZQ pin must be connected to

VDDIO of the relative supply for the I/Os before a Master

Reset.

Each port of the FullFlex families contains a programmable

burst address counter. The burst counter contains four

registers: a counter register, a mask register, a mirror register,

and a busy address register.

The counter register contains the address used to access the

RAM array. It is changed only by the master reset (MRST),

Counter Reset, Counter Load, Retransmit, and Counter

Increment operations.

Document #: 38-06072 Rev. *I

Page 13 of 53

FullFlex

The mask register value affects the Counter Increment and

Counter Reset operations by preventing the corresponding

bits of the counter register from changing. It also affects the

counter interrupt output (CNTINT). The mask register is only

changed by Mask Reset, Mask Load, and MRST. The Mask

Load operation loads the value of the address bus into the

mask register. The mask register defines the counting range

of the counter register. The mask register is divided into two or

three consecutive regions. Zero or more “0s” define the

masked region and one or more “1s” define the unmasked

portion of the counter register. The counter register may only

be divided into up to three regions. The region containing the

least significant bits must be no more than two “0s”. Bits one

and zero may be “10” respectively, masking the least signif-

icant counter bit and causing the counter to increment by two

instead of one. If bits one and zero are “00”, the two least

significant bits are masked and the counter will increment by

four instead of one. For example, in the case of a 256Kx72

configuration, a mask register value of 003FC divides the

mask register into three regions. With bit 0 being the least

significant bit and bit 17 being the most significant bit, the two

least significant bits are masked, the next eight bits are

unmasked, and the remaining bits are masked.

Counter Load Operation^[1]

The address counter and mirror registers are both loaded with

the address value presented on the address lines. This value

ranges from 0 to FFFFF.

Mask Load Operation^[1]

The mask register is loaded with the address value presented

on the address bus. This value ranges from 0 to FFFFF though

not all values permit correct increment operations. Permitted

values are in the form of 2ⁿ–1, 2ⁿ–2, or 2ⁿ–4. The counter

register can only be segmented in up to three regions. From

the most significant bit to the least significant bit, permitted

values have zero or more “0s”, one or more “1s”, and the least

significant two bits can be “11”, “10”, or “00”. Thus FFFFE,

7FFFF, and 03FFC are permitted values but 2FFFF, 03FFA,

and 7FFE4 are not.

Counter Readback Operation

The internal value of the counter register can be read out on

the address lines. The address will be valid t_CAafter the

selected number of latency cycles configured by FTSEL. This

is the same as data in SDR mode and one half cycle earlier

than data latency for DDR mode. The data bus (DQ) is

tri-stated on the cycle that the address is presented on the

address lines. Figure 4 shows a block diagram of the logic.

The mirror register is used to reload the counter register on

retransmit operations (see “retransmit” below) and wrap

functions (see “counter increment” below). The last value

loaded into the counter register is stored in the mirror register.

The mirror register is only changed by master reset (MRST),

Counter Reset, and Counter Load.

Mask Readback Operation

The internal value of the mask register can be read out on the

address lines. The address will be valid t_CAafter the selected

number of latency cycles configured by FTSEL. For pipelined

SDR and DDR mode this is two cycles. The data bus (DQ) is

tri-stated on the cycle that the address is presented on the

address lines. Figure 4 shows a block diagram of the

operation.

Table 8 summarizes the operations of these registers and the

required input control signals. All signals except MRST are

synchronized to the ports clock.

Table 8. Burst Counter and Mask Register Control Operation (Any Port) ^[20,21]

C

MRST CNTRST CNT/MSK CNTEN ADS RET

Operation

Description

X

L

X

Master Reset

Reset address counter to all 0s, mask register

to all 1s, and busy address to all 0’s.

H

L

H

X

Counter Reset

Reset counter and mirror unmasked portion to

all 0s.

H

L

X

L

X

L

X

Mask Reset

Reset mask register to all 1s.

H

Counter Load

Load burst counter and mirror with external

address value presented on address lines.

H

L

X

Mask Load

Retransmit

Load mask register with value presented on the

address lines.

H

L

H

L

Load counter with value in the mirror register

H

Counter

Internally increment address counter value.

Increment

H

L

H

L

H

Counter Hold

Constantly hold the address value for multiple

clock cycles.

Counter

Readback

Read out counter internal value on address

lines.

Mask Readback Read out mask register value on address lines.

Notes:

20. X” = “Don’t Care”, “H” = HIGH, “L” = LOW.

21. Counter operation and mask register operation is independent of chip enables.

Document #: 38-06072 Rev. *I

Page 14 of 53

FullFlex

Table 8. Burst Counter and Mask Register Control Operation (Any Port) (continued)^[20,21]

C

MRST CNTRST CNT/MSK CNTEN ADS RET

Operation

Description

H

L

H

L

Busy Address

Readback

Read out first busy address after last busy

address readback

H

L

H

L

X

L

Reserved

L

H

L

H

L

H

L

Counter Reset Operation

operation is useful in applications where wait states are

needed, or when address is available a few cycles ahead of

data in a shared bus interface.

All unmasked bits of the counter are reset to “0”. All masked

bits remain unchanged. The new burst counter value is loaded

into the mirror registers. A mask reset followed by a counter

reset will reset the counter and mirror registers to 00000.

Retransmit

Retransmit allows repeated access to the same block of

memory without the need to reload the initial address. An

internal mirror register stores the address counter value last

loaded. While RET is asserted low, the counter will continue to

wrap back to the value in the mirror register independent of the

state of WRP.

Mask Reset Operation

The mask register is reset to all “1s”, which unmasks every bit

of the burst counter.

Increment Operation^[1]

Once the address counter is initially loaded with an external

address, the counter can internally increment the address

value and address the entire memory array. Only the

unmasked bits of the counter register are incremented. In

order for a counter bit to change, the corresponding bit in the

mask register must be “1”. If the two least significant bits of the

mask register are “11”, the burst counter will increment by one.

If the two least significant bits are “10”, the burst counter will

increment by two, and if they are “00”, the burst counter will

increment by four. If all unmasked counter bits are incre-

mented to “1” and WRP is deasserted, the next increment will

wrap the counter back to the initially loaded value. The cycle

before the increment that results in all unmasked counter bits

to become “1s”, a counter interrupt flag (CNTINT) is asserted

if the counter is incremented again. This increment will cause

the counter to reach its maximum value and the next increment

will return the counter register to its initial value that was stored

in the mirror register if WRP is deasserted. If WRP is asserted,

the unmasked portion of the counter is filled with “0” instead.

The example shown in Figure 5 shows an example of the

CYDD36S18V18 device with the mask register loaded with a

mask value of 0007F unmasking the seven least significant

bits. Setting the mask register to this value allows the counter

to access the entire memory space. The address counter is

then loaded with an initial value of 00005 assuming WRP is

deasserted. The base address bits (in this case, the seventh

address through the twentieth address) do not increment once

the counter is configured for increment operation. The counter

address will start at address 00005 and will increment its

internal address value until it reaches the mask register value

of 0007F. The counter wraps around the memory block to

location 00005 at the next count. CNTINT is issued when the

counter reaches the maximum –1 count.

Counter Interrupt

The counter interrupt (CNTINT) is asserted LOW one clock

cycle before an increment operation that results in the

unmasked portion of the counter register being all “1s”. It is

deasserted by counter reset, counter load, mask reset, mask

load, counter increment, re-transmit, and MRST.

Counting by Two

When the two least significant bits of the mask register are

“10,” the counter increments by two.

Counting by Four

When the two least significant bits of the mask register are

“00,” the counter increments by four.

Mailbox Interrupts

The upper two memory locations can be used for message

passing and permit communications between ports. Table 9

shows the interrupt operation for both ports. The highest

memory location is the mailbox for the right port and the

maximum address–1 is the mailbox for the left port.

When one port Writes to the other ports mailbox, the INT flag

of the port that the mailbox belongs to is asserted LOW. The

INT flag remains asserted until the mailbox location is read by

the other port. When a port reads it’s mailbox, the INT flag is

deasserted HIGH after one cycle of latency with respect to the

input clock of the port to which the mailbox belongs and is

independent of OE.

Table 9 shows that in order to set the INT_Rflag, a Write

operation by the left port to address FFFFF will assert INT_R

LOW. A valid Read of the FFFFF location by the right port will

reset INT_RHIGH after one cycle of latency with respect to the

Hold Operation

The value of all three registers can be constantly maintained

unchanged for an unlimited number of clock cycles. Such

Document #: 38-06072 Rev. *I

Page 15 of 53

FullFlex

right port’s clock. At least one byte enable has to be activated

to set or reset the mailbox interrupt.

CNT/MSK

CNTEN

Decode

Logic

A

CNTRST

RET

MRST

A

C

Mask

Register

Counter/

Address

Register

Address

Decode

RAM

Array

Load/Increment

19

From

Address

Lines

Mirror

Counter

To Readback

and Address

Decode

1

0

1

0

From

Increment

Logic

Mask

Register

19

Wrap

19

From

Mask

Bit 0

and 1

From

Counter

+1

+2

+4

Wrap

Detect

Wrap

To

1

0

19

1

0

Counter

Figure 4. Counter, Mask, and Mirror Logic Block Diagram^[1]

Document #: 38-06072 Rev. *I

Page 16 of 53

FullFlex

CNTINT

H

Example:

Load

Counter-Mask

0

0s

1

0

Register = 00007F

2¹⁹2¹⁸

2⁶2⁵2⁴2³2²2¹2⁰

Unmasked Address

2⁷

Masked Address

Mask

Register

LSB

Load

Address

Counter = 000005

H

L

X

Xs

0

1

0

1

X

2¹⁹2¹⁸

2⁶2⁵2⁴2³2²2¹2⁰

Address

Counter

LSB

2⁷

Max

Address

Value

X

1

1 1

1

2¹⁹2¹⁸

2⁶2⁵2⁴2³2²2¹2⁰

Max + 1

Address

Value

H

X

0

1

0

1

X

2¹⁹2¹⁸

2⁶2⁵2⁴2³2²2¹2⁰

Figure 5. Programmable Counter-Mask Register Operation with WRP deasserted^[1,25]

Table 9. Interrupt Operation Example ^{[1, 20, 22, 23, 24]}

Left Port

A_0L–19L

Right Port

A_0R–19R

Function

Set Right INT_RFlag

Reset Right INT_RFlag

Set Left INT_LFlag

R/W_L

CE_L

L

INT_L

X

R/W_R

CE_R

X

INT_R

L

X

H

Max. Address

X

H

L

X

L

Max. Address

Max. Address–1

X

H

X

L

X

Reset Left INT_LFlag

L

Max. Address–1

H

X

Master Reset

OR capable output with a strong pull-up and weak pull-down.

Up to four outputs may be connected together. For faster

pull-down of the signal, connect a 250-Ω resistor to VSS. If the

DLL and VIM circuits are disabled for a port, the port will be

operational within five clock cycles. However, the READY will

be asserted within 160 clock cycles.

The FullFlex family of dual-ports undergo a complete reset

when MRST is asserted. MRST must be driven by VDDIO_L

referenced levels. The MRST can be asserted asynchronously

to the clocks and must remain asserted for at least t_RS. Once

asserted MRST deasserts READY, initializes the internal burst

counters, internal mirror registers, and internal Busy

Addresses to zero, and initializes the internal mask register to

all “1s”. All mailbox interrupts (INT), Busy Address Outputs

(BUSY), and burst counter interrupts (CNTINT) are

deasserted upon master reset. Additionally, MRST must not

be released until all power supplies including VREF are fully

ramped, all port clocks and mode select inputs (LOWSPD, ZQ,

CQEN, DDRON, FTSEL, and PORTSTD) are valid and stable.

This begins calibration of the DLL and VIM circuits. READY

will be asserted within 1024 clock cycles. READY is a wired

IEEE 1149.1 Serial Boundary Scan (JTAG)

The FullFlex families incorporate an IEEE 1149.1 serial

boundary scan test access port (TAP). The TAP operates

using JEDEC-standard 3.3V or 2.5V I/O logic levels depending

on the VTTL power supply. It is composed of four input

connections and one output connection required by the test

logic defined by the standard.

Notes:

22. CE is internal signal. CE = LOW if CE = LOW and CE = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the C and

0

1

can be deasserted after that. Data will be out after the following C edge and will be tri-stated after the next C edge.

23. OE is “Don’t Care” for mailbox operation.

24. At least one of BE0, BE1, BE2, BE3, BE4, BE5, BE6, or BE7 must be LOW.

25. The “X” in this diagram represents the counter’s upper bits.

Document #: 38-06072 Rev. *I

Page 17 of 53

FullFlex

Table 10.JTAG IDCODE Register Definitions

Table 11.Scan Registers Sizes

Part Number

CYDD36S36V18

CYDD36S18V18

CYDD18S72V18

CYDD18S36V18

CYDD18S18V18

CYDD09S72V18

CYDD09S36V18

CYDD09S18V18

CYDD04S72V18

CYDD04S36V18

CYDD04S18V18

Configuration

512Kx72

1024Kx36

256Kx72

512Kx36

128Kx72

256Kx36

64Kx72

Value

Register Name

Instruction

Bit Size

0C041069h

0C042069h

0C043069h

0C044069h

0C045069h

0C046069h

0C047069h

0C048069h

0C049069h

0C04A069h

0C04B069h

4

1

Bypass

Identification

Boundary Scan

32

n^[26]

64Kx72

128Kx36

Table 12.Instruction Identification Codes

Instruction Code

EXTEST

Description

0000

1111

1011

0111

Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.

Places the BYR between TDI and TDO.

BYPASS

IDCODE

HIGHZ

Loads the IDR with the vendor ID code and places the register between TDI and TDO.

Places BYR between TDI and TDO. Forces all FullFlex72 and FullFlex36 output drivers

to a High-Z state.

CLAMP

0100

Controls boundary to 1/0. Places BYR between TDI and TDO.

SAMPLE/PRELOAD 1000

Captures the input/output ring contents. Places BSR between TDI and TDO.

RESERVED

All other codes Other combinations are reserved. Do not use other than the above.

Note:

26. Details of the boundary scan length can be found in the BSDL file for the device.

Document #: 38-06072 Rev. *I

Page 18 of 53

FullFlex

Maximum Ratings

Operating Range

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Range

Ambient Temperature

VCORE

Commercial

0°C to +70°C

1.8V ± 100 mV

1.5V ± 80 mV

Storage Temperature ................................ –65°C to + 150°C

Ambient Temperature with

Power Applied............................................–55°C to + 125°C

Industrial

–40°C to +85°C

1.8V ± 100 mV

1.5V ± 80 mV

Supply Voltage to Ground Potential.............. –0.5V to + 4.1V

Power Supply Requirements

DC Voltage Applied to

Outputs in High-Z State.......................–0.5V to V_DDIO+ 0.5V

Min.

Typ.

Max.

3.6V

2.7V

1.9V

3.6V

2.7V

0.95V

LVTTL VDDIO

2.5V LVCMOS VDDIO

HSTL VDDIO

3.0V

2.3V

1.4V

1.7V

3.0V

2.3V

0.68V

3.3V

2.5V

1.5V

1.8V

3.3V

2.5V

0.75V

DC Input Voltage.................................–0.5V to V_DDIO+ 0.5V

Output Current into Outputs (LOW) ............................ 20 mA

Static Discharge Voltage...........................................> 2200V

(JEDEC JESD8-6, JESD8-B)

1.8V LVCMOS VDDIO

3.3V VTTL

Latch-up Current.....................................................> 200 mA

2.5V VTTL

HSTL VREF

Electrical Characteristics Over the Operating Range

All Speed Bins^[27]

Typ.

Parameter

Description

Output HIGH Voltage

Configuration

Min.

2.4^[28]

Max.

Unit

V_OH

LVTTL

V

(V_DDIO= Min., I_OH= –8 mA)

(V_DDIO= Min., I_OH= –4 mA)

(V_DDIO= Min., I_OH= –6 mA)

(V_DDIO= Min., I_OH= –4 mA)

HSTL(DC)^[29]

HSTL(AC)^[29]

2.5V LVCMOS

1.8V LVCMOS

LVTTL

VDDIO – 0.4^[28]

VDDIO – 0.5^[28]

1.7^[28]

V

VDDIO – 0.45^[28]

V_OL

Output HIGH Voltage

0.4^[28]

(V_DDIO= Min., I_OL= 8 mA)

(V_DDIO= Min., I_OL= 4 mA)

(V_DDIO= Min., I_OL= 6 mA)

(V_DDIO= Min., I_OL= 4 mA)

Input HIGH Voltage

HSTL(DC)^[29]

HSTL(AC)^[29]

2.5V LVCMOS

1.8V LVCMOS

LVTTL

HSTL(DC)^[29]

2.5V LVCMOS

1.8V LVCMOS

LVTTL

0.4^[28]

0.5^[28]

0.7^[28]

V

0.45^[28]

V_IH

2

VREF + 0.1

1.7

VDDIO + 0.3

1.26

V_IL

Input LOW Voltage

–0.3

0.8

HSTL(DC)^[29]

2.5V LVCMOS

1.8V LVCMOS

–0.3

VREF – 0.1

0.7

0.36

Notes:

27. LVTTL and 2.5V LVCMOS are not available for 4-Mbit, 9-Mbit, 18-Mbit devices running at 250 MHz SDR and 36-Mbit devices running at 200 MHz SDR.

28. These parameters are met with VIM disabled.

29. The (DC) specifications are measured under steady state conditions. The (AC) specifications are measured while switching at speed. AC VIH/VIL in HSTL mode

are measured with 1V/ns input edge rates

Document #: 38-06072 Rev. *I

Page 19 of 53

FullFlex

Electrical Characteristics Over the Operating Range (continued)

READY

V_OH

Output HIGH Voltage

(V_DDIO= Min., I_OH= –24 mA)

LVTTL

2.7^[28]

V

(V_DDIO= Min., I_OH= –12 mA)

(V_DDIO= Min., I_OH= –15 mA)

(V_DDIO= Min., I_OH= –12 mA)

HSTL(DC)^[29]

HSTL(AC)^[29]

2.5V LVCMOS

1.8V LVCMOS

LVTTL

VDDIO – 0.4^[28]

VDDIO – 0.5^[28]

2.0^[28]

V

VDDIO – 0.45^[28]

READY

V_OL

Output HIGH Voltage

0.4^[28]

V

(V_DDIO= Min., I_OL= 0.12 mA)

(V_DDIO= Min., I_OL= 0.15 mA)

(V_DDIO= Min., I_OL= 0.08 mA)

Output Leakage Current

HSTL(DC)^[29]

HSTL(AC)^[29]

2.5V LVCMOS

1.8V LVCMOS

0.4^[28]

0.5^[28]

0.7^[28]

0.45^[28]

10

V

I_OZ

I_IX1

I_IX2

–10

µA

Input Leakage Current

10

Input Leakage Current TDI, TMS, MRST,

TRST, TCK

–300

10

I_IX3

Input Leakage Current PORTSTD,

DDRON

–10

300

µA

Document #: 38-06072 Rev. *I

Page 20 of 53

FullFlex

Electrical Characteristics Over the Operating Range

–200^[27]

Typ.

–167^[27]

Typ.

–133

Max. Unit

Parameter

Description

Configuration

Max.

N/A

1140

N/A

980

N/A

800

N/A

930

N/A

790

N/A

640

N/A

880

N/A

740

N/A

590

N/A

Max.

1800

N/A

1620

N/A

1350

N/A

980

1030

880

930

720

780

790

830

700

740

570

600

740

770

650

680

520

530

Typ.

1280

1330

1120

1170

930

980

N/A

I_CC

Operating Current

(V_CORE= Max.,I_OUT= 0 mA)

Outputs Disabled

512Kx72 Com.

N/A

930

N/A

800

N/A

640

N/A

770

N/A

640

N/A

540

N/A

740

N/A

620

N/A

510

N/A

1440

N/A

1280

N/A

1050

N/A

800

820

700

730

570

590

640

660

560

580

470

490

620

630

540

550

450

460

1620

1730

1430

1550

1220

1330

N/A

mA

SDR^[30]

Ind.

512Kx36x2 Com.

DDR

Ind.

1024Kx18x2 Com.

DDR

Ind.

256Kx72 Com.

SDR^[30]

Ind.

256Kx36x2 Com.

DDR

Ind.

512Kx18x2 Com.

DDR

Ind.

128Kx72 Com.

SDR^[30]

Ind.

128Kx36x2 Com.

DDR

Ind.

256Kx18x2 Com.

DDR

Ind.

64Kx72

SDR^[30]

Com.

Ind.

64Kx36x2 Com.

DDR

Ind.

128Kx18x2 Com.

DDR

Ind.

Note:

30. Use this number if any one of the two ports is operating in SDR mode.

Document #: 38-06072 Rev. *I

Page 21 of 53

FullFlex

Electrical Characteristics Over the Operating Range (continued)

–200^[27]

Typ.

–167^[27]

Typ.

–133

Max. Unit

Parameter

Description

Standby Current

Configuration

Max.

N/A

700

N/A

630

N/A

570

N/A

560

N/A

490

N/A

440

N/A

520

N/A

450

N/A

400

N/A

Max.

1250

N/A

1160

N/A

1050

N/A

630

680

580

630

530

580

490

540

450

490

400

430

450

480

400

430

360

370

Typ.

920

970

830

880

740

790

N/A

I_SB1

512Kx72 Com.

N/A

570

N/A

500

N/A

460

N/A

460

N/A

400

N/A

380

N/A

440

N/A

380

N/A

360

N/A

1000

N/A

920

N/A

820

N/A

500

530

460

490

410

440

400

420

360

380

340

360

380

390

340

350

320

330

1160

1260

1060

1170

960

1080

N/A

mA

(Both Ports TTL Level)

CE_Land CE_R≥ V_IH,

f = f_MAX

SDR^[30]

Ind.

512Kx36x2 Com.

DDR

Ind.

1024Kx18x2 Com.

DDR

Ind.

256Kx72 Com.

SDR^[30]

Ind.

256Kx36x2 Com.

DDR

Ind.

512Kx18x2 Com.

DDR

Ind.

128Kx72 Com.

SDR^[30]

Ind.

128Kx36x2 Com.

DDR

Ind.

256Kx18x2 Com.

DDR

Ind.

64Kx72

SDR^[30]

Com.

Ind.

64Kx36x2 Com.

DDR

Ind.

128Kx18x2 Com.

DDR

Ind.

Document #: 38-06072 Rev. *I

Page 22 of 53

FullFlex

Electrical Characteristics Over the Operating Range (continued)

–200^[27]

Typ.

–167^[27]

Typ.

–133

Max. Unit

Parameter

Description

Standby Current

Configuration

Max.

N/A

890

N/A

790

N/A

670

N/A

730

N/A

630

N/A

530

N/A

680

N/A

580

N/A

480

N/A

Max.

1570

N/A

1410

N/A

1210

N/A

790

840

710

760

610

670

630

670

560

610

470

500

580

610

510

550

420

440

Typ.

1160

1210

1020

1070

870

920

N/A

I_SB2

512Kx72 Com.

N/A

760

N/A

650

N/A

550

N/A

620

N/A

520

N/A

460

N/A

590

N/A

500

N/A

440

N/A

1300

N/A

1160

N/A

980

N/A

650

680

580

610

490

520

550

460

480

400

430

500

510

440

450

380

390

1410

1520

1260

1370

1100

1210

N/A

mA

(One Port TTL or CMOS

Level)

CE_L| CE_R≥ V_IH,

f = f_MAX

SDR^[30]

Ind.

512Kx36x2 Com.

DDR

Ind.

1024Kx18x2 Com.

DDR

Ind.

256Kx72 Com.

SDR^[30]

Ind.

256Kx36x2 Com.

DDR

Ind.

512Kx18x2 Com.

DDR

Ind.

128Kx72 Com.

SDR^[30]

Ind.

128Kx36x2 Com.

DDR

Ind.

256Kx18x2 Com.

DDR

Ind.

64Kx72

SDR^[30]

Com.

Ind.

64Kx36x2 Com.

DDR

Ind.

128Kx18x2 Com.

DDR

Ind.

Document #: 38-06072 Rev. *I

Page 23 of 53

FullFlex

Electrical Characteristics Over the Operating Range (continued)

All Speed Bins^[27]

Typ.

Parameter

I_SB3

Description

Standby Current

(Both Ports CMOS Level)

CE_Land CE_R≥ V_CORE– 0.2V,

f = 0

Configuration

Max.

590

700

590

700

590

700

300

350

300

350

300

350

200

220

200

220

200

220

150

170

150

170

150

170

Unit

mA

512Kx72

Com.

Ind.

410

460

410

460

410

460

210

230

210

230

210

230

150

170

150

170

150

170

130

140

130

140

130

140

SDR^[30]

512Kx36x2

DDR

Com.

Ind.

1024Kx18x2

DDR

Com.

Ind.

256Kx72

SDR^[30]

Com.

Ind.

256Kx36x2

DDR

Com.

Ind.

512Kx18x2

DDR

Com.

Ind.

128Kx72

SDR^[30]

Com.

Ind.

128Kx36x2

DDR

Com.

Ind.

256Kx18x2

DDR

Com.

Ind.

64Kx72

SDR^[30]

Com.

Ind.

64Kx36x2

DDR

Com.

Ind.

128Kx18x2

DDR

Com.

Ind.

Table 13.Capacitance

Signals

Packages

CYDD18S72V18

CYDD09S72V18

CYDD04S72V18

CYDD18S36V18

CYDD09S36V18

CYDD04S36V18

CYDD18S18V18

CYDD09S18V18

CYDD04S18V18

CYDD36S36V18

CYDD36S18V18

OE

12 pF

10 pF

12 pF

18 pF

10 pF

20 pF

16 pF

20 pF

30 pF

16 pF

BE, DQ

All other signals

Document #: 38-06072 Rev. *I

Page 24 of 53

FullFlex

AC Test Load and Waveforms

V _{R E F}= N C

V _{R E F}

50 O hm

50 O h m

O utput

T e st P o int

R = 250 O h m

C = 10 pF

V T H

R E A D Y Z Q

D e vice und er

test

R Q = 250 O hm

V T H = 1.5V for LV T T L

V T H = 50 % V D D IO for 2.5 V C M O S

V T H = 50 % V D D IO for 1.8 V C M O S

Figure 6. Output Test Load for LVTTL/CMOS

V

=

0 .7 5 V

5 0 O h m

R E F

V

R E F

5 0 O h m

O u tp u t

T e s t P o i n t

R = 2 5 0 O h m

V T H

R E A D Y

Z Q

C = 0 p F fo r D D R

C = 1 0 p F fo r S D R

D e v i c e u n d e r

te s t

R Q = 2 5 0 O h m

V T H

= 5 0 % V D D IO

Figure 7. Output Test Load for HSTL

Figure 8. HSTL Input Waveform

Document #: 38-06072 Rev. *I

Page 25 of 53

FullFlex

Switching Characteristics Over the Operating Range

Table 14.DDR Mode with 2.5 Pipelined Stages and DLL Enabled (LOWSPD-HIGH)^[33]

–200

–167

–133

Parameter

f_MAX

Description

Maximum Operating Frequency

C/C Clock Cycle Time

Min.

Max.

200

6.3

Min.

127

6.00^[34]

Max.

167

Min.

100

7.50^[34]

Max.

133

Unit

MHz

ns

159

5.00^[34]

t_CYC

7.88

10.00

t_CH

C/C Clock HIGH Time

2.00

2.40

3.00

ns

t_CL

C/C Clock LOW Time

2.00

2.40

3.00

ns

t_CHCH

t_SD

C/C Clock Rise to C/C Clock Rise

2.20

0.45^[32]

2.70

0.55^[32]

3.38

0.75^[32]

ns

Data Input Set-up Time to HSTL

ns

C/C Rise

1.8V LVCMOS

2.5V LVCMOS 0.65^[32]

3.3V LVTTL

0.75^[32]

0.95^[32]

ns

t_HD

Data Input Hold Time after C/C Rise

Byte enable Set-up Time to HSTL

0.45

0.45^[32]

0.55

0.55^[32,]

0.75

0.65^[32]

ns

t_SBE

C/C Rise

1.8V LVCMOS

2.5V LVCMOS 0.65^[32]

3.3V LVTTL

0.75^[32]

0.85^[32]

ns

t_HBE

t_SAC

Byte enable Hold Time after C/C Rise

0.45

1.50^[34]

0.55

1.70^[34]

0.65

1.80^[34]

ns

Address & Control Input HSTL

except BE Set-up Time to C 1.8V LVCMOS

Rise

2.5V LVCMOS 1.75^[34]

3.3V LVTTL

1.95^[34]

0.60

2.05^[34]

0.70

ns

t_HAC

t_OE

Address & Control Input except BEHoldTime

after C Rise

0.50

Output Enable to Data Valid

OE to Low Z

4.40^[32,34]

5.00^[32,34]

5.50^[32,34]ns

ns

5.50^[32,34]ns

0.85^[32]ns

[31]

t_OLZ

1.00

[31]

t_OHZ

OE to High Z

4.40^[32,34]

0.65^[32]

5.00^[32,34]

0.75^[32]

[35]

t_CD

C/C Rise to DQ Valid

HSTL

1.8V LVCMOS

2.5V LVCMOS

3.3V LVTTL

0.65^[32]

0.75^[32]

0.85^[32]ns

[35]

t_DC

DQ Output Hold after C/C HSTL

–0.65

–0.75

–0.85

ns

Rise

1.8V LVCMOS

2.5V LVCMOS

3.3V LVTTL

[35]

t_CCQ

C/C Rise to CQ/CQ Rise

HSTL

1.8V LVCMOS

2.5V LVCMOS –0.65^[36]

3.3V LVTTL

–0.65^[36]

0.65

0.60

–0.75^[36]

0.75

0.70

–0.85^[36]

0.85

0.80

ns

[35]

t_CQHQV

Echo Clock (CQ/CQ) High HSTL

to Output Valid 1.8V LVCMOS

0.35^[32]

0.45^[32]

0.40^[32]

0.50^[32]

0.50^[32]ns

0.60^[32]ns

2.5V LVCMOS

3.3V LVTTL

Notes:

31. Parameters specified with the load capacitance in Figure 6 and Figure 7.

32. For the x18 devices, add 200 ps to this parameter in the table above.

33. Test conditions assume a signal transition time of 2 V/ns.

34. Add 15% to this parameter if a VCORE of 1.5V is used.

35. This parameter assumes input clock cycle to cycle jitter of +/- 0ps.

36. For the x18 devices, subtract 200ps from this parameter in the table above.

Document #: 38-06072 Rev. *I

Page 26 of 53

FullFlex

Table 14.DDR Mode with 2.5 Pipelined Stages and DLL Enabled (LOWSPD-HIGH)^[33]

–200 –167

–133

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Unit

[35]

t_CQHQX

Echo Clock (CQ/CQ) High HSTL

–0.35^[36]

–0.40^[36]

–0.50^[36]

ns

to Output Hold

1.8V LVCMOS

2.5V LVCMOS –0.50^[36]

3.3V LVTTL

–0.55^[36]

–0.65^[36]

ns

[31,35]

t_CKHZ

C Rise to DQ Output High Z HSTL

1.8V LVCMOS

0.65^[32]

0.75^[32]

0.85^[32]ns

2.5V LVCMOS

3.3V LVTTL

0.85^[32]ns

[31,35]

t_CKLZ

C Rise to DQ Output Low Z HSTL

–0.65

–0.75

–0.85

ns

1.8V LVCMOS

2.5V LVCMOS

3.3V LVTTL

t_CA

t_AC

C Rise to Address Readback Valid

5.00^[34]

6.00^[34]

7.50^[34]ns

ns

7.50^[34]ns

Address Output Hold after C Rise

C Rise to Address Output High Z

C Rise to Address Output Low Z

C Rise to CNTINT Low

1.00

0.50

1.00

0.50

1.00

0.50

1.00

[31]

t_CKHZA

[31]

t_CKLZA

ns

t_SCINT

t_RCINT

t_SINT

t_RINT

t_BSY

3.30^[34]

7.00^[34]

3.30^[34]

+/- 200

4.00^[34]

8.00^[34]

4.00^[34]

+/- 200

5.00^[34]ns

9.00^[34]ns

5.00^[34]ns

C Rise to CNTINT High

C Rise to INT Low

C Rise to INT High

C Rise to BUSY Valid

t_JIT

Clock Input Cycle to Cycle Jitter

+/- 200

ps

Table 15.SDR Mode with Flow-Through Mode

–200^[27]

–167^[27]

–133

Parameter

f_MAX

Description

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Maximum Operating Frequency for

100

77

66.7

MHz

(FLOW-THROUGH) Flow-through Mode

t_CYC

C Clock Cycle Time for Flow-through 10.00^[34]

13.00^[34]

15.00^[34]

ns

(FLOW-THROUGH) mode

t_CD1

C Rise to DQ Valid for Flow-through

Mode (LowSPD = 1)

7.20^[32,34]

7.20^[34]

9.00^[32,34]

9.00^[34]

11.00^[32,ns

34]

t_CA1

C Rise to Address Readback Valid for

Flow-through Mode

11.00^[34]ns

[31]

t_CKHZ1

C Rise to DQ Output High Z in

Flow-through Mode

1.00

7.20^[32,34]

1.00

9.00^[32,34]

1.00

11.00^[32,ns

34]

[31]

t_CKLZ1

C Rise to DQ Output Low Z in

Flow-through Mode

ns

[31]

t_CKHZA1

C Rise to Address Output High Z for

Flow-through Mode

7.20^[34]

9.00^[34]

11.00^[34]ns

Table 16.SDR Mode with Pipeline Mode, DLL Enabled (LOWSPD-HIGH)^[33]

–200^[27]

–167^[27]

–133

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Unit

f_MAX(PIPELINED) Maximum Operating Frequency for

Pipelined Mode

100

250

100

200

100

167

MHz

Document #: 38-06072 Rev. *I

Page 27 of 53

FullFlex

Table 16.SDR Mode with Pipeline Mode, DLL Enabled (LOWSPD-HIGH)^[33](continued)

–200^[27]–167^[27]

–133

Parameter

Description

Min.

Max.

10.00

55

Min.

5.00^[34]

45

Max.

10.00

55

Min.

6.00^[34]

45

Max.

10.00

55

Unit

ns

t_CYC(PIPELINED) C Clock Cycle Time for Pipelined Mode 4.00^[34]

t_CKD

t_SD

C Clock Duty Time

45

1.20^[32,34]

%

Data Input Set-up HSTL

1.50^[32,34]

1.70^[32,34]

ns

Time to C Rise

1.8V LVCMOS

2.5V LVCMOS

3.3V LVTTL

1.45^[32,34]

1.75^[32,34]

1.95^[32,34]

ns

t_HD

Data Input Hold Time after C Rise

0.50

1.20^[32,34]

0.50

1.50^[32,34]

0.50

1.70^[32,34]

ns

t_SAC

Address & Control HSTL

Input Set-up Time 1.8V LVCMOS

to C Rise

2.5V LVCMOS

3.3V LVTTL

1.45^[32,34]

0.50

1.75^[32,34]

0.50

1.95^[32,34]

0.60

ns

t_HAC

t_OE

Address & Control Input Hold Time

after C Rise

Output Enable to Data Valid

OE to Low Z

3.40^[32,34]

4.40^[32,34]

5.00^[32,34]ns

ns

5.00^[32,34]ns

4.00^[32,34]ns

[31]

t_OLZ

1.00

[31]

t_OHZ

OE to High Z

3.40^[32,34]

2.64^[32,34]

4.40^[32,34]

3.30^[32,34]

[35]

t_CD2

C Rise to DQ Valid for Pipelined Mode

(LowSPD = 1)

t_CA2

C Rise to Address Readback Valid for

Pipelined Mode

4.00^[34]

5.00^[34]

6.00^[34]ns

[35]

t_DC

DQ Output Hold after C Rise

C Rise to CQ Rise

1.00

ns

4.00^[34]ns

0.80^[32]ns

[35]

t_CCQ

2.64^[34]

0.60^[32]

3.30^[34]

0.70^[32]

[35]

t_CQHQV

Echo Clock (CQ) HSTL

High to Output Valid 1.8V LVCMOS

2.5V LVCMOS

3.3V LVTTL

0.70^[32]

0.80^[32]

0.90^[32]ns

[35]

t_CQHQX

Echo Clock (CQ) HSTL

High to Output Hold 1.8V LVCMOS

–0.60

–0.75

1.00

–0.70

–0.85

1.00

–0.80

–0.95

1.00

ns

2.5V LVCMOS

3.3V LVTTL

ns

4.00^[32,34]ns

ns

[31,35]

t_CKHZ2

C Rise to DQ Output High Z in

Pipelined Mode

2.64 ^[32,

3.30^[32,34]

34]

[31,35]

t_CKLZ2

t_AC

C Rise to DQ Output Low Z in

Pipelined Mode

1.00

Address Output Hold after C Rise

1.00

ns

[31]

t_CKHZA2

C Rise to Address Output High Z for

Pipelined Mode

4.00^[34]

5.00^[34]

6.00^[34]ns

[31]

t_CKLZA

t_SCINT

t_RCINT

t_SINT

t_RINT

t_BSY

C Rise to Address Output Low Z

C Rise to CNTINT Low

C Rise to CNTINT High

C Rise to INT Low

1.00

0.50

1.00

0.50

1.00

0.50

1.00

ns

4.00^[34]ns

8.00^[34]ns

4.00^[34]ns

2.64^[34]

6.00^[34]

2.64^[34]

+/- 200

3.30^[34]

7.00^[34]

3.30^[34]

+/- 200

C Rise to INT High

C Rise to BUSY Valid

t_JIT

Clock Input Cycle to Cycle Jitter

+/- 200

ps

Document #: 38-06072 Rev. *I

Page 28 of 53

FullFlex

Table 17.SDR Mode with Pipeline Mode, DLL Disabled (LOWSPD-LOW)^[33]

All Speed Bins

Parameter

f_MAX(PIPELINED)

t_CYC(PIPELINED)

t_CKD

Description

Maximum Operating Frequency for Pipelined Mode

C Clock Cycle Time for Pipelined Mode

C Clock Duty Time

Min.

Max.

Unit

MHz

ns

100

10.00^[34]

45

55

%

t_SD

Data Input Set-up Time to C Rise HSTL

1.8V LVCMOS

1.80^[32,34]

ns

2.5V LVCMOS

3.3V LVTTL

2.05^[32,34]

ns

t_HD

Data Input Hold Time after C Rise

0.50

1.80^[32,34]

ns

t_SAC

Address & Control Input Set-up

Time to C Rise

HSTL

1.8V LVCMOS

2.5V LVCMOS

3.3V LVTTL

2.05^[32,34]

0.70

ns

t_HAC

t_OE

Address & Control Input Hold Time after C Rise

Output Enable to Data Valid

ns

5.50^[32,34]

[31]

t_OLZ

OE to Low Z

1.00

[31]

t_OHZ

OE to High Z

5.50^[32,34]

6.00^[32,34]

7.50^[34]

[35]

t_CD2

C Rise to DQ Valid for Pipelined Mode (LowSPD = 0)

C Rise to Address Readback Valid for Pipelined Mode

DQ Output Hold after C Rise

t_CA2

[35]

t_DC

1.00

[35]

t_CCQ

C Rise to CQ Rise

6.00^[34]

0.90^[32]

[35]

t_CQHQV

Echo Clock (CQ) High to Output HSTL

Valid

1.8V LVCMOS

2.5V LVCMOS

3.3V LVTTL

1.00^[32]

ns

[35]

t_CQHQX

Echo Clock (CQ) High to Output HSTL

Hold 1.8V LVCMOS

–0.90

–1.05

2.5V LVCMOS

3.3V LVTTL

[31,35]

t_CKHZ2

C Rise to DQ Output High Z in Pipelined Mode

C Rise to DQ Output Low Z in Pipelined Mode

Address Output Hold after C Rise

C Rise to Address Output High Z for Pipelined Mode

C Rise to Address Output Low Z

C Rise to CNTINT Low

1.00

0.50

1.00

6.00^[32,34]

ns

[31,35]

t_CKLZ2

t_AC

[31]

t_CKHZA2

7.50^[34]

[31]

t_CKLZA

t_SCINT

t_RCINT

t_SINT

t_RINT

t_BSY

4.50^[34]

8.50^[34]

4.50^[34]

C Rise to CNTINT High

C Rise to INT Low

C Rise to INT High

C Rise to BUSY Valid

Table 18.Master Reset Timing

–200^[27]

Min. Max.

–167^[27]

Min. Max.

–133

Parameter

t_PUP

t_RS

Description

Min.

Max.

Unit

ms

Power-up Time

1

5

1

5

1

5

Master Reset Pulse Width

cycles

Document #: 38-06072 Rev. *I

Page 29 of 53

FullFlex

Table 18.Master Reset Timing

–200^[27]

–167^[27]

–133

Max.

Parameter

t_RSR

t_RSF

Description

Min.

Max.

Min.

Max.

Min.

Unit

cycles

ns

Master Reset Recovery Time

Master Reset to Outputs Inactive/Hi-Z

Master Reset Release to Port Ready

C Rise to Port Ready

5

12

15

18

[37]

t_RDY

t_CORDY

1024

8^[34]

1024

9.5^[34]

1024

11^[34]

cycles

ns

[38]

Table 19.JTAG Timing

–200^[27]

–167^[27]

–133

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Unit

MHz

ns

f_JTAG

t_TCYC

t_TH

JTAG TAP Controller Frequency

TCK Cycle Time

20

50

20

10

50

20

10

50

20

10

TCK High Time

ns

t_TL

TCK Low Time

ns

t_TMSS

t_TMSH

t_TDIS

t_TDIH

t_TDOV

t_TDOX

t_JXZ

TMS Set-up to TCK Rise

TMS Hold to TCK Rise

TDI Set-up to TCK Rise

TDI Hold to TCK Rise

TCK Low to TDO Valid

TCK Low to TDO Invalid

TCK Low to TDO hi-Z

TCK Low to TDO Active

ns

10

ns

0

ns

15

ns

t_JZX

ns

Notes:

37. READY is a wired OR capable output with a weak pull-down. For a decreased falling delay, connect a 250 Ω resistor to VSS.

38. Add this propagation delay after t for all Master Reset Operations

RDY

Document #: 38-06072 Rev. *I

Page 30 of 53

FullFlex

Switching Waveforms

JTAG Timing

t_TH

t_TL

Test Clock

TCK

t_TCYC

t_TMSS

t_TMSH

Test Mode Select

TMS

t_TDIS

t_TDIH

Test Data-In

TDI

Test Data-Out

TDO

t_TDOX

t_TDOV

Master Reset^[37]

~

V

CORE

t

RS

PUP

MRST

C

~

t

RDY

CORDY

~

t

READY

RSF

All Address

& Data

t

RSR

All Other

Inputs

~

Document #: 38-06072 Rev. *I

Page 31 of 53

FullFlex

Switching Waveforms (continued)

READ Cycle for Pipelined Mode, DDRON = LOW

t

CYC

C

t

HAC

SAC

R/W

A

n+6

n

n+1

x

n+2

n

n+3

n+4

n+5

A

2 pipelined stages

DQ

n+4

x-1

n+1

n+2

n+3

DQ

t

DC

t

CD

WRITE Cycle for Pipelined and Flow-through Modes, DDRON = LOW

t

CYC

C

R/W

A

n+6

n

n+1

n+2

n+3

n+4

n+5

A

2 pipelined stages

DQ

n+5

n+6

DQ

n

n+1

n+3

n+4

n+2

t_SDt_HD

Document #: 38-06072 Rev. *I

Page 32 of 53

FullFlex

Switching Waveforms (continued)

READ with Address Counter Advance for Pipelined Mode, DDRON = LOW

t

CYC

C

A

n

Internal

Address

A

n+1

A

n

n+2

n+3

ADS

CNTEN

DQ

n+1

x-1

x

n

DQ

n+3

n+2

READ with Address Counter Advance for Flow-through Mode, DDRON = LOW

tCYC

C

t^SACtHAC

A

An

ADS

CNTEN

DQ

tSAC tHAC

tCD1

DQx

DQn

DQn + 1

DQn + 2

DQn + 3

DQn + 4

tDC

READ EXTERNAL ADDRESS

READ W ITH COUNTER

COUNTER HOLD

READ W ITH COUNTER

Document #: 38-06072 Rev. *I

Page 33 of 53

FullFlex

Switching Waveforms (continued)

Mailbox Interrupt Output, DDRON = LOW

t_CYC

C

L

A_L

A_MAX

R/W_L

DQ_L

INT_R

t_SINT

t_RINT

C_R

A_MAX

A_R

R/W_R

DQ_R

DQ_MAX

Document #: 38-06072 Rev. *I

Page 34 of 53

FullFlex

Switching Waveforms (continued)

Port-to-Port WRITE–READ for Pipelined Mode, DDRON = LOW

t

CYC

Left Port

C

L

A

L

n

R/W

DQ

L

DQ

L

n

Right Port

t

CCS

C

R

t

CYC

A

R

n

R/W

R

t

SAC HAC

DQ

R

n

t

DC

CD2

Chip Enable READ for Pipelined Mode, DDRON = LOW

t

CYC

C

CE0

CE1

R/W

A

t

SAC HAC

A

n+6

n

n+1

n+2

n+3

n+4

n+5

DQ

n+3

n

t

CKLZ2

t

CKHZ2

CD2

Document #: 38-06072 Rev. *I

Page 35 of 53

FullFlex

Switching Waveforms (continued)

OE Controlled WRITE for Pipelined Mode, DDRON = LOW

t

CYC

C

A

n+3

x+1

x+2

x+3

n

n+1

n+2

R/W

OE

t

OHZ

DQ

x+1

DQ

n+3

x-1

x

n

n+1

n+2

DQ

OE Controlled WRITE for Flow-through Mode, DDRON = LOW

t

CYC

C

A

n+3

x+1

x+2

x+3

n

n+1

n+2

R/W

OE

t_OHZ

DQ

x+2

DQ

n+3

DQ

x

x+1

n

n+1

n+2

Document #: 38-06072 Rev. *I

Page 36 of 53

FullFlex

Switching Waveforms (continued)

Byte-Enable READ for Pipelined Mode, DDRON = LOW

t_CYC

C

A

n

n+1

n+2

n+3

A

R/W

BE7

BE6

BE5

BE4

BE3

BE2

BE1

BE0

t_CKLZ2

t_CKHZ2

DQ_n+1(63:71)

DQ

63:71

DQ_n+1(54:62)

DQ

54:62

DQ_n+2(45:53)

45:53

36:44

DQ_n+2(36:44)

DQ_n+1(27:35)

DQ

27:35

DQ_n+2(18:26)

18:26

DQ_n+3(9:17)

DQ

9:17

0:8

DQ_n+3(0:8)

Document #: 38-06072 Rev. *I

Page 37 of 53

FullFlex

Switching Waveforms (continued)

Port-to-Port WRITE-to-READ for Flow-through Mode, DDRON = LOW

CL

R/W L

tSAC

tHAC

NO MATCH

AL

MATCH

tSD

tHD

VALID

DQL

tCCS

`

CR

tCD1

R/W R

tHAC

tSAC

NO MATCH

AR

MATCH

tCD1

DQR

VALID

tDC

BUSY Address Readback for Pipelined and Flow-through Modes, DDRON = CNT/MSK = RET = LOW^[39]

t

CYC

~

C

Internal

Address

A_match+2

A_match+3

A_match+4

BUSY

~

CNTEN

ADS

~

External

Address

A_match

Pipelined

t_AC

t_CA2

External

A_match

Address

Flow-through

t_AC

t_CA1

Note:

39. A

is the matching address which will be reported on the address bus of the losing port. The counter operation selected for reporting the address is “Busy

match

Address Readback.”

Document #: 38-06072 Rev. *I

Page 38 of 53

FullFlex

Switching Waveforms (continued)

Read Cycle for Flow-through Mode, DDRON = LOW

tCYC

C

CE0

CE1

tSAC

t^HAC

BEn

R/W

tSAC

tHAC

A

An

An + 1

An + 2

An + 3

tCKHZ1

tCD1

tDC

DQ

DQn

DQn + 1

DQn + 2

tDC

tCKLZ1

tOLZ

tOHZ

OE

tOE

READ-to-WRITE for Pipelined Mode, DDRON = LOW (OE = V_IL)^{[40, 41, 42]}

t_CYC

t_CL

C

t_CH

A

x

A

n

n+1

n+2

t_SACt_HAC

R/W

DQ

x

DQ

x-2

x-1

DQ

n+2

DQ

n+1

n

t_DC

t_CD2

t_CKHZ2

t_SDt_HD

Notes:

40. When OE = V , the last read operation is allowed to complete before the DQ bus is tri-stated and the user is allowed to drive write data.

IL

41. Two dummy writes should be issued to accomplish bus turnaround. The third instruction is the first valid write.

42. Chip enable or all byte enables should be held inactive during the two dummy writes to avoid data corruption.

Document #: 38-06072 Rev. *I

Page 39 of 53

FullFlex

Switching Waveforms (continued)

READ-to-WRITE for Pipelined Mode, DDRON = LOW (OE Controlled)^{[43, 44]}

t_CYC

C

A

n+3

x

x+1

x+2

n

n+1

n+2

A

t_SACt_HAC

R/W

OE

DQ

t_OHZ

t_SDt_HD

DQ

x

DQ

n+3

x-2

x-1

n

n+1

n+2

READ-to-WRITE-to-READ for DDR, DDRON = HIGH^{[40,41,45,46]}

t_CHt_CL

C

t_CYC

C

t_SAC

t_CHCHt_CHCH

t_HAC

A

n+2

A

x

n

A

n+1

t_SACt_HAC

R/W

DQ

t_CKHZ

DQ_n[1] DQ_n[0]

DQ_x-2[0]

DQ [0]

n+2

DQ [1]

DQ [0]

n+1

DQ [1]

x-1

x

DQ [0]

x

x-1

DQ [1]

n+1

n+2

DQ [1]

n+2

t_CD

t_DC

t_SDt_HD

Notes:

43. OE should be deasserted and t

allowed to elapse before the first write operation is issued.

OHZ

44. Any write scheduled to complete after OE is deasserted will be preempted.

45. The address should be held constant during the two dummy writes and first valid write to avoid data corruption.

46. D[1]/Q [1] contains data [71:36]; D[0]/Q[0] contains data [35:0].

Document #: 38-06072 Rev. *I

Page 40 of 53

FullFlex

Switching Waveforms (continued)

Read-to-Write-to-Read for Flow-through Mode, DDRON = LOW (OE = LOW)

tCYC

C

tSAC tHAC

CE0

CE1

BEn

tSAC

tHAC

R/W

A

An

An + 1

An + 2

An + 3

An + 4

tSD

tHD

DQIN

DQn + 2

tCD1

DQn

tDC

DQOUT

DQn + 1

DQn + 3

tCKHZ1

tCKLZ1

tDC

READ

NOP

W RITE

READ

Document #: 38-06072 Rev. *I

Page 41 of 53

FullFlex

Switching Waveforms (continued)

Read-to-Write-to-Read for Flow-through Mode, DDRON = LOW (OE Controlled)

tCYC

C

tHAC

tSAC

CE0

CE¹

BEn

tHAC

tSAC

R/W

A

An

An + 1

An + 2

tHD

An + 3

An + 4

An + 5

tSD

DQIN

DQn + 2

DQn + 3

tOE

tCD1

tDC

tCD1

DQOUT

DQn

DQn + 4

tDC

tCKLZ1

tOHZ

OE

READ

W RITE

READ

Document #: 38-06072 Rev. *I

Page 42 of 53

FullFlex

Switching Waveforms (continued)

BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow-through Modes, Clock Timing Violates t_CCS. (Flag Both

Ports)

Port A

C

A

R/W

BUSY

C

t_BSY

< t_CCS

Port B

A

R/W

t_BSY

BUSY

BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow-through Modes, Clock Timing Meets t_CCS. (Flag Losing

Port)

Losing Port

C

A

R/W

t_ccs

t_BSY

BUSY

t_BSY

Winning Port

C

A

Match

R/W

BUSY

Document #: 38-06072 Rev. *I

Page 43 of 53

FullFlex

Switching Waveforms (continued)

Read with Echo Clock for Pipelined Mode (CQEN = HIGH)

C

t

HAC

SAC

R/W

A

n

n+1

n+2

n+3

n+4

n+5

n+6

CQ0

CQ1

t

CCQ

CQ1

DQ

t

CQHQX

t

CQHQV

DQ

n+4

DQ

x

n

n+1

n+2

n+3

x-1

Document #: 38-06072 Rev. *I

Page 44 of 53

FullFlex

Ordering Information

256K

×

72/256K

×

36

× 2 (18 Mbit) 1.8V/1.5V Synchronous CYDD18S72V18 Dual-Port SRAM (SDR and DDR I/O)

Speed

(MHz)

Package

Name

Operating

Range

Ordering Code

Package Type

200 CYDD18S72V18-200BGXC BY484A 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD18S72V18-200BGC BG484A 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Commercial

167 CYDD18S72V18-167BGXC BY484A 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD18S72V18-167BGC

CYDD18S72V18-167BGXI

CYDD18S72V18-167BGI

BG484A 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Commercial

BY484A 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Industrial

BG484A 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Industrial

128K

×

72/128K

×

36

× 2 (9 Mbit) 1.8V/1.5V Synchronous CYDD09S72V18 Dual-Port SRAM (SDR and DDR I/O)

Speed

(MHz)

Package

Name

Operating

Range

Ordering Code

Package Type

200 CYDD09S72V18-200BGXC BY484A 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD09S72V18-200BGC BG484A 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Commercial

167 CYDD09S72V18-167BGXC BY484A 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD09S72V18-167BGC

CYDD09S72V18-167BGXI

CYDD09S72V18-167BGI

BG484A 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Commercial

BY484A 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Industrial

BG484A 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Industrial

64K

×

72/64K

×

36

×

2 (4 Mbit) 1.8V/1.5V Synchronous CYDD04S72V18 Dual-Port SRAM (SDR and DDR I/O)

Package

Speed

(MHz)

Operating

Range

Ordering Code

Name

Package Type

200 CYDD04S72V18-200BGXC BY484A 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD04S72V18-200BGC BG484A 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Commercial

167 CYDD04S72V18-167BGXC BY484A 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD04S72V18-167BGC

CYDD04S72V18-167BGXI

CYDD04S72V18-167BGI

BG484A 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Commercial

BY484A 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Industrial

BG484A 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Industrial

1024K

×

36

×

2 (36 Mbit) 1.8V/1.5V Synchronous CYDD36S36V18 Dual-Port SRAM (DDR only I/O)

Package

Speed

(MHz)

Operating

Range

Ordering Code

Name

Package Type

167 CYDD36S36V18-167BGXC BY484S 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD36S36V18-167BGC BG484S 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Commercial

133 CYDD36S36V18-133BGXC BY484S 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD36S36V18-133BGC

CYDD36S36V18-133BGXI

CYDD36S36V18-133BGI

BG484S 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Commercial

BY484S 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Industrial

BG484S 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Industrial

Document #: 38-06072 Rev. *I

Page 45 of 53

FullFlex

Ordering Information (continued)

512K

×

36

×

2 (18 Mbit) 1.8V/1.5V Synchronous CYDD18S36V18 Dual-Port SRAM (DDR only I/O)

Package

Speed

(MHz)

Operating

Range

Ordering Code

Name

Package Type

200 CYDD18S36V18-200BBXC BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD18S36V18-200BBC BB256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Leaded) Commercial

167 CYDD18S36V18-167BBXC BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD18S36V18-167BBC

CYDD18S36V18-167BBXI

CYDD18S36V18-167BBI

BB256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Leaded) Commercial

BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Lead-Free) Industrial

BB256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Leaded) Industrial

256K

×

36

×

2 (9 Mbit) 1.8V/1.5V Synchronous CYDD09S36V18 Dual-Port SRAM (DDR only I/O)

Package

Speed

(MHz)

Operating

Range

Ordering Code

Name

Package Type

200 CYDD09S36V18-200BBXC BW256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD09S36V18-200BBC BB256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial

167 CYDD09S36V18-167BBXC BW256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD09S36V18-167BBC

CYDD09S36V18-167BBXI

CYDD09S36V18-167BBI

BB256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial

BW256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Industrial

BB256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Industrial

128K × 36 × 2 (4 Mbit) 1.8V/1.5V Synchronous CYDD04S36V18 Dual-Port SRAM (DDR only I/O)

Speed

(MHz)

Package

Name

Operating

Range

Ordering Code

Package Type

200 CYDD04S36V18-200BBXC BW256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD04S36V18-200BBC BB256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial

167 CYDD04S36V18-167BBXC BW256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD04S36V18-167BBC

CYDD04S36V18-167BBXI

CYDD04S36V18-167BBI

BB256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial

BW256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Industrial

BB256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Industrial

2048K

×

18

×

2 (36 Mbit) 1.8V/1.5V Synchronous CYDD36S18V18 Dual-Port SRAM (DDR only I/O)

Package

Speed

(MHz)

Operating

Range

Ordering Code

Name

Package Type

167 CYDD36S18V18-167BGXC BY484S 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD36S18V18-167BGC BG484S 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Commercial

133 CYDD36S18V18-133BGXC BY484S 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD36S18V18-133BGC

CYDD36S18V18-133BGXI

CYDD36S18V18-133BGI

BG484S 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Commercial

BY484S 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Industrial

BG484S 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Industrial

1024K

×

18

×

2 (18 Mbit) 1.8V/1.5V Synchronous CYDD18S18V18 Dual-Port SRAM (DDR only I/O)

Package

Speed

(MHz)

Operating

Range

Ordering Code

Name

Package Type

200 CYDD18S18V18-200BBXC BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD18S18V18-200BBC BB256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Leaded) Commercial

167 CYDD18S18V18-167BBXC BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD18S18V18-167BBC

CYDD18S18V18-167BBXI

CYDD18S18V18-167BBI

BB256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Leaded) Commercial

BW256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Lead-Free) Industrial

BB256C 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Leaded) Industrial

Document #: 38-06072 Rev. *I

Page 46 of 53

FullFlex

Ordering Information (continued)

512K

×

18

×

2 (9 Mbit) 1.8V/1.5V Synchronous CYDD09S18V18 Dual-Port SRAM (DDR only I/O)

Package

Speed

(MHz)

Operating

Range

Ordering Code

Name

Package Type

200 CYDD09S18V18-200BBXC BW256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD09S18V18-200BBC BB256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial

167 CYDD09S18V18-167BBXC BW256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD09S18V18-167BBC

CYDD09S18V18-167BBXI

CYDD09S18V18-167BBI

BB256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial

BW256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Industrial

BB256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Industrial

256K

×

18

×

2 (4 Mbit) 1.8V/1.5V Synchronous CYDD04S18V18 Dual-Port SRAM (DDR only I/O)

Package

Speed

(MHz)

Operating

Range

Ordering Code

Name

Package Type

200 CYDD04S18V18-200BBXC BW256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD04S18V18-200BBC BB256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial

167 CYDD04S18V18-167BBXC BW256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial

CYDD04S18V18-167BBC

CYDD04S18V18-167BBXI

CYDD04S18V18-167BBI

BB256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial

BW256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Industrial

BB256E 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Industrial

Document #: 38-06072 Rev. *I

Page 47 of 53

FullFlex

Package Diagrams

256-ball Lead-Free FBGA (17 x 17 mm) BW256

256-ball Leaded FBGA (17 x 17 mm) BB256

TOP VIEW

BOTTOM VIEW

Ø0.05 M C

Ø0.25 M C A B

PIN 1 CORNER

Ø0.45 0.05(256X)ꢀCPꢁD DEVICES (37K & 39K)

PIN 1 CORNER

+0.10

Ø0.50 (256X)ꢀAꢁꢁ OTHER DEVICES

ꢀ0.05

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

A

B

C

D

E

F

G

H

J

G

H

J

K

ꢁ

K

ꢁ

M

N

P

R

T

M

N

P

R

T

1.00

B

7.50

15.00

A

17.00 0.10

A

SEATING PꢁANE

0.20(4X)

A1

C

REFERENCE JEDEC MOꢀ192

A1 0.36 0.56

1.40 MAX. 1.70 MAX.

51-85108-*F

A

Document #: 38-06072 Rev. *I

Page 48 of 53

FullFlex

Package Diagrams (continued)

256-ball Lead-Free FBGA (19 x 19 x 1.7 mm) BW256

256-ball Leaded FBGA (19 x 19 x 1.7 mm) BB256

BOTTOM VIEW

TOP VIEW

A1 CORNER

Ø0.05 M C

Ø0.25 M C A B

Ø0.50 (256 X)

1

3

PIN A1 CORNER

13

1

9

11

15

11

9

8

5

3

7

12

14

16

14

12

2

6

10

6

2

4

8

4

A

B

C

D

E

A

B

C

D

E

F

G

H

J

G

H

J

K

ꢁ

K

ꢁ

M

N

P

R

T

M

N

P

R

T

1.00 (REF)

ꢀBꢀ

15.00 (REF)

19.00 +/ꢀ 0.10

ꢀAꢀ

0.15(4X)

Package Weight ꢀ 1.1 grams

Jedec Outline ꢀ Design Guide 4.14

ꢀCꢀ

SEATING PꢁANE

001-00915-*A

Document #: 38-06072 Rev. *I

Page 49 of 53

FullFlex

Package Diagrams (continued)

484-ball Lead-Free PBGA (23 mm x 23 mm x 2.03 mm) BY484

484-ball Leaded PBGA (23 mm x 23 mm x 2.03 mm) BG484

Ø0.50~Ø0.70(484X)

PIN #1 CORNER

9

1

11

7

3

1

3

5

7

9

21

20 22

13

5

11

13 15 17 19

10 12 14 16 18

21

17 15

19

2

4

6

8

22 20 18 16 14 12 10

8

6

4

2

Ø1.00(3X) REF.

A

B

A

B

C

D

E

D

E

F

G

H

J

G

H

J

K

ꢁ

M

N

P

M

N

P

R

T

U

V

U

V

W

Y

W

Y

AA

AB

AA

AB

1.00

ꢀBꢀ

21.00

3.20*45°(4x)

20.00 REF.

ꢀAꢀ

23.00 0.20

0.20(4X)

30° TYP.

Package Weight ꢀ 2.0 grams

Jedec Outline ꢀ Design Guide 4.14

ꢀCꢀ

SEATING PꢁANE

51-85218-**

Document #: 38-06072 Rev. *I

Page 50 of 53

FullFlex

Package Diagrams (continued)

484-ball Lead-Free PBGA (27 mm x 27 mm x 2.33 mm) BY484S

484-ball Leaded PBGA (27 mm x 27 mm x 2.33 mm) BG484S

001-07825-**

FullFlex is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are

trademarks of their respective holders.

Document #: 38-06072 Rev. *I

Page 51 of 53

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

FullFlex

Document History Page

Document Title: FullFlex™ Synchronous DDR Dual-Port SRAM

Document Number: 38-06072

Issue

Date

Orig. of

Change

REV.

**

ECN NO.

Description of Change

274729 See ECN

294239 See ECN

SPN

New data sheet

*A

Updated VIM section

Added notes 7

Added timing for 100 MHz with DLL Disabled

Removed t_PS

*B

*C

301331 See ECN

318834 See ECN

SPN

Added note 19

Updates Selectable I/O Standard Section

Updated Block Diagram

Updated 484 pinouts, changed pins D11, W12, K3, K20

Added note 4 - Leaving pin DNU disables VIM

Updated 256 pinout, changed pins C10, G5, N7, N10

Added note 18, 19, 20, 21

Updated parameters in table 16

Updated note 1

*D

386692 See ECN

SPN

Updated ordering information

Added statement about no echo clocks for flow-through mode

Updated electrical characteristics

Added note 27 (timing for x18 devices)

Updated address readback latency to 2 cycles for DDR mode

Updated DDR timing numbers for t_CD, t_DC, t_CCQ, t_CQHQV, t_CQHQX, t_CKHZ, t_CKLZ

Updated input edge rate

Removed -133 speed bin electrical characteristics and timing columns

Updated Table 5 on collision detection to be the same as the one found in the EROS

Added description of busy readback in collision detection section

Changed dummy write descriptions

Updated PORTSTD[1:0] connection details

Updated ZQ pins connection details

Updated address count notes

Updated note 17, BO to BEO

Added power supply requirements to MRST and VC_SEL

Updated 484 ball package

Changed name from FLEX72-E, FLEX36-E, AND FLEX18-E to FullFlex72,

FullFlex36, and FullFlex18

*E

401662 See ECN

KGH

Updated READY description to include Wired OR note

Updated master reset to include wired OR note for READY

Updated electrical characteristics to include I_OHand I_OLvalues

Updated electrical characteristics to include READY

Added I_IX3

Updated maximum input capacitance

Added note 29

Updated Pin Definitions for CQ0, CQ0, CQ1, and CQ1

Changed voltage name from VDDQ to VDDIO

Changed voltage name from V_DDto V_CORE

Updated the Package Type for the CYDXXS36V18 parts

Updated the Package Type for the CYDXXS18V18 parts

Included the Package Diagram for the 256-Ball FBGA (19 x 19 mm) BW256

Included an OE Controlled Write for Flow-through Mode Switching Waveform

Included a Read with Echo Clock Switching Waveform

Included a Unit column for Table 5

Removed Switching Characteristic t_CAfrom chart

Included t_OHZin Switching Waveform OE Controlled Write for Pipelined Mode

Included t_CKLZ2in Waveform Read-to-Write-to-Read for Flow-through Mode

Updated AC Test Load and Waveforms

Included FullFlex36 DDR 484-ball BGA Pinout (Top View)

Included FullFlex18 DDR 484-ball BGA Pinout (Top View) Included Timing

Parameter t_CORDY

Document #: 38-06072 Rev. *I

Page 52 of 53

FullFlex

Document Title: FullFlex™ Synchronous DDR Dual-Port SRAM

Document Number: 38-06072

Issue

Date

Orig. of

Change

REV.

ECN NO.

Description of Change

*F

458129 SEE ECN

YDT

Changed ordering information with lead-free part numbers

Removed VC_SEL

Added I/O and core voltage adders

Removed references to bin drop for LVTTL/2.5V LVCMOS and 1.5V core modes

Updated Cin and Cout

Updated ICC, ISB1, ISB2 and ISB3 tables

Updated device widths information on first page

Updated busy address read back timing diagram

Added HTSL input waveform

Removed HSTL (AC) from DC tables

Added 484-ball 27mmx27mmx2.33mm PBGA package

*G

470037 SEE ECN

YDT

Changed VOL of 1.8V LVCMOS to 0.45V and VOH to VDDIO - 0.45V

Updated tRSF

VREF is left DNU when HSTL is not used

Changed LVTTL/LVCMOS adder for DDR

Formatted pin description table

Changed VDDIO pins for 36Mx36 and 36Mx18

Changed 36Mx72 JTAG IDCODE

*H

*I

499993 SEE ECN

627539 SEE ECN

YDT

QSL

DLL Change, added Clock Input Cycle to Cycle Jitter

Modified DLL description

Changed Input Capaciance Table

Changed tCCS number

Added note 34

change all NC to DNU

corrected switching waveform for (CQEN = High) from both Pipeline and

Flowthrough mode to only pipeline mode

Added note 17 to DDRON restriction

Modified Master Reset Description

Created a new table for flow-through mode only

changed note 29 description

Modified tSD, tHD, tSBE, tHBE, tCD, tDC, tCCQ, tCQHQV, tCQHQX, tCKHZ, and

tCKLZ timing parameter

Removed all instances of CYDD36S72V18

Document #: 38-06072 Rev. *I

Page 53 of 53


型号：	CYDD36S36V18-167BGXC
厂家：	CYPRESS
描述：	Dual-Port SRAM, 512KX72, 9ns, CMOS, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-484 时钟静态存储器内存集成电路
文件：	总53页 (文件大小：2422K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CYDD36S36V18-167BGXC [CYPRESS]

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