CYDM128B16-40BVXC [CYPRESS]
Dual-Port SRAM, 8KX16, 40ns, CMOS, PBGA100, 6 X 6 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, MO-195C, VFBGA-100;
| 型号： | CYDM128B16-40BVXC |
| 厂家： | 
CYPRESS |
| 描述： | Dual-Port SRAM, 8KX16, 40ns, CMOS, PBGA100, 6 X 6 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, MO-195C, VFBGA-100 静态存储器 内存集成电路 |
| 文件： | 总25页 (文件大小：517K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYDM256B16
CYDM128B16
CYDM064B16
1.8V 4K/8K/16K x 16
MoBL® Dual-Port Static RAM
• Full asynchronous operation
• Automatic power-down
Features
• True dual-ported memory cells that allow simultaneous
• Pin select for Master or Slave
access of the same memory location
• Expandable data bus to 32 bits with Master/Slave chip
• 4/8/16K × 16 organization
• High-speed access: 40 ns
• Ultra Low operating power
— Active: ICC = 15 mA (typical) at 55 ns
— Active: ICC = 25 mA (typical) at 40 ns
— Standby: ISB3 = 2 µA (typical)
select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• Input Read Registers and Output Drive Registers
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Industrial temperature ranges
• Small footprint: Available in a 6x6 mm 100-pin
Lead(Pb)-free fBGA
• Port-independent 1.8V, 2.5V, and 3.0V I/Os
Selection Guide for VCC = 1.8V
CYDM256B16, CYDM128B16,
CYDM256B16, CYDM128B16,
CYDM064B16
-40
CYDM064B16
-55
Port I/O Voltages (P1-P2)
Maximum Access Time
Typical Operating Current
Typical Standby Current for ISB1
Typical Standby Current for ISB3
1.8V-1.8V
1.8V-1.8V
Unit
ns
mA
µA
40
25
2
55
15
2
2
2
µA
Selection Guide for VCC = 2.5V
CYDM256B16, CYDM128B16,
CYDM256B16, CYDM128B16,
CYDM064B16
-40
CYDM064B16
-55
Port I/O Voltages (P1-P2)
Maximum Access Time
Typical Operating Current
Typical Standby Current for ISB1
Typical Standby Current for ISB3
2.5V-2.5V
2.5V-2.5V
Unit
ns
mA
µA
40
39
6
55
28
6
4
4
µA
Selection Guide for VCC = 3.0V
CYDM256B16, CYDM128B16,
CYDM256B16, CYDM128B16,
CYDM064B16
-40
CYDM064B16
-55
Port I/O Voltages (P1-P2)
Maximum Access Time
Typical Operating Current
Typical Standby Current for ISB1
Typical Standby Current for ISB3
3.0V-3.0V
3.0V-3.0V
Unit
ns
mA
µA
40
49
7
55
42
7
6
6
µA
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Document #: 001-00217 Rev. *D
Revised February 15, 2006
CYDM256B16
CYDM128B16
CYDM064B16
I/O[15:0]R
I/O[15:0]L
UBR
LBR
UBL
LBL
IO
IO
Control
Control
16K X 16
Dual Ported Array
Address Decode
Address Decode
A[13:0]L
CE L
A [13:0]R
CE R
Interrupt
OE L
R/W L
SEML
OE
Arbitration
R/WRR
SEMR
Semaphore
BUSY R
BUSY L
M/S
INTL
Mailboxes
INTR
Input Read
Register and
Output Drive
Register
CEL
OEL
R/WL
CE R
OE R
R/W R
IRR0 ,IRR1
ODR0 - ODR4
SFEN
Figure 1. Top Level Block Diagram[1, 2]
Notes:
1. A –A for 4K devices; A –A for 8K devices; A –A for 16K devices.
0
11
0
12
0
13
2. BUSY is an output in master mode and an input in slave mode.
Document #: 001-00217 Rev. *D
Page 2 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Pin Configurations [3, 4, 5, 6, 7]
100-Ball 0.5-mm Pitch BGA
Top View
CYDM064B16/CYDM128B16/CYDM256B16
1
2
3
4
5
6
7
8
9
10
A5R
A3R
A0R
A8R
A11R
UBR
VSS
SEMR I/O15R I/O12R I/O10R
VSS
A
B
C
D
E
F
A4R
A1R
A7R
A2R
A9R
A6R
CER
LBR
A10R
VSS
R/WR
OER
I/O14R I/O11R
I/O13R I/O8R
VDDIOR I/O9R
I/O6R
VSS
IRR1[6]
I/O7R
I/O5R
[3]
ODR4 ODR2 BUSYR INTR
A12R
I/O2R
VSS
VSS
M/S
ODR3
INTL
A1L
VSS
VSS
I/O4R VDDIOR I/O1R
I/O3R I/O0R
I/O11L I/O12L I/O14L I/O13L
SFEN ODR1 BUSYL
VCC
I/O15L VDDIOL
[3]
ODR0
A0L
A2L
A4L
A7L
A5L
A9L
A12L
OEL
CEL
VCC
I/O3L
I/O1L
VSS
G
H
J
NC[7]
I/O6L
NC[7]
I/O8L
LBL
VDDIOL
I/O4L
I/O10L
I/O9L
IRR0[5]
A3L
A10L
A6L
A8L
A11L
UBL
SEML R/WL
I/O0L
I/O2L
I/O5L
I/O7L
K
1
2
3
4
5
6
7
8
9
10
Notes:
3. A12L and A12R are NC pins for CYDM064B16.
4. IRR functionality is not supported for the CYDM256B16 device.
5. This pin is A13L for CYDM256B16 device.
6. This pin is A13R for CYDM256B16 device.
7. Leave this pin unconnected. No trace or power component can be connected to this pin.
Document #: 001-00217 Rev. *D
Page 3 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Pin Definitions
Left Port
CEL
Right Port
CER
Description
Chip Enable
R/WL
OEL
R/WR
OER
Read/Write Enable
Output Enable
A0L–A13L
I/O0L–I/O15L
SEML
UBL
LBL
A0R–A13R
I/O0R–I/O15R
SEMR
UBR
LBR
INTR
Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices).
Data Bus Input/Output for x16 devices
Semaphore Enable
Upper Byte Select (I/O8–I/O15).
Lower Byte Select (I/O0–I/O7).
Interrupt Flag
INTL
BUSYL
BUSYR
Busy Flag
IRR0, IRR1
Input Read Register for CYDM064B16, CYDM128B16.
A13L, A13R for CYDM256B16.
ODR0-ODR4
SFEN
M/S
Output Drive Register; These outputs are Open Drain.
Special Function Enable
Master or Slave Select
VCC
Core Power
GND
Ground
VDDIOL
VDDIOR
NC
Left Port I/O Voltage
Right Port I/O Voltage
No Connect. Leave this pin Unconnected.
The CYDM256B16, CYDM128B16, CYDM064B16 are
available in 100-ball 0.5-mm pitch Ball Grid Array (BGA)
Functional Description
The CYDM256B16, CYDM128B16, CYDM064B16 are
low-power CMOS 4K, 8K,16K x 16 dual-port static RAMs.
Arbitration schemes are included on the devices to handle
situations when multiple processors access the same piece of
data. Two ports are provided, permitting independent,
asynchronous access for reads and writes to any location in
memory. The devices can be utilized as standalone 16-bit
dual-port static RAMs or multiple devices can be combined in
order to function as a 32-bit or wider master/slave dual-port
static RAM. An M/S pin is provided for implementing 32-bit or
wider memory applications without the need for separate
master and slave devices or additional discrete logic. Appli-
cation areas include interprocessor/multiprocessor designs,
packages.
Power Supply
The core voltage (VCC) can be 1.8V, 2.5V or 3.3V, as long as
it is lower than or equal to the I/O voltage.
Each port can operate on independent I/O voltages. This is
determined by what is connected to the VDDIOL and VDDIOR
pins. The supported I/O standards are 1.8V/2.5V LVCMOS
and 3.0V LVTTL.
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summa-
rized in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port tDDD after the data is presented on the other port.
communications
status
buffering,
and
dual-port
video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt flag
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a Chip
Enable (CE) pin.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after
OE is asserted. If the user wishes to access a semaphore flag,
Document #: 001-00217 Rev. *D
Page 4 of 25
CYDM256B16
CYDM128B16
CYDM064B16
then the SEM pin must be asserted instead of the CE pin, and
OE must also be asserted.
The inputs will be 1.8V/2.5V LVCMOS or 3.0V LVTTL,
depending on the core voltage supply (VCC). Refer to Table 3
for Input Read Register operation.
Interrupts
IRR is not available in the CYDM256B16, as the IRR pins are
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CYDM064B16, 1FFF for the CYDM128B16, 3FFF for the
CYDM256B16) is the mailbox for the right port and the
second-highest memory location (FFE for the CYDM064B16,
1FFE for the CYDM128B16, 3FFE for the CYDM256B16) is the
mailbox for the left port. When one port writes to the other
port’s mailbox, an interrupt is generated to the owner. The
interrupt is reset when the owner reads the contents of the
mailbox. The message is user-defined.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
used as extra address pins A13L and A13R
.
Output Drive Register
The Output Drive Register (ODR) determines the state of up
to five external binary state devices by providing a path to VSS
for the external circuit. These outputs are Open Drain.
The five external devices can operate at different voltages
(1.5V ≤ VDDIO ≤ 3.5V) but the combined current cannot exceed
40 mA (8 mA max for each external device). The status of the
ODR bits are set using standard write accesses from either
port to address x0001 with a “1” corresponding to on and “0”
corresponding to off.
The status of the ODR bits can be read with a standard read
access to address x0001. When SFEN = VIL, the ODR is active
and address x0001 is not available for memory accesses.
When SFEN = VIH, the ODR is inactive and address x0001 can
be used for standard accesses.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin. On power up, an initialization program should be run
and the interrupts for both ports must be read to reset them.
During reads and writes to ODR DQ<4:0> are valid and
DQ<15:5> are don’t care. Refer to Table 4 for Output Drive
Register operation.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
Semaphore Operation
Busy
The CYDM256B16, CYDM128B16, CYDM064B16 provide
eight semaphore latches, which are separate from the
dual-port memory locations. Semaphores are used to reserve
resources that are shared between the two ports. The state of
the semaphore indicates that a resource is in use. For
example, if the left port wants to request a given resource, it
sets a latch by writing a zero to a semaphore location. The left
port then verifies its success in setting the latch by reading it.
After writing to the semaphore, SEM or OE must be
deasserted for tSOP before attempting to read the semaphore.
The semaphore value will be available tSWRD + tDOE after the
rising edge of the semaphore write. If the left port was
successful (reads a zero), it assumes control of the shared
resource, otherwise (reads a one) it assumes the right port has
control and continues to poll the semaphore. When the right
side has relinquished control of the semaphore (by writing a
one), the left side will succeed in gaining control of the
semaphore. If the left side no longer requires the semaphore,
a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same
manner as a normal memory access. When writing or reading
a semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 5 shows
sample semaphore operations.
The CYDM256B16, CYDM128B16, CYDM064B16 provide
on-chip arbitration to resolve simultaneous memory location
access (contention). If both ports’ CEs are asserted and an
address match occurs within tPS of each other, the busy logic
will determine which port has access. If tPS is violated, one port
will definitely gain permission to the location, but it is not
predictable which port will get that permission. BUSY will be
asserted tBLA after an address match or tBLC after CE is taken
LOW.
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY input has settled (tBLC or tBLA),
otherwise, the slave chip may begin a write cycle during a
contention situation. When tied HIGH, the M/S pin allows the
device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration
outcome to a slave.
Input Read Register
The Input Read Register (IRR) captures the status of two
external input devices that are connected to the Input Read
pins.
The contents of the IRR read from address x0000 from either
port. During reads from the IRR, DQ0 and DQ1 are valid bits
and DQ<15:2> are don’t care. Writes to address x0000 are not
allowed from either port.
Address x0000 is not available for standard memory accesses
when SFEN = VIL. When SFEN = VIH, address x0000 is
available for memory accesses.
Document #: 001-00217 Rev. *D
Page 5 of 25
CYDM256B16
CYDM128B16
CYDM064B16
When reading a semaphore, all sixteen data lines output the
semaphore value. The read value is latched in an output
register to prevent the semaphore from changing state during
a write from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will
definitely be obtained by one side or the other, but there is no
guarantee which side will control the semaphore. On
power-up, both ports should write “1” to all eight semaphores.
I/O and address lines, and control signals (CE, OE, R/W).
These control pins permit independent access for reads or
writes to any location in memory. To handle simultaneous
writes/reads to the same location, a BUSY pin is provided on
each port. Two Interrupt (INT) pins can be utilized for
port-to-port communication. Two Semaphore (SEM) control
pins are used for allocating shared resources. With the M/S
pin, the devices can function as a master (BUSY pins are
outputs) or as a slave (BUSY pins are inputs). The devices
also have an automatic power-down feature controlled by CE.
Each port is provided with its own output enable control (OE),
which allows data to be read from the device.
Architecture
The CYDM256B16, CYDM128B16, CYDM064B16 consist of
an array of 4K, 8K, or 16K words of 16 dual-port RAM cells,
Table 1. Non-Contending Read/Write
Inputs
Outputs
CE
H
X
L
L
L
L
L
L
X
H
X
H
X
L
R/W
X
X
L
L
OE
X
X
X
X
X
L
L
L
H
L
L
UB
X
H
L
H
L
L
H
L
X
X
H
X
H
L
LB
X
H
H
L
L
H
L
SEM
H
H
H
H
H
H
H
H
X
L
L
L
L
I/O8–I/O15
High Z
High Z
Data In
High Z
Data In
Data Out
High Z
Data Out
High Z
Data Out
Data Out
Data In
Data In
I/O0–I/O7
High Z
High Z
Operation
Deselected: Power-down
Deselected: Power-down
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
High Z
Data In
Data In
High Z
Data Out
Data Out
High Z
Data Out
Data Out
Data In
Data In
L
H
H
H
X
H
H
L
X
X
H
X
H
X
L
Outputs Disabled
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write DIN0 into Semaphore Flag
Write DIN0 into Semaphore Flag
Not Allowed
X
X
X
X
X
X
L
L
L
X
Not Allowed
Table 2. Interrupt Operation Example (Assumes BUSYL = BUSYR = HIGH)[8]
Left Port
Right Port
Function
R/WL CEL
OEL
X
X
X
L
A0L–13L
3FFF[11]
X
INTL R/WR CER OER
A0R–13R
X
3FFF[11]
3FFE[11]
X
INTR
L[10]
H[9]
X
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
L
X
X
X
L
X
X
L
X
X
L[9]
H[10]
X
X
L
X
L
L
X
L
X
X
X
3FFE[11]
X
X
X
Notes:
8. See Interrupts Functional Description for specific highest memory locations by device.
9. If BUSY = L, then no change.
R
10. If BUSY = L, then no change.
L
11. See Functional Description for specific addresses by device.
Document #: 001-00217 Rev. *D
Page 6 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Table 3. Input Read Register Operation[12, 15]
SFEN
H
L
CE
L
L
R/W
H
H
OE
L
L
UB
L
X
LB
L
L
ADDR
I/O0–I/O1 I/O2–I/O15
Mode
x0000-Max VALID[13] VALID[13] Standard Memory Access
x0000
VALID[14]
X
IRR Read
Table 4. Output Drive Register [16]
SFEN
CE
L
L
R/W
H
L
OE
X[17]
X
UB
L[13]
X
LB
L[13]
L
ADDR
I/O0–I/O4 I/O5–I/O15
Mode
H
L
L
x0000-Max VALID[13] VALID[13] Standard Memory Access
x0001
x0001
VALID[14]
VALID[14]
X
X
ODR Write[16, 18]
ODR Read[16]
L
H
L
X
L
Table 5. Semaphore Operation Example
Function I/O0–I/O15 Left I/O0–I/O15 Right
Status
No action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore-free
Left port writes 0 to semaphore
Right port writes 0 to semaphore
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
Left Port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore-free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore-free
Left port writes 1 to semaphore
Notes:
12. SFEN = V for IRR reads
IL
13. UB or LB = V . If LB = V , then DQ<7:0> are valid. If UB = V then DQ<15:8> are valid.
IL
IL
IL
IL
14. LB must be active (LB = V ) for these bits to be valid.
15. SFEN active when either CE = V or CE = V . It is inactive when CE = CE = V .
IH
L
IL
R
IL
L
R
16. SFEN = V for ODR reads and writes.
IL
17. Output enable must be low (OE = V ) during reads for valid data to be output.
IL
18. During ODR writes data will also be written to the memory.
Document #: 001-00217 Rev. *D
Page 7 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Maximum Ratings[19]
Output Current into Outputs (LOW)............................. 90 mA
Static Discharge Voltage.......................................... > 2000V
Latch-up Current.................................................... > 200 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Range
Ambient Temperature
VCC
Power Applied.............................................–55°C to +125°C
Commercial
0°C to +70°C
1.8V ± 100 mV
2.5V ± 100 mV
3.0V ± 300 mV
1.8V ± 100 mV
2.5V ± 100 mV
3.0V ± 300 mV
Supply Voltage to Ground Potential............... –0.5V to +3.3V
DC Voltage Applied to
Outputs in High-Z State..........................–0.5V to VCC + 0.5V
Industrial
–40°C to +85°C
DC Input Voltage[20] ...............................–0.5V to VCC + 0.5V
Electrical Characteristics for VCC = 1.8V Over the Operating Range
CYDM256B16,
CYDM256B16,
CYDM128B16,
CYDM064B16
CYDM128B16,
CYDM064B16
-40
-55
P1 I/O
P2 I/O
Parameter
Description
Voltage Voltage Min.
Typ. Max. Min.
Typ. Max. Unit
VOH
Output HIGH Voltage (IOH = –100 µA)
1.8V (any port)
VDDIO
– 0.2
VDDIO
V
– 0.2
Output HIGH Voltage (IOH = –2 mA)
Output HIGH Voltage (IOH = –2 mA)
Output LOW Voltage (IOL = 100 µA)
Output HIGH Voltage (IOL = 2 mA)
Output HIGH Voltage (IOL = 2 mA)
2.5V (any port)
3.0V (any port)
1.8V (any port)
2.5V (any port)
3.0V (any port)
2.0
2.1
2.0
2.1
V
V
VOL
0.2
0.4
0.4
0.2
0.2
0.2
VDDIO
+ 0.2
VDDIO
+ 0.3
0.2
0.4
0.4
0.2
0.2
0.2
VDDIO
+ 0.2
VDDIO
+ 0.3
V
V
V
V
V
V
V
VOL ODR ODR Output LOW Voltage (IOL = 8 mA) 1.8V (any port)
2.5V (any port)
3.0V (any port)
1.8V (any port)
2.5V (any port)
3.0V (any port)
VIH
Input HIGH Voltage
1.2
1.7
2.0
1.2
1.7
2.0
V
V
VDDIO
+ 0.2
VDDIO
+ 0.2
VIL
Input LOW Voltage
1.8V (any port)
2.5V (any port)
3.0V (any port)
–0.2
–0.3
–0.2
–1
–1
–1
–1
–1
–1
0.4
0.6
0.7
1
1
1
1
1
1
–0.2
–0.3
–0.2
–1
–1
–1
–1
–1
–1
0.4
0.6
0.7
1
1
1
1
1
1
V
V
V
µA
µA
µA
µA
µA
µA
IOZ
Output Leakage Current
1.8V
2.5V
3.0V
1.8V
2.5V
3.0V
1.8V
2.5V
3.0V
1.8V
2.5V
3.0V
ICEX ODR ODR Output Leakage Current.
OUT = VDDIO
V
Notes:
19. The voltage on any input or I/O pin can not exceed the power pin during power-up.
20. Pulse width < 20 ns.
Document #: 001-00217 Rev. *D
Page 8 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Electrical Characteristics for VCC = 1.8V (continued) Over the Operating Range
CYDM256B16,
CYDM128B16,
CYDM064B16
CYDM256B16,
CYDM128B16,
CYDM064B16
-40
-55
P1 I/O
P2 I/O
Parameter
IIX
Description
Input Leakage Current
Voltage Voltage Min.
Typ. Max. Min.
Typ. Max. Unit
1.8V
2.5V
3.0V
1.8V
1.8V
2.5V
3.0V
1.8V
–1
–1
–1
1
1
1
–1
–1
–1
1
1
1
µA
µA
µA
mA
ICC
Operating Current (VCC = Max.,
IOUT = 0 mA) Outputs Disabled
Standby Current (Both Ports TTL Ind.
Level) CEL and CER ≥ VCC – 0.2,
SEML = SEMR = VCC – 0.2, f = fMAX
Ind.
25
2
40
15
2
25
ISB1
1.8V
1.8V
6
6
µA
ISB2
ISB3
Standby Current (One Port TTL
Ind.
1.8V
1.8V
1.8V
1.8V
8.5
2
18
6
8.5
2
14
6
mA
Level) CEL | CER ≥ VIH, f = fMAX
Standby Current (Both Ports
Ind.
µA
CMOS Level) CEL & CER
≥
V
CC − 0.2V, SEML and SEMR >
VCC – 0.2V, f = 0
ISB4
Standby Current (One Port CMOS Ind.
1.8V
1.8V
8.5
18
8.5
14
mA
[21]
Level) CEL | CER ≥ VIH, f = fMAX
Notes:
21. f
= 1/t = All inputs cycling at f = 1/t (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
RC RC
MAX
standby I
.
SB3
Document #: 001-00217 Rev. *D
Page 9 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Electrical Characteristics for VCC = 2.5V Over the Operating Range
CYDM256B16,
CYDM256B16,
CYDM128B16,
CYDM064B16
CYDM128B16,
CYDM064B16
-40
-55
P1 I/O
P2 I/O
Parameter
Description
Voltage Voltage Min.
Typ. Max. Min.
Typ. Max. Unit
VOH
Output HIGH Voltage (IOH = –2 mA)
2.5V (any port)
3.0V (any port)
2.5V (any port)
3.0V (any port)
2.0
2.1
2.0
2.1
V
V
VOL
Output LOW Voltage (IOL = 2 mA)
0.4
0.4
0.2
0.2
0.4
0.4
0.2
0.2
V
V
V
V
V
VOL ODR ODR Output LOW Voltage (IOL = 8 mA) 2.5V (any port)
3.0V (any port)
2.5V (any port)
VIH
Input HIGH Voltage
1.7
2.0
VDDIO
1.7
2.0
VDDIO
+ 0.3
+ 0.3
3.0V (any port)
VDDIO
+ 0.2
VDDIO
+ 0.2
V
VIL
IOZ
Input LOW Voltage
2.5V (any port)
3.0V (any port)
–0.3
–0.2
–1
–1
–1
–1
–1
–1
0.6
0.7
1
1
1
1
1
1
55
–0.3
–0.2
–1
–1
–1
–1
–1
–1
0.6
0.7
1
1
1
1
1
1
40
V
V
Output Leakage Current
2.5V
3.0V
2.5V
3.0V
2.5V
3.0V
2.5V
2.5V
3.0V
2.5V
3.0V
2.5V
3.0V
2.5V
µA
µA
µA
µA
µA
µA
mA
ICEX ODR ODR Output Leakage Current.
VOUT = VCC
IIX
Input Leakage Current
ICC
Operating Current (VCC = Max.,
Ind.
39
6
28
6
I
OUT = 0 mA) Outputs Disabled
ISB1
Standby Current (Both Ports TTL Ind.
Level) CEL and CER ≥ VCC – 0.2,
SEML= SEMR = VCC – 0.2, f = fMAX
2.5V
2.5V
8
8
µA
ISB2
ISB3
Standby Current (One Port TTL
Ind.
2.5V
2.5V
2.5V
2.5V
21
4
30
6
18
4
25
6
mA
Level) CEL | CER ≥ VIH, f = fMAX
Standby Current (Both Ports
Ind.
µA
CMOS Level) CEL & CER
≥
V
CC − 0.2V, SEML and SEMR >
VCC – 0.2V, f = 0
ISB4
Standby Current (One Port CMOS Ind.
2.5V
2.5V
21
30
18
25
mA
[21]
Level) CEL | CER ≥ VIH, f = fMAX
Document #: 001-00217 Rev. *D
Page 10 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Electrical Characteristics for 3.0V Over the Operating Range
CYDM256B16,
CYDM128B16,
CYDM064B16
CYDM256B16,
CYDM128B16,
CYDM064B16
-40
-55
P1 I/O
P2 I/O
Parameter
VOH
VOL
V
VIH
Description
Output HIGH Voltage (IOH = –2 mA)
Output LOW Voltage (IOL = 2 mA)
Voltage Voltage Min.
Typ. Max. Min.
Typ. Max. Unit
3.0V (any port)
3.0V (any port)
2.1
2.0
2.1
V
0.4
0.2
0.4
0.2
V
V
V
OL ODR ODR Output LOW Voltage (IOL = 8 mA) 3.0V (any port)
Input HIGH Voltage
3.0V (any port)
VDDIO
2.0
VDDIO
+ 0.2
+ 0.2
VIL
IOZ
Input LOW Voltage
Output Leakage Current
3.0V (any port)
–0.2
–1
–1
0.7
1
1
–0.2
–1
–1
0.7
1
1
V
µA
µA
3.0V
3.0V
3.0V
3.0V
ICEX ODR ODR Output Leakage Current.
VOUT = VCC
IIX
ICC
Input Leakage Current
Operating Current (VCC = Max.,
OUT = 0 mA) Outputs Disabled
Standby Current (Both Ports TTL Ind.
Level) CEL and CER ≥ VCC – 0.2,
SEML = SEMR = VCC – 0.2, f = fMAX
3.0V
3.0V
3.0V
3.0V
–1
1
70
–1
1
60
µA
mA
Ind.
49
7
42
7
I
ISB1
3.0V
3.0V
10
10
µA
ISB2
ISB3
Standby Current (One Port TTL
Ind.
3.0V
3.0V
3.0V
3.0V
28
6
40
8
25
6
35
8
mA
Level) CEL | CER ≥ VIH, f = fMAX
Standby Current (Both Ports
Ind.
µA
CMOS Level) CEL & CER
≥
V
CC − 0.2V, SEML and SEMR >
VCC – 0.2V, f = 0
ISB4
Standby Current (One Port CMOS Ind.
3.0V
3.0V
28
40
25
35
mA
[21]
Level) CEL | CER ≥ VIH, f = fMAX
Capacitance[22]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 3.0V
Max.
9
10
Unit
pF
pF
CIN
COUT
V
Note:
22. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-00217 Rev. *D
Page 11 of 25
CYDM256B16
CYDM128B16
CYDM064B16
7
AC Test Loads and Waveforms
3.0V/2.5V/1.8V
3.0V/2.5V/1.8V
R1
RTH = 6 kΩ
R1
OUTPUT
C = 30 pF
OUTPUT
OUTPUT
C = 5 pF
C = 30 pF
R2
R2
VTH = 0.8V
(a) Normal Load
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE, and tLZWE
including scope and jig)
(b) Thévenin Equivalent (Load 1)
ALL INPUT PULSES
3.0V/2.5V
1022Ω
1.8V
13500Ω
10800Ω
1.8V
GND
R1
R2
90%
90%
10%
≤ 3 ns
10%
792Ω
≤ 3 ns
Switching Characteristics for VCC = 1.8V Over the Operating Range[23]
CYDM256B16,
CYDM128B16,
CYDM064B16
CYDM256B16,
CYDM128B16,
CYDM064B16
-40
-55
Parameter
Read Cycle
Description
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable Access Time
Min.
40
5
Max.
Min.
55
5
Max.
Unit
tRC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
55
tOHA
[24]
tACE
tDOE
tLZOE
40
25
55
30
[25, 26, 27]
[25, 26, 27]
5
5
0
5
5
0
tHZOE
tLZCE
15
15
25
25
[25, 26, 27]
[25, 26, 27]
tHZCE
[27]
[27]
tPU
tPD
40
40
55
55
[24]
tABE
Write Cycle
tWC
Write Cycle Time
40
30
30
0
55
45
45
0
ns
ns
ns
ns
[24]
tSCE
tAW
tHA
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Notes:
23. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V /2, input pulse levels of 0 to V , and output loading of the specified
CC
CC
I
/I and 30-pF load capacitance.
OI OH
24. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t
time.
SCE
25. At any given temperature and voltage condition for any given device, t
26. Test conditions used are Load 3.
is less than t
and t
is less than t
.
LZOE
HZCE
LZCE
HZOE
27. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with
Busy waveform
Document #: 001-00217 Rev. *D
Page 12 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Switching Characteristics for VCC = 1.8V Over the Operating Range[23] (continued)
CYDM256B16,
CYDM128B16,
CYDM064B16
CYDM256B16,
CYDM128B16,
CYDM064B16
-40
-55
Parameter
Description
Address Set-up to Write Start
Write Pulse Width
Data Set-up to Write End
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
Min.
0
25
20
0
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
[24]
tSA
tPWE
tSD
0
40
30
0
tHD
[26, 27]
tHZWE
tLZWE
tWDD
tDDD
15
25
[26, 27]
0
0
[28]
55
45
80
65
[28]
Busy Timing[29]
tBLA
tBHA
tBLC
tBHC
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-up for Priority
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
30
30
30
30
45
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
[30]
tPS
5
0
20
5
0
35
tWB
tWH
tBDD
[31]
30
40
Interrupt Timing[29]
tINS
tINR
INT Set Time
INT Reset Time
35
35
45
45
ns
ns
Semaphore Timing
tSOP
tSWRD
tSPS
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
10
10
15
10
10
ns
ns
ns
ns
tSAA
40
55
Notes:
28. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
29. Test conditions used are Load 2.
30. Add 2ns to this parameter if V and V
are <1.8V, and V
is >2.5V at temperature <0°C.
CC
DDIOR
DDIOL
PWE
31. t
is a calculated parameter and is the greater of t
– t
(actual) or t
– t (actual).
BDD
WDD
DDD SD
Document #: 001-00217 Rev. *D
Page 13 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Switching Characteristics for VCC = 2.5V Over the Operating Range
CYDM256B16,
CYDM128B16,
CYDM064B16
CYDM256B16,
CYDM128B16,
CYDM064B16
-40
-55
Parameter
Read Cycle
Description
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable Access Time
Min.
40
5
Max.
Min.
Max.
Unit
tRC
tAA
55
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
55
tOHA
[24]
tACE
tDOE
tLZOE
40
25
55
30
[25, 26, 27]
[25, 26, 27]
2
2
0
2
2
0
tHZOE
tLZCE
15
15
25
25
[25, 26, 27]
[25, 26, 27]
tHZCE
[27]
[27]
tPU
tPD
40
40
55
55
[24]
tABE
Write Cycle
tWC
Write Cycle Time
CE LOW to Write End
40
30
30
0
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[24]
tSCE
tAW
tHA
Address Valid to Write End
Address Hold From Write End
Address Set-up to Write Start
Write Pulse Width
Data Set-up to Write End
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
[24]
tSA
tPWE
tSD
0
0
25
20
0
40
30
0
tHD
[26, 27]
tHZWE
tLZWE
tWDD
tDDD
15
25
[26, 27]
0
0
[28]
55
45
80
65
[28]
Busy Timing[29]
tBLA
tBHA
tBLC
tBHC
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-up for Priority
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
30
30
30
30
45
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
[30]
tPS
5
0
20
5
0
35
tWB
tWH
tBDD
[31]
30
40
Interrupt Timing[29]
tINS
tINR
INT Set Time
INT Reset Time
35
35
45
45
ns
ns
Document #: 001-00217 Rev. *D
Page 14 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Switching Characteristics for VCC = 2.5V Over the Operating Range (continued)
CYDM256B16,
CYDM128B16,
CYDM064B16
CYDM256B16,
CYDM128B16,
CYDM064B16
-40
-55
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Semaphore Timing
tSOP
tSWRD
tSPS
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
10
10
15
10
10
ns
ns
ns
ns
tSAA
40
55
Switching Characteristics for VCC = 3.0V Over the Operating Range
CYDM256B16,
CYDM128B16,
CYDM064B16
CYDM256B16,
CYDM128B16,
CYDM064B16
-40
-55
Parameter
Read Cycle
Description
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable Access Time
Min.
40
5
Max.
Min.
Max.
Unit
tRC
tAA
55
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
55
tOHA
[24]
tACE
tDOE
tLZOE
40
25
55
30
[25, 26, 27]
[25, 26, 27]
1
1
0
1
1
0
tHZOE
tLZCE
15
15
25
25
[25, 26, 27]
[25, 26, 27]
tHZCE
[27]
tPU
tPD
[27]
40
40
55
55
[24]
tABE
Write Cycle
tWC
Write Cycle Time
CE LOW to Write End
40
30
30
0
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[24]
tSCE
tAW
tHA
Address Valid to Write End
Address Hold From Write End
Address Set-up to Write Start
Write Pulse Width
Data Set-up to Write End
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
[24]
tSA
tPWE
tSD
0
0
25
20
0
40
30
0
tHD
[26, 27]
tHZWE
tLZWE
tWDD
tDDD
15
25
[26, 27]
0
0
[28]
55
45
80
65
[28]
Document #: 001-00217 Rev. *D
Page 15 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Switching Characteristics for VCC = 3.0V Over the Operating Range (continued)
CYDM256B16,
CYDM128B16,
CYDM064B16
CYDM256B16,
CYDM128B16,
CYDM064B16
-40
-55
Parameter
Busy Timing[29]
Description
Min.
Max.
Min.
Max.
Unit
tBLA
tBHA
tBLC
tBHC
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-up for Priority
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
30
30
30
30
45
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
[30]
tPS
5
0
20
5
0
35
tWB
tWH
tBDD
[31]
30
40
Interrupt Timing[29]
tINS
tINR
INT Set Time
INT Reset Time
35
35
45
45
ns
ns
Semaphore Timing
tSOP
tSWRD
tSPS
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
10
10
15
10
10
ns
ns
ns
ns
tSAA
40
55
Document #: 001-00217 Rev. *D
Page 16 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Switching Waveforms
Read Cycle No.1 (Either Port Address Access)[32, 33, 34]
t
RC
ADDRESS
DATA OUT
t
AA
t
t
OHA
OHA
PREVIOUS DATAVALID
DATA VALID
Read Cycle No.2 (Either Port CE/OE Access)[32, 35, 36]
t
ACE
CE and
LB or UB
t
HZCE
t
DOE
OE
t
HZOE
t
LZOE
DATA VALID
DATA OUT
t
LZCE
t
PU
t
PD
ICC
CURRENT
ISB
Read Cycle No. 3 (Either Port)[32, 34, 37, 38]
t
RC
ADDRESS
t
AA
t
OHA
UB or LB
t
t
HZCE
t
t
LZCE
LZCE
t
ABE
CE
HZCE
t
ACE
DATA OUT
Notes:
32. R/W is HIGH for read cycles.
33. Device is continuously selected CE = V and UB or LB = V . This waveform cannot be used for semaphore reads.
IL
IL
34. OE = V
.
IL
35. Address valid prior to or coincident with CE transition LOW.
36. To access RAM, CE = V , UB or LB = V , SEM = V . To access semaphore, CE = V , SEM = V .
IL
IL
IL
IH
IH
37. R/W must be HIGH during all address transitions.
38. A write occurs during the overlap (t or t ) of a LOW CE or SEM and a LOW UB or LB.
SCE
PWE
Document #: 001-00217 Rev. *D
Page 17 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Switching Waveforms (continued)
Write Cycle No.1: R/W Controlled Timing[37, 38, 39, 40, 41, 42]
t
WC
ADDRESS
OE
[43]
t
HZOE
t
AW
[41, 42]
CE
[40]
PWE
t
t
t
HA
SA
R/W
DATA OUT
DATA IN
[43]
HZWE
t
t
LZWE
NOTE 44
NOTE 44
t
t
HD
SD
Write Cycle No. 2: CE Controlled Timing[37, 38, 39, 44]
t
WC
ADDRESS
t
AW
[41, 42]
CE
t
t
t
HA
SA
SCE
R/W
t
t
HD
SD
DATA IN
Notes:
39. t is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
HA
40. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or (t
+ t ) to allow the I/O drivers to turn off and data to
HZWE SD
PWE
be placed on the bus for the required t . If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
SD
as the specified t
.
PWE
41. To access RAM, CE = V , SEM = V
.
IH
IL
42. To access upper byte, CE = V , UB = V , SEM = V .
IH
IL
IL
IL
To access lower byte, CE = V , LB = V , SEM = V .
IH
IL
43. Transition is measured ±0 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
44. During this period, the I/O pins are in the output state, and input signals must not be applied.
Document #: 001-00217 Rev. *D
Page 18 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[45, 46]
t
t
OHA
SAA
A0–A2
VALID ADRESS
VALID ADRESS
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
I/O0
DATAIN VALID
DATAOUT VALID
t
HD
t
t
PWE
SA
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
Timing Diagram of Semaphore Contention[47, 48]
A0L–A2L
MATCH
R/WL
SEML
t
SPS
A0R–A2R
MATCH
R/WR
SEMR
Notes:
45. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
46. CE = HIGH for the duration of the above timing (both write and read cycle).
47. I/O = I/O = LOW (request semaphore); CE = CE = HIGH.
0R
SPS
0L
R
L
48. If t
is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Document #: 001-00217 Rev. *D
Page 19 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Switching Waveforms (continued)
Timing Diagram of Read with BUSY (M/S = HIGH)[49]
t
WC
ADDRESSR
R/WR
MATCH
t
PWE
t
t
HD
SD
DATA INR
VALID
t
PS
ADDRESSL
MATCH
t
BLA
t
BHA
BUSYL
t
BDD
t
DDD
DATAOUTL
VALID
t
WDD
Write Timing with Busy Input (M/S = LOW)
t
PWE
R/W
t
t
WH
WB
BUSY
Note:
49. CE = CE = LOW.
L
R
Document #: 001-00217 Rev. *D
Page 20 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Switching Waveforms (continued)
Busy Timing Diagram No.1 (CE Arbitration)
CEL Valid First[50]
ADDRESSL,R
ADDRESS MATCH
CEL
t
PS
CER
t
t
BHC
BLC
BUSYR
CEL Valid First
ADDRESSL,R
ADDRESS MATCH
CER
CEL
t
PS
t
t
BHC
BLC
BUSYL
Busy Timing Diagram No.2 (Address Arbitration)[50]
Left Address Valid First
t
or t
WC
RC
ADDRESSL
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
t
t
BHA
BLA
BUSYR
Right Address Valid First
t
or t
WC
RC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESSL
BUSYL
t
t
BHA
BLA
Note:
50. If t is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
PS
Document #: 001-00217 Rev. *D
Page 21 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR:
t
WC
ADDRESSL
CEL
WRITE 1FFF (OR 1/3FFF)
[51]
t
HA
R/WL
INTR
[52]
t
INS
Right Side Clears INTR:
t
RC
READ 1FFF
ADDRESSR
CER
(OR 1/3FFF)
[52]
t
INR
R/WR
OER
INTR
Right Side Sets INTL:
t
WC
ADDRESSR
CER
WRITE 1FFE (OR 1/3FFE)
[51]
t
HA
R/WR
INTL
[52]
INS
t
Left Side Clears INTL:
t
RC
READ 1FFE
ADDRESSL
OR 1/3FFE)
CEL
[52]
t
INR
R/WL
OEL
INTL
Notes:
51. t depends on which enable pin (CE or R/W ) is deasserted first.
HA
L
L
52. t
or t
depends on which enable pin (CE or R/W ) is asserted last.
INR L L
INS
Document #: 001-00217 Rev. *D
Page 22 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Ordering Information
16K x16 1.8V Asynchronous Dual-Port SRAM
Speed
Package
Operating
Range
Commercial
Commercial
Industrial
(ns)
Ordering Code
CYDM256B16-40BVXC
CYDM256B16-55BVXC
CYDM256B16-55BVXI
Name
BZ100
BZ100
BZ100
Package Type
40
55
55
100-ball Lead-free 0.5-mm Pitch BGA
100-ball Lead-free 0.5-mm Pitch BGA
100-ball Lead-free 0.5-mm Pitch BGA
8K x16 1.8V Asynchronous Dual-Port SRAM
Speed
Package
Name
BZ100
BZ100
BZ100
Operating
Range
Commercial
Commercial
Industrial
(ns)
40
Ordering Code
CYDM128B16-40BVXC
CYDM128B16-55BVXC
CYDM128B16-55BVXI
Package Type
100-ball Lead-free 0.5-mm Pitch BGA
100-ball Lead-free 0.5-mm Pitch BGA
100-ball Lead-free 0.5-mm Pitch BGA
55
55
4K x16 1.8V Asynchronous Dual-Port SRAM
Speed
Package
Name
BZ100
BZ100
BZ100
Operating
Range
Commercial
Commercial
Industrial
(ns)
40
Ordering Code
CYDM064B16-40BVXC
CYDM064B16-55BVXC
CYDM064B16-55BVXI
Package Type
100-ball Lead-free 0.5-mm Pitch BGA
100-ball Lead-free 0.5-mm Pitch BGA
100-ball Lead-free 0.5-mm Pitch BGA
55
55
Document #: 001-00217 Rev. *D
Page 23 of 25
CYDM256B16
CYDM128B16
CYDM064B16
Package Diagram
100 VFBGA (6 x 6 x 1.0 mm) BZ100A
"/44/- 6)%7
!ꢀ #/2.%2
4/0 6)%7
ꢁꢂꢁꢃ - #
ꢁꢂꢀꢃ - # ! "
!ꢀ #/2.%2
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ꢀ
ꢈ ꢄ ꢇ ꢃ ꢊ ꢎ ꢉ ꢌ ꢀꢁ
ꢀꢁ
ꢌ
ꢉ
ꢎ ꢊ ꢃ ꢇ ꢄ ꢈ ꢀ
!
!
"
#
$
%
"
#
$
%
&
&
'
'
(
(
*
*
+
+
ꢈꢂꢈꢃ
!
!
ꢁꢂꢃꢁ
ꢇꢂꢃꢁ
"
ꢊꢂꢁꢁ¼ꢁꢂꢀꢁ
"
ꢊꢂꢁꢁ¼ꢁꢂꢀꢁ
ꢁꢂꢀꢃꢅꢇ8ꢆ
2%&%2%.#% *%$%# -/ꢋꢀꢌꢃ#
0+'ꢂ7%)'(4ꢍ4"$ ꢅ.%7 0+'ꢂꢆ
3%!4).' 0,!.%
#
51-85209-*B
MoBL is a registered trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this
document are the trademarks of their respective holders.
Document #: 001-00217 Rev. *D
Page 24 of 25
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CYDM256B16
CYDM128B16
CYDM064B16
Document History Page
Document Title: CYDM064B16/CYDM128B16/CYDM256B16 1.8V 4K/8K/16K x 16 Dual-Port Static RAM
Document Number: 001-00217
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
369423
SEE ECN
YDT
New data sheet
*A
381721
SEE ECN
YDT
Updated 2.5V/3.0V ICC, ISB1, ISB2, ISB4
Updated VOL ODR to 0.2V
*B
*C
396697
404777
SEE ECN
SEE ECN
KGH
KGH
Updated ISB2 and ISB4 typo to mA.
Updated tINS and tINR for -55 to 31ns.
Updated IOH and IOL values for the 1.8V, 2.5V and 3.0V parameters VOH and
VOL
Replaced -35 speed bin with -40
Updated Switching Characteristics for VCC = 2.5V and VCC = 3.0V
Included note 35
*D
426637
SEE ECN
KGH
Removed part numbers CYDM128B08 and CYDM064B08
Document #: 001-00217 Rev. *D
Page 25 of 25
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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