CYIFS781BZXCT [CYPRESS]

Low EMI Spectrum Spread Clock; 低EMI的扩频时钟


型号：	CYIFS781BZXCT
厂家：	CYPRESS
描述：	Low EMI Spectrum Spread Clock 低EMI的扩频时钟晶体时钟发生器微控制器和处理器外围集成电路光电二极管
文件：	总12页 (文件大小：252K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FS781/82/84

Low EMI Spectrum Spread Clock

Features

Functional Description

The Cypress FS781/82/84 are Spread Spectrum clock

generator ICs (SSCG) designed for the purpose of reducing

electromagnetic interference (EMI) found in today’s

high-speed digital systems.

• Spread Spectrum clock generator (SSCG) with 1×, 2×,

and 4× outputs

• 6- to 82-MHz operating frequency range

• Modulates external clocks including crystals, crystal

oscillators, or ceramic resonators

The FS781/82/84 SSCG clocks use a Cypress-proprietary

technology to modulate the input clock frequency, XIN, by

modulating the frequency of the digital clock. By modulating

the reference clock the measured EMI at the fundamental and

harmonic frequencies of FSOUT is greatly reduced. This

reduction in radiated energy can significantly reduce the cost

of complying with regulatory requirements without degrading

digital waveforms.

• Programmable modulation with simple R-C external

loop filter (LF)

• Center spread modulation

• 3V-5V power supply

• TTL-/CMOS-compatible outputs

• Low short-term jitter

The Cypress FS781/82/84 clocks are very simple and

versatile devices to use. By programming the two range select

lines, S0 and S1, any frequency from 6- to 82-MHz operating

range can be selected. The FS781/2/4 are designed to

operate over a very wide range of input frequencies and

provides 1×, 2×, and 4× modulated clock outputs.

• Low-power Dissipation

— 3.3 VDC = 37 mW – typical

— 5.0 VDC = 115 mW – typical

• Available in 8-pin SOIC and TSSOP packages

The FS78x devices have a simple frequency selection table

that allows operation from 6 MHz to 82 MHz in four separate

ranges. The bandwidth of the frequency spread at FSOUT is

determined by the values of the loop filter components. The

modulation rate is determined internally by the input frequency

and the selected input frequency range.

Applications

• Desktop/notebook computers

• Printers, copiers, and MFP

• Scanners and fax

The Bandwidth of these products can be programmed from as

little as 1.0% up to as much as 4.0% by selecting the proper

loop filter value. Refer to the Loop Filter Selection chart in

Table 2 and Table 3 for the recommended values. Due to a

wide range of application requirements, an external loop filter

(LF) is used on the FS78x products. The user can select the

exact amount of frequency modulation suitable for the appli-

cation. Using a fixed internal loop filter would severely limit

the use of a wide range of modulation bandwidths (Spread %)

to a few discrete values. Refer to FS791/2/4 products for appli-

cations requiring 80- to 140-MHz frequency range.

• LCD displays and monitors

• CD-ROM, VCD, and DVD

• Automotive and embedded systems

• Networking, LAN/WAN

• Digital cameras and camcorders

• Modems

Benefits

• Programmable EMI reduction

• Fast time to market

• Lower cost of compliance

• No degradation in rise/fall times

• Lower component and PCB layer count

Cypress Semiconductor Corporation

Document #: 38-07029 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 2, 2005

[+] Feedback

FS781/82/84

Pin Configuration

Block Diagram

Loop Filter

4(6)

Xin

VDD

250 K

Xout

FS78x

FSOUT

VSS

Reference

Divider

1(3)

Xin

Phase

Detector

8 pF

VCO

10 pF.

8 Pin SOIC Package

Modulation

Control

2(4)

Xout

8 pF

VCO / N

FSOUT

VSS

Output

Divider

and

VDD

FS78x

Power Contol

Logic

8(2)

6(8)

VDD

Input Control Logic

VDD

FSOUT

Xin

Mux

Xout

VSS

(TSSOP Pin #)

7(1)

5(7)

3(5)

8 Pin TSSOP Package

VSS

Pin Description

Name

X_IN/X_OUT

I/O

Type

Description

1/2 (SOIC)

3/4 (TSSOP)

I/O

Analog

Pins form an on-chip reference oscillator when connected to terminals

of an external parallel resonant crystal. X_INmay be connected to

TTL/CMOS external clock source. If X_INis connected to an external clock

other than crystal, leave X_OUT(pin 2) unconnected.

7/3 (SOIC)

1/5 (TSSOP)

S0 / S1

CMOS/TTL Digital control inputs to select input frequency range and output

frequency scaling. Refer to Table 2 and Table 3 for selection. S0 has internal

pull-down. S1 has internal pull-up.

4 (SOIC)

6 (TSSOP)

Analog

Loop Filter. Single ended three-state output of the phase detector. A two-pole

passive loop filter is connected to LF.

6 (SOIC)

8 (TSSOP)

FSOUT

CMOS/TTL Modulated Clock Frequency Output. The center frequency is the same as

the input reference frequency for FS781. Input frequency is multiplied by 2×

and 4× for FS782 and FS784, respectively.

8 (SOIC)

2 (TSSOP)

V_DD

V_SS

Power

Positive Power Supply.

5 (SOIC)

Power

Power Supply Ground.

7 (TSSOP)

Output Frequency Selection

Table 1. FSOUT SSCG (Modulated Output Clock) Product Selection

Product Number

FS781

FSOUT Frequency Scaling

Description

1×

2×

4×

1× modulated frequency of input clock

2× modulated frequency of input clock

4× modulated frequency of input clock

FS782

FS784

Loop Filter Selection Chart

LF (pin 4)

The following table provides a list of recommended loop filter

values for the FS781/82/84. The FS78X is divided into four

ranges and operated at both 3.3V and 5.5 VDC. The loop filter

at the right is representative of the loop filter components in

Table 2.

Document #: 38-07029 Rev. *F

Page 2 of 12

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FS781/82/84

Table 2. FS781/82/84 Recommended Loop Filter Values C7 (pF) @ +3.3 VDC ±5% (R6 = 3.3K)^{[1, 2, 3, 4]}

Input MHz S1 S0 BW = 1.0%^[3]BW = 1.5%^[3]BW = 2.0%^[3]BW = 2.5%^[3]BW = 3.0%^[3]BW = 3.5%^[3]BW = 4.0%^[3]

10,000/1000

10,000/330

1040

830

1550

990

680

420

230

980

750

730

640

400

300

230

180

170

860

820

690

600

620

680

580

440

360

325

270

250

210

185

220

860

850

760

750

740

780

770

720

670

620

540

910

820

460

300

200

760

580

470

410

250

220

180

140

120

640

620

520

420

380

400

270

260

250

220

200

185

165

150

560

540

560

500

470

440

270

260

250

780

640

360

220

160

580

470

390

270

210

180

150

120

100

520

470

410

340

275

250

220

210

190

185

170

150

130

120

410

400

350

320

370

300

280

240

210

700

520

300

200

140

470

415

320

230

180

150

130

100

640

450

240

190

100

410

370

220

200

160

140

100

560

400

210

170

580

10000

1200

1000

960

385

300

190

180

150

120

920

660

470

330

10000

2200

1500

960

430

400

340

280

230

210

190

180

170

155

140

120

100

340

330

260

300

250

230

210

190

380

330

290

220

210

190

180

160

150

135

130

330

290

240

160

180

170

165

140

120

100

940

950

900

790

660

470

445

430

295

270

1180

1120

1160

1110

1000

910

290

280

220

230

240

220

210

190

170

230

220

210

170

190

170

160

156

150

900

Notes:

1. If the value selected from the above chart is not a standard, use the next available larger value.

2. All bandwidths indicated above are total peak-to-peak spread. 1% = +0.5% to –0.5%. 4% = +2.0% to –2.0%.

3. If C8 is not listed in the chart for a particular bandwidth and frequency, it is not used in the loop filter.

4. Contact Cypress for LF values less than 1.0% bandwidth.

Document #: 38-07029 Rev. *F

Page 3 of 12

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FS781/82/84

Table 3. FS781/82/84 Recommended Loop Filter Values C7 (pF) @ +5.0 VDC ±5% (R6 = 3.3K)^{[1, 2, 3, 4]}

Input MHz S1 S0 BW = 1.0%^[3]BW = 1.5%^[3]BW = 2.0%^[3]BW = 2.5%^[3]BW = 3.0%^[3]BW = 3.5%^[3]BW = 4.0%^[3]

1140

1170

1030

760

1030

970

660

340

240

970

870

680

560

360

270

230

200

1000

990

970

880

800

680

560

420

280

330

340

280

210

220

240

800

720

630

690

650

575

500

550

600

570

540

930

740

430

230

180

730

650

480

330

250

210

180

150

740

710

670

560

460

360

260

280

200

205

180

160

250

120

580

490

400

365

330

340

355

330

290

240

250

830

570

350

200

140

590

510

370

260

200

170

150

110

570

520

480

380

290

260

220

210

190

180

170

140

120

110

710

460

280

180

100

480

430

280

230

180

150

110

100

470

420

380

310

240

220

200

180

170

160

140

110

100

610

400

210

160

510

280

130

450

2490

1360

990

430

370

190

200

160

110

100

370

310

250

190

150

820

530

430

250

Note 4

1030

790

410

360

310

270

230

200

190

170

140

130

120

110

370

300

230

220

190

170

140

120

110

1110

830

560

510

470

450

430

Note 4

430

375

320

285

250

245

230

220

210

200

330

285

240

225

210

205

200

190

185

180

250

200

150

170

190

180

175

170

165

160

180

140

100

140

180

170

165

160

155

150

140

Document #: 38-07029 Rev. *F

Page 4 of 12

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FS781/82/84

Table 4. Modulation Rate Divider Ratios

Input Frequency Range (MHz)

Modulation Divider Number

6 to 16

16 to 32

32 to 66

66 to 82

120

240

480

720

quently, higher energy peaks. Regulatory agencies test

electronic equipment by the amount of peak energy radiated

from the equipment. By reducing the peak energy at the funda-

mental and harmonic frequencies, the equipment under test is

able to satisfy agency requirements for EMI. Conventional

methods of reducing EMI have been to use shielding, filtering,

multi-layer PCBs, etc. These FS781/2 and 4 reduce the peak

energy in the clock by increasing the clock bandwidth and

lowering the Q of the clock.

SSCG Modulation Profile

The digital control inputs S0 and S1 determine the modulation

frequency of FS781/2/4 products. The input frequency is

divided by a fixed number, depending on the operating range

that is selected. The modulation frequency of the FS78x can

be determined from Table 4. To compute the modulation

frequency, determine the values of S0 and S1, and find the

modulation divider number in Table 4.

SSCG

Theory of Operation

The FS781/82/84 products use a unique method of modulating

the clock over a very narrow bandwidth and controlled rate of

change, both peak to peak and cycle to cycle. The FS78x

products take a narrow band digital reference clock in the

range of 6–82 MHz and produce a clock that sweeps between

a controlled start and stop frequency and precise rate of

change. To understand what happens to an SSCG clock,

consider that we have a 20-MHz clock with a 50% duty cycle.

From a 20-MHz clock we know the following:

The FS781/82/84 devices are phase-locked loop-(PLL)-type

clock generators using Direct Digital Synthesis (DDS). ‘By

precisely controlling the bandwidth of the output clock, the

FS781/2/4 products become a low-EMI clock generator. The

theory and detailed operation of these products will be

discussed in the following sections.

EMI

All clocks generate unwanted energy in their harmonics.

Conventional digital clocks are square waves with a duty cycle

that is very close to 50%. Because of the 50/50 duty cycle,

digital clocks generate most of their harmonic energy in the

odd harmonics (e.g., third, fifth, seventh). It is possible to

reduce the amount of energy contained in the fundamental

and harmonics by increasing the bandwidth of the funda-

mental clock frequency. Conventional digital clocks have a

very high Q factor, which means that all of the energy at that

frequency is concentrated in a very narrow bandwidth, conse-

Clock Frequency = Fc = 20 MHz.

Clock Period = Tc = 1/20 MHz = 50 ns.

Consider that this 20-MHz clock is applied to the X_INinput of

the FS78x as either an externally driven clock or the result of

a parallel resonant crystal connected to pins 1 and 2 of the

FS78x. Also consider that the products are operating from a

5V DC power supply and the loop filter is set for a total

bandwidth spread of 2%. Refer to Figure 2.

+ .5%

1.0%_Xin

Total

- .5%

TIME (microseconds)

Figure 1. Frequency Profile in Time Domain^[5]

Note:

5. With the correct loop filter connected to Pin 4, the following profile will provide the best EMI reduction. This profile can be seen on a Time Domain Analyzer.

Document #: 38-07029 Rev. *F

Page 5 of 12

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FS781/82/84

50%

Tc = 50 ns.

Figure 2. 20-MHz Unmodulated Clock

From the above parameters, the output clock at FSOUT will be

sweeping symmetrically around a center frequency of 20 MHz.

Tc =49.50 ns.

Tc = 50.50 n

The minimum and maximum extremes of this clock will be

+200 kHz and –200 kHz. So we have a clock that is sweeping

from 19.8 MHz to 20.2 MHz and back again. If we were to look

at this clock on a spectrum analyzer we would see the picture

in Figure 3. Keep in mind that this is a drawing of a perfect

clock with no noise.

Figure 4. Period Comparison Chart

Looking at Figure 3, you will note that the peak amplitude of

the 20-MHz non-modulated clock is higher than the wideband

modulated clock. This difference in peak amplitudes between

modulated and unmodulated clocks is the reason why SSCG

clocks are so effective in digital systems. This figure refers to

the fundamental frequency of a clock. A very important charac-

teristic of the SSCG clock is that the bandwidth of the funda-

mental frequency is multiplied by the harmonic number. In

other words, if the bandwidth of a 20-MHz clock is 200 kHz,

the bandwidth of the third harmonic will be 3 × 200, or 600 kHz.

The amount of bandwidth is relative to the amount of energy

in the clock. Consequently, the wider the bandwidth, the

greater the energy reduction of the clock.

Fc = 20 MHz

Fmin =

Fmax =

19.8 MHz

20.2 MHz

Most applications will not have a problem meeting agency

specifications at the fundamental frequency. It is the higher

harmonics that usually cause the most problems. With an

SSCG clock, the bandwidth and peak energy reduction

increases with the harmonic number. Consider that the

eleventh harmonic of a 20-MHz clock is 220 MHz. With a total

spread of 200 kHz at 20 MHz, the spread at the eleventh

harmonic would be 2.20 MHz, which greatly reduces the peak

energy content. It is typical to see as much as 12- to 18-dB

reduction at the higher harmonics, due to a modulated clock.

Figure 3. Spectrum Analysis of 19.8–20.2 MHz Clock

We see that the original 20-MHz reference clock is at the

center frequency (Cf), and the min. and max. extremes are

positioned symmetrically about the center frequency. This type

of modulation is called Center-Spread. Figure 4 shows a

20-MHz clock as it would be seen on an oscilloscope. The top

trace is the non-modulated reference clock. The bottom trace

is the modulated clock at pin 6. From this comparison chart

you can see that the frequency is decreasing and the period

of each successive clock is increasing. The Tc measurements

on the left and right of the bottom trace indicate the max. and

min. extremes of the clock. Intermediate clock changes are

small and accumulate to achieve the total period deviation.

The reverse of this figure would show the clock going from

minimum extreme back to the high extreme.

The difference in the peak energy of the modulated clock and

the non-modulated clock in typical applications will see a

2 – 3 dB reduction at the fundamental and as much as 8 – 10

dB reduction at the intermediate harmonics: third, fifth,

seventh, etc. At the higher harmonics, it is quite possible to

reduce the peak harmonic energy, compared to the unmodu-

lated clock, by as much as 12 to 18 dB.

Application Notes and Schematic

Figure 5 is configured for the following parameters:

Package selected = FS781.

X_IN= 20-MHz crystal

FSOUT = 20 MHz (S0 = 1 and S1 = 0).

Bandwidth of the FSOUT clock is determined by the values of

the loop filter connected to pin 4.

Document #: 38-07029 Rev. *F

Page 6 of 12

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FS781/82/84

Crystal is 20 MHz is 1st Order

with 18 pF load capacitance.

VDD

Xin

VDD

20 MHz

If Crystal load capacitance is

different than 18 pF, C1 and C2

must be re-calculated.

0.1 uF

27 pF

Xout

For third overtone crystals, a

parallel or series resonant trap

is required.

FS781

(SOIC)

27 pF

FSOUT

VSS

Mount loop filter components as

close to LF pin as possible.

** Occasionally, C8 is used to

create a second pole for this loop

filter. Refer to Loop Filter Selection

table.

Figure 5. FS781 Schematic

Document #: 38-07029 Rev. *F

Page 7 of 12

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FS781/82/84

Absolute Maximum Ratings^[6]

This device contains circuitry to protect the input against

damage due to high static voltages or electric fields; however,

precautions should be taken to avoid application of any

voltage higher than the absolute maximum rated voltages to

this circuit. For proper operation, V_INand V_OUTshould be

constrained to the range, V_SS< (V_INor V_OUT) < V_DD. All digital

inputs are tied high or low internally. Refers to electrical speci-

fications for operating supply range.

Table 5. Absolute Maximum Ratings

Parameter

V_DD

Description

Min.

3.0

–0.3

Max.

6.0

Unit

VDC

°C

Operating Voltage

VIRvss

VORvss

TOP

Input, relative to V_SS

V_DD+ 0.3

+70

Output, relative to V_SS

Temperature, Operating

Temperature, Storage

Temperature, Junction

TST

–65

–

+150

°C

T_J

+125

°C

Table 6. DC Electrical Characteristics V_DD= 3.3V and 5.0V ±10%, X_IN= 48 MHz, T_A= 0°C to 70°C

Parameter

V_IL

Description

Min.

–

Typ.

Max.

Unit

Input Low Voltage

Input High Voltage

Input Low Current

Input High Current

0.3 * V_DD

VDC

µA

V_IH

0.7 * V_DD

I_IL

100

0.4

I_IH

µA

V_OL

V_OH

V_OL

V_OH

Rpd

Rpu

C_xin

C_xout

I_CC

Output Low Voltage I_OL= 10 mA, V_DD= 5V

Output High Voltage I_OH= 10 mA, V_DD= 5V

Output Low Voltage I_OL= 6 mA, V_DD= 3.3V

Output High Voltage I_OH= 5 mA, V_DD= 3.3V

Resistor, Pull-down (Pin 7)

VDC

Ω

V_DD– 1.0

0.4

2.4

60K

125K

200K

Resistor, Pull-up (Pin 3)

Ω

Input Capacitance (Pin 1)

Output Capacitance (Pin 2)

5V Dynamic Supply Current (CL = No Load)

3.3V Dynamic Supply Current (CL = No Load)

Short Circuit Current (FSOUT)

BW% Variations, 3.30V^[7]

BW% Variations, 5.00V^[7]

I_CC

ISC

–20

–30

+20

+30

Table 7. Timing Electrical Characteristics V_DD= 3.3V and 5.0V ±10%, T_A= 0°C to 70°C, C_L= 15 pF, X_IN= 48 MHz

Parameter

tTLH

Description

Min.

1.8

1.5

0.5

2.1

1.7

0.7

0.6

Typ.

2.2

Max.

2.7

2.5

0.8

3.2

2.6

1.2

1.1

Unit

Output Rise Time Measured at 10%–90% @ 5 VDC

Output Fall Time Measured at 10%–90% @ 5 VDC

Output Rise Time Measured at 0.8V–2.0V @ 5 VDC

Output Fall Time Measured at 0.8V–2.0 V @ 5 VDC

Output Rise Time Measured at 10%–90% @ 3.3 VDC

Output Fall Time Measured at 10%–90% @ 3.3 VDC

Output Rise Time Measured at 0.8V–2.0V @ 3.3 VDC

Output Fall Time Measured at 0.8V–2.0 V @ 3.3 VDC

Output Duty Cycle

tTHL

2.0

tTLH

0.65

2.65

2.1

tTHL

tTLH

tTHL

tTLH

0.95

0.85

tTHL

TsymF1

Notes:

6. Single Power Supply: The Voltage on any input or /O pin cannot exceed the power pin during power-up.

7. Percentage variations from the bandwidth % values given in Table 2 and Table 3.

Document #: 38-07029 Rev. *F

Page 8 of 12

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FS781/82/84

Table 7. Timing Electrical Characteristics V_DD= 3.3V and 5.0V ±10%, T_A= 0°C to 70°C, C_L= 15 pF, X_IN= 48 MHz (continued)

Parameter

CCJ

Description

Min.

Typ.

320

310

270

390

Max.

370

360

325

440

Unit

FSOUT, Cycle-to-Cycle Jitter, 48 MHz @ 3.30 VDC (Pin 6)

FSOUT, Cycle-to-Cycle Jitter, 48 MHz @ 5.0 VDC (Pin 6)

FSOUT, Cycle-to-Cycle Jitter, 72 MHz @ 3.30 VDC (Pin 6)

FSOUT, Cycle-to-Cycle Jitter, 72 MHz @ 5.0 VDC (Pin 6)

–

CCJ

Table 8. Range Selection Table

Fin (MHz)

(pin 2/3)

Modulation

Rate

FS781

FS782

FS784

(pin 3)

(pin 7)

FSOUT (pin 6)

32–64 MHz

64–82 MHz

N/A

6–16

16–32

32–66

66–82

Fin/120

Fin/240

Fin/480

Fin/720

6–16 MHz

12–32 MHz

32–64 MHz

64–82 MHz

N/A

16–32 MHz

32–66 MHz

66–82 MHz

N/A

Ordering Information^[8]

Part Number

IMIFS781BZB

Package Type

Product Flow

8-pin 150-mil SOIC

Commercial, 0 to 70°C

IMIFS781BZBT

IMIFS782BZB

8-pin 150-mil SOIC – Tape and Reel

8-pin 150-mil SOIC

IMIFS782BZBT

IMIFS784BZB

8-pin 150-mil SOIC – Tape and Reel

8-pin 150-mil SOIC

IMIFS784BZBT

IMIFS781BT

8-pin 150-mil SOIC – Tape and Reel

8-pin (4.4 mm body) TSSOP

IMIFS781BTT

8-pin (4.4 mm body) TSSOP – Tape and Reel

8-pin (4.4 mm body) TSSOP

IMIFS784BT

IMIFS784BTT

8-pin (4.4 mm body) TSSOP – Tape and Reel

Lead-free

CYIFS781BSXC

CYIFS781BSXCT

CYIFS782BSXC

CYIFS782BSXCT

CYIFS784BSXC

CYIFS784BSXCT

CYIFS781BZXC

CYIFS781BZXCT

CYIFS782BZXC

CYIFS782BZXCT

CYIFS784BZXC

8-pin 150-mil SOIC

Commercial, 0 to 70°C

8-pin 150-mil SOIC – Tape and Reel

8-pin 150-mil SOIC

8-pin 150-mil SOIC – Tape and Reel

8-pin 150-mil SOIC

8-pin 150-mil SOIC – Tape and Reel

8-pin (4.4 mm body) TSSOP

8-pin (4.4 mm body) TSSOP – Tape and Reel

8-pin (4.4 mm body) TSSOP

8-pin (4.4 mm body) TSSOP – Tape and Reel

8-pin (4.4 mm body) TSSOP

CYIFS784BZXCT

8-pin (4.4 mm body) TSSOP – Tape and Reel

Note:

8. The ordering part number differs from the marking on the actual device.

Document #: 38-07029 Rev. *F

Page 9 of 12

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FS781/82/84

Marking Example

Cypress

FS781BS

Cypress

FS781BT

Date Code, Lot #

FS781 B S

Package

S = SOIC

T = TSSOP

Revision

Cypress Device Driver

Package Drawing and Dimensions

8-lead (150-Mil) SOIC S8

PIN 1 ID

1. DIMENSIONS IN INCHES[MM] MIN.

MAX.

2. PIN 1 ID IS OPTIONAL,

ROUND ON SINGLE LEADFRAME

RECTANGULAR ON MATRIX LEADFRAME

0.150[3.810]

0.157[3.987]

3. REFERENCE JEDEC MS-012

4. PACKAGE WEIGHT 0.07gms

0.230[5.842]

0.244[6.197]

PART #

S08.15 STANDARD PKG.

SZ08.15 LEAD FREE PKG.

0.189[4.800]

0.196[4.978]

0.010[0.254]

0.016[0.406]

X 45°

SEATING PLANE

0.061[1.549]

0.068[1.727]

0.004[0.102]

0.050[1.270]

BSC

0.0075[0.190]

0.0098[0.249]

0.004[0.102]

0.0098[0.249]

0°~8°

0.016[0.406]

0.035[0.889]

51-85066-*C

0.0138[0.350]

0.0192[0.487]

Document #: 38-07029 Rev. *F

Page 10 of 12

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FS781/82/84

Package Drawing and Dimensions (continued)

8-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z8

PIN 1 ID

DIMENSIONS IN MM[INCHES] MIN.

MAX.

6.25[0.246]

6.50[0.256]

4.30[0.169]

4.50[0.177]

0.65[0.025]

BSC.

0.25[0.010]

BSC

0.19[0.007]

0.30[0.012]

1.10[0.043] MAX.

GAUGE

PLANE

0°-8°

0.076[0.003]

0.85[0.033]

0.95[0.037]

0.50[0.020]

0.70[0.027]

0.05[0.002]

0.15[0.006]

0.09[[0.003]

0.20[0.008]

SEATING

PLANE

2.90[0.114]

3.10[0.122]

51-85093-*A

All product and company names mentioned in this document may be the trademarks of their respective holders.

Document #: 38-07029 Rev. *F

Page 11 of 12

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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FS781/82/84

Document History Page

Document Title: FS781/82/84 Low EMI Spectrum Spread Clock

Document Number: 38-07029

Orig. of

REV.

ECN NO. Issue Date Change

Description of Change

Convert from IMI to Cypress

106948

111654

118355

122679

277189

314274

417662

06/07/01

02/27/02

08/30/02

12/14/02

See ECN

IKA

IKL

Add new marking suffix for SOIC packages. Converted to FrameMaker.

Swap the location of S0 and S1 in tables 2 and 3 in pages 2,3 and 4.

Add power up requirements to operating conditions information.

Added Lead-free Devices

RGL

RBI

RGL

Fixed the Ordering Information to match the DevMaster

Added Maximum Junction Temperature in Absolute Maximum Ratings table

Document #: 38-07029 Rev. *F

Page 12 of 12

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CYIFS781BZXCT [CYPRESS]

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