CYIH1SM1000AA-HHCES [CYPRESS]
Detailed Specification - ICD; 详细规格 - ICD
| 型号： | CYIH1SM1000AA-HHCES |
| 厂家： | 
CYPRESS |
| 描述： | Detailed Specification - ICD |
| 文件： | 总71页 (文件大小：1863K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYIH1SM1000AA-HHCS
Detailed Specification - ICD
1.7 Handling Precautions
1. Introduction
The component is susceptible to damage by electro-static
discharge. Therefore, suitable precautions shall be employed for
protection during all phases of manufacture, testing, packaging,
shipment and any handling. The following guidelines are appli-
cable:
1.1 Scope
This version of the ICD is the version generated after qualifi-
cation campaign closure.
This specification details the ratings, physical, geometrical,
electrical and electro-optical characteristics, test- and
inspection-data for the High Accuracy Star Tracker (HAS)
Version 2 CMOS Active Pixel image Sensor (CMOS APS).
■
Always manipulate the devices in an ESD controlled
environment.
■
Always store the devices in a shielded environment that
protects against ESD damage (at least a non-ESD generating
tray and a metal bag).
The device described in this document is protected by US patent
6,225,670 and others.
1.2 Component Type Variants
■
■
Always wear a wrist strap when handling the devices and use
ESD safe gloves.
A summary of the type variants of the basic CMOS image sensor
is given in Table 1 on page 8. The complete list of detailed speci-
fications for each type variant is given in Table 3 on page 9 for
each type separately.
The HAS2 is classified as class 1A (JEDEC classification -
[AD03]) device for ESD sensitivity.
1.8 Storage Information
All specifications in Table 3 on page 9 are given at 25 ± 3°C,
under nominal clocking and bias conditions. Exceptions are
noted in the 'remarks' field.
The components must be stored in a dust-free and temperature-,
humidity and ESD controlled environment.
■
Devices must always be stored in special ESD-safe trays such
that the glass window is never touched.
1.3 Maximum Rating
The maximum ratings which shall not be exceeded at any time
during use or storage are as scheduled in Table 2 on page 9.
■
■
The trays are closed with EDS-safe rubber bands.
The trays are sealed in an ESD-safe conductive foil in clean
room conditions.
1.4 Physical Dimensions and Geometrical Information
The physical dimensions of the assembled component are
shown in Figure 2 on page 25. The geometrical information in
Figure 4 on page 26 describes the position of the die in the
package.
■
For transport and storage outside a clean room the trays are
packed ina secondESD-savebag that is sealed in clean room.
1.9 Procurement Requirements
1.5 Pin Assignment
The HAS2 image sensor can be procured at Cypress Semicon-
ductor or its distributors, using the following references:
Figure 6 on page 27 contains the pin assignment. The figure
contains a schematic drawing and a pin list. A detailed functional
description of each pin can be found in “Pin List” on page 39.
■
■
Flight sensors: CYIH1SM1000AA-HHCS.
Engineering sensors: CYIH1SM1000AA-HHCES.
1.6 Soldering Instructions
The HAS sensor is subject to the standard European export
regulations for dual use products.
Soldering is restricted to manual soldering only. No wave or
reflow soldering is allowed. For the manual soldering, following
restrictions are applicable:
A Certificate of Conformance will be issued upon request at no
additional charge. The CoC will refer to this Detailed Specifi-
cation.
■
■
Solder 1 pin on each of the 4 sides of the sensor.
Additional screening tests can be done upon request at
additional cost.
Cool down period of min. 1 minute before soldering another pin
on each of the 4 sides.
The following data is by default delivered with FM sensors:
■
Repeat soldering of 1 pin on each side, including a 1 minute
cool down period.
■
■
■
■
■
Sensor calibration data
Temperature calibration data
Certificate of Conformance to this detailed specification
Visual inspection report
Bad pixel map
Cypress Semiconductor Corporation
Document Number: 001-54123 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 18, 2009
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CYIH1SM1000AA-HHCS
2. Ordering Information
Marketing Part Number
CYIH1SM1000AA-HHCS
CYIH1SM1000AA-HHCES
Description
Space qualified (mono version)
Standard Market (mono version)
Package
84 pin JLCC
84 pin JLCC
Production
In production
Nov-09
3. Applicable Documents
The following documents form part of this specification and shall be read in conjunction with it:
Nr. Reference Title
Issue
Date
AD01 ESCC Generic Specification
9020
Charge Coupled Devices, Silicon, Photosensitive 2 Draft F
AD02 Cypress 001-06225[1]
Electro-optical test methods for CMOS image
sensors
E
B
October, 2008
June, 2000
AD03 JESD22-A114-B
Electrostatic Discharge (ESD) Sensitivity Testing
Human Body Model (HBM)
AD04 APS2-FVD-06-003
AD05 Cypress 001-49283
AD06 Cypress 001-49280
Process Identification Document for HAS2
Visual Inspection for FM devices
HAS2 FM Screening
2
1
2
February, 2008
January, 2008
June, 2009
4. Acronyms Used
For the purpose of this specification, the terms, definitions, abbreviations, symbols, and units specified in ESCC basic Specification
21300 shall apply. In addition, the following table contains terms that are specific to CMOS image sensors and are not listed in
ESCC21300
Abbreviation
ADC
Description
Analog to Digital Convertor
Active Pixel Sensor
APS
CDS
Correlated Double Sampling
Differential Non Linearity
Destructive Readout
DNL
DR
DSNU
EPPL
ESD
Dark Signal Non Uniformity
European Preferred Parts List
Electro-Static Discharge
Fixed Pattern Noise
FPN
HAS
High Accuracy Startracker
Integral Non Linearity
INL
MTF
Modulated Transfer Function
Non Destructive Readout
Pixel Response Non Uniformity
To be Confirmed
NDR
PRNU
TBC
TBD
To be Defined
RGA
Residual Gas Analysis
Note
1. This specification will be superseded by the ESCC basic specification 25000 which is currently under development. The current reference is an internal Cypress
procedure which is a confidential document.
Document Number: 001-54123 Rev. *A
Page 2 of 71
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CYIH1SM1000AA-HHCS
Thefollowingformulasareapplicabletoconvert%VsatandmV/s
into e- and e-/s:
tions and the tolerances as indicated in Figure 2 on page 25 and
Figure 3 on page 26.
5.2.3 Weight
FPN[%Vsat]*Vsat
FPN[e−] =
The maximum weight of the components specified herein shall
be as specified in Table 3 on page 9 - Mechanical Specifications,
item 2.
conversion _ gain
Dark
_
signal
[V / s]
Dark _ signal[e − / s] =
5.3 Materials and Finishes
conversion
_
gain
The materials and finishes shall be as specified herein. Where
a definite material is not specified, a material which will enable
the components specified herein to meet the performance
requirements of this specification shall be used.
DSNU[%Vsat]*Vsat
DSNU[e−] =
conversion _ gain
5.3.1 Case
Other definitions:
The case shall be hermetically sealed and have a ceramic body
and a glass window.
Analog Range
ADC Re solution
ConversionGain
ADC Re solution
Type
JLCC-84
Material
Black Alumina
BA-914
ADC Quantization Noise =
Thermal expansion coefficient
Hermeticity
7.6 x 10-6 /K
< 5·10-7 atms.
cm3/s
■
■
■
Conversion gain for HAS: 14.8 µV/e-
Definition for Local measurements: 32 x 32 pixels
Definition for Global measurements: Full pixel array
Thermal resistance
(Junction to case)
3.633 °C/W
5.3.2 Lead material and finish
5. Detailed Information
Lead material
1e Finish
2nd Finish
KOVAR
5.1 Deviations from Generic Specification
Nickel, min 2
Gold, min 1.5
μ
μ
m
Lot acceptance and screening are based on ESCC 9020 issue 2
draft F. section 5.9 on page 5 of this specification describes the
lot acceptance and screening.
m
5.3.3 Window
5.2 Mechanical Requirements
The window material is a BK7G18 glass lid with anti-reflective
coating applied on both sides.
5.2.1 Dimension Check
The optical quality of the glass shall have the following specifi-
cation:
The dimensions of the components specified herein shall be
checked. They shall comply with the specifications and the toler-
ances as indicated in Figure 2 on page 25.
See Table 3 on page 9 - glass window specification
The anti reflective coating shall have a reflection coefficient <
1.3% absolute and < 0.8% on average, over a bandwidth from
440 nm to 1100 nm.
5.2.2 Geometrical Characteristics
The geometrical characteristics of the components specified
herein shall be checked. They shall comply with the specifica-
Document Number: 001-54123 Rev. *A
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CYIH1SM1000AA-HHCS
5.4 Marking
5.4.1 General
The marking Shall consist of a lead identification and traceability information.
5.4.2 Lead Identification
An index to pin 1 shall be located on the top of the package in the position defined in Figure 2 on page 25. The pin numbering is
counter clock-wise, when looking at the top-side of the component.
5.4.3 Traceability Information
Each component shall be marked such that complete traceability can be maintained.
The component shall bear a number that is constituted as follows:
Indication of type. To be replaced
by detail specification number
when this is allocated.
HAS2 - FM
Type variant
000001
Serial number
061006
Production date (YYMMDD)
5.5 Electrical and Electro-optical Measurements
5.6 Burn-in Test
5.5.1 Electrical and Electro-optical Measurements at Reference
Temperature
5.6.1 Parameter Drift Values
The parameter drift values for power burn-in are specified in
Table 7 on page 18 of this specification. Unless otherwise
specified the measurements shall be conducted at a environ-
mental temperature of 22±3°C and under nominal power supply,
bias and timing conditions.
The parameters to be measured to verify the electrical and
electro-optical specifications are scheduled in Table 4 on page
14 and Table 13 on page 24. Unless otherwise specified, the
measurements shall be performed at a environmental temper-
ature of 22±3°C.
The parameter drift values shall not be exceeded. In addition to
these drift value requirements, also the limit values of any
parameter - as indicated in Table 4 on page 14 - shall not be
exceeded.
For all measurements the nominal power supply, bias and
clocking conditions apply. The nominal power supply and bias
conditions are given in Table 14 on page 24, the timing diagrams
in Figure 35 on page 51 and Figure 37 on page 53.
Conditions for high temperature reverse bias burn-in
Remark: The given bias and power supply settings imply that the
devices are measured in "soft- reset" condition.
Not Applicable
5.6.2 Conditions for Power Burn-in
5.5.2 Electrical and Electro-optical measurements at High and
Low Temperature
The conditions for power burn-in shall be as specified in Table
10 on page 21 of this specification
The parameters to be measured to verify the electrical and
electro-optical specifications are scheduled in Table 5 on page
15 and Table 6 on page 16. Unless otherwise specified, the
measurements shall be performed at
5.6.3 Electrical Circuits for High Temperature Reverse Bias
Burn-in
Not Applicable
-40 (-5 +0) °C and at +85 (+5 -0) °C.
5.6.4 Electrical Circuits for Power Burn-in
5.5.3 Circuits for Electrical and Electro-optical Measurements
Circuits to perform the power burn-in test are shown in Figure 48
on page 63 and next ones of this specification.
Circuits for performing the electro-optical tests in Table 4 on page
14 and Table 13 on page 24 are shown in Figure 48 on page 63
to Figure 51 on page 63.
Document Number: 001-54123 Rev. *A
Page 4 of 71
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CYIH1SM1000AA-HHCS
5.7 Environmental and Endurance Tests
5.8 Total Dose Radiation Test
5.7.1 Electrical and Electro-optical Measurements on
Completion of Environmental Test
5.8.1 Application
The total dose radiation test shall be performed in accordance
with the requirements of ESCC Basic specification 22900.
The parameters to be measured on completion of environmental
tests are scheduled in Table 11 on page 21. Unless otherwise
stated, the measurements shall be performed at a environmental
temperature of 22±3°C. Measurements of dark current must be
performed at 22±1°C and the actual environmental temperature
must be reported with the test results.
5.8.2 Parameter Drift Values
The allowable parameter drift values after total dose irradiation
are listed in Table 8 on page 19. The parameters shown are valid
after a total dose of 42KRad and 168h/100°C annealing.
5.7.2 Electrical and Electro-optical Measurements At
Intermediate Point During Endurance Test
5.8.3 Bias conditions
Continuous bias shall be applied during irradiation testing as
shown in Figure 48 on page 63 and next ones of this specifi-
cation.
The parameters to be measured at intermediate points during
endurance test of environmental tests are scheduled in Table 11
on page 21. Unless otherwise stated, the measurements shall
be performed at an environmental temperature of 22±3°C
5.8.4 Electrical and Electro-optical Measurements
The parameters to be measured, prior to, during and on
completion of the irradiation are listed in Table 13 on page 24 of
this specification. Only devices that meet the specification in
Table 4 on page 14 of this specification shall be included in the
test samples.
5.7.3 Electricalandelectro-opticalmeasurementsonCompletion
of Endurance Test
The parameters to be measured on completion of endurance
tests are scheduled in Table 11 on page 21. Unless otherwise
stated, the measurements shall be performed at a environmental
temperature of 22±3°C
5.9 Lot Acceptance and Screening
This paragraph describes the Lot Acceptance Testing (LAT) and
screening on the HAS FM devices. All tests on device level have
to be performed on screened devices (see Table 5.9.6 on page
7).
5.7.4 Conditions for Operating Life Test
The conditions for operating life tests shall be as specified in
Table 10 on page 21 of this specification.
5.7.5 Electrical Circuits for Operating Life Test
5.9.1 Wafer Lot Acceptance
Circuits for performing the operating life test are shown in Figure
48 on page 63 and next ones of this specification.
This is the acceptance of the silicon wafer lot. This has to be
done on every wafer lot that will be used for the assembly of flight
models.
5.7.6 Conditions for High Temperature Storage Test
The temperature to be applied shall be the maximum storage
temperature specified in Table 2 on page 9 of this specification.
Test
Test method
Number of devices
NA
Test condition
NA
Test location
CY
Wafer processing data review PID
SEM
ESCC 21400
4 naked dies
3 devices
NA
Test house
Total dose test
Endurance test
ESCC 22900
42 krad : 1krad/h
2000h at +125 C
ESTEC by CY
Test House
MIL-STD-883
Method 1005
6 devices
Before and after total dose test and endurance test:
5.9.2 Glass Lot Acceptance
Transmission and reflectance curves that are delievered with
each lot shall be compared with the specifications in Table ,
“Glass Lid Specification,” on page 10
■
Electricalmeasurementsbeforeandafterathigh, lowandroom
temperature. Conform Table 4 on page 14 and Table 5 on page
15,Table 6 on page 16 of this specification.
3 glass lid shall be chosen randomly from the lot and will be
measured in detail. All obtained results will be compared with
Figure 5 on page 27.
■
■
Visual inspection before and after
Detailed electro optical measurements before and after
Document Number: 001-54123 Rev. *A
Page 5 of 71
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CYIH1SM1000AA-HHCS
5.9.3 Package lot acceptance
A solderability test is covered in the assembly lot acceptance
tests (Table 5.9.4).
5 packages shall be chosen randomly from the lot and will be
measured in detail. All obtained results will be compared with
Figure 2 on page 25.
5.9.4 Assembly Lot Acceptance
Number of
devices
Test
Test method
Test condition
Test location
Special assembly house in
process control
Assembly House
Bond strength test
MIL-STD-883 method 2011
Review
2
D
D
Assembly House
CY
Assembly House Geometrical
data review
All
Solder ability
MIL-STD883, method 2003
MIL-STD 883, method 2004
ESCC 24800
Test House
3
Terminal strength
Marking permanence
Geometrical measurements
Temperature cycling
PID
All
CY
MIL-STD 883, method 1010
Condition B
50 cycles
Test House
5
4
-55°C/+125°C
Moisture resistance
DPA:
JEDEC Std. Method A101-B
240h at 85°C/85%
Test House
Die shear test
Bond pull test
MIL-STD-883 method 2019
MIL-STD-883 method 2011
N/A
Test House
Test House
All wires
Before and after the following tests are done:
■
■
■
Electrical measurements conform Table 4 on page 14 of this specification
Detailed visual inspection
Fine leak test + Gross leak test
Fine- and gross-leak tests shall be performed using the following methods:
Fine Leak test: MIL-STD-883, Test Method 1014, Condition A
Gross Leak test: MIL-STD-883, Test Method 1014, Condition C
The required leak rate for fine leak testing is 5·10-7 atms. cm3/s
Document Number: 001-54123 Rev. *A
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CYIH1SM1000AA-HHCS
5.9.5 Periodic Testing
Number of
devices
Test
Test method
Test condition
Test location
Mechanical Shock
MIL-STD 883, method 2002
2
B - 5 shocks, 1500g
– 0,5ms – ½ sine,
6 axes
Test House
Mechanical Vibration
MIL-STD 883, method 2007
2
A - 4 cycles, 20g 80
to 2000 Hz, 0,06
inch 20 to 80 Hz,
3 axes
Test House
DPA:
Die shear test
Bond pull test
MIL-STD-883 method 2019
MIL-STD-883 method 2011
N/A
Test House
Test House
2
All wires
Periodic testing is required every 2 years. Before and after the following tests are done:
■
■
■
Electrical measurements conform Table 4 on page 14.
Detailed visual inspection
Fine leak test + Gross leak test
Fine- and gross-leak tests shall be performed using the following methods:
Fine Leak test: MIL-STD-883, Test Method 1014, Condition A
Gross Leak test: MIL-STD-883, Test Method 1014, Condition C
The required leak rate for fine leak testing is 5·10 7 atms. cm3/s
5.9.6 Screening
Number of
Test
Nr.
Test
Test method
001-53958
Test location
devices
condition
1
HCRT Electrical measure-
ments
All
HT +85°C
LT -40°C
CY
RT +25°C
2
3
4
5
6
7
8
Visual inspection
Die placement measurements
XRAY
001-49283 + ICD
All
All
All
All
All
All
All
CY
Cypress internal proc.
ESCC 20900
CY
Test House
Test House
Test House
Test House
Test House
Stabilization bake
Fine leak test
MIL-STD-883 method 1008
MIL-STD-883 method 1014
MIL-STD-883 method 1014
MIL-STD-883 method 1010
48h at 125°C
A
C
Gross leak test
Temperature cycling
B - 10 cycles
-55°C +125°C
9
Biased Burn-in
ICD
All
All
All
All
All
240h at +125°C.
CY
10
11
12
13
Mobile Particle Detection
Fine leak test
MIL-STD-883 method 2020
MIL-STD-883 method 1014
MIL-STD-883 method 1014
001-53958
A
A
C
Test House
Test House
Test House
CY
Gross leak test
HCRT Electrical measure-
ments
HT +85°C
LT -40°C
RT +25°C
14
Final Visual Inspection
001-49283 + ICD
All
CY
Document Number: 001-54123 Rev. *A
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6. Tables and Figures
6.1 Specification Tables
Table 1. Type Variant Summary
HAS2 Type Variants
Engineering samples (HHCES)
Flight model samples (HHCS)
Optical Quality (See “Optical quality - Definitions” on page 70.)
Dead pixels
100
50
150
5
20
20
50
0
Bright pixels in FPN image
Bad pixels in PRNU image
Bad columns
Bad rows
5
0
Bright pixel clusters:
2 adjacent bright pixels
25
10
2
4 or more adjacent bright pixels
DSNU defects @ 22 dec BOL
DSNU defects @ 22 dec EOL
Particle Contamination
0
1200
1500
1000
1250
Fixed particles outside focal plane
Mobile particles > 20um
N/A
0
N/A
0
Fixed particles on focal plane > 20um
Mobile particles > 10um and < 20um
Fixed particles on focal plane > 10um and < 20um
Particles < 10um
0
0
20
10
N/A
N/A
Wafer lot acceptance (section 5.9.1 on page 5)
Glass lot acceptance (section 5.9.2 on page 5)
Assembly lot acceptance (Table 5.9.4 on page 6)
Periodic testing (Table 5.9.5 on page 7)
NO
NO
NO
NO
NO
YES
YES
YES
YES
YES
Screening (Table 5.9.6 on page 7)
Calibration data
Optional
Optional
YES
YES
Visual Inspection + particle mapping
Document Number: 001-54123 Rev. *A
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Table 2. Maximum Ratings
No
1
Characteristic
Min
-0.5
-0.5
Typ
3.3
3.3
Max
+7.0
+5.0
Unit
Remarks
Any supply voltage except VDD_RES
Supply voltage at VDD_RES
V
V
2
3.3V for normal operation; up
to 5V for increased full well
capacity.
3
4
Voltage on any input terminal
Soldering temperature
-0.5
NA
3.3
NA
Vdd +
0.5
V
260
°C
Hand soldering only; See
section 1.6 on page 1 for
soldering instructions
5
6
Operating temperature
Storage temperature
-40
-55
NA
NA
+85
°C
°C
+125
Table 3. Detailed Specification All Type Variants
General Characteristics
No
Characteristic
Image sensor format
Min
Typ
Max
Unit
Remarks
1
N/A
1024x
1024
N/A
pixels
2
3
Pixel size
N/A
N/A
18
12
N/A
N/A
μ
m
ADC resolution
bit
10 bit accuracy at 5 Msamples
/ sec
Silicon Particle Contamination Specification
No
Characteristic
Optical quality:
Particle max size
Min
Typ
Max
Unit
Remarks
1
N/A
N/A
20
um
See “Type Variant Summary”
on page 8
Mechanical Specifications
No
Characteristic
Min
Typ
Max
Unit
Remarks
1a
Flatness of image area
NA
7.4
NA
μ
m
Peak-to-peak at 25 ± 3 °C
Specified by the foundry over
an entire 8” wafer
1b
2
Flatness of glass lid
Mass
NA
7.7
3.2
NA
NA
90
7.85
3.3
150
8.0
3.4
0.1
0.1
μ
m
Towards ceramic package
g
3
Total thickness
mm
mm
mm
mm
Package + epoxy + glass lid
Die in center of cavity
4a
4b
5
Die position, X offset
Die position, Y offset
NA
NA
Die in center of cavity
Die position, parallelism vs window
Die position, parallelism vs backside
-0.1
0.1
0
0
0.1
0.1
6
7
8
Die position, Y tilt
Die position, X tilt
Die – window distance
-0.1
-0.1
0.25
0
0
0.1
0.1
°
°
0.3
0.35
mm
Document Number: 001-54123 Rev. *A
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CYIH1SM1000AA-HHCS
Glass Lid Specification
No
Characteristic
Min
Typ
Max
Unit
Remarks
1a
XY size
26.7x
26.7
26.8 x
26.8
26.9 x
26.9
mm
1b
2a
2b
Thickness
1.4
440
NA
1.5
NA
1.6
mm
nm
%
Spectral range for optical coating of window
Reflection coefficient for window
1100
<1.3
<0.8
Over bandwidth indicated in
2a
3
Optical quality:
N/A
N/A
Scratch max width
Scratch max number
Dig max size
10
5
60
μ
m
Dig max number
25
Environmental Specification
No
1
Characteristic
Min
-40
-55
Typ
NA
NA
Max
+85
Unit
°C
Remarks
Operating temperature
Storage temperature
2
+125
°C
Lower storage temperatures
(to -80 deg C ) have been
testedandthedevicesurvives
but this is not a fully qualified
temperature.
3
4
Sensor total dose radiation tolerance
sensor SEL threshold with ADC enabled
N/A
NA
42
N/A
krad
(Si)
Tested for functionality up to
300krad, 42 krad is
guaranteed
NA
>110
MeV
cm3
Equivalent LET value
mg-1
Document Number: 001-54123 Rev. *A
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CYIH1SM1000AA-HHCS
Electrical Specification
No
1
Characteristic
Min
16
Typ
18.5
37
Max
21
Unit
mA
mA
Remarks
Total power supply current stand-by
Total power supply current, operational
2
35
40
ADC at 5MHz sampling rate
Measured
3
4
Power supply current to ADC, opera-
tional: analog + digital
17
14
19
21
17
mA
mA
ADC at 5MHz sampling rate
Measured
Power supply current to image core,
operational
15.5
5
6
7
8
Input impedance digital input
Input impedance ADC input
Output amplifier voltage range
Output amplifier gain setting 0
3
NA
NA
2.45
1
NA
NA
2.6
NA
MΩ
MΩ
V
3
2.2
NA
-
Nominal 1
measured reference
9
Output amplifier gain setting 1
Output amplifier gain setting 2
Output amplifier gain setting 3
1.9
3.8
7.2
2.1
4.1
7.7
2.3
4.4
8.2
-
-
-
Nominal 2
relative to setting 0
10
11
Nominal 4
relative to setting 0
Nominal 8
relative to setting 0
12
13
14
15
16
17
18
19
Output amplifier offset setting 0
Output amplifier offset setting 31
Output amplifier offset setting 32
Output amplifier offset setting 63
ADC ladder network resistance
ADC Differential non linearity
ADC Integral non linearity
0.86
1.30
0.43
0.80
NA
0.93
1.35
0.51
0.90
1.8
7
1.0
1.40
0.6
1.0
NA
11
V
V
0 decodes to middle value
V
V
kΩ
lsb
lsb
ns
Typical value
NA
NA
8
18
ADC set-up time
5
NA
NA
Analog_in stable to CLK_ADC
rising
20
ADC hold time
10
NA
NA
ns
Analog_in stable after
CLK_ADC rising edge
21
22
23
24
25
ADC delay time
NA
NA
NA
6.5
20
NA
2.0
NA
2.1
ns
-
ADC latency
Cycles of CLK_ADC
VLOW_ADC to VHIGH_ADC
VDD_RES=3.3V
ADC ideal input range
Saturation voltage output swing
Output range
0.85
1.20
0.8
NA
V
V
V
1.49
NA
Measured with PGA in unity
gain, offset=0.8V, low is dark,
high is bright.
26
Linear range of pixel signal swing
40
50
0.75
NA
ke-
V
Measured within ±1%
27
28
Linear range
60
90
82
NA
NA
ke-
ke-
Measured within ±5%
Full well charge
100
Measured with
VDD_RES=3.3V
29
30
Quantum efficiency x Fillfactor
Spectral response
NA
NA
45
NA
NA
%
%
Measured between 500 nm
and 650 nm. Refer to section
6.3.1 for complete curve.
33.3
Measured average over
400-900nm.
Document Number: 001-54123 Rev. *A
Page 11 of 71
[+] Feedback
CYIH1SM1000AA-HHCS
Electrical Specification
No
31
32
Characteristic
Min
NA
13
Typ
16.9
14.8
Max
NA
Unit
Remarks
Charge to voltage conversion factor
Charge to voltage conversion factor
μ
V/e-
V/e-
At pixel
15.6
μ
Measured at output
SIGNAL_OUT, unity gain
33a
33b
33c
Temporal noise (Soft Reset)
Temporal noise (Hard Reset)
Temporal noise (HTS Reset)
NA
N/A
NA
55
75
65
95
e-
e-
e-
Dark noise, with DR/DS,
internal ADC
125
110
Dark noise, with DR/DS,
internal ADC
Dark noise, with DR/DS,
internal ADC
34a
34b
34c
35
Temporal noise (NDR Soft reset)
Temporal noise (NDR Hard reset)
Temporal noise (NDR HTS reset)
ADC quantization noise
NA
NA
NA
NA
NA
75
75
70
7
100
100
100
NA
e-
e-
e-
e-
e-
36a
Local fixed pattern noise standard
deviation (Hard reset)
110
160
With DR/DS
With DR/DS
With DR/DS
With DR/DS
With DR/DS
With DR/DS
36b
36c
37a
37b
37c
37d
37e
38
Local fixed pattern noise standard
deviation (Soft reset)
NA
NA
NA
NA
NA
14
70
95
140
140
180
140
180
18
e-
e-
e-
e-
e-
e-
e-
Local fixed pattern noise standard
deviation (HTS reset)
Global fixed pattern noise standard
deviation (Hard reset)
115
90
Global fixed pattern noise standard
deviation (Soft reset)
Global fixed pattern noise standard
deviation (HTS reset)
110
15
Global fixed pattern noise standard
deviation (NDR, Soft reset)
With NDR/CDS and external
ADC
Local Column fixed pattern noise
standard deviation (NDR, Soft reset)
14
15
18
With NDR/CDS and external
ADC
Average dark signal
NA
190
400
e-/s
At 25 ± 2 °C die temp, BOL
see “Dark Current vs Temper-
ature Model” on page 33
39
40
Average dark signal
NA
5
5550
5.8
8730
8
e-/s
°C
At 25 ± 2 °C die temp, EOL (25
krad)
Dark signal temperature dependency
Sensor temperature increase
for doubled average dark
current.
41
42
43
44
45
46
Local dark signal non uniformity
standard deviation
NA
N/A
NA
NA
NA
NA
260
275
0.8
400
500
1.0
5
e-/s
e-/s
%
At 25 ± 2 °C die temp, BOL
96% of BOL average
Global dark signal non uniformity
standard deviation
At 25 ± 2 °C die temp, BOL
96% of BOL average
Local photo response non uniformity,
standard deviation
Of average response
Global photo response non uniformity,
standard deviation
1.8
%
Of average response
MTF X direction
0.35
0.35
NA
NA
NA
-
At Nyquist
measured
MTF Y direction
At Nyquist
measured
Document Number: 001-54123 Rev. *A
Page 12 of 71
[+] Feedback
CYIH1SM1000AA-HHCS
Electrical Specification
No
Characteristic
Min
Typ
Max
Unit
Remarks
47
Pixel to pixel crosstalk X direction
NA
9.8
NA
%
Of total source signal – see
section 6.3.6 for 2-D plot
48
Pixel to pixel crosstalk Y direction
NA
9.8
NA
%
Of total Source signal – see
section 6.3.6 for 2-D plot
49
50
51
52
Anti-blooming capability
Pixel rate
200
NA
NA
1000
5
NA
10
Typical
MHz
Temperature sensor transfer curve
-4.64
NA
NA
mV/°C
BOL
BOL
Temperature sensor output signal
range, Min to Max (typical)
800
1700
mV
53
54
55
Temperature sensor linearity
NA
NA
3
NA
NA
mV
mV/°C
NA
BOL
EOL
EOL
Temperature sensor transfer curve
-4.64
NA
Temperature sensor output signal
range, Min to Max (typical)
800
1700
56a
56b
56c
Image lag (Soft reset)
Image lag (Hard reset)
Image lag (HTS reset)
NA
NA
NA
0.54
-0.2
NA
NA
NA
-
-
-
Soft reset
Hard reset
HTS reset
-0.15
Document Number: 001-54123 Rev. *A
Page 13 of 71
[+] Feedback
CYIH1SM1000AA-HHCS
Table 4. Electrical and Electro-optical Measurements at Room Temperature
Electrical and Electro-optical Measurements at Room Temperature 22°C
No.
1
Characteristic
Min
16
Typ
18.5
37
Max
21
Unit
mA
mA
mA
Remarks
Total power supply current stand-by
Total power supply current, operational
2
35
40
ADC at 5MHz sampling rate
ADC at 5MHz sampling rate
3
Power supply current to ADC, opera-
tional
17
19
21
4
Power supply current to image core,
operational
14
15.5
17
mA
5
6
Input impedance digital input
Input impedance ADC input
3
NA
NA
NA
NA
2.45
1
NA
NA
400
1
MΩ
MΩ
W
3
7
Output impedance digital outputs
Output impedance analogue output
Output amplifier voltage range
Output amplifier gain setting 0
NA
NA
2.2
NA
8
kΩ
V
9
2.6
NA
10
-
Nominal 1
measured reference
11
12
13
Output amplifier gain setting 1
Output amplifier gain setting 2
Output amplifier gain setting 3
1.9
3.8
7.2
2.1
4.1
7.7
2.3
4.4
8.2
-
-
-
Nominal 2
relative to setting 0
Nominal 4
relative to setting 0
Nominal 8
relative to setting 0
14
15
16
17
18
19
20
21
Output amplifier offset setting 0
Output amplifier offset setting 31
Output amplifier offset setting 32
Output amplifier offset setting 63
ADC Differential non linearity
ADC Integral non linearity
0.86
1.30
0.43
0.80
N/A
N/A
1.20
0.8
0.93
1.35
0.51
0.90
7
1.0
1.40
0.6
1.0
11
V
V
0 decodes to middle value
V
V
lsb
lsb
V
8
18
Saturation voltage output swing
Output range
1.49
NA
NA
2.1
VDD_RES=3.3V
V
PGAinunitygain, offset=0.8V,
low is dark, high is bright.
22a
22b
22c
Temporal noise (Soft reset)
Temporal noise (Hard reset)
Temporal noise (HTS reset)
NA
NA
NA
55
75
65
95
e-
e-
e-
Dark noise, with DR/DS,
internal ADC
125
110
Dark noise, with DR/DS,
internal ADC
Dark noise, with DR/DS,
internal ADC
23a
23b
23c
24
Temporal noise (NDR Soft reset)
Temporal noise (NDR Hard reset)
Temporal noise (NDR HTS reset)
ADC quantization noise
NA
NA
NA
NA
N/A
75
75
70
7
100
100
100
NA
e-
e-
e-
e-
e-
25a
Local fixed pattern noise standard
deviation (Soft reset)
70
140
With DR/DS
With DR/DS
With DR/DS
25b
25c
Local fixed pattern noise standard
deviation (Hard reset)
NA
NA
110
95
160
140
e-
e-
Local fixed pattern noise standard
deviation (HTS reset)
Document Number: 001-54123 Rev. *A
Page 14 of 71
[+] Feedback
CYIH1SM1000AA-HHCS
Electrical and Electro-optical Measurements at Room Temperature 22°C
No.
Characteristic
Min
Typ
Max
Unit
Remarks
26a
Global fixed pattern noise standard
deviation (Soft reset)
NA
90
140
e-
With DR/DS
26b
26c
Global fixed pattern noise standard
deviation (Hard reset)
NA
NA
115
110
180
180
e-
e-
With DR/DS
With DR/DS
Global fixed pattern noise standard
deviation (HTS reset)
27
28
Average dark signal
NA
NA
190
260
400
400
e-/s
e-/s
At 25 ± 2 °C die temp
At 25 ± 2 °C
Local dark signal non uniformity
standard deviation
29
30
31
Global dark signal non uniformity
standard deviation
NA
NA
NA
275
0.8
1.8
500
1.0
5
e-/s
%
At 25 ± 2 °C
Local photo response non uniformity,
standard deviation
Of average response
Of average response
Global photo response non uniformity,
standard deviation
%
32a
32b
32c
Image lag (Soft reset)
Image lag (Hard reset)
Image lag (HTS reset)
NA
NA
NA
0.54
-0.2
NA
NA
NA
-
-
-
-0.15
Table 5. Electrical and Electro-optical measurements at High Temperature
Electrical and Electro-optical Measurements at High Temperature +85°C
No
1
Characteristic
Min
17
Typ
20
Max
23
Unit
mA
mA
mA
Remarks
Total power supply current stand-by
Total power supply current, operational
2
35
38
41
ADC at 5MHz sampling rate
ADC at 5MHz sampling rate
3
Power supply current to ADC, opera-
tional
17
19
21
4
Power supply current to image core,
operational
14
15.5
17
mA
5
6
Input impedance digital input
Input impedance ADC input
3
NA
NA
NA
NA
2.45
1
NA
NA
400
1
MΩ
MΩ
W
3
7
Output impedance digital outputs
Output impedance analogue output
Output amplifier voltage range
Output amplifier gain setting 0
NA
NA
2.2
NA
8
kΩ
V
9
2.6
NA
10
-
Nominal 1
measured reference
11
12
13
Output amplifier gain setting 1
Output amplifier gain setting 2
Output amplifier gain setting 3
1.9
3.7
7.0
2.1
4.0
7.5
2.3
4.3
8.0
-
-
-
Nominal 2
relative to setting 0
Nominal 4
relative to setting 0
Nominal 8
relative to setting 0
14
15
16
17
18
19
Output amplifier offset setting 0
Output amplifier offset setting 31
Output amplifier offset setting 32
Output amplifier offset setting 63
ADC Differential non linearity
ADC Integral non linearity
0.89
1.30
0.43
0.83
NA
0.94
1.36
0.53
0.93
8
1.0
1.42
0.63
1.03
11
V
V
0 decodes to middle value
V
V
lsb
lsb
NA
10
18
Document Number: 001-54123 Rev. *A
Page 15 of 71
[+] Feedback
CYIH1SM1000AA-HHCS
Electrical and Electro-optical Measurements at High Temperature +85°C
No
20
21
Characteristic
Saturation voltage output swing
Output range
Min
1.20
0.8
Typ
1.52
NA
Max
NA
Unit
V
Remarks
VDD_RES=3.3V
2.1
V
PGAinunitygain, offset=0.8V,
low is dark, high is bright.
22a
22b
22c
23a
23b
23c
24
Temporal noise (Soft reset)
Temporal noise (Hard reset)
Temporal noise (HTS reset)
Temporal noise (NDR Soft reset)
Temporal noise (NDR Hard reset)
Temporal noise (NDR HTS reset)
ADC quantization noise
NA
NA
NA
NA
NA
NA
NA
NA
66
85
73
200
170
65
7
110
125
110
400
300
125
NA
e-
e-
e-
e-
e-
e-
e-
e-
DR/DS
DR/DS
DR/DS
25a
Local fixed pattern noise standard
deviation (Soft reset)
82
160
With DR/DS
25b
25c
26a
26b
26c
Local fixed pattern noise standard
deviation (Hard reset)
NA
NA
NA
NA
NA
95
100
80
160
160
140
160
300
e-
e-
e-
e-
e-
With DR/DS
Local fixed pattern noise standard
deviation (HTS reset)
With DR/DS
Global fixed pattern noise standard
deviation (Soft reset)
With DR/DS
Global fixed pattern noise standard
deviation (Hard reset)
97
With DR/DS
Global fixed pattern noise standard
deviation (HTS reset)
115
With DR/DS
27
28
Average dark signal
NA
NA
41000
2800
60000
4000
e-/s
e-/s
At +85 ± 2 °C die temp
Local dark signal non uniformity
standard deviation
29
30
31
Global dark signal non uniformity
standard deviation
NA
NA
NA
3100
0.74
1.7
4500
1.0
5
e-/s
%
Local photo response non uniformity,
standard deviation
Of average response
Of average response
Global photo response non uniformity,
standard deviation
%
32a
32b
32c
Image lag (Soft reset)
Image lag (Hard reset)
Image lag (HTS reset)
NA
NA
NA
-0.13
-0.09
-0.12
NA
NA
NA
-
-
-
Soft reset
Hard reset
HTS reset
Table 6. Electrical and Electro-optical measurements at Low Temperature
Electrical and Electro-optical Measurements at Low Temperature -40°C
No
1
Characteristic
Min
16
Typ
18
Max
21
Unit
mA
mA
mA
Remarks
Total power supply current stand-by
Total power supply current, operational
2
35
37
40
ADC at 5MHz sampling rate
ADC at 5MHz sampling rate
3
Power supply current to ADC, opera-
tional
17
19
21
4
Power supply current to image core,
operational
14
15.5
17
mA
5
6
7
Input impedance digital input
Input impedance ADC input
Output impedance digital outputs
3
3
NA
NA
NA
NA
NA
MΩ
MΩ
W
NA
400
Document Number: 001-54123 Rev. *A
Page 16 of 71
[+] Feedback
CYIH1SM1000AA-HHCS
Electrical and Electro-optical Measurements at Low Temperature -40°C
No
8
Characteristic
Min
NA
2.2
NA
Typ
NA
2.45
1
Max
1
Unit
kΩ
V
Remarks
Output impedance analogue output
Output amplifier voltage range
Output amplifier gain setting 0
9
2.6
NA
10
-
Nominal 1
measured reference
11
12
13
Output amplifier gain setting 1
Output amplifier gain setting 2
Output amplifier gain setting 3
1.9
3.8
7.2
2.1
4.1
7.7
2.3
4.4
8.2
-
-
-
Nominal 2
relative to setting 0
Nominal 4
relative to setting 0
Nominal 8
relative to setting 0
14
15
16
17
18
19
20
21
Output amplifier offset setting 0
Output amplifier offset setting 31
Output amplifier offset setting 32
Output amplifier offset setting 63
ADC Differential non linearity
ADC Integral non linearity
0.86
1.30
0.43
0.80
N/A
N/A
1.20
0.8
0.93
1.35
0.51
0.90
7
1.0
1.40
0.6
1.0
11
V
V
0 decodes to middle value
V
V
lsb
lsb
V
11
18
Saturation voltage output swing
Output range
1.49
NA
NA
2.1
VDD_RES=3.3V
V
PGAinunitygain,offset=0.8V,
low is dark, high is bright.
22a
22b
22c
23a
23b
23c
24
Temporal noise (Soft reset)
Temporal noise (Hard reset)
Temporal noise (HTS reset)
Temporal noise (NDR Soft reset)
Temporal noise (NDR Hard reset)
Temporal noise (NDR HTS reset)
ADC quantization noise
NA
NA
NA
NA
NA
NA
NA
NA
59
77
70
80
80
75
7
100
125
125
125
125
125
NA
e-
e-
e-
e-
e-
e-
e-
e-
DR/DS
DR/DS
DR/DS
25a
Local fixed pattern noise standard
deviation (Soft reset)
70
140
With DR/DS
With DR/DS
With DR/DS
With DR/DS
With DR/DS
With DR/DS
25b
25c
26a
26b
26c
Local fixed pattern noise standard
deviation (Hard reset)
NA
NA
NA
NA
NA
90
100
70
140
160
140
140
180
e-
e-
e-
e-
e-
Local fixed pattern noise standard
deviation (HTS reset)
Global fixed pattern noise standard
deviation (Soft reset)
Global fixed pattern noise standard
deviation (Hard reset)
95
Global fixed pattern noise standard
deviation (HTS reset)
120
27
28
Average dark signal
NA
NA
3.3
6
10
20
e-/s
e-/s
Local dark signal non uniformity
standard deviation
29
30
31
Global dark signal non uniformity
standard deviation
NA
NA
NA
8
30
1.0
5
e-/s
%
Local photo response non uniformity,
standard deviation
0.8
1.8
Of average response
measured
Global photo response non uniformity,
standard deviation
%
Of average response
measured
Document Number: 001-54123 Rev. *A
Page 17 of 71
[+] Feedback
CYIH1SM1000AA-HHCS
Electrical and Electro-optical Measurements at Low Temperature -40°C
No
32a
32b
32c
Characteristic
Min
NA
NA
NA
Typ
0.6
Max
NA
Unit
Remarks
Soft reset
Image lag
Image lag
Image lag
-
-
-
0.2
NA
Hard reset
-1.2
NA
HTS reset
Table 7. Parameter Drift Values for Burn In
Electrical and Electro-optical Measurements at Room Temperature +22°C
No
1
Characteristic
Typical Value
Max Drift
Unit
mA
Remarks
Total power supply current stand-by
Total power supply current, operational
18.5
37
2
3
2
2
mA
mA
ADC at 5MHz sampling rate
ADC at 5MHz sampling rate
3
Power supply current to ADC, opera-
tional
19
4
Power supply current to image core,
operational
15.5
2
mA
5
6
7
8
Output impedance digital outputs
Output impedance analogue output
Output amplifier voltage range
Output amplifier gain setting 0
NA
NA
2.45
1
20
20
W
W
V
-
0.3
N/A
Nominal 1
measured reference
9
Output amplifier gain setting 1
Output amplifier gain setting 2
Output amplifier gain setting 3
2.1
4.1
7.7
0.2
0.4
0.6
-
-
-
Nominal 2
relative to setting 0
10
11
Nominal 4
relative to setting 0
Nominal 8
relative to setting 0
12
13
14
15
16
17
18
19
Output amplifier offset setting 0
Output amplifier offset setting 31
Output amplifier offset setting 32
Output amplifier offset setting 63
ADC Differential non linearity
ADC Integral non linearity
0.93
1.35
0.51
0.90
7
0.1
0.1
0.1
0.1
2
V
V
0 decodes to middle value
V
V
lsb
lsb
V
8
2
Saturation voltage output swing
Output range
1.49
NA
0.2
0.2
VDD_RES=3.3V
V
PGAinunitygain,offset=0.8V,
low is dark, high is bright.
20a
20b
20c
Temporal noise (Soft reset)
Temporal noise (Hard reset)
Temporal noise (HTS reset)
55
75
65
+15
+15
+15
e-
e-
e-
Dark noise, with DR/DS,
internal ADC
DARK noise, with DR/DS,
internal ADC
Dark noise, with DR/DS,
internal ADC
21a
21b
21c
22
Temporal noise (NDR Soft reset)
Temporal noise (NDR Hard reset)
Temporal noise (NDR HTS reset)
ADC quantisation noise
75
75
70
7
+15
+15
+15
NA
e-
e-
e-
e-
e-
23a
Local fixed pattern noise standard
deviation (Soft reset)
70
+15
With DR/DS
Document Number: 001-54123 Rev. *A
Page 18 of 71
[+] Feedback
CYIH1SM1000AA-HHCS
Electrical and Electro-optical Measurements at Room Temperature +22°C
No
Characteristic
Typical Value
Max Drift
Unit
Remarks
With DR/DS
23b
Local fixed pattern noise standard
deviation (Hard reset)
110
+15
e-
e-
e-
e-
e-
23c
24a
24b
24c
Local fixed pattern noise standard
deviation (HTS reset)
95
90
+30
+15
+15
+50
With DR/DS
With DR/DS
With DR/DS
With DR/DS
Global fixed pattern noise standard
deviation (Soft reset)
Global fixed pattern noise standard
deviation (Hard reset)
115
110
Global fixed pattern noise standard
deviation (HTS reset)
25
26
Average dark signal
190
260
+50
+50
e-/s
e-/s
At 25 ± 2 °C die temp
At 25 ± 2 °C
Local dark signal non uniformity
standard deviation
27
28
29
Global dark signal non uniformity
standard deviation
275
0.8
1.8
+50
+0.1
+0.3
e-/s
%
At 25 ± 2 °C
Local photo response non uniformity,
standard deviation
Of average response
Of average response
Global photo response non uniformity,
standard deviation
%
30a
30b
30c
Image lag (Soft reset)
Image lag (Hard reset)
Image lag (HTS reset)
0.54
-0.2
NA
NA
NA
-
-
-
-0.15
Table 8. Parameter Drift Values for Radiation Testing
Electrical and Electro-optical Measurements at Room Temperature +22°C
No
1
Characteristic
Typical Value
Max Drift
Unit
Remarks
Total power supply current stand-by
Total power supply current, operational
18.5
37
2
3
2
mA
mA
mA
2
ADC at 5MHz sampling rate
ADC at 5MHz sampling rate
3
Power supply current to ADC, opera-
tional
19
4
Power supply current to image core,
operational
15.5
2
mA
5
6
7
8
Output impedance digital outputs
Output impedance analogue output
Output amplifier voltage range
Output amplifier gain setting 0
N/A
N/A
2.45
1
20
20
W
W
V
-
0.2
N/A
Nominal 1
measured reference
9
Output amplifier gain setting 1
Output amplifier gain setting 2
Output amplifier gain setting 3
2.1
4.1
7.7
0.2
0.3
0.5
-
-
-
Nominal 2
relative to setting 0
10
11
Nominal 4
relative to setting 0
Nominal 8
relative to setting 0
12
13
14
15
Output amplifier offset setting 0
Output amplifier offset setting 31
Output amplifier offset setting 32
Output amplifier offset setting 63
0.93
1.35
0.51
0.90
0.1
0.1
0.1
0.1
V
V
V
V
0 decodes to middle value
Document Number: 001-54123 Rev. *A
Page 19 of 71
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CYIH1SM1000AA-HHCS
Electrical and Electro-optical Measurements at Room Temperature +22°C
No
16
17
18
19
Characteristic
ADC Differential non linearity
ADC Integral non linearity
Saturation voltage output swing
Output range
Typical Value
Max Drift
Unit
lsb
lsb
V
Remarks
7
8
1
1
1.49
N/A
0.2
0.2
VDD_RES=3.3V
V
PGA in unity gain, offset=0.8V,
low is dark, high is bright.
20a
20b
20c
Temporal noise (Soft reset)
Temporal noise (Hard reset)
Temporal noise (HTS reset)
55
75
65
+30
+30
+30
e-
e-
e-
Dark noise, with DR/DS,
internal ADC
Dark noise, with DR/DS,
internal ADC
Dark noise, with DR/DS,
internal ADC
21a
21b
21c
22
Temporal noise (NDR Soft reset)
Temporal noise (NDR Hard reset)
Temporal noise (NDR HTS reset)
ADC quantisation noise
75
75
70
7
+40
+40
+40
NA
e-
e-
e-
e-
e-
23a
Local fixed pattern noise standard
deviation (Soft reset)
70
+200
With DR/DS
With DR/DS
With DR/DS
With DR/DS
With DR/DS
With DR/DS
23b
23c
24a
24b
24c
Local fixed pattern noise standard
deviation (Hard reset)
110
95
+100
+100
+200
+100
+100
e-
e-
e-
e-
e-
Local fixed pattern noise standard
deviation (HTS reset)
Global fixed pattern noise standard
deviation (Soft reset)
90
Global fixed pattern noise standard
deviation (Hard reset)
115
110
Global fixed pattern noise standard
deviation (HTS reset)
25
26
Average dark signal
190
260
+6000
+1500
e-/s
e-/s
At 25 ± 2 °C die temp
At 25 ± 2 °C
Local dark signal non uniformity
standard deviation
27
28
29
Global dark signal non uniformity
standard deviation
275
0.8
1.8
+1500
+0.1
e-/s
%
At 25 ± 2 °C
Local photo response non uniformity,
standard deviation
Of average response
Of average response
Global photo response non uniformity,
standard deviation
+0.3
%
30a
30b
30c
Image lag (Soft reset)
Image lag (Hard reset)
Image lag (HTS reset)
0.54
-0.2
NA
NA
NA
-
-
-
-0.15
Table 9. Conditions for High Temperature Reverse Bias Burn-in
No
Characteristics
Symbol
Test condition
Unit
Not applicable
Document Number: 001-54123 Rev. *A
Page 20 of 71
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CYIH1SM1000AA-HHCS
Table 10. Conditions for Power Burn-in and Operating Life Tests
No
1
Characteristics
Ambient temp
Symbol
Tamb
Vdd
Test condition
Unit
°C
125
3.3
2
All power supplies
Bias conditions
V
3
See Figure 48 on page
63 and next ones
4
Clock frequency
10
MHz
Table 11. Electrical and Electro-optical Measurements on Completion of Environmental Tests and at Intermediate Points and
on Completion of Endurance Testing
Electrical and Electro-optical Measurements at Room Temperature +22°C
No
1
Characteristic
Min
16
Typ
18.5
37
Max
21
Unit
mA
mA
Remarks
Total power supply current stand-by
Total power supply current, operational
2
35
40
ADC at 5MHz sampling rate
measured
3
4
Power supply current to ADC, opera-
tional
17
14
19
21
17
mA
mA
at 5MHz
Power supply current to image core,
operational
15.5
5
6
Input impedance digital input
Input impedance ADC input
3
NA
NA
NA
NA
2.45
1
NA
NA
400
1
MΩ
MΩ
W
3
7
Output impedance digital outputs
Output impedance analogue output
Output amplifier voltage range
Output amplifier gain setting 0
NA
NA
2.2
NA
8
kΩ
V
9
2.6
NA
10
-
Nominal 1
measured reference
11
12
13
Output amplifier gain setting 1
Output amplifier gain setting 2
Output amplifier gain setting 3
1.9
3.8
7.2
2.1
4.1
7.7
2.3
4.4
8.2
-
-
-
Nominal 2
relative to setting 0
Nominal 4
relative to setting 0
Nominal 8
relative to setting 0
14
15
16
17
18
19
20
21
Output amplifier offset setting 0
Output amplifier offset setting 31
Output amplifier offset setting 32
Output amplifier offset setting 63
ADC Differential non linearity
ADC Integral non linearity
0.86
1.30
0.43
0.80
NA
0.93
1.35
0.51
0.90
7
1.0
1.40
0.6
1.0
11
V
V
0 decodes to middle value
V
V
lsb
lsb
V
NA
8
18
Saturation voltage output swing
Output range
1.20
0.8
1.49
NA
N/A
2.1
VDD_RES=3.3V
V
PGAinunitygain, offset=0.8V,
low is dark, high is bright.
22a
22b
22c
Temporal noise (Soft reset)
Temporal noise (Hard reset)
Temporal noise (HTS reset)
NA
NA
NA
55
75
65
95
e-
e-
e-
DARK noise, with DR/DS,
internal ADC
125
110
Dark noise, with DR/DS,
internal ADC
Dark noise, with DR/DS,
internal ADC
23a
23b
Temporal noise (NDR Soft reset)
Temporal noise (NDR Hard reset)
NA
NA
75
75
100
100
e-
e-
Document Number: 001-54123 Rev. *A
Page 21 of 71
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CYIH1SM1000AA-HHCS
Electrical and Electro-optical Measurements at Room Temperature +22°C
No
23c
24
Characteristic
Temporal noise (NDR HTS reset)
ADC quantisation noise
Min
NA
NA
NA
Typ
70
7
Max
100
NA
Unit
e-
Remarks
e-
25a
Local fixed pattern noise standard
deviation (Soft reset)
70
140
e-
With DR/DS
25b
25c
26a
26b
26c
Local fixed pattern noise standard
deviation (Hard reset)
NA
NA
NA
NA
NA
110
95
160
140
140
180
180
e-
e-
e-
e-
e-
With DR/DS
With DR/DS
With DR/DS
With DR/DS
With DR/DS
Local fixed pattern noise standard
deviation (HTS reset)
Global fixed pattern noise standard
deviation (Soft reset)
90
Global fixed pattern noise standard
deviation (Hard reset)
115
110
Global fixed pattern noise standard
deviation (HTS reset)
27
28
Average dark signal
NA
NA
190
260
400
400
e-/s
e-/s
At 25 ± 2 °C die temp
At 25 ± 2 °C
Local dark signal non uniformity
standard deviation
29
30
31
Global dark signal non uniformity
standard deviation
NA
NA
NA
275
0.8
1.8
500
1.0
5
e-/s
%
At 25 ± 2 °C
Local photo response non uniformity,
standard deviation
Of average response
Of average response
Global photo response non uniformity,
standard deviation
%
32a
32b
32c
Image lag (Soft reset)
Image lag (Hard reset)
Image lag (HTS reset)
NA
NA
NA
0.54
-0.2
NA
NA
NA
-
-
-
-0.15
Table 12. Electrical and Electro-optical Measurements during and on Completion of Total-dose Irradiation Testing (50krad)
Electrical and Electro-optical Measurements at Room Temperature +22°C
Characteristic
No
Min
Typ
Max
Unit
Remarks
Symbol
1
2
Total power supply current stand-by
16
35
18.5
37
21
40
mA
mA
Total power supply current, opera-
tional
ADC at 5MHz sampling rate
ADC at 5MHz sampling rate
3
4
Power supply current to ADC, opera-
tional
17
14
19
21
17
mA
mA
Power supply current to image core,
operational
15.5
5
6
7
8
Output impedance digital outputs
Output impedance analogue output
Output amplifier voltage range
Output amplifier gain setting 0
NA
NA
2.2
NA
NA
NA
2.45
1
400
1
W
kΩ
V
2.6
NA
-
Nominal 1
measured reference
9
Output amplifier gain setting 1
Output amplifier gain setting 2
1.9
3.8
2.1
4.1
2.3
4.4
-
-
Nominal 2
relative to setting 0
10
Nominal 4
relative to setting 0
Document Number: 001-54123 Rev. *A
Page 22 of 71
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CYIH1SM1000AA-HHCS
Electrical and Electro-optical Measurements at Room Temperature +22°C
Characteristic
No
Min
Typ
Max
Unit
Remarks
Symbol
11
Output amplifier gain setting 3
7.2
7.7
8.2
-
Nominal 8
relative to setting 0
12
13
14
15
16
17
18
19
Output amplifier offset setting 0
Output amplifier offset setting 31
Output amplifier offset setting 32
Output amplifier offset setting 63
ADC Differential non linearity
ADC Integral non linearity
0.86
1.30
0.43
0.80
N/A
N/A
1.20
0.8
0.93
1.35
0.51
0.90
8
1.0
1.40
0.6
1.0
11
V
V
0 decodes to middle value
V
V
lsb
lsb
V
9
18
Saturation voltage output swing
Output range
1.49
N/A
N/A
2.1
VDD_RES=3.3V
V
PGAinunitygain,offset=0.8V,
low is dark, high is bright.
20
21
Temporal noise (Soft reset)
Temporal noise (Hard reset)
Temporal noise (HTS reset)
NA
NA
NA
55
75
65
95
e-
e-
e-
Dark noise, with DR/DS,
internal AD
125
110
Dark noise, with DR/DS,
internal ADC
22a
Dark noise, with DR/DS,
internal ADC
22b
22c
23a
23b
23c
Temporal noise (NDR Soft reset)
Temporal noise (NDR Hard reset)
Temporal noise (NDR HTS reset)
ADC quantization noise
NA
NA
NA
NA
NA
75
75
70
7
100
100
100
NA
e-
e-
e-
e-
e-
Local fixed pattern noise standard
deviation (Soft reset)
70
350
With DR/DS
With DR/DS
With DR/DS
With DR/DS
With DR/DS
With DR/DS
24
Local fixed pattern noise standard
deviation (Hard reset)
NA
NA
NA
NA
NA
110
95
160
200
350
180
200
e-
e-
e-
e-
e-
25a
25b
25c
26a
Local fixed pattern noise standard
deviation (HTS reset)
Global fixed pattern noise standard
deviation (Soft reset)
90
Global fixed pattern noise standard
deviation (Hard reset)
115
110
Global fixed pattern noise standard
deviation (HTS reset)
26b
26c
Average dark signal
NA
NA
5550
260
8730
2000
e-/s
e-/s
At 25 ± 2 °C die temp
At 25 ± 2 °C
Local dark signal non uniformity
standard deviation
27
28
29
Global dark signal non uniformity
standard deviation
NA
NA
NA
275
0.8
1.8
2000
1.0
5
e-/s
%
At 25 ± 2 °C
Local photo response non uniformity,
standard deviation
Of average response
Of average response
Global photo response non uniformity,
standard deviation
%
30
31
Image lag (Soft reset)
Image lag (Hard reset)
Image lag (HTS reset)
NA
NA
NA
0.54
-0.2
NA
NA
NA
-
-
-
32a
-0.15
Document Number: 001-54123 Rev. *A
Page 23 of 71
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CYIH1SM1000AA-HHCS
Table 13. Electro-optical Measurements on the Optical Bench
Characteristic
No
Min
Typ
Max
Unit
Remarks
Symbol
1
Linear range of pixel signal swing
40
50
0.75
NA
ke-
V
Measured within ±1%
2
3
Linear range
60
90
82
NA
NA
ke-
ke-
Measured within ±5%
Full well charge
100
Measured
VDD_RES=3.3V
4
Quantum efficiency x Fillfactor
NA
45
NA
%
Measured between 500 nm
and 650 nm. Refer to “Speci-
fication Figures” on page 25
for complete curve
5
Spectral Response
NA
33.3
-
%
Measured average over
400-900nm.
6
7
Charge to voltage conversion factor
Charge to voltage conversion factor
NA
13
16.9
14.8
-
μ
μ
V/e-
V/e-
at pixel
15.6
Measured at output
SIGNAL_OUT, unity gain
8
9
MTF X direction
NA
NA
NA
0.35
0.35
9.8
NA
NA
NA
-
-
at Nyquist measured
at Nyquist measured
MTF Y direction
10
Pixel to pixel crosstalk X direction
%
of total source signal – see
“Specification Figures” on
page 25 for 2-D plot
11
12
Pixel to pixel crosstalk Y direction
Anti-blooming capability
NA
NA
9.8
NA
NA
%
of total source signal – see
“Specification Figures” on
page 25 for 2-D plot
1000
Ke-
predicted value
Table 14. Typical Power Supply Settings and Sensor Settings
Power Supply Settings
ADC_VLOW
ADC_VHIGH
V_ADC_DIGITAL
V_ADC_ANALOG
VDDD
0.85V
2.0V
3.3V
3.3V
3.3V
VDDA
3.3V
VRES
3.3V for SR / 4.2V for HR
3.3V (for HTS switched to 0.75V)
VPIX
Sensor Settings
Read Out Modes
Integration Time
Gain Setting
Destructive – Non Destructive
195 us
Unity
0
Offset Setting
X Clock Period
100ns
Document Number: 001-54123 Rev. *A
Page 24 of 71
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CYIH1SM1000AA-HHCS
6.2 Specification Figures
Figure 1. 84L JLCC Package
001-07594**
Figure 2. Physical and Geometrical Package Drawings
001-07594**
Document Number: 001-54123 Rev. *A
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CYIH1SM1000AA-HHCS
Figure 3. HAS2 Assembled Device Side View
Figure 4. Die Placement Dimensions
Document Number: 001-54123 Rev. *A
Page 26 of 71
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CYIH1SM1000AA-HHCS
Figure 5. Glass Lid Dimensions
Figure 6. Pin Assignment
Document Number: 001-54123 Rev. *A
Page 27 of 71
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CYIH1SM1000AA-HHCS
Figure 7. HAS2 Physical Layout
6.3 Typical data
6.3.1 Spectral Response
Figure 8. Measured Spectral Response of HAS Rad-hard Pixel. Black Curve indicates Average Spectral Response
0.3
60
%
50 %
40 %
0.25
0.2
30 %
20
%
0.15
0.1
10 %
0.05
0
400
500
600
700
800
900
1000
Wavelength [nm]
Document Number: 001-54123 Rev. *A
Page 28 of 71
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CYIH1SM1000AA-HHCS
Figure 9. Average Measured Spectral Response of HAS Rad-hard Pixel Recalculated to QExFF
50
45
40
35
30
25
20
15
10
5
measured average curve
smoothed trend
0
400
500
600
700
800
900
1000
Wavelength [nm]
6.3.2 Photo-response Curve
Figure 10. Pixel Response Curve: Photo-electrons versus Signal Voltage
1.6
1.4
1.2
1
pix 1
pix 2
pix 3
pix 4
0.8
0.6
0.4
0.2
0
0
20000
40000
60000
80000
100000
120000
140000
Number of electrons
Fit to the linear response curve with the same conversion gain (solid black line). The dashed lines indicate linear response curves
with -5% and +5% conversion gain
A detailed analysis is performed in the range < 4000 e-. The dashed lines corresponds to soft reset. The others to hard reset.
Document Number: 001-54123 Rev. *A
Page 29 of 71
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CYIH1SM1000AA-HHCS
Figure 11. Pixel Response Curve < 4000e-
Figure 12. Measured Response Curves of Two Pixels on Two Devices at different Gain Setting
gain 4 (4.54)
2
gain 2 (2.27)
gain 8 (8.55)
1.5
gain 1 (1)
1
0.5
0
0
20000
40000
60000
80000
100000
120000
Number of electrons [e-]
Document Number: 001-54123 Rev. *A
Page 30 of 71
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CYIH1SM1000AA-HHCS
Table 15. Overview of the Offset at different Gain Settings
Device
Offset
1
6
Average
Average
Gain setting
[V]
[V]
[V]
Offset drift [mV]
1
2
4
8
offset_g1
offset_g2
offset_g4
offset_g8
0.86
0.93
1.02
1.18
0.85
0.91
0.99
1.14
0.86
0.92
1.00
1.16
0
65
149
303
6.3.3 Fixed Pattern Noise
Figure 13 shows a log linear plot of the fixed pattern noise in destructive readout before and after radiation.
Figure 13. Typical FPN Histogram in DR Before and After TID
FPN DR Histogram TID
100000
BOL
4KRad TID
13KRad TID
20KRad TID
41KRad TID
1000 0
1000
10 0
10
1
100
150
200
250
300
350
400
2^12 [DN]
Figure 12 on page 30 shows a log linear plot of the fixed pattern noise in destructive readout before and after a 2000h life test which
can be considered as EOL 41ehavior.
Document Number: 001-54123 Rev. *A
Page 31 of 71
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CYIH1SM1000AA-HHCS
Figure 14. Fpn Histogram in DR before and after 2000h Life Test
DR Histogram BOL - EOL
100000
BOL
EOL
10000
100 0
100
10
1
200
2 20
24 0
26 0
280
3 00
3 20
34 0
2^12 [DN]
Figure 15 shows a log linear plot of the fixed pattern noise in non destructive readout before and after a 2000h life test which can be
considered as EOL 42ehavior.
Figure 15. FPN Histogram in NDR before and after 2000h Life test
NDR Reset Level Histogram BOL - EOL
100000
BOL
EOL
10000
1000
10 0
10
1
0
100
200
300
400
500
600
700
800
900
1000
2^12 [DN]
Document Number: 001-54123 Rev. *A
Page 32 of 71
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CYIH1SM1000AA-HHCS
6.3.4 Dark Current vs Temperature Model
Figure 16. Temperature Dependence of the Dark Current (in e/s) Measured on a Sample
1000000
100000
10000
1000
100
y = 16.336e0.1082x
R2 = 0.9995
Theoretical Curve
10
1
-60
-40
-20
0
20
40
60
80
100
0.1
Temperature [degC]
Following model is consistent with what has been measured for typical values:
T −T0
T −T0
DC = DC0 2ΔT
+ aDC TID 2ΔT
DC ,d1
DC ,d 2
T −T0
T −T0
DCNU = DCNU0 2ΔT
+ aDCNU TID 2ΔT
DCNU ,d1
DCNU ,d 2
with
DC the dark current in e/s
DC0 the dark current at 30 °C and 0 krad = 300 e/s
TID the total ionizing dose (in krad(Si))
T the temperature (in °C)
aDC the slope of the curve at 30 °C = 325 e/s/krad(Si)
Δ
TDC,d1 = 5.8 °C and
ΔTDC,d2 = 7.1 °C
DCNU0 the dark current non-uniformity at 30 °C and 0 krad = 230 e/s
aDCNU the slope of the curve at 30 °C = 33.6 e/s/krad(Si)
Δ
TDCNU,d1 = 9.5 °C and
ΔTDCNU,d2 = 9.5 °C
T0 = 30 °C
Document Number: 001-54123 Rev. *A
Page 33 of 71
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CYIH1SM1000AA-HHCS
Following model is consistent with what has been measured for worst case values:
T −T0
T −T0
DC = DC0 2ΔT
+ aDC TID 2ΔT
for T < T0
for T > T0
for T < T0
for T > T0
DC,d1,L
DC,d2,L
T −T0
T−T0
DC = DC0 2ΔT
+ aDC TID 2ΔT
DC,d1,H
DC ,d 2,H
T −T0
T −T0
DCNU = DCNU0 2ΔT
DCNU = DCNU0 2ΔT
+ aDCNU TID 2ΔT
DCNU ,d1,L
DCNU ,d 2,L
T −T0
T−T0
+ aDCNU TID 2ΔT
DC NU ,d1,H
DC NU ,d 2,H
with
DC the dark current in e/s
DC0 the dark current at 30 °C and 0 krad = 550 e/s
TID the total ionizing dose (in krad(Si))
T the temperature (in °C)
aDC the slope of the curve at 30 °C = 480 e/s/krad(Si)
Δ
Δ
TDC,d1,L = 6.6 °C and
TDC,d1,H = 5 °C and
Δ
Δ
TDC,d2,L = 8 °C for T < T0
TDC,d2,H = 6.5 °C for T > T0
DCNU0 the dark current non-uniformity at 30 °C and 0 krad = 400 e/s
aDCNU the slope of the curve at 30 °C = 45 e/s/krad(Si)
Δ
Δ
TDCNU,d1,L = 10.5 °C and
TDCNU,d1,H = 8.5 °C and
Δ
Δ
TDCNU,d2,L = 10.5 °C for T < T0
TDCNU,d2,H = 8.5 °C for T > T0
T0 = 30 °C
Document Number: 001-54123 Rev. *A
Page 34 of 71
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CYIH1SM1000AA-HHCS
DCNU Distributions
Figure 17 and Figure 18 show the distributions of the dark current in mV/s and e/s respectively for a number of devices and the average
distribution.
Figure 17. Dark Current Distribution (in mV/s) at 25 ºC Ambient Temperature
10000
ext dev 1
ext dev 6
1000
ext dev 10
int dev 1
int dev 6
int dev 10
average
100
10
1
0.1
0.01
0.001
0
20
40
60
80
100
120
140
160
180
200
Dark current [mV/s]
Figure 18. Dark Current Distribution (in e/s) at 25 ºC Ambient Temperature
10000
1000
100
10
ext dev 1
ext dev 6
ext dev 10
int dev 1
int dev 6
int dev 10
average
1
0.1
0.01
0.001
0
2000
4000
6000
8000
10000
12000
Dark current [e/s]
Document Number: 001-54123 Rev. *A
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CYIH1SM1000AA-HHCS
Figure 19 and Figure 20 show the cumulative distributions of the dark current in mV/s and e/s respectively for a number of devices
and the average cumulative distribution.
Figure 19. Cumulative Dark Current Distribution (in mV/s) at 25 ºC Ambient Temperature
100
ext dev 1
ext dev 6
ext dev 10
10
int dev 1
int dev 6
int dev 10
average
1
0.1
0.01
0.001
0.0001
0
20
40
60
80
100
120
140
160
180
200
Dark current [mV/s]
Figure 20. Cumulative Dark Current Distribution (in e/s) at 25 ºC Ambient Temperature
100
ext dev 1
ext dev 6
ext dev 10
10
int dev 1
int dev 6
int dev 10
average
1
0.1
0.01
0.001
0.0001
0
2000
4000
6000
8000
10000
12000
Dark current [e/s]
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CYIH1SM1000AA-HHCS
Figure 21 shows the percentage of pixels versus their normalized dark current for the measurement and for a Gaussian distribution
with the same average value and standard deviation. In the measured distribution, about 1.1-1.2 % of the pixels exhibit a dark current
that exceeds the 3
distribution).
σ
limit that is typically used to exclude pixels from the measurements (about 10 times larger than for Gaussian
Figure 21. Comparison between Measured Distribution and Gaussian Distribution
100
measurement
gaussian distribution
10
1
0.1
0.01
0.001
0.0001
0
1
2
3
4
5
6
7
8
9
10
(dark current - average dark current) / (st. dev. dark current)
Figure 22 shows the DSNU distributions during TID irradiation
Figure 22. DSNU Distributions during TID Irradiation
DSNU distribution during Total Dose Irradiation
and after annealing
10000
1000
100
10
Pre Rad
4Krad
14Krad
20Krad
41Krad
168h HT Annealing
3mnth RT Annealing
Biased
Condit ions
1
0
500
1000
1500
2000
2500
3000
3500
4000
4500
ADU value [0 - 2^12]
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6.3.5 Temperature Sensor
Figure 23. Temperature Sensor Voltage Sensitivity: The solid line indicates a linear fit
with 1.38 V as output voltage at 30 ºC and a slope of -4.64 mV/ºC
1.4
1.38
1.36
1.34
1.32
1.3
5
measurement points
fitted curve
deviation
4
3
2
1
0
1.28
1.26
1.24
1.22
1.2
-1
-2
-3
-4
-5
30
35
40
45
50
55
60
65
70
75
Temperature [C]
6.3.6 Pixel-to-Pixel Cross Talk
Figure 24. Cross talk with central pixel uniformly illuminated with 100 %. Estimation from Knife-edge measurements
0.0
0.2
1.3
0.2
0.0
0.2
1.3
9.8
1.3
0.2
1.3
9.8
49.0
9.8
0.2
1.3
9.8
1.3
0.2
0.0
0.2
1.3
0.2
0.0
1.3
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CYIH1SM1000AA-HHCS
7. Pin Description
7.1 Pin Type Information
The following conventions are used in the pin list.
Pin Types
AI
AO
Analogue Input
Analogue Output
Analogue Bias
Digital Input
AB
DI
DO
VDD
GND
Digital Output
Supply Voltage
Supply Ground
7.2 Power Supply Considerations
It is suggested to use one regulator for all digital supply pins together, one regulator for the sensor core analogue supplies together,
and one regulator for the ADC analogue supply (if used). Analogue ground returns must be of very low impedance, as short-term
peaks of 200mA can be encountered.
The ADC can be disabled by connecting all of its power and ground pins to system ground, leaving all other pins open.
7.3 Pin List
Doubled-up pins have the same pin name, but are indicated with (*). These pins are at the same potential on the chip.
Pin No.
Name
Type
Purpose
Power Supply and Ground Connections
10
33
11
32
8
VDD_DIG (1)
VDD
VDD
GND
GND
VDD
VDD
GND
GND
GND
GND
VDD
VDD
VDD
Logic power, 3.3V
Logic ground
VDD_DIG (2)
GND_DIG (1)
GND_DIG (2)
VDD_ANA (1)
VDD_ANA (2)
GND_ANA (1)
GND_ANA (2)
GND_ANA (3)
GND_ANA (4)
VDD_PIX (1)
VDD_PIX (2)
VDD_RES
Analogue power, 3.3V
Analogue ground
35
9
34
55
73
58
70
74
Pixel array power, 3.3V
Reset power, 3.3V, optionally up to 5V for increased full well
Sensor Biasing
75
52
51
GND_AB
AB
AB
AB
Antiblooming ground, connect to system ground or to a low-impedant
1V source for enhanced anti-blooming
NBIAS_DEC
NBIAS_PGA
Connect with 200kΩ to VDD_ANA, decouple with 100nF to
GND_ANA
Connect with 200kΩ to VDD_ANA, decouple with 100nF to
GND_ANA
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CYIH1SM1000AA-HHCS
Pin No.
50
Name
NBIAS_UNI40
Type
AB
Purpose
Connect with 75kΩ to VDD_ANA, decouple with 100nF to GND_ANA
Connect to GND_ANA
49
NBIAS_LOAD
AB
48
NBIAS_PRECHARGE
AB
Connect with 110kΩ to VDD_ANA, decouple with 100nF to
GND_ANA
47
46
NBIAS_PREBUF
NBIAS_COLUMN
AB
AB
Connect with 200kΩ to VDD_ANA, decouple with 100nF to
GND_ANA
Connect with 110kΩ to VDD_ANA, decouple with 100nF to
GND_ANA
Analog Signal Input and Outputs
31
SIGNAL_OUT
AO
Output of PGA, range ## .. ## V, straight polarity i.e. a low output
voltage corresponds to a dark pixel reading.
Input to PGA input multiplexer.
Input to PGA input multiplexer.
Input to PGA input multiplexer.
Input to PGA input multiplexer.
Reference photodiode
60
59
57
56
54
A_IN1
AI
AI
A_IN2
A_IN3
AI
A_IN4
AI
PHOTODIODE
AO
Logic Control Inputs and Status Outputs
71
A9
DI
Parallel sensor programming interface shared address/data bus,
MSB
69
68
67
66
65
64
63
62
61
A8
A7
A6
A5
A4
A3
A2
A1
A0
DI
DI
DI
DI
DI
DI
DI
DI
DI
Parallel sensor programming interface shared address/data bus,
LSB
72
76
77
78
LD_Y
DI
DI
DI
DI
Load strobe: copy A[9..0] into Y1 start register
Load strobe: copy A[9..0] into X1 start register
Load strobe: copy A[7..0] into parameter register indicated by A[9..8]
Asynchronous reset for internal registers
LD_X
LD_REG
RES_REGn
82
84
36
SYNC_YRD
SYNC_YRST
SYNC_XRD
DI
DI
DI
Initialise Y read shift register (YRD) to position indicated by Y1 start
register
Initialise Y reset shift register (YRST) to position indicated by Y1 start
register
Initialise X read shift register (XRD) to position indicated by X1 start
register
83
1
CLK_YRD
DI
DI
Advance shift register YRD one position
Advance shift register YRST one position
CLK_YRST
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CYIH1SM1000AA-HHCS
Pin No.
Name
Type
Purpose
25
CLK_X
EOS
DI
Advance shift register XRD; note: two clock cycles needed for one
pixel output
53
2
DO
DI
End Of Scan monitor output for YRD,YRST,XRD shift registers,
selected through an internal register
YRST_YRDn
RESET
Enable YRD to address the pixel array when ‘0’;
Enable YRST to address the pixel array when ‘1’
4
DI
Reset the line pointed to by YRST (YRST_YRDn=’1’) or pointed to
by YRD (YRST_YRDn=’0’)
37
3
BLANK
SEL
DI
DI
Assert when in line blanking / non-readout phase
Select for readout the line pointed to by YRST (YRST_YRDn=’1’) or
YRD (YRST_YRDn=’0’)
5
6
PRECHARGE
R
DI
DI
Precharge column bus
Sample the selected line’s levels onto the column amplifier reset level
bus
7
S
DI
DI
Sample the selected line’s levels onto the column amplifier signal
level bus
38
CAL
Calibrate PGA
ADC
30
27
23
22
21
20
19
18
17
16
15
14
13
12
43
42
41
44
IN_ADC
CLK_ADC
DATA_11
DATA_10
DATA_9
DATA_8
DATA_7
DATA_6
DATA_5
DATA_4
DATA_3
DATA_2
DATA_1
DATA_0
SPI_DIN
SPI_LD
AI
Analogue input to ADC
DI
ADC conversion clock, pixel rate, latency is 6.5 cycles
ADC data output, MSB
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DI
ADC data output, LSB
Serial calibration interface data in
Serial calibration interface load strobe
Serial calibration interface bit clock
DI
SPI_CLK
ADC_NBIAS
DI
AB
Connect with 60 kOhm resistor to ADC_PBIAS, decouple with 100nF
to ground
45
39
40
ADC_PBIAS
VLOW_ADC
VHIGH_ADC
AB
AI
Connect with 60 kOhm resistor to ADC_NBIAS, decouple with 100nF
to VDD_ADC_ANA
ADC low threshold reference voltage, connect with 90 Ohm to GND
and 130 Ohm to VHIGH_ADC, decouple with 100nF to ground
AI
ADC high threshold reference voltage, connect with 130 Ohm to
VDD_ANA_ADC, decouple with 100nF to ground
81
80
REF_COMP_LOW
REF_MID
AO
AO
Decouple with 100nF to ground
Decouple with 100nF to ground
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CYIH1SM1000AA-HHCS
Pin No.
79
Name
REF_COMP_HIGH
VDD_ADC_ANA
GND_ADC_ANA
VDD_ADC_DIG
GND_ADC_DIG
Type
AO
Purpose
Decouple with 100nF to ground
29
VDD
GND
VDD
GND
Analogue supply, 3.3V
Analogue ground
Digital supply, 3.3V
Digital ground
28
24
26
7.4 Electrical Characteristics
7.4.1 Multiplexer Inputs
Pin nr.
60
Name
A_IN1
A_IN2
A_IN3
A_IN4
Imput impedance
Capacitive 10pF
Capacitive 10pF
Capacitive 10pF
Capacitive 10pF
Settling Time
100ns
59
100ns
57
100ns
56
100ns
7.4.2 Digital I/O
Figure 25. Simulation results Digital "0" and Digital "1"
DC simulation of different input buffers of HAS2
incertain if input is seen as a high or low signal
3.50E+00
Low signal
3.00E+00
2.50E+00
2.00E+00
1.50E+00
1.00E+00
5.00E-01
0.00E+00
Low signal, but
leackage current
through buffer
High signal, but
leackage current
through buffer
High signal
0.00E+00
5.00E-01
1.00E+00
1.50E+00
2.00E+00
2.50E+00
3.00E+00
3.50E+00
Digital input
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CYIH1SM1000AA-HHCS
7.5 Package Pin Assignment
The HAS sensor is packaged in a 84 pins JLCC84 package with large cavity. The figure below shows the pin configuration.
Figure 26. Pin Configuration
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
75 GND_AB
76 LD_X
EOS
53
52
51
50
49
NBIAS_DEC
NBIAS_PGA
NBIAS_UNI40
NBIAS_LOAD
77 LD_REG
78 RES_REGn
79 REF_COMP_HIGH
80 REF_MID
81 REF_COMP_LOW
82 SYNC_YRD
83 CLK_YRD
84 SYNC_YRST
1 CLK_YRST
2 YRST_YRDn
3 SEL
4 RESET
5 PRECHARGE
6 R
7 S
8 VDD_ANA
9 GND_ANA
10 VDD_DIG
11 GND_DIG
(0,1023)
(1023,1023)
NBIAS_PRECHARGE 48
NBIAS_PREBUF
NBIAS_COLUMN
ADC_PBIAS
ADC_NBIAS
SPI_DIN
SPI_LD
SPI_CLK
VHIGH_ADC
VLOW_ADC
CAL
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Image Core 1024x1024
(0,0)
x- direction
ADC
(1023,0)
BLANK
SYNC_XRD
VDD_ANA
GND_ANA
VDD_DIG
Drivers
Output amplifier
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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CYIH1SM1000AA-HHCS
8. User Manual
8.1 Image Sensor Architecture
Sensor Block Diagram
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8.1.1 Pixel Architecture
A square array contains 1024x1024 three-transistor linearly-integrating pixels of each 18 x 18
reset line, for power, an output select line, and eventually the pixel's output signal
μ
m. Each pixel has a connection for a
Figure 27. Three-transistor Pixe: Transistor-level Diagram (left), and Functional Equivalent (right)
There are three transistors in a pixel. The first one acts as a
switch between the power supply and the photodiode. The
photodiode is equivalent to a capacitor with a light-controlled
current source. The second transistor is a source follower
amplifier, buffering the voltage at the photodiode/capacitor
cathode for connection to the outside world. The third transistor
again is a switch, connecting the output of the buffer amplifier to
an output signal bus.
diode by impinging photons. During this integration the voltage
on the photodiode cathode decreases.
When the select line is asserted the voltage on the capacitor is
connected to the pixel output through the source follower buffer
transistor.
All pixels in a line have their select lines tied together: upon
selection a whole line of pixel output signals is driven onto the
1024 column buses that lead into the column amplifiers for
further processing and complete or partial sequential readout to
the ADC.
Activating the reset line drains the charges present on the pixel's
embedded photodiode capacitor, corresponding to a black, dark,
pre-exposure state, or high voltage. As all pixels on a row (line)
share their reset control lines, the pixels in a row can only be
reset together.
All pixels on a line have their reset lines tied together: the reset
mechanism works on all pixels in a line simultaneously, no
individual or addressed pixel reset (IPR) is possible.
With both reset and select lines disabled the pixel amasses
photo charges on its capacitor, charges generated in the photo-
Figure 28. Signal Lifetime in a Three-transistor Pixel: Reset to black level (high voltage),
Photo Charge Integration (dropping voltage), voltage readout
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8.1.2 Array Coordinate System
Figure 29. Front View of Sensor Die: Package pin 1 is on the left side. The focal plane origin is in the bottom-left corner.
Lines (Y) are scanned down to top, pixels (X) left to right
8.1.3 Line Addressing
The sensor operates line wise: a line of pixels can be selected and reset, and a line of pixels can be selected for readout into the
column amplifier structures. There is no frame reset operation, there is no frame transfer.
Image acquisition is done by sequencing over all lines of interest and applying the required reset and/or readout control to each line
selected.
The sensor array contains two vertical shift registers for line addressing. These registers are one-hot, i.e. they contain a pattern like
"00001000000", at each time pointing to one line of pixels.
Figure 30. Line Addressing Structures: YRD and YRST one-hot shift register pointers
and Y1 programmable start-of-scan register
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In Double Sampling / Destructive readout, one of these registers
is typically dedicated to addressing the lines to read, and the
other is used for addressing the lines to reset as part of the
electronic shutter operation.
8.1.6 Input Signal Multiplexer
An analogue signal multiplexer with six inputs connects a
number of sources to the output buffer.
One input always is connected to the pixel-serial output of the
pixel array.
In Correlated Double Sampling / Non-Destructive Readout, it is
the user's choice whether one or both shift registers will be used.
Four inputs are connected to analogue input pins and are
intended for monitoring voltages in the neighborhood of the
sensor.
Both Y shift registers can be initialized to a position indicated by
an on-chip address register. This address register is written by
the user through the parallel sensor programming interface. With
this programmable initial position windowed readout
(region-of-interest) is possible.
The last multiplexer input is connected to the on-chip temper-
ature sensor.
The multiplexer is controlled by an internal register, written
through the parallel sensor programming interface.
Both registers can be advanced one position at a time under user
control.
8.1.7 Programmable Gain Amplifier (PGA)
8.1.4 Pixel Addressing
A voltage amplifier conditions the output signal of the multiplexer
for conversion by the ADC. Signal gain and offset can be
controlled by a register written through the parallel sensor
programming interface.
Pixels are read from left to right, generating a pixel-sequential
output signal for each line. The pixel addressing is similar to the
line addressing.
Close to the column amplifiers resides a horizontal shift register
for pixel/column addressing. This register is one-hot, i.e. it
contains a pattern like "00001000000", at a time pointing to
exactly one pixel and one column amplifier.
When connected to the pixel array, the PGA also subtracts pixel
black level from pixel signal level when in DS/DR mode.
8.1.8 Parallel Sensor Programming Interface
Line acquisition is done by sequencing over all pixels of interest
and applying each time the required pixel readout and ADC
control signals.
The sensor is controlled via a number of on-chip settings
registers for X and Y addressing, PGA gain and offset, one-off
calibration of the column amplifiers, ...
The X shift register can be initialized to a position indicated by an
on-chip address register. This address register is written by the
user through the parallel sensor programming interface. With this
These registers are written by the user through a parallel bus.
8.1.9 12-bit Analog to Digital Convertor (ADC)
programmable
initial
position
windowed
readout
The on-chip ADC is a 12 bit pipelined convertor. It has a latency
of 6.5 pixel clock cycles, i.e. it samples the input on a rising clock
edge, and outputs the converted signal 6 pixel clock periods
afterwards on the falling edge.
(region-of-interest) is possible. The X register can be advanced
one position under user control. This requires a pixel clock signal
at twice the frequency of the desired pixel rate.
8.1.5 Column Amplifiers
The ADC contains its own SPI serial interface for the optional
upload of calibration settings, enhancing its performance.
At the bottom of each column of pixels sits one column amplifier,
for sampling the addressed pixel's signal and reset levels. These
signals are then locally hold until that particular pixel is sent to
the output channel, in this case PGA, multiplexer, buffer, and
ADC.
The ADC is electrically isolated from the actual sensor core:
when unused it can be left non-powered for lower dissipation,
and without risk for latch-up.
When used, the input voltage range of the ADC is set with a
two-node voltage divider connected to pins VLOW_ADC and
VHIGH_ADC.
The combination of column amplifiers and PGA can perform
Double Sampling: in this case a pixel's signal level is read into
the structures, then the pixel is reset, then the reset level is read
into the structures and subtracted from the previously-stored
signal level, cancelling fixed pattern noise.
The ADC has an accuracy of 10 bit at 5 Mhz operation speed.
8.1.10 Temperature Sensor
In Correlated Double Sampling mode the column amplifiers are
used in bypass mode, and the raw signal level (which can be
either a dark reset level or a post-illumination signal level) is sent
to the output amplifier, and then to the output for storage and
correlated subtraction off-chip. This cancels fixed pattern noise
as well as temporal KTC noise.
A PN-junction type temperature sensor is integrated on the chip.
The temperature-proportional voltage at its output can be routed
to the ADC through one of the six analogue inputs of the multi-
plexer.
The temperature sensor must be calibrated on
device-to-device base. Its nominal response is -4.64 mV/°C .
a
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CYIH1SM1000AA-HHCS
tional to the exposure time, hence the electronic shutter
operation.
8.2 Image Sensor Operation
The following s describe the HAS' two readout mechanisms and
give the detailed timing and control diagrams to implement these
mechanisms.
At line readout the signal levels of the pixels in the addressed
line are copied onto the column amplifiers' signal sample nodes.
Immediately after this the line of pixels is reset, and the pixels'
black levels are copied onto the column amplifiers' reset sample
nodes. This is destructive readout.
8.2.1 Double Sampling - Destructive Readout
In Double Sampling / Destructive Readout (DS/DR) mode the
YRST pointer runs over the frame, top to bottom, each time
resetting the line it addresses. Lagging behind this runs the YRD
pointer, each time reading out the line it addresses. The distance
between the YRD pointer and the YRD pointer is then propor-
The column amplifiers/PGA then subtract the black levels from
the signal levels during sequential pixel out. This is uncorrelated
double sampling, eliminating any static pixel-to-pixel offsets of
the sensor array.
Figure 31. Double Sampling: Pixel signal is read (s), then pixel is reset, then reset level is read (r)
8.2.2 Correlated Double Sampling - Non-Destructive Readout
In Correlated Double Sampling/Non-Destructive Readout (CDS/NDR) mode the YRST or YRD pointer quickly runs over the frame,
top to bottom, resetting each line it addresses. This leaves the pixel array drained of charges, in black or dark state.
Then the YRD or YRST pointer is run over the region of interest of the frame, and of each line addressed the pixels' black levels are
read out and passed on to the ADC. The user stores these black levels in an off-chip frame-sized memory.
Then the system is held idling during the exposure time.
After the exposure time has elapsed, the frame is scanned once more with the YRD or YRST pointer, and each line addressed is read
out again. These signal levels are passed on to the ADC and then to the end user. At the same time, the user retrieves the corre-
sponding black levels from the memory and subtracts them from the signal levels. This is correlated double sampling, eliminating
static offsets as well as kTC noise
Document Number: 001-54123 Rev. *A
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CYIH1SM1000AA-HHCS
Figure 32. Correlated Double Sampling: Pixel is reset, reset level is read and stored (r), pixel is exposed,
signal level is read (s), difference is output
8.2.3 Possible Exposure Times
Windows or regions-of-interest are defined by their top-left and
bottom-right coordinates (X1,Y1)-(X2,Y2). The full frame then
corresponds to (0,0)-(1023,1023). Note that (X1,Y1) is to be
programmed into the sensor, while (X2,Y2) is not: windowed
readout is obtained by pointing the sensor to (X1,Y1), followed
by reading out (Y2-Y1+1) lines of (X2-X1+1) pixels.
The range of exposure times attainable by the HAS is entirely
dependent on the user control strategy, although two obvious
scenarios can be envisaged:
In Destructive Readout/Double Sampling, a typical case would
be a minimal exposure time equal to the line readout time, and
a maximal exposure time equal to the frame time. With
A frame readout sequence consists of a number of line readout
sequences.
1a0m2o4uxn1t0s2to4 9p8iμxels in a frame, 10 frames per second, this
s and 100ms.
A line readout sequence consists of
In Non-Destructive Readout/Correlated Double Sampling it is not
even possible to pinpoint a typical case, as all depends on the
exact reset (R), reset-read (r) and signal-read (s) scheme the
user employs. In the specific case of 10MHz pixel rate rate
operation, 10 windowed frames per second, and 40 windows of
20x20, each receiving the same exposure time, and the whole
FPA reset (R) at the start of the frame, the minimal exposure time
would be 7.3ms, the maximal exposure time 90.2ms. Depending
on window configuration, shorter and longer times are possible,
though.
■
A line select sequence for the YRD and YRST pointer shift
registers, during which a line may be selected for readout and
another line may be selected for reset
■
A line blanking sequence during which the line selected for
readout copies its pixel signals into the column amplifiers, the
column amplifiers are operated, and both lines selected are
optionally reset (the line selected for read can be reset as part
ofthedestructivereadout/doublesamplingoperation;theother
line can be reset as part of the electronic shutter operation).
■
A pixel readout sequence
8.2.4 Timing and Control Sequences
Definitions
A pixel readout sequence consists of
The HAS is a line-scan imager with 1024 horizontal lines (Y)
each of 1024 pixels (X). Pixel coordinates are defined relative to
an origin (X=0,Y=0), and projected onto the user's display view:
the origin (0,0) is in the top-left corner of the displayed image,
lines are scanned top-down, and the pixels in a line are scanned
left to right.
■
■
■
Initialization of the pixel pointer XRD to position X1
A sequencing through the region-of-interest,
While the output amplifier and the ADC are activated and pixel
values are sequentially selected, connected to the PGA, and
converted by the ADC.
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CYIH1SM1000AA-HHCS
Figure 33. Line Selection Timing Diagram
Above timing diagram is valid for CLK_YRD/SYNC_YRD and for CLK_YRST/SYNC_YRST.
Description
SYNC_Y* setup
CLK_Y* high width
CLK_Y* period
Min
Typ
Max
Remarks
t1
t2
t3
t4
t5
50 ns
100 ns
200 ns
No constraint on duty cycle
Address delay
30 ns
Setup to next blanking
100 ns
Destructive Readout Timing Diagram
n this mode the unit of timing is conveniently chosen to equal the time needed to read out a line of pixels. Hence, the exposure time
tEXP can be expressed as an equivalent number of lines.
Table 16. Threads of Operation for Destructive Readout with Double Sampling
Comment
YRD - read side
YRST - reset side
init
Load registers Y1 and X1 with the window start coordinates
Initialize YRD with Y1
Initialise YRST with Y1
expose
read
For YRST = Y1 to Y1+tEXP loop
.select line YRST
.reset line YRST
.wait for one line time
.advance YRST one position
end loop
.do nothing
For YRD = Y1 to Y2 loop
.select line YRD
.operate column amplifiers for DS/DR
.read pixels X1 to X2
.advance YRD
.select line YRST
.reset line YRST
.advance YRST
end loop
Figure 34. DS/DR Sequence: Exposure is initiated with running YRST over the array, resetting lines. After tEXP YRD sTarts
running over the array too, reading and then resetting lines
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Figure 35. Destructive Readout Timing Diagram
Description
BLANK setup
Min
13 ns
10 ns
400 ns
30 ns
Typ
Max
Remarks
t1
t2
25 ns
25 ns
S setup
t3
PRECHARGE width
t4
50 ns
25 ns
t5
S active when SEL
RESET width
2μs
t6
11 ns
400 ns
100 ns
100 ns
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
R active when SEL
2 s
μ
10 ns
100 ns
100 ns
22 ns
25 ns
25 ns
YRST_YRDn setup
YRST_YRDn hold
BLANK hold
Second RESET is optional
BLANK hold
100 ns
25 ns
When no second RESET
Once per frame or per line
CAL delay ref. BLANK
The CAL signal initiates the programmable gain amplifier to a known 'black' state. This initialization should be done at the start of each
frame.
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Non-Destructive Readout Timing Diagram
In describing this mode the unit of timing is conveniently chosen to equal the time needed to read out a line of pixels. Hence, the
exposure time tEXP can be expressed as an equivalent number of lines. (Note however that the user is under no obligation to link
tEXP to the line read time: tEXP can be chosen arbitrarily as its timing and nature are only dependent on the external system controlling
the HAS).
Table 17. Threads of Operation for Non-destructive Readout with Off-chip CDS
Comment
YRD - read side
YRST - reset side
init
Load registers Y1 and X1 with the window start coordinates
initialize YRD with Y1
Initialize YRST with Y1
clear frame
for YRST = 1 to 1023 loop
.select line YRST
.do nothing
.reset line YRST
.advance YRST one position
end loop
read black levels
for YRD = Y1 to Y2 loop
.select line YRD
.operate column amplifiers for CDS/NDR, black levels
.read pixels X1 to X2
.advance YRD
end loop
exposure
wait for time tEXP
read signal levels
for YRD = Y1 to Y2 loop
.select line YRD
.operate column amplifiers for CDS/NDR, signal levels
.read pixels X1 to X2
.advance YRD
end loop
Proper operation can be attained by using just one Y pointer register, YRD or YRST, for all of the frame's phases. The above operation
scheme is just an example, using YRST for the frame reset phase.
Figure 36. CDS/NDR Sequence: First array is reset completely with YRST. Then black levels are read with YRD.
Then, after a time tEXP, all signal levels are read, again with YRD
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Figure 37. Non-destructive Readout Timing Diagram
Description
BLANK setup
Min
Typ
Max
Remarks
t1
t2
13 ns
100 ns
400 ns
13 ns
10 ns
400 ns
30 ns
25 ns
YRST_YRDn s/h
RESET width
Optional, only when YRST is used instead of YRD
t3
t4
BLANK setup
S/R setup
25 ns
25 ns
t5
t6
PRECHARGE width
t7
50 ns
t8
S/R active when SEL
2.4 s
μ
t9
11 ns
11 ns
25 ns
25 ns
t10
t11
t12
SEL hold
BLANK hold
100 ns
25 ns
CAL delay ref.
BLANK
once per frame or per line/window
Figure 38. Pixel Readout Timing Diagram
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The externally applied clock CLK_X runs at twice the pixel rate. From address pointer XRD shift to output signal available exists a
latency of 6 CLK_X cycles. The above timing diagram supposes an ADC sampling at the rising edge of CLK_ADC.
Description
CLK_X period
Min
Typ
Max
Remarks
t1
t2
t3
t4
50 ns
100 ns
50% duty cycle required, +/-2.5 ns
output settle time
output hold time
CAL off setup
15 ns
2 ns
50 ns
BLANK off setup when no CAL
PGA and Signal Multiplexer Control
Figure 39. Programmable Gain Amplifier and Signal Multiplexer Diagram
Figure 40. Amplifier Calibration Timing Diagram
The output of the column amplifiers is a stream of raw or FPN-corrected pixels. These pixels then pass the Programmable Gain
Amplifier, where gain and DC-offset can be adjusted. Then follows a signal multiplexer that selects between the pixel signal or the
temperature sensor and four externally-accessible analogue inputs. The output of the multiplexer is buffered and then made available
at output pad SIGNAL_OUT.
The PGA must be calibrated periodically with a black reference input signal, triggered by CAL. After each change of the gain settings,
the PGA have to be calibrated to set the correct offset on the PGA. It is suggested to make this CAL signal equal to the BLANK signal.
Remark: The BLANK signal resets the X shift register. So after each active BLANK period, there has to be a SYNCING of the x shift
register before reading out any pixel.
For gain and offset control, see section 8.2.5 on page 56.
Description
CAL width
CAL-to-pixel-readout
Min
Typ
Max
Remarks
t1
t2
200 ns
50 ns
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Multiplexer operation:
MODE.PGA[2..0]
Selected input
000
001
010
011
100
101
110
111
pixel array
TEMP
-
-
AIN1
AIN2
AIN3
AIN4
Changing gain during read out
It's possible to change the gain settings during the read out of 1 line. The following procedure is suggested.
For example: gain changing between pixel 56 and 57
■
■
■
■
■
■
■
When pixel 56 comes out, stop the x clock after the falling edge.
The output stays at the same level of this pixel (see Figure 38 on page 53)
Change the gain settings by setting the internal registers as described in section 8.2.5 on page 56
Assert the CAL signal for 200 ns but leave the BLANK signal inactive
After the CAL signal has felled down, wait 50 ns.
Reactivate the X clock starting with the rising edge
The first pixel that comes out is pixel 57
The total time needed to change the gain settings is about 450 ns
Hard Reset - Soft Reset - Hard-to-Soft Reset
See “Reset Modes Timing Controls” on page 61.
Figure 41. ADC Timing Diagram
The ADC is a pipelined device that samples on each rising edge of its clock CLK_ADC. The output DATA is updated on each falling
edge of CLK_ADC. There is an input-to-output latency of 6.5 clock cycles.
Description
input setup
Min
5 ns
Typ
Max
Remarks
t1
t2
t3
t4
t5
input hold
sample clock
Latency
20 ns
100 ns
50% duty cycle required, +/-5%
exact
6.5t3
output delay
10 ns
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8.2.5 Sensor Programming
Parallel Sensor Programming Interface
The operational modes and start-of-window addresses of the HAS are kept in seven on-chip registers. These internal registers are
programmable through a parallel interface similar to the one on the STAR250.
This interface comprises of a 10-bit wide A bus, and 3 load strobes: LD_X, LD_Y, and LD_REG.
With LD_Y or LD_X asserted (rising edge), the full 10 bits of A are loaded into respectively the line start address (Y1) and the column
start address (X1) (as similar to the STAR250).
With a rising edge on LD_REG, the upper two bits of A are decoded as an internal register address, and the 8 lower bits of A are
loaded into the corresponding register. These 4 registers are reset to their default values by asserting RES_REGn.
Address Register Load Timing Diagram
Figure 42. Line/column address upload timing diagram
The YRD/YRST and XRD pointer start address registers Y1 and X1 are latches that pass the input value when LD_Y/LD_X is asserted,
and freeze their output values when LD_Y/LD_X is deasserted
Description
Min
Typ
Max
Remarks
t1
t2
t3
t4
A setup
100 ns
100 ns
75 ns
LD_* width
delay
A hold
100 ns
Figure 43. Mode Registers Upload Timing Diagram
The mode setting registers are edge-triggered flip flops that freeze their outputs at the rising edge of LD_REG.
Description
Min
Typ
Max
Remarks
t1
t2
t3
t4
A setup
100 ns
100 ns
75 ns
LD_REG width
delay
A hold
100 ns
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Internal Registers Global Description
Are registers are programmed using the parallel upload interface. Two styles of register access methods are used.
Address registers loaded with LD_Y or LD_X:
Register
name
Value A[9..0]
Default
Description
Y1
9:0
0
start position of the YRD and YRST one-hot addressing shift registers,
range 0..1023
X1
9:0
0
start position of the XRD one-hot pixel address register, range 0..1023
Mode registers loaded with LD_REG and reset to default with RES_REGn:
Register
Address A[9..8]
Value A[7..0]
Default
Description
End of scan multiplexer
name
MODE
00
6:5
4:2
1
0
0
0
PGA input multiplexer
1 = non destructive readout
0 = destructive readout, dual sampling
0
0
1 = standby
0 = APS in active mode
AMP
01
7:2
1:0
7:0
7:0
0
0
0
0
Amplifier raw offset
Amplifier gain.
BLACK
10
11
NDR mode black level
DR mode column bus offset correction
OFFSET
Internal Registers Detailed Description
X1 Register:
X1
strobe: LD_X
A[9..0] = X1[9..0]
X1[9..0]
start coordinate of XRD shift register for pixel scan
strobe :LD_Y
Y1 Register:
Y1
A[9..0] = Y1[9..0]
Y1[9..0]
start coordinate of YRD and YRST shift registers for line scan
Legal (decimal) values are 0 (first line of the array) to 1023 (last line of the array)
MODE Register:
MODE
A[9..8] = “00”
LD_REG
A[7..0] = “X”&EOS[2..0]&PGA[2..0]&NDR&StandBy
EOS[1..0]
End-Of-Scan indicator selector
00
01
10
11
output of YRD shift pointer register to pin EOS
output of YRST shift pointer register to pin EOS
output of XRD shift pointer register to pin EOS
output of XRD shift pointer register to pin EOS
PGA[2..0]
PGA input multiplexer
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MODE
A[9..8] = “00”
000
LD_REG
pixel array
001
010
011
100
101
110
111
TEMP temperature sensor
-
-
AIN1 analogue telesense input
AIN2
AIN3
AIN4
NDR
Non-Destructive Readout selector
NDR off, DS/DR enabled
0
1
NDR on, CDS/NDR enabled
StandBy
power switch
0
1
sensor operational
sensor in standby / low power
EOS[1..0] connects the output of the last stage of either one of
the internal array=addressing shift register pointers YRD, YRST
or XRD to the outside world at pin EOS.
NDR selects DR or NDR mode.
Standby puts the sensor in a low-power mode, in which the
current mirror bias network drivers of the column structures,
PGA, output buffer, and internal offset DACs are disabled.
PGA[2..0] selects one of 6 possible analogue signals to be
connected to the analogue output pin.
AMP
A[9..8] = “01”
LD_REG
A[7..0] = Offset[5..0]&Gain[1..0]
Offset[5..0]
PGA offset
Gain[1..0]
PGA gain
00
01
10
11
1
2
4
8
This register sets the Programmable Gain Amplifier's output
offset and gain. The PGA output signal offset is controlled in 64
steps of 16 mV each, from 0.3 V to 1.3 V. Output offset control is
used to adapt the PGA's output to the ADC used (internal or
external ADC). See “Other definitions:” on page 3.
The reset value of AMP.Offset is 0, decoding to the middle offset
value of 0.8V. AMP.Offset range 0 to 31 corresponds to levels of
0.8 to 1.3V, while AMP.Offset range 32 to 63 corresponds to
levels of 0.3 to 0.8V.
Gain is controlled in 4 steps for nominal values of 1,2,4, and 8.
Real gain values are expected to be somewhat lower and will be
characterized.
For unity gain and internal ADC use, the recommended default
setting is:
AMP_OFFSET = 60
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BLACK Register:
BLACK
A[9..8] = “10”
LD_REG
A[7..0] = BLACK[7..0]
BLACK[7..0]
NDR mode black level
The BLACK register sets the black level of the column amplifier
structures and column prechargers when used in NDR mode.
2.9V in steps of 10mV. BLACK range 128 to 255 corresponds to
0.4V to 1.65V in steps of 10 mV.
The reset value of BLACK is 0, setting the internal black level to
half-way full scale: BLACK range 0..127 corresponds to 1.65V to
The recommended default setting is:
BLACK = 10
OFFSET Register:
OFFSET
A[9..8] = “11”
LD_REG
A[7..0] = OFFSET[7..0]
OFFSET[7..0]
Column bus offset correction.
The column signal path and later parts of the signal path is split
in an odd bus with amplifiers and an even bus with amplifiers.
As these structures are inherently imperfectly matched in offset,
user calibration of this parameter is required when the sensor is
operated in destructive readout / double sampling mode.
Using the OFFSET register, the offsets for these two signal paths
can be calibrated to obtain a balanced performance.
The default (reset) values for this parameter puts the internal
calibration signal generators in their neutral, middle-value mode.
The reset value of OFFSET is 0, driving the offset generator to
half-scale (0mV) . OFFSET range 0 to 127 corresponds to 0 to
ADC Corrections
+17.5mV in steps of 140
sponds to -17.5mV to 0mV in steps of 137 V.
μ
V. OFFSET ranμge 128 to 255 corre-
Concept
The ADC is a pipelined device with 11 identical conversion
stages in series. Each conversion stage is built around an
amplifier with calibratable gain. Each amplifier's gain can be
tuned individually with an 8 bit code, totaling 11 words of 8 bits
to be loaded into the ADC through a separate serial interface.
Expressed in electrons, this gives the following numbers:
Total offset correction range: 2365 electrons
Step of correction: 9.3 electrons
The recommended default setting is:
ADC Tuning Codes
OFFSET = 0 (sample depended).
Tuning codes each span the range 0 to 255, with value 127
denoting the amplifier's central gain setting (default after
power-on, i.e. without user calibration, and allowing nominal
operation of the device). Code 0 reduces the gain with 5%, tuning
code 255 increases gain with 5%. The code-gain relation is
guaranteed monotonous.
It's recommended to calibrate the device while taking a dark
image.
8.2.6 Sensor Calibration
NDR Mode Black Level
BLACK=10.
ADC Linearity Tuning Method
Column Amplifier Offset Correction
The ideal calibration code is 75 for each stage.
The column amplifier structures comprise of two independent
signal buses, one handling pixels from odd columns, one
handling pixels from even columns.
It is expected that a complete set of calibration values will be
provided in the sensor datasheet, or when necessary, with each
device individually.
ADC Serial Interface
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Description
SPI_CLK width
Min
Typ
Max
Remarks
t1
t2
t3
1000 ns
0 ns
SPI_LD setup
SPI_LD width
1000 ns
All 11 8-bit correction words are uploaded in one burst of 88 bits.
The word for stage 11 first, then stage 10, and so down to stage
1. Within each word the MSB comes first. Bits are sampled on
the rising edge of SPI_CLK, and thus should change on the
falling edge of SPI_CLK. The complete set of words is registered
in the ADC on the rising edge of SPI_LD.
The lower threshold is set to the voltage injected at pin
VLOW_ADC. The upper threshold is set to the voltage injected
at pin VHIGH_ADC. For both settings it is recommended to use
a resistive voltage divider: 90 Ohm from GND_ADC_ANA to
VLOW_ADC, 130 Ohm from VLOW_ADC to VHIGH_ADC, 130
Ohm from VHIGH_ADC to VDD_ADC_ANA.
8.2.7 Sensor Biasing
8.2.8 Temperature Sensor
The operating points of the sensor and ADC's analogue circuitry
are set with external passive components (resistors and capac-
itors). These components have their recommended values listed
in “Detailed Information” on page 3 (pin list).
An internal temperature sensor presents
ature-dependent voltage which can be made available at pin
SIGNAL_OUT through the multiplexer.
a
temper-
The voltage-temperature dependency is approximately -4.64
mV/°C, but the absolute level is to be characterized on a
device-by-device basis for demanding applications.
ADC Input Range Setting
The input voltage range of the ADC (pin ADC_IN) is to be
matched to the signal at hand, in this case the output voltage
range at pin SIGNAL_OUT.
With the on-chip ADC biased for an input window of 0.7 to 1.9 V,
the temperature sensor/ADC combination can be used from -40
to +125 °C.
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8.2.9 Reset Modes Timing Controls
Figure 44. Hard Reset
Figure 45. Soft Reset
Figure 46. Hard to Soft Reset
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8.3 Application and Test Circuits
Figure 47. Sensor Pinning
All ground pins may be connected to 1 point except the anti blooming ground (GNDAB).
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Figure 48. Sensor Biasing Circuits
Figure 49. Sensor Power Supply Decoupling Circuits
Figure 50. Reference Voltages End Circuit
Figure 51. Sencor ADC Circuitry
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The reference voltages can be either injected by a power supply
voltage or can be generated from a resistance divider. See “ADC
Input Range Setting” on page 60.
Until proven otherwise by evaluation testing these devices must
be considered as Class 0 in the HBM ESDS component classifi-
cation. This specification can possibly be widened when the
results of the evaluation test program are known.
8.4 Device handling
8.4.2 Storage Information
8.4.1 Handling Precautions
The components must be stored in a dust-free and temperature-,
humidity and ESD controlled environment.
The component is susceptible to damage by electro-static
discharge. Therefore, suitable precautions shall be employed for
protection during all phases of manufacture, testing, packaging,
shipment and any handling.
The specific storage conditions are mentioned in Table 2 on page
9 of this specification.
9. Frequent Asked Questions
Question:
In my datasheet for the HAS2, the pixel readout timing diagram is lacking some information I need. It appears SYNC_X should change
on the rising edge of CLK_X. And while SYNC_X is high, a rising edge of CLK_X should sync XRD to X1 register. But the diagram
shows SYNC_X high for 2 CLK_X periods. Due to timing variations, SYNC_X could technically be high for as many as 3 different
rising edges of CLK_X! The timing diagram doesn't show any setup or hold timing for SYNC_X and CLK_X.
Answer:
CLK_X is divided internally in the sensor. SYNC_X is based upon this divided clock. When SYNC_X is high for a even pair of this
divided clock cycles the XRD will be pushed the length of this even pair of clock cycles. Though, when SYNC_X drops during an
un-even pair of divided clock cycles it is unclear what XRD will do. But this behavior is most unlikely.
Question:
RES_REGn doesn't have any timing info either. It's the asynchronous reset for internal registers. How long must it be held low?
Answer:
To be on the safe side you have to keep it low for at least 1us.
You can apply the following sequence when powering up the sensor:
■
■
■
Power on device with known register settings
During power on, keep RES_REGn low for at least 1us
Apply Line/column address upload timing diagram
Question:
The ADC serial interface timing diagram is incomplete. It appears the SPI_DATA is supposed to change on the falling edge of
SPI_CLK. If so, then what is the setup and hold times of the SPI_DATA around the rising edge of SPI_CLK? The SPI_CLK has a
period of 1000 ns, so the SPI_DATA would be present for 500 ns prior to the rising edge of SPI_CLK. But what is the SPI_DATA setup
time for the *first* rising edge of SPI_CLK (first bit of data)?
Answer:
The best way to operate the device is to change your SPI data during the falling edge of the SPI clock. This gives you plenty of time
before the data is being sampled on the rising edge of the SPI clock.
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But to answer onto the question. You have to consider a 100ns hold and setup time of the SPI data around the rising edge of the SPI
clock. Theoretically you are right about the 500ns but please consider 100ns for your timing.
For the first rising edge please consider a 500ns setup time for the SPI data.
Question:
I noticed that BLANK remains high for the Destructive readout timing diagram, and even during the reset of YRST row. But in the
Nondestructive readout timing diagram, you have BLANK shown going low between a reset and line selection, but no timing infor-
mation regarding that.
What does the timing need to be? Or can I leave BLANK constantly high during a line reset and subsequent line selection during
Nondestructive readout?
Answer:
For the non destructive read out you can extend T1 and reduce T4. So meaning that you can leave the BLANK signal high.
Question:
What is your recommendation to do with the unused Analog inputs to the multiplexor (A_IN1-4)? Grounding them would place them
at 0 volts which is outside of the VLOW_ADC range. Should they be left floating? Or should they be tied to some constant voltage
source between VHIGH_ADC and VLOW_ADC?
Answer:
If you don't use the analog inputs I propose to ground them. But most of our customers are using these inputs to monitor some supply
voltages. For example, you could monitor your 3.3V input voltage. Of course you have to divide it with a resistance divider to have
the voltage inside the ADC range. You could use it also to monitor some external voltages that are used on your board and which are
important to be stable. Just some idea's…
Question:
What are the implications of turning off the analog power supplies (VDDA), but keeping the digital power supply (VDD) active? Is this
bad? I'm trying to improve the standby low power mode.
Answer:
No this is not bad. In fact the total power supply current will reduce even a little bit more.
Question:
Spec sheet describes the ADC input range setting: 90 Ohm from GND_ADC_ANA to VLOW_ADC, 130 Ohm from VLOW_ADC to
VHIGH_ADC, 130 Ohm from VHIGH_ADC to VDD_ADC_ANA. The VDD_ADC_ANA is 3.3V so this puts VLOW_ADC = 0.85 V and
VHIGH_ADC = 2.07 V.
But Table 14 on page 24 lists typical power supply settings and sensor settings: It says ADC_VLOW = 0.8V and ADC_VHIGH = 2.5V.
Which way do you recommend? Can you describe the discrepancy?
Answer:
The correct ADC range is as you described with the resistance divider. An alternative without resistance divider is to directly inject this
voltage by a power supply circuitry. This how we do it inside our characterization system.
In that way you can tune your ADC settings as you want.
But if you want to stick with the resistances please use the values as described above.
Table 14 on page 24 is a typo. It should be 0.85V and 2.0V
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Question:
In your datasheet, ADC High/Low bias voltages are recommended to be set with a resistive divider. But the datasheet doesn't mention
anything about temperature stability. For the STAR-1000, there was an internal resistor between ADC_HIGH and ADC_LOW that
had temperature dependence. Because of this, for STAR-1000 designs, I used to set my ADC bias voltages with buffers that would
keep the bias levels constant over temperature. Do I need to repeat the same principle for the HAS2? Or does the HAS2 remove
any temperature dependence for the ADC bias voltages?
Answer:
For good temperature stability, it is better the same principle as the STAR-1000. So use external buffers to keep ADC_HIGH and
ADC_LOW to a fixed voltage level
Question:
In your datasheet, in the “ADC Timing Diagram” on page 55, the table lists t5, output delay, as typically 10 ns. The STAR-1000 had
a troublesome output delay variability of 20 - 60 ns, some parts had even 70 ns! Have the digital output drivers been significantly
improved for the HAS2 ADC? What are typical rise/fall times for the outputs?
Answer:
The output delay and stability has been improved compared to STAR-1000
Question:
Could you please discuss the differences between BLANK, CAL, and PRECHARGE? The STAR-1000 only had a CAL signal.
Answer:
The extra BLANK signal is used to reset the internal CLKX divider. PRECHARGE is used to pre-charge the column lines and column
caps to ground
Question:
I liked the flexibility of the STAR-1000. The HAS2 seems more restrictive. For example, your application note says, "…repeated use
of pixel re-addressing (register X1) potentially injects offset-noise into any windows that overlap in Y-coordinates." If I understand
correctly, this means I cannot address each pixel along a line individually? I cannot readout every other pixel, or every 2nd, or 5th,
or 10th? I have to readout all the pixels in a line? Can you think of any options?
Answer:
You still can start reading at any X or Y position. You have only keep in mind that there is an analog pipeline on the pixel data. So if
you individual read 2 pixels of the same line closer together then the analog pipe, the second pixel will be addressed when you are
only interested in the first pixel. So when you want to read that second pixel by a new SyncX, it will be the second time you address it.
As a result, there is a risk of a deviated value. Probably some deviated offset on the pixel value. You have probably the same problem
with STAR-1000 but maybe the analog pipe is there smaller.
Question:
For NDR/CDS mode, there is parasitic exposure given your suggested algorithm. Can I do this algorithm instead?
a. Reset Row X
i. Start integration timer
b. Readout Row X
c. Reset Row X+1
d. Readout Row X+1
e. Reset Row X+2
f. Readout Row X+2
g. (repeat to region of interest)
h. (wait for integration timer completion)
i. Readout Row X
j. (wait for time to reset a row)
k. Readout Row X+1
l. (wait for time to reset a row)
m.Readout Row X+2
n. (wait for time to reset a row)
o. (repeat to region of interest)
Answer:
I don't see a problem with your algorithm
Document Number: 001-54123 Rev. *A
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CYIH1SM1000AA-HHCS
Question:
I would be interested to get more insight about the HAS anti-blooming capability. In our target application, we must be able to operate
with the sun in our field of view. From initial calculations, this means that we can have a sun spot on the sensor around 50 pxls in
diameter, over-exposed by a factor of ~1000 against our other target spots.My questions are :
■
■
■
What is the role of the anti-blooming ground pin (GND_AB) and how does it impact the sensor behavior?
Is the anti-blooming capability sufficient to prevent any additional "recovery" time of the sensor?
What pixel to pixel crosstalk behavior can we expect around the sun spot? 9.8% of the full well ( Table 13 on page 24), or ...
Answer:
When a pixel is saturated and even goes to negative voltage levels, it isn't anymore suitable for lower electro potential level to attract
new photon-electrons. So the extra photo-electrons can now more easily go to nearby pixels instead of to the pixel where the electrons
are generated. This is visible in the image as blooming.
The anti-blooming method is keeping the photo-diode at an attractive electro-potential that still attract new electrons. This can be done
by holding the gate of the reset transistor higher then ground level.
The 'row_select' line thats selects a specific row of the pixel array is a digital signal that swaps between 'GND_DIG' and 'VDD_DIG'.
The 'row_reset' line that resets a specific row of pixels uses the same drivers as the 'row_select' line but the lower voltage level isn't
'GND_DIG' but 'GND_AB'.
So the lower level of gate of the pixel reset transistor can be set by adapting the voltage level of 'GND_AB'.
It is suggested to not go higher with the voltage level of 'GND_AB' than 1V. The digital circuits of the sensor should still see it as a
digital '0'.
Some second order effect of keeping GND_AB higher then ground:
■
The swing of row_reset is now lower. This means less cross-talk to the photo-diode and higher dark-level. Probably you don't see
much changes if you read the sensor in dual sampling. Both the signal and the dark reference changes in level, so the subtraction
is still the same. But you use the photo-diode on a slightly higher voltage level. Therefore, the pixel cap can be a little lower. (Non
linear behavior of the cap of a diode).
■
The swing of the diode is also lowered, but probably only the part of the swing that was not read-out anyway.
It is very difficult to get any quantification of the anti-blooming effect. The best way of figuring is just trying it. The anti-blooming function
is not part of the characterization of the sensor.
Document Number: 001-54123 Rev. *A
Page 67 of 71
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CYIH1SM1000AA-HHCS
Question:
I am trying to estimate the pulse height distribution (PHD) from electrons and protons traversing the focal plane array. The PHD is the
probability of seeing a pulse of a given size in a single pixel from an
electron or proton coming from a random direction and striking in a random location. When an electron traverses a unit cell it excites
electrons. The total amount of charge is proportional to the length of
the path (the chord length) through the unit cell. Charge that is created outside the collection region of the detector has little effect.
The charge in the photodiode is collected and looks like signal. In order to calculate the chord length distribution through the photo-
diode I need its dimensions. I have been assuming that it is 7.5 microns on a side, living within the 15 micron unit cell. The thing I
have no clue
about is the thickness of the collection region. It could be quite thick, but I have been assuming a fairly thin geometry. The production
of streaks by protons is sensitive to the thickness of the photodiode as well (thicker means longer streaks). >So I think the answer to
your question is that I need all three
dimensions of the photodiodes in the array. I would also like to know if the unit cells are simply repeated across the array or if they
are arranged with mirror images next to each other (or something like that) which would make the light sensitive regions cluster in
groups of two or four.
Answer:
Question:
Will pixel-to-pixel crosstalk only appear if a pixel is fully saturated? Or will it also appear if for instance the pixel is only as half it's full
well capacity. If it does happen even if the pixel is not fully saturated do you know to what extent it will happen - will it also be the same
extent as shown in “Pixel-to-Pixel Cross Talk” on page 38 of your datasheet? Will pixel-to-pixel crosstalk only lead to charge leaking
from a pixel with higher signal to a pixel with low signal or vice versa?
Document Number: 001-54123 Rev. *A
Page 68 of 71
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CYIH1SM1000AA-HHCS
Answer:
The pixel-to-pixel crosstalk chown in “Pixel-to-Pixel Cross Talk” on page 38. is cross-talk caused by floating generated electrons that
are not yet captured by any photo-diode. So it has nothing to do with the actual level on the accumulated photo-diodes. Only when
the photo-diode is really totally saturated, the floating electrons can behave differently. The saturated photo-diode cannot capture
more electrons, so incoming electrons are not kept. The generated electrons will be captured by neighboring photo-diodes that are
not yet completely saturated (or recombined).
So cross-talk as measured in “Pixel-to-Pixel Cross Talk” on page 38 goes both from pixel with higher to lower signal levels and vice
versa. It doesn't matter as long they are not fully saturated. Note that the anti-blooming ground can keep the pixel out of a completely
saturation state.
Question:
The test results after proton beam are not as expected. In order to interpret the results we want to know what the thickness is of the
epitaxial layer. Ore more in detail the thickness of the active area of the photo diode.
Answer:
EPI thickness: 5 m, the nwell is about 1um deep.
μ
Question:
How large is the active area compared to the overall pixel?
Almost the whole photo-sensitive area is active area.
Answer:
96% of the whole pixel is active area. Everything expect the transistors and nwell, is p-doped
Question:
Is there a spice model available for the radiation hard pixel used in the HAS device?
Answer:
No. The models that are used are just non-radiation hard models.
Question:
What is the penetration depth of photons in the HAS2 pixel versus the spectral range? Doe we have such graphs available?
Answer:
This is theory. We have penetration versus spectral range but this depends on the actual doping levels of the substrate. So it is never
actual measured.
Question:
How would the MTF behave with increasing wavelength? Is there an MTF graph available versus spectral range?
Answer:
You can expect a large decrease in MTF when using higher wavelengths. To known how it behaves on the HAS2, new MTF measure-
ments are needed.
Question:
In chapter 6.2 of the actual data sheet it is suggested to use one regulator for all digital supply pins together, one regulator for the
sensor core analogue supplies together, and one regulator for the ADC analogue supply. Against it the test circuit in chapter 7.3 uses
5 different supply voltages (VDDD, VDDA, VPIX, VadcA, VadcD).
With the first information I decided to use 3 regulators: One for VDD_ANA + VDD_PIX, one for VDD_DIG + VDD_ADC_DIG and one
only for VDD_ADC_ANA. Moreover I use two grounds (analog and digital). Sadly with this configuration I have some problems in
Window-Mode. Every 2nd line of the first lines of a window overshoot there. The more lines are sampled the lower is that effect. After
may be 20 to 30 lines the effect exists no longer. In an other PCB I use a separate regulator for VDD_PIX instead for VDD_ADC_ANA
(VDD_ADC_ANA is connected to VDD_ANA) and everything works fine. Could that may be the problem or do you have any other
ideas?
Answer:
I expect that the peak currents of VPIX make the power regulator that you use unstable. This is no problem as long the VPIX isn't use
by other parts of the sensor.
So it is normal that when VPIX has its own regulator, nothing strange becomes visible in the image. But probably, VPIX is still not
stable. However, the double sampling (both the signal and the black level are affected by the voltage level of VPIX) hide the problem
for you.
Document Number: 001-54123 Rev. *A
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10. Addenda
AN-APS-FF-WO-06-001 (v1.): Application note on HAS readout methods
11. Optical quality - Definitions
The following definitions and limits are used to define the optical quality of the HAS2 type variants as outlined in Table 1 on page 8 of
Section “Specification Tables” on page 8.
Dead Pixel
A dead pixel is defined as a pixel which has no electrical response. In the image this is resulted in a pixel with fixed ADC value. The
number of pixels with ADC value 0 are count and accumulated.
Bright Pixel in FPN image
A FPN image is defined as a dark image with the shortest possible integration time. A bright pixel in this image is defined as a pixel
with an ADC value higher then 20% of the full range of the entire pixel array.
Bad Pixel in PRNU image
A PRNU image is defined as an image where all pixels have a 50% response of the full range of the entire pixel array. A bad pixel in
this image is defined as a pixel with an ADC value that differs more then 10% of the average response. This average reponse can be
calculated on the total pixel array for a global measurement or on 32x32 pixels for a local measurement.
Bad Row/Column
A bad row/column is detected in the PRNU image. A row / column is defective when it differs more then 5% from the average of a
moving window of 32 rows/columns. A row/column is also defined as defective when it has 100 or more adjacent bad, bright or dead
pixels.
Document Number: 001-54123 Rev. *A
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Document History Page
Document Title: CYIH1SM1000AA-HHCS Detailed Specification - ICD
Document Number: 001-54123
Orig. of Submission
Revision
ECN
Description of Change
Change
Date
**
2725727
2765859
FVD
See ECN Initial Release
*A
NVEA
09/18/09 Updated Ordering Information table
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