CYII4SC014KAA-GTC [CYPRESS]
14Megapixel CMOS Image Sensor; 14Megapixel CMOS图像传感器
| 型号： | CYII4SC014KAA-GTC |
| 厂家： | 
CYPRESS |
| 描述： | 14Megapixel CMOS Image Sensor |
| 文件： | 总27页 (文件大小：1318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYII4SC014KAA-GTC
CYII4SM014KAA-GEC
IBIS4-14000 14Megapixel CMOS Image Sensor
Features
The IBIS4-14000 is a CMOS active pixel image sensor that is
comprised of 14 MegaPixels with 3048 x 4560 active pixels on
an 8m pitch. The sensor has a focal plane array of 36 x 24mm2
and operates in rolling shutter mode. At 15 MHz, 3 fps are
achieved at full resolution. On-chip FPN correction is available
The pixel design is based on the high-fill-factor active pixel
sensor technology of Cypress Semiconductor Corporation
(US patent No. 6,225,670 and others). The sensor is available
in a monochrome version and a Bayer (RGB) patterned color
filter array.
This data sheet allows the user to develop a camera system
based on the described timing and interfacing.
Applications
Table 1. Key Performance Parameters
• Digital photography
• Document scanning
• Biometrics
Parameter
Active Pixels
Typical Value
3048 (H) x 4560 (V)
8 µm x 8 µm
35 mm
Pixel Size
Optical format
Shutter Type
Rolling Shutter
15 MHz
Master Clock
Frame rate
3 fps at full resolution
1256 V.m2/W.s
65.000 e-
Sensitivity (@ 650 nm)
Full Well Charge
kTC Noise
35 e-
Dark current
223 e-/s
Dynamic Range
Supply Voltage
Power Consumption
Color Filter Array
Packaging
65.4 dB
3.3V
< 176 mW
Mono and RGB
49-pins PGA
Cypress Semiconductor Corporation
Document #: 38-05709 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 8, 2007
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Architecture and Operation
Floor Plan
The basic architecture of the sensor is shown in Figure 1.
Figure 1. Block Diagram of the IBIS4-14000 Image Sensor
pixel array
4560 x 3048 active pixels
Pixel (0,0)
CLK_YL
SYNC_YL
CLK_YR
SYNC_YR
SHS
SHR
3048 column amplifiers
x-shift register
4 parallel
analog
outputs
CLK_X
SYNC_X
The Y shift registers point at a row of the imager array. This
row is selected and/or reset by the row drivers. There are 2 Y
shift registers: one points at the row that is read out and the
second one points at the row to be reset. The second pointer
may lead the first pointer by a specific number of rows. In that
case, the time difference between both pointers is the
integration time. Alternatively, both shift registers can point at
the same row for reset and readout for a faster reset
sequence. When the row is read out, it is also reset in order to
do double sampling for fixed pattern noise reduction.
The pixel array of the IBIS4-14000 consists of 4536 x 3024
active pixels and 24 additional columns and rows, which can
also be addressed (see Figure 2 on page 3). The column
amplifiers read out the pixel information and perform the
double sampling operation. They also multiplex the signals on
the readout buses, which are buffered by the output amplifiers.
The shift registers can be configured for various subsampling
modes. The output amplifiers can be individually powered
down. And some other extra functions are foreseen. These
options are configurable via a serial input port.
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Figure 2. Location of the 24 Additional Columns and Rows, Scan Direction of the Array
24 x 4536 dummy pixels
3024 x 24 dummy pixels
Top of camera
3024 x 4536 active pixels
3048 x 4560 total pixels
------------- SKY --------------
pixel 0,0
4 analog outputs
Pixel Specifications
Architecture
Figure 3. Pixel and Column Structure Schematic
Column
VDD_ARRAY
PC
RESET
M1
SELECT
M2
M3
SHS
SHR
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The pixel is a classic 3-transistor active pixel. The photodiode
is a high-fill-factor n-well/p-substrate diode. Separate power
supplies are foreseen: general power supply for the analog
image core (VDD), power supply for the reset line drivers
(VDDR) and a separate power supply for the pixel itself
(VDDARRAY).
The IBIS4-14000 can also be processed with a Bayer RGB
color pattern. Pixel (0,0) has a green filter and is situated on a
green-red row.
Figure 5 shows the response of the color filter array as
function of the wavelength. Note that this response curve
includes the optical cross talk and the NIR filter of the color
glass lid as well (see “Cover Glass” on page 24 for response
of the color glass lid).
FPN and PRNU
Fixed Pattern Noise correction is done on chip with the
so-called Double Sampling technique. The pixel is readout
and this voltage value is sampled on capacitor SHS. After read
out the pixel is reset again and this value is sampled by SHR.
Both sample and reset values of each pixel are subtracted in
the column amplifiers to subtract FPN. Raw images taken by
the sensor typically feature a residual (local) FPN of 0.11%
RMS of the saturation voltage.
Output Stage
Unity gain buffers are implemented as output amplifiers.
These amplifiers can be directly DC-coupled to the
analog-digital converter or coupled to an external program-
mable gain amplifier.
The (dark reference) offset of the output signal is adjustable
between 1.7V and 3V. The amplifier output signal is negative
going with increasing light levels, with a max. amplitude of
1.2V (at 4V reset voltage, in hard reset mode). The output
signal range of the output amplifiers is between 0.5V and 3V.
The Photo Response Non Uniformity (PRNU), caused by
mismatch of photodiode node capacitances, is not corrected
on-chip. Measurements indicate that the typical PRNU is <1%
RMS of the signal level.
Notes on analog video signal and output amplifier specifica-
tions:
Color Filter Array (CFA)
• Video polarity: the video signal is negative going with
increasing light level.
Figure 4. Color Filter Arrangement on the Pixels
• Signal offset: the analog offset of the video signal is settable
by an external DC bias (pin 12 DARKREF). The settable
rangeisbetween1.7Vand3V, with2.65Vbeingthenominal
expected set point. The output range (including 1.2V video
signal) is thus between 3V and 0.5V.
• Power control: the output amplifiers can be switched
between an “operating” mode and a “standby” mode via the
serial port of the imager (see “SPI Register ” on page 13 for
the configuration).
Figure 5. Color Filter Response Curve
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.
• Coupling: the IBIS4-14000 can be DC- or AC-coupled to the
AD converter.
Figure 6. Output Amplifier Crossbar Switch
CLK_YR
Output Amplifier Crossbar Switch (multiplexer)
A crossbar switch is available that routes the green pixels
always to the same output (this is useful for a color device to
avoid gain and offset differences between green pixels). The
switch can be controlled automatically (with a toggle on every
CLK_Y rising edge) or manually (through the SPI register).
Manual
SYNC_YR
Q
Figure 6 shows how it works. A pulse on SYNC_Y resets the
crossbar switch. The initial state after reset of the switchboard
is read from the SPI control register. When the automatic
toggling of the switchboard is enabled, it toggles on every
rising edge of the CLK_Y clock. Separate pins are used for the
SYNC_Y and CLK_Y signals on the crossbar logic these pins
can be connected to the SYNC_YL and CLK_YL pins of the
shift register that is used for readout.
Power
Power
Power
Power
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Readout and Subsampling Modes
The subsampling modes available on the IBIS4-14000 are summarized in Table 2.
Table 2. Subsampling Modes
Subsampling Modes Programmed into SPI Register
X shift register subsampling settings
Bitcode
000
001
010
Mode
Use
1:1
Full resolution (4 outputs)
4:1 subsampling
Full resolution (all columns)
011
100
101
24:1
24:1 subsampling ( 2 outputs)
8:1 subsampling (2 outputs)
12:1 subsampling (2 outputs)
Select 4 columns/ skip 20
8:1
Select 4 columns / skip 4s
12:1
Select 4 columns / skip 8
Y shift register subsampling settings
Bitcode Mode
000
Use
4:1
4:1 subsampling
010
100
Select 2 rows / skip 2
001
011
101
1:1
Full resolution
Full resolution (all rows)
6:1
6:1 subsampling
12:1 subsampling
Select 2 rows / skip 4
12:1
Select 2 rows / skip 10
Each mode is selected independently for the X and Y shift
registers. The subsampling mode is configured via the serial
input port of the chip. The Y and X shift registers have some
different subsampling modes, due to constraints in the design
of the chip.
mentation is chosen for easy subsampling of color images
through a 2-channel readout. In this way color data from 2x2
pixels is made available in all subsample modes. On
monochrome sensors this is not required—only one output
can be used and the each second row selected by the Y shift
register can be skipped. This doubles the frame rate. Note that
for 2 or 1 channel readout, the not-used output amplifiers can
be powered down through the SPI shift register.
The baseline full resolution operation mode uses 4 outputs to
read out the entire image. 4 consecutive pixels of a row are put
in parallel on the 4 parallel outputs.
Rows can also be skipped by extra CLK_Y pulses. It is not
required to apply additional control pulses to rows that are
skipped. This is a way to implement extra subsampling
schemes. For example, to support the 24:1 X shift register
mode also vertically, the Y shift register can be set to the 12:1
mode and an additional CLK_Y pulse needs to be given at the
start of each row.
Subsampling is implemented by
a shift register with
hard-coded subsample modes. Depending on the selected
mode, the shift register skips the required number of pixels
when shifting the row or column pointer.
The X shift register always selects 4 consecutive columns in
parallel. Subsampling in X can be done by activating one of
the modes wherein a multiple of 4 consecutive columns is
skipped on a CLK_X pulse. The Y shift register selects a single
row. It will consecutively select 2 adjacent rows and then skip
an amount of rows set by the subsample mode. This imple-
Table 3 lists the frame rates of the IBIS4-14000 in various
subsample modes with only one output. The row blanking time
(dead time between readout of successive rows) has been set
to 17.5 s.
Table 3. Frame Rates and Resolution for Various Subsample Modes
Ratio
1:1
# Outputs
Image Resolution
3024 x 4536
756 x 1134
Frame rate [frames/s]
Frame readout time [s]
4
1
1
1
3.25
12.99
41.30
77.13
0.308
0.077
0.024
0.013
4:1
8:1
378 x 567
12:1
252 x 378
Note that the 24 additional columns and rows do not subsample (see Figure 2 on page 3).
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Figure 7. B and C Subsample Mode
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
mode B - 1:1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
mode C - 1:4
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Figure 8. D and E Subsample Mode
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
modeD - 1:6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
modeE - 1:8
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Figure 9. F Subsample Mode
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
mode F - 1:12
Sensor Readout Timing Diagrams
edge of PC occur at the same position. The falling edge of
RESET lags behind the rising PC edge.
Row Sequencer
• SHR (Sample & Hold pixel Reset level): this signal controls
another track & hold circuit in the column amplifiers. It is
used to sample the pixel reset level in the columns (for
double sampling). (0 = track ; 1 = hold)
The row sequencer controls pulses to be given at the start of
each new line. Figure 10 on page 10 shows the timing diagram
for this sequence.
The signals to be controlled at each row are:
• SYL (Select YL register): Selects the YL shift register to
drive the reset line of the pixel array
• CLK_YL and CLK_YR: These are the clocks of the YL and
YR shift register. They can be driven by the same signals
and at a continuous frequency. At every rising edge, a new
row is being selected.
• SYR (Select YR register): Selects the YR shift register to
drive the reset line of the pixel array. For rolling shutter appli-
cations, SYL and SYR are complementary. In full frame
readout, both registers may be selected together, only if it
is guaranteed that both shift registers point to the same row.
This can reduce the row blanking time.
• SELECT: This signal connects the pixels of the currently
sampled line with the columns. It is important that PC and
SELECT are never active together.
• SYNC_YR and SYNC_YL: Synchronization pulse for the
YR and YL shift registers. The SYNC_YR/SYNC_YL signal
is clocked in during a rising edge on CLK_YR/CLK_YL and
resets the YR/YL shift register to the first row. Both pulses
arepulsedonlyonceeachframe. Theexactpulsingscheme
depends on the mode of use (full frame/ rolling shutter). A
200 ns set-up time applies. See Table 4 on page 10.
• PC: An initialization pulse that needs to be given to
precharge the column.
• SHS (Sample & Hold pixel Signal): This signal controls the
track & hold circuits in the column amplifiers. It is used to
sample the pixel signal in the columns. (0 = track ; 1 = hold)
• RESET: This pulse resets the pixels of the row that is
currentlybeingselected.Inrollingshuttermode,theRESET
signal is pulsed a second time to reset the row selected by
the YR shift register. For “reset black” dark reference
signals, the reset pulse can be pulsed also during the first
PCpulse. Normally,therisingedgeofRESETandthefalling
• SYNC_X: Resets the column pointer to the first row. This
has to be done before the end of the first PC pulse, in case
when the previous line has not been read out completely.
Figure 10 shows the basic timing diagram of the IBIS4-14000
image sensor and Table 4 shows the timing specifications of
the clocking scheme
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Figure 10. Line Readout Timing
k
CLOCK_YL
Once each
frame
a
SYNC_YR
SYNC_YL
l
b
b
PC
c
SHS
f
d
d
e
e
SELECT
RESET
For each
new row
j
j
g
m
h
h
h
Optional reset pulse
for reset black
c
f
SHR
SYL
i
SYR
Only when the electronic
shutter is used
Table 4. Timing Constraints for the Row Sequencer
Symbol
Min.
Typ.
Description
a
200 ns
600 ns Min. SYNC set-up times. SYNC_Y is clocked in on rising edge on CLK_Y. SYNC_Y pulse
must overlap CLK_Y by one clock period. Set-up times of 200 ns apply after SYNC edges.
Within this set-up time no rising CLK edge may occur
b
c
2.7 µs Duration of PC pulse
10 µs Delay between falling edge on PC and rising edge on SHS/SHR. Duration of SHS/SHR
pulse
d
e
f
1.3 µs Delay between rising edge on PC and rising edge on SELECT
6.5 µs Delay between rising edge on SELECT and rising edge on SHS/SHR.
100 ns Delay between rising edge on SHS and falling edge on SELECT.
1.4 µs Delay between falling edge of SELECT and rising edge of RESET
g
h
i
5 µs
Duration of RESET pulse
1.28 µs Delay between rising edge on SHR and rising edge on SYR
500 ns SYL and SYR pulses must overlap second RESET pulse at both sides by one clock cycle
240 ns Duration of CLOCK_Y pulse
j
h+2*CLK
k
l
3µs
Delay between falling edge of CLK_Y and Falling edge of PC and SHS
m
500ns Delay between falling edge of RESET and falling edge of PC and SHR
Notes:
CLK_YL. The SYNC_YR pulse leads the SYNC_YL pulse by
a given number of rows. Relative to the row timing, both SYNC
pulses are given at the same time position.
CLK = one clock period of the master clock, shortest system
time period available.
SYNC_YR and SYNC_YL are only pulsed once each frame,
SYNC_YL is pulsed when the first row will be read out and
In the above timing diagram, the YR shift register is used for
the electronic shutter. The CLK_YR is driven identically as
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SYNC_YR is pulsed for the electronic shutter at the appro-
priate moment.
Note The SYNC_X signal has a set-up time Ts of 150 ns. For
the YR and YS shift registers, the set-up time is 200 ns. CLK_X
must be stable at least during this set-up time.
This timing assumes that the registers that control the
subsampling modes have been loaded in advance (through
the SPI interface), before the pulse on SYNC_YL or
SYNC_YR.
In the case where a partial row readout has been performed,
2 CLK_X pulses (with SYNC_X = LOW) are required to fully
deselect the column where the X pointer has been stopped. A
single CLK_X will leave the column partially selected, which
will then have a different response when read out in the next
row. When full row readout has been performed, the last
column will be fully deselected by a single CLK_X pulse (with
SYNC_X = LOW). The X-register is reset by a single CLK_X
pulse (with SYNC_X = LOW). In case of partial row readout,
the SYNC_X pulse has to be given before the sample pulses
(SHR and SHS) of the row sampling process, in order to avoid
a different response of the last column of the previous window.
The second reset pulse and the pulses on SYL and SYR (all
pulses drawn in red) are only applied when the rolling
electronic shutter is used. For full frame integration, these
pulses are skipped.
The SYNC_Y pulse is also used to initialize the switchboard
(output multiplexer). This is also done by a synchronous reset
on the rising edge of CLK_Y. Normally the switchboard is
controlled by the shift register used for readout (this is the YL
shift register). This means that pin SYNC_Y can be connected
to SYNC_YL, and pin CLK_Y can be connected to CLK_YL.
For the X shift register, the analog signal is delayed by 2 clock
periods before it becomes available at the output (due to
internal processing of the signal in the columns and output
amplifier). The figure gives an example of an ADC clock for an
ADC that samples on the rising edge.
The additional RESET BLACK pulse (indicated in dashed lines
in Figure 10 on page 10) can be given to make one or more
lines black. This can be useful to generate a dark reference
signal.
Fast Frame Reset Timing Diagram
Timing Pulse Pattern for Readout of a Pixel
Figure 12 on page 12 shows the reset timing for a fast frame
reset.
Figure 11 shows the timing diagram to preset (sync) the X shift
register, read out the image row, and analog-digital
conversion. There are 3 tasks:
SYL and SYR can be kept both high to make the reset
mechanism faster and reduce propagation delays. PC, SHS,
SHR can be kept high since they don’t interact with the pixel
reset mechanism.
• Preset the X shift register: apply a low level to SYNC_X
during a rising edge on CLK_X at the start of a new row
• Readout of the image row: pulse CLK_X
• Analog-digital conversion: clock the ADC
Table 5 on page 12 lists timing specifications for RESET,
CLK_Y and SELECT.
The SYNC pulses perform a synchronous reset of the shift
registers to the first row/column on a rising edge on CLK. This
is identical for all shift registers (YR, YL and X).
Figure 11. Row Readout Timing Sequence
Ts
Ts
SYNC_X
CLK_X
Analog
Output
pixel 1
pixel 2
pixel 3
CLK_ADC
(exam ple)
X
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Table 5. Fast Reset Timing Constraints
Symbol Typical Description
a
0 µs
Delay between rising CLK_Y edge and
Reset.
b
c
d
e
4 µs
0
Reset pulse width.
Reset hold time.
Select pulse width.
1.6 µs
1 µs
Setup hold time.
CONSTRAINT: a + e > 1 us due to
propagation delay on pixel select line.
Figure 12. Fast Reset Sequence Timing
CLK_YR
CLK_YL
a
c
e
d
SELECT
PC
SHS
b
RESET
SHR
SYL
SYR
b
SYNC_YR
SYNC_YL
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SPI Register
SPI Interface Architecture
The elementary unit cell of the serial to parallel interface consists of two D-flip-flops. The architecture is shown in Figure 13. 16
of these cells are connected in parallel, having a common /CS and SCLK form the entire uploadable parameter block, where Din
is connected to Dout of the next cell. The uploaded settings are applied to the sensor on the rising edge of signal /CS.
Figure 13. SPI Interface
To sensor core
16 outputs to sensor core
Din
D
Dout
Q
Q
SCLK
CS
C
Entire uploadable parameter block
CS
D
Din
Dout
SCLK
SCLK
C
Th
Tsclk
D0
D1
D2
D15
Unity Cell
Din
CS
Data
valid
Ts
• Output crossbar switch control bits. The crossbar switch is
used to route the green pixels to the same output amplifiers
at all time. A first bit controls the crossbar. When a second
bit is set, the first bit will toggle on every CLK_Y edge in
order to automatically route the green pixels of the bayer
filter pattern.
Table 6. Timing Requirements Serial-Parallel Interface
Parameter
Value
100 ns
50 ns
50 ns
Tsclk
Ts
Th
The code is uploaded serially as a 16-bit word (LSB uploaded
first).
SPI Register Definition
Table 7 on page 14 lists the register definition. The default
code for a full resolution readout is 33342 (decimal) or 1000
0010 0011 1110.
Sensor parameters can be serially uploaded inside the sensor
at the start of a frame. The parameters are:
• Subsampling modes for X and Y shift registers (3-bit code
for 6 subsampling modes)
• Power control of the output amplifiers, column amps and
pixel array. Each amplifier can be individually powered
up/down
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Table 7. Serial Sensor Parameters Register Bit Definitions
BIT
Description’
0 (LSB)
set to zero (0)
1
2
3
4
5
6
7
8
1 = power on sensor array ; 0 = power-down
1 = power up output amplifier 4; 0 = power-down
1 = power up output amplifier 3; 0 = power-down
1 = power up output amplifier 2; 0 = power-down
1 = power up output amplifier 1; 0 = power-down
3-bit code for subsampling mode of X shift register:
000 = full resolution
001 = full resolution
010 = full resolution
011 = select 4, skip 20
100 = select 4, skip 4
101 = select 4, skip 8
9
3-bit code for subsampling mode of Y shift registers:
000 = select 2, skip 2
001 = full resolution
010 = select 2, skip 2
011 = select 2, skip 4
100 = select 2, skip 2
101 = select 2, skip 2
10
11
12
Crossbar switch (output multiplexer) control bit initial value.
This initial value is clocked into the crossbar switch at a SYNC_YR rising edge pulse (when the array
pointers jump back to row 1).
The crossbar switch control bit selects the correspondence between multiplexer busses and output
amplifiers. Bus-to-output correspondence is according to the following table:
Bus
1
when bit set to 0
output 1
when bit set to 1
output 2
2
output 2
output 3
output 4
output 1
output 4
output 3
3 (4 outputs)
4 (4 outputs)
13
1 = Toggle crossbar switch control bit on every odd/even line. In order to let green pixels always use the
same output amplifier automatically, this bit must be set to 1. On every CLK_Y rising edge (when a new
row is selected), the crossbar switch control bit will toggle. Initial value (after SYNC_Y) is set by bit 12.
14
Not used.
15 (MSB)
1 = Power-up sensor array; 0 = Power-down
Three pins are used for the serial data interface. This interface
converts the serial data into an (internal) parallel data bus
(Serial-Parallel Interface or SPI). The control lines are:
• CS: chip select, a rising edge on CS loads the parallelized
data into the on-chip register.
The initial state of the register is undefined. However, no state
exists that destroys the device.
• DATA: the data input. LSB is clocked in first.
• CLK: clock, on each rising edge, the value of DATA is
clocked in
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Pin Configuration
Table 7 on page 14 lists the pin configuration of the IBIS4-14000. Figure 17 on page 21 shows the assignment of pin numbers
on the package.
Table 8. Pin List
Pin #
Name
OBIAS
Function
Comment
1
Bias current output amplifiers.
Connect with 10kΩ to VDD and decouple with 100 nF to
GND.
2
3
4
5
6
7
8
9
GND
Ground for output 3.
Output 3.
OUT3
GND
Ground for output 4.
Output 4.
OUT4
VDD
Power supply.
Ground.
Nominal 3.3V
0V
GND
OUT2
GND
Output 2.
Ground for output 2.
Output 1.
10
11
12
13
OUT1
GND
Ground for output 1.
Offset level of output signal.
DARKREF
TEMP1
Typ. 2.6V. min. 1.7V max. 3V
Temperature sensor.
Located near the output amplifiers (pixel
Any voltage above GND forward biases the diode.
Connect to GND if not used.
4536, 0) near the stitch line).
14
PHDIODE
Photodiode output.
Yields the equivalent photocurrent of 250 x Connect to GND if not used.
Reverse biased by any voltage above GND
50 pixels. Diode is located right under the
pad.
15
16
17
CLK_Y
Y clock for switchboard.
Clocks on rising edge
Connect to CLK_YL (or drive identically)
SYNC_Y
TEMP2
Y SYNC pulse for switchboard.
Low active: synchronous sync on rising edge of CLK_Y
Connect to SYNC_YL (or drive identically)
Temperature sensor.
Located near pixel (24,0).
Any voltage above GND forward biases the diode.
Connect to GND if not used.
18
19
20
21
GNDAB
GND
Anti-blooming reference level (= pin 33).
Ground.
Typ. 0V. Set to 1.5V for improved anti-blooming.
0V
VDD
Power supply.
Nominal 3.3V
VDDR
Power supply for reset line drivers
Nominal 4V
Connected on-chip to pin 30
22
23
CLK_YR
SYR
Clock of YR shift register.
Shifts on rising edge.
Activate YR shift register for driving of reset High active. Exact pulsing pattern see timing diagram.
and select line of pixel array.
Both SYR = 1 and SYL = 1 is not allowed, except when the
same row is selected!
24
SYNC_YR
Sets the YR shift register to row 1.
Low active. Synchronous sync on rising edge of CLK_YR
200 ns set-up time
25
26
27
VDDARRAY Pixel array power supply (= pin 26).
VDDARRAY Pixel array power supply (= pin 25).
3V
3V
SYNC_YL
Sets the YL shift register to row 1.
Low active. Synchronous sync on rising edge of CLK_YL
200 ns set-up time.
28
SYL
Activate YL shift register for driving of reset High active. Exact pulsing pattern see timing diagram.
and select line of pixel array.
Both SYR = 1 and SYL = 1 is not allowed, except when the
same row is selected.
Document #: 38-05709 Rev. *B
Page 15 of 27
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Table 8. Pin List (continued)
Pin #
29
Name
CLK_YL
VDDR
Function
Clock of YL shift register.
Comment
Shifts on rising edge.
Nominal 4V.
30
Power supply for reset line drivers.
Connected on-chip to pin 21.
31
32
33
34
35
36
VDD
Power supply.
Nominal 3.3V
GND
Ground.
0V
GNDAB
SELECT
RESET
CBIAS
Anti-blooming reference level (= pin 33).
Control select line of pixel array.
Reset of the selected row of pixels.
Bias current column amplifiers.
Typ. 0V. Set to 1V for improved anti-blooming.
High active. See timing diagrams.
High active. See timing diagrams.
Connect with 22 kΩ to VDD and decouple with 100 nF to
GND.
37
PCBIAS
Bias current.
Connect with 22 kΩ to VDD and decouple with 100 nF to
GND.
38
39
40
41
42
DIN
Serial data input.
16-bit word. LSB first.
SCLK
CS
SPI interface clock.
Chip select.
Shifts on rising edge.
Data copied to registers on rising edge.
See timing diagrams.
PC
Row initialization pulse.
Sets the X shift register to row 1.
SYNC_X
Low active. Synchronous sync on rising edge of CLK_X
150 ns set-up time.
43
44
45
46
GND
VDD
Ground.
0V
Power supply.
Nominal 3.3V
Shifts on rising edge.
See timing diagram.
CLK_X
SHR
Clock of YR shift register.
Row track & hold reset level
(1 = hold; 0 = track).
47
48
49
SHS
Row track & hold signal level (1 = hold;
0 = track).
See timing diagram.
XBIAS
ABIAS
Bias current X multiplexer.
Connect with 10 kΩ to VDD and decouple with 100 nF to
GND.
Bias current pixel array.
Connect with 10 MΩ to VDD and decouple with 100 nF to
GND.
Document #: 38-05709 Rev. *B
Page 16 of 27
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Specifications
General Specifications
Table 9. IBIS4-14000 General Specifications
Parameter
Value
Remarks
Pixel architecture
Technology
Pixel size
3T pixel
CMOS
2
8 x 8 µm
Resolution
3048 x 4560
3.3V
13.9 megapixels
Power supply
Shutter type
Pixel rate
Electronic rolling shutter
15 MHz nominal
20 MHz with extra power dissipation.
Frame rate
3.25 frames/s
Full resolution with 4 parallel analog outputs
@ 15 MHz/channel
Power dissipation
176 mW
53 mA
Electro-optical Specifications
Overview
All parameters are measured using the default settings (see recommended operating conditions) unless otherwise specified.
Table 10.IBIS4-14000 Electro-optical Specifications
Parameter
Value
Remarks
Effective conversion gain
18.5 V/e-
25 V/e-
Full range. See note 1.
Linear range. See note 1.
Spectral response * fill factor
Peak Q.E. * fill factor
Full Well charge
0.22 A/W (peak)
45%
Between 500 and 700 nm.
See note 1.
65000 electrons
90% of full well charge
Linear range
Linearity definition: < 3% deviation from straight line through zero
point.
Temporal noise
(kTC noise limited)
35 electrons
kTC noise, being the dominant noise source in the dark at short
integration times.
Dynamic range
1857:1 (65.4 dB)
1671:1 (64.5 dB)
See note 1.
Linear dynamic range
Average dark current
Dark current signal
See note 1; 3% deviation.
2
55 pA/cm
Average value @ 24°C lab temperature.
Average value @ 24°C lab temperature.
223 electrons/s
4.13 mV/s
MTF at Nyquist
0.55 in X
0.57 in Y
Measured at 600 nm.
Fixed pattern noise (local)
Fixed pattern noise (global)
PRNU
0.11% Vsat RMS
0.15% Vsat RMS
<1% RMS of signal
Average value of RMS variation on local 32 x 32 pixel windows.
5
Anti-blooming
10
Charge spill-over to neighboring pixels (= CCD blooming
mechanism)
Note
1. Settings: VDD = 3.3V, VDDR = 4V and VDD_ARRAY = 3V.
Document #: 38-05709 Rev. *B
Page 17 of 27
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Spectral Response Curve
Figure 14. IBIS4-14000 Spectral Response Curve
Electro-voltaic Response Curve
Figure 15. IBIS4-14000 Electro-voltaic Response Curve
Document #: 38-05709 Rev. *B
Page 18 of 27
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Electrical Specifications
Absolute Maximum Ratings
Table 11.IBIS4-14000 Absolute Maximum Ratings
Parameter
Description
Value
Unit
V
V
V
V
I
DC supply voltage
–0.5 to +4.5
DC
DC input voltage
–0.5 to V + 0.5
V
IN
DC
DC output voltage
–0.5 to V + 0.5
V
OUT
DC
DC current per pin; any single input or output
Storage temperature range
±50
mA
°C
T
–10 to 66 (@ 15% RH)
–10 to +38 (@ 86% RH)
(RH = relative humidity)
STG
Altitude
8000
feet
Recommended Operating Specifications
Table 12.IBIS4-14000 Recommended Operating Specifications
Parameter
Description
Nominal power supply
Min.
Typ.
3.3
4
Max.
Unit
VDD
3.6
V
V
VDDRL
VDDRR
Reset power supply level
VDD_ARRAY
DARKREF
GNDAB
Pixel supply level
3
2.65
0
V
Dark reference offset level
Anti-blooming ground level
Analog output level
1.7
0
3
1
V
V
V
V
V
0.5
2.5
0
3
V
OUT
IH
Logic input high level
3.3
1
V
Logic input low level
V
IL
T
Commercial operating temperature
Commercial operating temperature
0
50
38
°C (@ 15% RH)
°C (@ 86% RH)
A
T
0
A
Bias Currents and References
[2]
Table 13.IBIS4-14000 Bias Currents
Pin Number
Pin Name
OBIAS
CBIAS
Connection
10k to VDD
22k to VDD
22k to VDD
10k to VDD
or 10M to VDD
Input Current
179 µA
Pin Voltage
1.51V
1
36
37
48
49
91 µA
1.29V
PCBIAS
XBIAS
91 µA
1.29V
181 µA
1.49V
ABIAS
0.8V
Note
2. Tolerance on bias reference voltages: ±150 mV due to process variances.
Document #: 38-05709 Rev. *B
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Geometry and Mechanical
Die Geometry
Figure 16. Die Geometry and Location of Pixel (0,0)
Pin 1
pixel 0,0
4 output
channels
500 µm
Ground pad, also connected to
package ground plane
Analog output pad
Ground for output pad (not connected
to package ground plane)
Locations of temperature sensing
diodes
Location of photodiode array
Document #: 38-05709 Rev. *B
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Pin Number Assignment
Figure 17. Pin Number Assignment
32 33 34 35 36 37
38 39 40 41 42 43
31 30 29 28 27 26
49 48 47 46 45 44
Package
Back side
20 21 22 23 24 25
19 18 17 16 15 14
1 2 3 4 5 6
13 12 11 10 9 8 7
Note: “Solid” drawn pins are connected to die attach area for a proper ground plane
Document #: 38-05709 Rev. *B
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Package Drawings
Figure 18. Package Dimensions
all dimensions in mm
Document #: 38-05709 Rev. *B
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Die Placement Dimensions and Accuracy
Figure 19. Die Placement
all dimensions in mm
Figure 20. Tolerances
Document #: 38-05709 Rev. *B
Page 23 of 27
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Cover Glass
CYII4SM014KAA-GEC(monochrome)
Schott D-263 plain glass is the cover glass of the IBIS4-14000 monochrome.
Figure 21. D-263 Transmittance Curve
100
90
80
70
60
50
40
30
20
10
0
400
500
600
700
800
900
Wavelength [nm]
CYII4SC014KAA-GTC (color)
S8612 glass is the cover glass of the IBIS4-14000 color.
Figure 22. S8612 Transmittance Curve (w/o AR coating)
100
90
80
70
60
50
40
30
20
10
0
400
500
600
700
800
900
1000
Wavelength [nm]
Specification
• AR coating: 400–690 nm R < 1.5%
• Substrate: Schott S8612 glass
• Thickness: 0.7 mm ±0.050 mm
2
• Dig, haze, scratch 20 µm after coating
• Size: 31.9 x 44.9 mm ±0.2 mm
Document #: 38-05709 Rev. *B
Page 24 of 27
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Defects (digs, scratches) are detected at final test using F/11
light source. Glass defects that do not generate
non-correctable pixels are accepted.
of 1 MOhm between the human body and the ground to be
on the safe side.
• When directly handling the device with the fingers, hold the
part without the leads and do not touch any lead.
Storage and Handling
• To avoid generating static electricity:
Storage Conditions
— Do not scrub the glass surface with cloth or plastic
— Do not attach any tape or labels
Description Minimum Maximum Unit Conditions
— Do not clean the glass surface with dust-cleaning tape
Temperature
Temperature
–10
–10
66
38
°C
°C
@ 15% RH
@ 86% RH
• When storing or transporting the device, put it in a container
of conductive material
Note: RH = Relative Humidity
Dust and Contamination
Handling Precautions
Dust or contamination of the glass surface could deteriorate
the output characteristics or cause a scar. In order to
minimize dust or contamination on the glass surface, take the
following precautions:
Special care should be taken when soldering image sensors
with color filter arrays (RGB color filters), onto a circuit board,
since color filters are sensitive to high temperatures.
Prolonged heating at elevated temperatures may result in
deterioration of the performance of the sensor. The following
recommendations are made to ensure that sensor perfor-
mance is not compromised during end-users’ assembly
processes.
• Handlethedevice in aclean environment such asacleaned
booth (the cleanliness should be, if possible, class 100).
• Do not touch the glass surface with the fingers.
• Use gloves to manipulate the device
Soldering
ESD
Soldering should be manually performed with 5 seconds at
350°C maximum at the tip of the soldering iron.
Though not as sensitive as CCD sensors, the IBIS4-14000 is
vulnerable to ESD like other standard CMOS devices. Device
placement onto boards should be done in accordance with
strict ESD controls for Class 0, JESD22 Human Body Model,
and Class A, JESD22 Machine Model devices. Take into
account standard ESD procedures when manipulating the
device:
Precautions and Cleaning
Avoid spilling solder flux on the cover glass; bare glass and
particularly glass with antireflection filters may be adversely
affected by the flux. Avoid mechanical or particulate damage
to the cover glass. Avoid mechanical stress when mounting
the device.
• Assembly operators should always wear all designated and
approved grounding equipment; grounded wrist straps at
ESD protected workstations are recommended including
the use of ionized blowers. All tools should be ESD
RoHS (lead-free) Compliance
This paragraph reports the use of Hazardous chemical
substances as required by the RoHS Directive (excluding
packing material).
protected. To ground the human body, provide a resistance
Table 14.Chemical Substances and Information about Any Intentional Content
Any intentional
content?
If there is any intentional content,
in which portion is it contained?
Chemical Substance
Lead
NO
NO
NO
NO
NO
NO
-
-
-
-
-
-
Cadmium
Mercury
Hexavalent chromium
PBB (Polybrominated biphenyls)
PBDE (Polybrominated diphenyl ethers)
Document #: 38-05709 Rev. *B
Page 25 of 27
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Information on lead free soldering
1. A case that the above material is added as a chemical com-
position into the inquired product intentionally in order to
produce and maintain the required performance and func-
tion of the intended product .
CYII4SM014KAA-GEC: the product was tested successfully
for lead-free soldering processes, using a reflow temperature
profile with maximum 260°C, minimum 40s at 255°C and
minimum 90s at 217°C.
2. A case that the above material, which is used intentionally
in the manufacturing process, is contained in or adhered to
the inquired product
CYII4SC014KAA-GTC: the product will not withstand a
lead-free soldering process. Maximum allowed reflow or wave
soldering temperature is 220°C. Hand soldering is recom-
mended for this part type.
The following case is not treated as “intentional content”:
1. A case that the above material is contained as an impurity
into raw materials or parts of the intended product. The im-
purity is defined as a substance that cannot be removed
industrially, or it is produced at a process such as chemical
composing or reaction and it cannot be removed technical-
ly.
Note:
“Intentional content” is defined as any material demanding
special attention is contained into the inquired product by
following cases:
Ordering Information
Part Numbers
Table 15.Ordering Information
Part number
CYII4SM014KAA-GEC
Package
Monochrome/Color
Monochrome
Glass lid
Monochrome
Color
49-pin PGA package
49-pin PGA package
CYII4SC014KAA-GTC
RGB Color
Evaluation Kit
and display of images from the sensor. All acquired images
can be stored in different file formats (8 or 16-bit). All settings
can be adjusted on the fly to evaluate the sensors’ specs.
Default register values can be loaded to start the software in a
desired state. Please contact us for more information.
For evaluating purposes an IBIS4-14000 evaluation kit is
available. The IBIS4-14000 evaluation kit consists of a multi-
functional digital board (memory, sequencer and IEEE 1394
Fire Wire interface) and an analog image sensor board. Visual
Basic software (under Win 2000 or XP) allows the grabbing
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05709 Rev. *B
Page 26 of 27
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Document History Page
Document Title: IBIS4-14000 14Megapixel CMOS Image Sensor
Document Number: 38-05709
REV.
**
ECN NO.
310213
428177
Issue Date
See ECN
See ECN
Orig. of Change
Description of Change
SIL
Initial Cypress release
*A
FVK
Layout converted
Figure 10 on page 10 updated
Storage and handling section added
IBIS4-14000-C added
*B
642656
See ECN
FPW
Ordering information update+package spec label.
Moved figure captions to the top of the figures and
moved notes to the bottom of the page per new
template. Verified all cross-referencing. Moved the
specifications towards the back. Corrected all
variables on the Master pages.
Document #: 38-05709 Rev. *B
Page 27 of 27
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